JP2015082271A - Cyclic communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a cyclic communication system for reducing the processing load of a processor while securing guarantee for the simultaneity of data during cyclic communication.SOLUTION: Between a processor control unit 15a and a memory control unit 12a for performing a write/read to and from a cyclic memory 11a of cyclic communication data is provided a configuration for securing the simultaneity of each data when cyclic communication data is transmitted/received after being divided into in a plurality of data. This configuration is realized by providing a pair of transmission data memories 23a, 24a, a transmission data switching unit 22a for switching the read and write sides of the transmission data memories, a pair of reception data memories 26a, 27a, and a reception data switching unit 25a for switching the read and write sides of the reception data memories, as well as a data monitoring control unit 21a for transferring data between the transmission data memories or reception data memories and the cyclic memory 11a.

Description

  The present invention relates to a cyclic communication system in which a plurality of terminals (communication nodes) perform cyclic communication via a network (transmission path). In particular, the present invention relates to, for example, certain cyclic data or image data for industrial use. The present invention relates to a cyclic communication system using a general-purpose Ethernet (registered trademark) or the like for an application requiring an update period.

In a conventional cyclic communication system, a plurality of terminals transmit data on a network at a constant cycle, and a receiving terminal stores the latest data as a memory image and reads the memory (for example, Patent Document 1, Patent Document) 2).
In Patent Document 1, when the processor reads / writes the cyclic memory, the reception / transmission of the communication frame is stopped, thereby guaranteeing the simultaneity of the data read by the processor.
Further, in Patent Document 2, when the communication frame is received / transmitted when the processor reads / writes, the read / write is stopped to guarantee the simultaneity of the data read by the processor.

JP 2007-328589 A (pages 4-5, FIG. 1) JP-A-9-269934 (pages 4-6, FIG. 2) Japanese Patent Laid-Open No. 10-210085 (pages 4-6, FIG. 1) JP 62-295157 A (pages 3 to 5, FIG. 1)

  Since the conventional cyclic communication system is configured as described above, the communication frame transmission cycle of the transmitting terminal and the processor read cycle of the receiving terminal are not synchronized. The old data (data in which the transmission cycle of the communication frame is one time before in the read data) and the new data (data in which the transmission cycle of the communication frame is one time after the old data in the read data) are mixed When the processor reads the mixed cyclic data and processes the application on the processor, there is a problem that causes an erroneous operation.

In Patent Document 1, when the processor reads / writes the cyclic memory, the reception / transmission of the communication frame is stopped, thereby guaranteeing the simultaneity of the data read by the processor.
However, a communication buffer (primary storage memory for the communication frame) for stopping the reception / transmission of the communication frame is required, and the communication control unit associated therewith becomes complicated and the component cost increases.
Further, in Patent Document 2, when the communication frame is received / transmitted when the processor reads / writes, the read / write is stopped to guarantee the simultaneity of the data read by the processor. However, there is a problem in that the processor performance deteriorates because the processor performs reading / writing from the beginning after waiting for a while after stopping the reading / writing.

In Patent Document 3, as means for solving the degradation of the processor performance described in Patent Document 2, a cyclic memory (one surface) that is read / written by the processor, and a communication control unit that reads / writes data during reception / transmission. The cyclic memory (2 sides) to be written is physically separated so that even when a communication frame is received / transmitted, the processor can always read / write so that the processor performance is not deteriorated. .
However, since data simultaneity is ensured by switching between 1 and 2 each time data is received / transmitted in one communication frame unit, data simultaneity cannot be guaranteed for a plurality of communication frames. For this reason, when guaranteeing the simultaneity of large-capacity data divided into a plurality of communication frames, the processor analyzes the data contents of the plurality of communication frames and then processes the data. There remains a problem with reduced performance.

In addition, Patent Document 4 also has a cyclic memory as a means for solving the processor performance degradation described in Patent Document 2 and physically receives three communication frames depending on the application, and receives a communication frame. Even in such a case, the processor can always read data so as not to deteriorate the processor performance.
However, as in Patent Document 3, every time data is received in one communication frame unit, data synchronism is guaranteed by switching three planes, so data synchronism cannot be guaranteed for a plurality of communication frames. For this reason, there remains a problem that the processor performance deteriorates in a plurality of communication frames.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a cyclic communication system that reduces the burden of processor processing while ensuring data simultaneity during cyclic communication. And

  The cyclic communication system according to the present invention is a cyclic communication system in which a plurality of terminals perform cyclic communication via a network, and each terminal stores data used for cyclic communication. A memory, a memory control unit for controlling reading and writing of data to and from the cyclic memory, and transmitting a communication frame via the network using the data of the cyclic memory, and in the communication frame received via the network Control unit for storing the data in the cyclic memory, writing cyclic communication data transmitted in one cyclic communication cycle to the cyclic memory, and cyclic communication received in one cyclic communication cycle A processor for reading data, and When the cyclic communication data divided into a plurality of parts is transmitted / received by a plurality of communication frames, a data alignment unit is provided to ensure the simultaneity of the respective data. A counter value counted for each period is added, and the data alignment unit secures the simultaneity of each divided data of the cyclic communication data using the counter value.

  According to the present invention, a cyclic communication system in which a plurality of terminals perform cyclic communication via a network, each terminal having a cyclic memory for storing data used for cyclic communication, the cyclic communication A memory control unit that controls the reading and writing of data to and from the memory for memory, transmits data in the communication frame via the network using the data in the cyclic memory, and cyclically transmits data in the communication frame received via the network Writes cyclic communication data transmitted in one cyclic communication cycle and reads cyclic communication data received in one cyclic communication cycle to the communication control unit and cyclic memory stored in the memory. Processor and cyclic communication divided into multiple A data alignment unit that ensures the simultaneity of each data when the data is transmitted and received by a plurality of communication frames, and each divided data of the cyclic communication data includes a counter that is counted for each cyclic communication cycle Since the value is added and the data alignment unit uses the counter value to ensure the simultaneity of each divided data of the cyclic communication data, the data alignment unit can also synchronize each data even in large-capacity data transmitted and received by a plurality of communication frames It can be ensured and the processor processing load can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS It is a whole block diagram which shows the cyclic communication system by Embodiment 1 of this invention. It is a figure which shows the cyclic communication image of the cyclic communication system by Embodiment 1 of this invention. It is a figure which shows the timing of the cyclic communication of the cyclic communication system by Embodiment 1 of this invention. It is a timing diagram for demonstrating the problem of reading from the cyclic memory of a prior art. It is a block diagram which shows the inside of the terminal of the cyclic communication system by Embodiment 1 of this invention. It is a figure which shows the receiving frame format of the cyclic communication system by Embodiment 1 of this invention. It is an image figure which shows the transmission map of the cyclic communication system by Embodiment 1 of this invention. It is an image figure which shows the reception map of the cyclic communication system by Embodiment 1 of this invention. It is a figure which shows the timing which reads the received data of the cyclic memory of the cyclic communication system by Embodiment 1 of this invention. It is a block diagram which shows the terminal inside of the cyclic communication system by Embodiment 2 of this invention. It is a flowchart which shows the write-in process of the transmission data of the cyclic communication system by Embodiment 2 of this invention. It is a block diagram which shows the inside of the terminal of the cyclic communication system by Embodiment 3 of this invention. It is a block diagram which shows the terminal inside of the cyclic communication system by Embodiment 4 of this invention. It is a figure which shows the resending request | requirement frame format of the cyclic communication system by Embodiment 4 of this invention. It is a figure which shows the timing which requests resending when reading the received data of the cyclic memory of the cyclic communication system by Embodiment 4 of this invention. It is a block diagram which shows the inside of the terminal of the cyclic communication system by Embodiment 5 of this invention. It is a figure which shows the resending request | requirement frame format of the cyclic communication system by Embodiment 5 of this invention. It is a figure which shows the cyclic communication frame format with the resending request | requirement of the cyclic communication system by Embodiment 6 of this invention.

Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below with reference to the drawings.
1 is an overall configuration diagram showing a cyclic communication system according to Embodiment 1 of the present invention.
In FIG. 1, a terminal A1, a terminal B2, and a terminal C3 (communication node) transmit and receive cyclic communication frames via a network 4 (transmission path) and execute an application to operate the system. The internal configurations of the terminal A1, the terminal B2, and the terminal C3 are all the same as will be described later.
The terminal A1, the terminal B2, and the terminal C3 each have cyclic memories 11a, 11b, and 11c that store cyclic communication data.
Hereinafter, the cyclic communication frame is also referred to as a reception frame or a transmission frame.

FIG. 2 is a diagram showing a cyclic communication image of the cyclic communication system according to the first embodiment of the present invention.
2, when viewed from the terminal A in the system configuration of FIG. 1, data transmitted by itself (terminal A) is indicated by 111 a to 113 a and received by the terminal B / C, which is another terminal, for each cyclic use. Data stored in the memory is indicated by 111b to 113b / 111c to 113c.
Similarly, data transmitted by the terminal B is indicated by 114b to 116b, and the data received by the terminal A and stored in the cyclic memory 11a is indicated by 114a to 116a.
The same applies to the case where terminal C transmits, which are indicated by 117c to 119c and 117a to 119a, respectively.
Note that data transmitted by a single terminal at a constant cycle is composed of a plurality of data, and in FIG. 2, data are indicated by data # 1 to # 3 having consecutive addresses.
For example, transmission data from terminal A to terminal B is data # 1 (114a), data # 2 (115a), and data # 3 (116a).
As described above, in the cyclic communication, the data of all terminals connected to the network 4 can be referred to by the memory image by referring to the cyclic memory 11a on one terminal.

FIG. 3 is a diagram showing the timing of cyclic communication in the cyclic communication system according to the first embodiment of the present invention.
In FIG. 3, a cyclic communication frame is transmitted at an asynchronous timing possessed by each transmitting terminal, and all terminals receive all the cyclic communication frames and store them in a cyclic memory.

FIG. 4 is a timing chart for explaining the problem of reading from the cyclic memory according to the prior art.
In FIG. 4, the reception timing of the data # 1, # 2, and # 3 is shifted, and a period in which the new data and the old data of the third data and the fourth data are mixed is generated. When the processor reads during this mixed period, it is read in a mixed state of old and new data in the cyclic communication data.
Data # 1 reads new data, but data # 2 reads old data, so data simultaneity cannot be guaranteed, and an application in the processor malfunctions.
As described above, when there is no function for ensuring data simultaneity, there is a timing when simultaneity cannot be guaranteed.

FIG. 5 is a block diagram showing the inside of the terminal of the cyclic communication system according to the first embodiment of the present invention.
FIG. 5 shows the configuration of the terminal A1. Terminals B2 and C3 have the same configuration.
Basically, received data by cyclic communication is stored in the cyclic memory 11a, and the processor 14a instructs the processor control unit 15a to guarantee data concurrency (data alignment unit) and Reading is performed via the memory control unit 12a. The transmission data transmitted by the terminal itself is sent from the processor 14a to the processor control unit 15a so as to guarantee data simultaneity (data alignment unit) and the cyclic memory 11a via the memory control unit 12a. To write on.

  Here, a configuration (data alignment unit) for guaranteeing data simultaneity includes a data monitoring control unit 21a, a transmission data switching unit 22a, a transmission data memory 23a, a transmission data memory 24a, a transmission map 28a, and reception data, which will be described later. A switching unit 25a, a reception data memory 26a, a reception data memory 27a, and a reception map 29a are provided.

The communication control unit 13a performs control for transmitting and receiving cyclic communication frames. The memory control unit 12a reads / writes data to / from the cyclic memory 11a.
The communication control unit 13a writes data in a received frame received from the network 4 by cyclic communication and a counter value to be described later to the cyclic memory 11a via the memory control unit 12a and transmits from the cyclic memory 11a. Data is read out, a transmission frame is generated, and is transmitted to the network 4 in the cycle of the own terminal.
The processor 14a executes the application and instructs the processor control unit 15a to read / write data to / from the cyclic memory 11a.
Upon receiving an instruction from the processor 14a, the processor control unit 15a reads / writes data to / from the cyclic memory 11a and returns the read data to the processor 14a.

However, the read / write request destination of the processor control unit 15a at this time is the transmission data switching unit 22a and the reception data switching unit 25a. In the case of reading, the reception data switching unit 25a is the request destination, and in the case of writing, the transmission data switching unit 22a is the request destination.
The transmission data memory 23a and the transmission data memory 24a are a pair, and the transmission data switching unit 22a performs switching (surface switching) such that one is a reading side and the other is a writing side. At the time of writing, cyclic communication data is written from the processor control unit 15a. On the reading side, cyclic communication data is read out and written into the cyclic memory 11a by a data monitoring control unit 21a described later.

  The reception data memory 26a and the reception data memory 27a are paired, and the reading side and the writing side are switched by the reception data switching unit 25a. On the reading side, received data is read from the processor control unit 15a. On the writing side, data received from the cyclic memory 11a is written by the data monitoring controller 21a described later.

The data monitoring control unit 21a reads the received data of the cyclic memory 11a via the memory control unit 12a at a constant cycle unrelated to the cyclic communication frame reception process by the communication control unit 13a, and receives the received data on the writing side. Copy to memory.
The reception data switching unit 25a refers to a reception map 29a to be described later, regardless of the copy process of the data monitoring control unit 21a, on the surfaces (write side and read side) of the reception data memory 26a and the reception data memory 27a. Switch over.

The transmission data switching unit 22a monitors the write request of the processor control unit 15a, and switches the plane (the writing side and the reading side) of the transmission data memory 23a / 24a with reference to the transmission map 28a.
The data monitoring control unit 21a reads the data in the transmission data memory on the reading side at a constant cycle unrelated to the writing process of the cyclic communication data to the writing side of the transmission data memory, and stores the data in the cyclic memory 11a. Copy via 12a.

In FIG. 5, there is no problem even if the processor control unit 15a is not provided, that is, the processor 14a directly writes data to the transmission data memory and reads data from the reception data memory.
The same applies to the following second to sixth embodiments.

FIG. 6 is a diagram showing a reception frame format of the cyclic communication system according to the first embodiment of the present invention.
In FIG. 6, the reception frame 5 has a cyclic communication frame format that flows on the network 4.
The node ID 5a indicates a receiving terminal, but in the case of cyclic communication, it is assumed to be ALL-F indicating all terminals. The block NO5b is the number of the cyclic communication data uniquely assigned to each terminal and for each cyclic communication data, the offset 5c is the head address stored in the cyclic memory 11a, and the size 5d is the received frame 5 The data size and data 5e are data to be stored in the cyclic memory 11a.

In FIG. 6, the counter values 5f / 5g to be added for each cycle of transmitting cyclic communication frames are arranged at the beginning and end of the data 5e area, so that all received frames 5 of the same cyclic communication data are read at the time of reading. If the first counter value and the last counter value coincide with each other, it can be proved that the new data and the old data are not mixed. (Refer to the counter value in FIG. 9)
Further, by providing an FCS value 5h (CRC or other frame check sequence) at the end of the received frame 5, the FCS value 5h is checked at the time of reception so that the validity of the data in the received frame 5 can be guaranteed. Yes.

FIG. 7 is an image diagram showing a transmission map of the cyclic communication system according to the first embodiment of the present invention.
In FIG. 7, a transmission map 28a is an image diagram on the terminal A1, and is generated in advance. For all cyclic communication data transmitted by the terminal itself, block NO5b, offset 5c and size 5d stored in the cyclic communication frame are associated with each other and registered for each cyclic communication frame (one line in FIG. 7). ing.
However, when the amount of cyclic communication data becomes large, the cyclic communication data is divided into a plurality of cyclic communication frames. Therefore, even if the block NO5b in the cyclic communication frame is the same, the offset 5c The size 5d varies depending on the cyclic communication frame.
For example, if the maximum size of the cyclic communication frame is 4 Kbytes and the cyclic communication data is 12 Kbytes, the cyclic communication data is divided into three cyclic communication frames, so all three have a size of 4 Kbytes. The offset is obtained by adding 4 Kbytes to the offset address of the first cyclic communication frame at the offset 5c of the second and subsequent cyclic communication frames. In other words, it is a continuous address.

  Whenever transmission data is written in the transmission data memory 23a / 24a, the transmission data switching unit 22a transmits the data if the offset 5c and size 5d continuous address areas registered in the transmission map 28a are all written. The surface of the data memory 23a / 24a is switched instantaneously so that the data monitoring control unit 21a can always read data from the transmission data memory 23a / 24a while ensuring simultaneity.

FIG. 8 is an image diagram showing a reception map of the cyclic communication system according to the first embodiment of the present invention.
In FIG. 8, a reception map 29a is an image diagram on the terminal A1, and is generated in advance. All cyclic communication data received by the own terminal is registered for each cyclic communication data (in one line in FIG. 8) in association with the offset 5c and the size 5d. Incidentally, when divided into several frames, it is registered for each continuous address area.

The reception data switching unit 25a calculates the address of the counter value 5f / 5g from the offset 5c and the size 5d with reference to the reception-side reception data memory 27a at a constant cycle regardless of the operation of the data monitoring control unit 21a. When all the counter values 5f / 5g in the read and continuous address areas match, the surface of the reception data memory 26a / 27a is instantaneously switched, and the processor control unit 15a receives the data that always ensures simultaneity. 26a / 27a can be read.
For example, when the size of the cyclic communication data is 12 Kbytes, there are three communication frames, and the counter value 5f / 5g has three at the beginning and the last, so all six counter values 5f / 5g are referred to. Will do.

Next, the operation will be described.
In the first embodiment, a transmission data switching unit 22a, a transmission data memory 23a / 24a or a reception data switching unit 25a, a reception data memory 26a / 27a, and a data monitoring control are provided between the processor control unit 15a and the memory control unit 12a. The transmission / reception request destination of the processor control unit 15a is the transmission data switching unit 22a and the reception data switching unit 25a.
As a result, when the processor 14a reads continuous addresses, new and old data are not mixed in the reception data memory 26a / 27a, so that the processor 14a can always write transmission data for cyclic communication and at which timing. Thus, it is possible to always ensure simultaneity even if the received data is read out.

Next, the operation when the terminal A1 receives a cyclic communication frame will be described.
Every time a cyclic communication frame is received, the communication control unit 13a uses the FCS value 5h in the cyclic communication frame to cyclically check the cyclic communication frame whose validity has been guaranteed via the memory control unit 12a. The data 5e and the counter value 5f / 5g in the cyclic communication frame are written into the memory 11a.
The data monitoring control unit 21a reads the received data of the cyclic memory 11a at a constant cycle unrelated to the cyclic communication frame reception process of the communication control unit 13a, and stores the data 5e in the received data memory 27a on the writing side. The counter value 5f / 5g is copied.

The reception data switching unit 25a reads the data in the reception-side reception data memory 27a at a constant cycle regardless of the copy process of the data monitoring control unit 21a, and refers to the reception map 29a to perform cyclic communication in the continuous address area. When all the counter values 5f / 5g in the data match, the surface of the reception data memory 26a / 27a is switched.
When the processor 14a makes a read request to the reception data memory 26a on the reading side via the processor control unit 15a, the processor 14a can always read data ensuring simultaneity in units of cyclic communication data registered in the reception map 29a.
By this cyclic communication frame reception process, simultaneity can be ensured in units of cyclic communication data.

Next, transmission of a cyclic communication frame from the terminal A1 will be described.
The processor 14a can always make a write request for cyclic communication data to the transmission data memory 23a on the writing side via the processor control unit 15a. The processor control unit 15a writes the cyclic communication data to the transmission data memory at once.
The transmission data switching unit 22a monitors the write request of the processor control unit 15a, detects that all the continuous addresses indicated by the offset 5c and the size 5d of the transmission map 28a have been written, and then transmits the transmission data memory 23a / Switch the surface of 24a.
The data monitoring control unit 21a reads the transmission data memory 24a on the reading side at a fixed period unrelated to the cyclic communication data writing process of the processor control unit 15a, and sends it to the cyclic memory 11a via the memory control unit 12a. The data 5e in the cyclic communication frame is copied.

Next, the communication control unit 13a reads the cyclic communication data in the cyclic memory 11a via the memory control unit 12a in accordance with the cyclic transmission cycle of its own terminal, forms a cyclic communication frame, and sends it to the network 4 To do.
At this time, the communication control unit 13a places the counter value 5f / 5g to be added for each cyclic transmission cycle in the cyclic communication frame. By such surface switching of the transmission data memory 23a / 24a, it becomes possible to transmit data ensuring synchronization from the own terminal in units of cyclic communication data.

Next, the timing of reading the received data in the cyclic memory 11a will be described in more detail with reference to FIG.
Since it takes time to store the received data of the plurality of cyclic communication frames (data # 1 to data # 3 in FIG. 9) in the cyclic memory 11a, the data monitoring control unit 21a performs cyclic processing at a constant cycle. Depending on the timing of reading data from the memory 11a, cyclic communication data in which old data (third time in FIG. 9) and new data (fourth time in FIG. 9) are mixed may be read.
In FIG. 9, cyclic communication data in which old and new data are mixed from the time when the fourth data # 1 is written to the write side received data memory 27a is displayed. However, when the data is mixed, the received data switching unit 25a receives the received data memory 26a. Since the / 27a plane is not switched, the cyclic communication data that the processor 14a reads from the reception data memory 26a on the reading side remains the third old data. Therefore, data simultaneity can be ensured.

The reception data switching unit 25a reads the data in the reception-side reception data memory 27a at a fixed period, and when the counter values 5f / 5g all become the same value based on the offset 5c and the size 5d registered in the reception map 29a. The reception data memory 26a / 27a is switched (in FIG. 9, the data is switched from the second to the third data), but when the counter values 5f / 5g do not all become the same value, the reception data memory 26a / 27a Avoid switching faces.
Note that the reception data switching unit 25a does not switch the surface of the reception data memory 26a / 27a while the processor 14a is reading out the reception data memory on the reading side.
For this reason, when the processor 14a makes a read request to the reception data memory 26a on the reading side via the processor control unit 15a, the processor 14a can always read data ensuring simultaneity in units of cyclic communication data registered in the reception map 29a. it can.

According to the first embodiment, with the above configuration, new and old data are not mixed when the processor 14a reads continuous addresses of received data, so that synchronization is always ensured regardless of the timing at which received data is read. become able to.
In addition, since the configuration for ensuring the simultaneity of the large-volume data transmitted and received by a plurality of cyclic communication frames is provided separately, it is possible to reduce the load on the processor processing.
Further, the processor performance can be improved without stopping the processor by reading / writing cyclic communication data.
In addition, since the simultaneity of large-capacity data is ensured by a configuration different from the processor, application development on the processor can be simplified, and the design quality and performance can be improved.

Embodiment 2. FIG.
FIG. 10 is a block diagram showing the inside of the terminal of the cyclic communication system according to the second embodiment of the present invention.
FIG. 10 shows the configuration of the terminal A1, and 1, 11a to 15a, 21a, 24a to 27a, and 29a are the same as those in FIG. In FIG. 10, between the processor control unit 15a and the data monitoring control unit 21a, a copy request flag 31a (first flag) indicating the presence / absence of a copy request of the processor control unit 15a, and copying by the data monitoring control unit 21a are performed. A copy completion flag 32a (second flag) indicating whether or not the processing has been completed is provided.
In FIG. 10, the configuration (data alignment unit) for guaranteeing data simultaneity includes a data monitoring control unit 21a, a transmission data memory 24a, a copy request flag 31a (first flag), and a copy completion flag 32a (second ), A reception data switching unit 25a, a reception data memory 26a, a reception data memory 27a, and a reception map 29a.

  In the second embodiment, the processor control unit 15a can directly write the cyclic communication data to the transmission data memory 24a, and when the processor 14a writes all the cyclic communication data, the data monitoring control unit 21a is cyclic. A copy request flag 31a indicating that a copy request is made is set in the memory 11a. When the data monitoring control unit 21a completes the copy, a copy completion flag 32a is set to notify the processor 14a of the copy completion.

Next, with reference to FIG. 11, focusing on the copy request flag 31a and the copy completion flag 32a, writing to the cyclic memory 11a in units of cyclic communication data by the processor 14a will be described.
In the transmission data write flow, the processor 14a refers to the copy completion flag 32a before writing the transmission data (step S1), waits until the previous copy operation is completed, and then sets the copy request flag 31a to “no request”. (Step S2). Then, the transmission data is written in the transmission data memory 24a in units of cyclic communication data (step S3). When all address areas are written, data simultaneity can be secured. Therefore, by setting the copy request flag 31a to “Requested” (step S4), the data monitoring control unit 21a cyclically transmits data from the transmission data memory 24a. The transmission data is copied to the memory 11a. When copying is completed, the copy completion flag 32a is completed.

  According to the second embodiment, this eliminates the processing time of a certain period during which the data monitoring control unit 21a has updated the transmission data, speeds up the cyclic communication, and combines the transmission data memory into one. Therefore, the memory size can be reduced.

Embodiment 3 FIG.
FIG. 12 is a block diagram showing the inside of the terminal of the cyclic communication system according to the third embodiment of the present invention.
In FIG. 12, the configuration of the terminal A1 is shown, and 1, 11a to 15a, 21a, 24a, 26a, 27a, 29a, 31a, and 32a are the same as those in FIG. In FIG. 12, a transmission data memory 24a, a reception data memory 26a / 27a, and a reception map 29a are provided in the main memory 41a used by the processor 14a when executing an instruction.

In the third embodiment, as compared with the second embodiment, the processing of the reception data switching unit 25a is moved to the processor 14a, and the transmission data memory 24a, the reception data memory 26a / 27a, and the reception map 29a are executed by the processor 14a. The main memory 41a is sometimes used.
The data monitoring controller 21a makes a copy between the cyclic memory 11a and the main memory 41a, thereby eliminating the dedicated memory having the transmission data memory 24a, the reception data memory 26a / 27a, and the reception map 29a.
The processing flow of the third embodiment is the same as that of the second embodiment, but causes the processor 14a to perform the process of the reception data switching unit 25a.

  According to the third embodiment, this makes it possible to reduce hardware costs due to memory size reduction.

Embodiment 4 FIG.
FIG. 13 is a block diagram showing the inside of the terminal of the cyclic communication system according to the fourth embodiment of the present invention.
In FIG. 13, the configuration of the terminal A1 is shown, and 1, 11a to 15a and 21a to 29a are the same as those in FIG. In FIG. 13, retransmission request information 51 a is information for a retransmission request storing the node ID that has transmitted the discarded cyclic communication frame, which is notified to the communication control unit 13 a by the reception data switching unit 25 a.

FIG. 14 is a diagram showing a retransmission request frame format of the cyclic communication system according to the fourth embodiment of the present invention.
In FIG. 14, the structure of retransmission request frame 4005 is shown. 5a is the same as that in FIG. The retransmission request frame 4005 in FIG. 14 has fields of a node ID 5a and retransmission request information 5k that stores the node ID that transmitted the discarded cyclic communication frame as the retransmission request information.

In the fourth embodiment, the configuration shown in FIG. 5 of the first embodiment is configured such that a retransmission request can be made for received data.
When the received data switching unit 25a refers to the counter value 5f / 5g and the cyclic communication frame is discarded, the communication control unit 13a transmits the retransmission request information 51a storing the node ID that has transmitted the discarded cyclic communication frame. The communication control unit 13a that has received the request generates a retransmission request frame in which the node ID that has transmitted the discarded cyclic communication frame is registered and immediately transmits the frame.
The terminal that has received the retransmission request frame immediately retransmits all the cyclic communication frames of the cyclic communication data, so that the communication delay time can be shortened even in a network abnormal state in which frame discard frequently occurs. .

  FIG. 14 shows a format 4005 of a retransmission request frame in which the node ID that has transmitted the discarded cyclic communication frame is registered. Compared with the conventional reception frame 5, the node ID other than the destination node ID 5a is deleted, and the node ID that has transmitted the discarded cyclic communication frame as retransmission request information is registered. If the ID matches the ID, all communication frames of the cyclic communication data are immediately transmitted regardless of the transmission cycle of the ID.

Next, with reference to FIG. 15, the timing for reading the received data of the cyclic memory 11a in the fourth embodiment will be described.
Compared to the timing chart of FIG. 9, the communication control unit 13a indicates that the communication frame (data # 2) other than the first (data # 1) and the last (data # 3) has been discarded, and therefore data # 2 Since the old data (third time) cannot be updated to the new data (fourth time), the received data switching unit 25a makes the data # 1 and data # 3 new data, only the data # 2 becomes old data, and the data # 2 It detects that the cyclic communication frame is discarded.
When detected, the retransmission request frame 4005 is used to retransmit the discarded cyclic communication frame, so that the communication delay time can be shortened even in a network abnormal state in which frame discard frequently occurs.

  According to the fourth embodiment, the terminal that has received the retransmission request frame immediately retransmits all the cyclic communication frames of the cyclic communication data, so that the communication delay time can be maintained even in a network abnormal state in which frame discard frequently occurs. Can be shortened.

Embodiment 5 FIG.
FIG. 16 is a block diagram showing the inside of the terminal of the cyclic communication system according to the fifth embodiment of the present invention.
In FIG. 16, the configuration of the terminal A1 is shown, and 1, 11a to 15a and 21a to 29a are the same as those in FIG. In FIG. 16, the contents of retransmission request information 52a are increased from retransmission request information 51a in FIG.

FIG. 17 is a diagram showing a retransmission request frame format of the cyclic communication system according to the fifth embodiment of the present invention.
In FIG. 17, a retransmission request frame 5005 has fields of a node ID 5a and retransmission request information 5k, and the retransmission request information 5k includes the node ID that transmitted the discard frame, the block number, offset, and size of the discard frame. Storing.

In the fifth embodiment, the contents of the retransmission request frame are enriched.
The information stored in the retransmission request information 52a notified by the reception data switching unit 25a to the communication control unit 13a is specified not only for the node ID that transmitted the discarded cyclic communication frame but also for the cyclic communication data and the cyclic communication frame. The block NO, offset and size in the discarded cyclic communication frame are also stored so that they can be done.
As a result, the retransmitting terminal can retransmit only the discarded cyclic communication data and cyclic communication frames.

FIG. 17 shows the format of the retransmission request frame 5005 in which the node ID that transmitted the discarded cyclic communication frame and the block number, offset, and size in the cyclic communication frame are also registered.
Compared with the retransmission request frame of the fourth embodiment, by registering the block number, offset, and size in the cyclic communication frame, the retransmitting terminal can specify the discarded cyclic communication data and the cyclic communication frame. Therefore, only the necessary minimum cyclic communication frame can be retransmitted.

  According to the fifth embodiment, the retransmitting terminal can retransmit only the discarded cyclic communication data and the cyclic communication frame, and not only shortens the communication delay time even in a network abnormal state where frame discard frequently occurs. Thus, the increase in the number of communication frames accompanying retransmission can be reduced.

Embodiment 6 FIG.
The configuration of the terminal of the cyclic communication system according to the sixth embodiment is the same as that in FIG. In the sixth embodiment, the structure of a frame transmitted for a retransmission request from the communication control unit 13a is different from that in the fifth embodiment.

FIG. 18 is a diagram showing a cyclic communication frame format with a retransmission request in the cyclic communication system according to the sixth embodiment of the present invention.
18, 5a to 5h are the same as those in FIG. 6, and 5k are the same as those in FIG.

In the sixth embodiment, the communication control unit 13a that has received the notification of the retransmission request information 52a sends a cyclic communication frame 6005 in which the retransmission request information 52a is stored instead of the retransmission request frame shown in FIG. 17 at a normal cycle. Like to do.
As a result, not only can the communication delay time be shortened even in a network abnormal state in which frame discard frequently occurs, but also the increase in the number of communication frames accompanying a retransmission request can be reduced.

  FIG. 18 shows the format of the cyclic communication frame 6005 in which the retransmission request information 52a is also registered. Compared with the reception frame 5 of the first embodiment (FIG. 6), the field of the retransmission request information 5k storing the information of the retransmission request information 52a is provided in the cyclic communication frame. Since discarded cyclic communication data and cyclic communication frames can be specified, an increase in the number of frames can be further reduced.

  According to the sixth embodiment, since retransmission request information is transmitted by a cyclic communication frame, the receiving terminal can identify discarded cyclic communication data and cyclic communication frames, and the number of frames on the network. Can be reduced.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

1 terminal A, 2 terminal B, 3 terminal C, 4 network, 5 received frame,
11a cyclic memory, 11b cyclic memory,
11c cyclic memory, 12a memory control unit, 13a communication control unit,
14a processor, 15a processor control unit, 21a data monitoring control unit,
22a transmission data switching unit, 23a transmission data memory, 24a transmission data memory,
25a received data switching unit, 26a received data memory, 27a received data memory,
28a transmission map, 29a reception map, 31a copy request flag,
32a copy completion flag, 41a main memory, 51a retransmission request information,
52a retransmission request information, 4005 retransmission request frame, 5005 retransmission request frame,
6005 Cyclic communication frame.

Claims (9)

A cyclic communication system in which a plurality of terminals perform cyclic communication via a network,
Each of the above terminals
A cyclic memory for storing data used for the cyclic communication,
A memory control unit for controlling reading and writing of data with respect to the cyclic memory;
A communication control unit for transmitting communication frames via the network using data in the cyclic memory and storing data in the communication frames received via the network in the cyclic memory;
A processor for writing cyclic communication data transmitted in one cyclic communication cycle and reading cyclic communication data received in one cyclic communication cycle to the cyclic memory,
And a data alignment unit for ensuring the simultaneity of each data when transmitting and receiving the cyclic communication data divided into a plurality by communication frames,
A counter value that is counted for each cyclic communication cycle is added to each of the divided data of the cyclic communication data,
The cyclic communication system, wherein the data alignment unit secures simultaneity of each divided data of the cyclic communication data using the counter value. The data alignment unit
A read side and a write side are switched to each other, and from the read side, a pair of received data memories from which data received by the cyclic communication is read by the processor,
A data monitoring control unit for writing the data of the cyclic memory received by the cyclic communication at a fixed period to the write side of the reception data memory via the memory control unit;
A reception data switching unit that switches between the writing side and the reading side of the pair of reception data memories when the simultaneity of the data written on the writing side of the reception data memory is confirmed using the counter value; The cyclic communication system according to claim 1.   3. The cyclic communication system according to claim 2, wherein the pair of reception data memories are arranged on a main memory used by the processor when executing instructions, and the reception data switching unit is substituted for the processor. The data alignment unit
A read side and a write side are switched to each other, and on the write side, a pair of transmission data memories in which cyclic communication data to be transmitted is written by the processor,
A transmission data switching unit for detecting that writing to the writing side of the transmission data memory by the processor is completed, and switching between the writing side and the reading side of the pair of transmission data memories;
3. The data monitoring control unit writes the cyclic communication data on the reading side of the transmission data memory into the cyclic memory via the memory control unit at a constant cycle. 3. The cyclic communication system according to 3. The data alignment unit
A transmission data memory in which cyclic communication data to be transmitted is written by the processor;
A first flag indicating that the cyclic communication data has been written to the transmission data memory by the processor;
A second flag indicating that the cyclic communication data of the transmission data memory has been written to the cyclic memory;
The data monitoring controller refers to the first flag, writes the cyclic communication data of the transmission data memory to the cyclic memory via the memory controller at regular intervals,
4. The cyclic communication system according to claim 2, wherein the processor performs writing to the transmission data memory with reference to the second flag.   6. The cyclic communication system according to claim 5, wherein the transmission data memory is arranged on a main memory used by the processor when executing instructions.   When the received data switching unit detects that any of the divided data of the cyclic communication data is discarded due to an error, the received data switching unit retransmits the terminal ID that transmitted the discarded data. The request information is notified to the communication control unit, and the communication control unit receiving the request information forms a retransmission request frame storing the terminal ID and transmits the frame to the network. The cyclic communication system according to claim 6.   8. The cyclic communication system according to claim 7, wherein the retransmission request information and the retransmission request frame include discarded cyclic communication data and information that can identify a communication frame.   When the received data switching unit detects that any of the divided data of the cyclic communication data is discarded due to an error, the received data switching unit and the terminal ID that transmitted the discarded data are also discarded. Retransmission request information including information that can identify the cyclic communication data and the communication frame is notified to the communication control unit, and the communication control unit that receives the notification requests the communication frame of the cyclic communication to be transmitted at a constant cycle. The cyclic communication system according to any one of claims 2 to 6, wherein retransmission request information is stored and transmitted to the network.