JP2015080086A - High resistance circuit using mos transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resistance circuit using MOS transistors which give a resistive element having a stable resistance value irrespective of a voltage difference between terminals.SOLUTION: NMOS transistors M1, M2 are provided between first and second terminals IN, OUT with source terminals connected at a point of contact M and drain terminals connected to the first and second terminals IN, OUT. A gate-source voltage decided by a flow of constant current I1 to an NMOS transistor M3 on one of a differential pair is also applied to the NMOS transistors M1, M2. An NMOS transistor (one of M1, M2) connected to one of the first and second terminals IN, OUT which is a high voltage side functions as a resistive element. Whichever of the first and second terminals IN, OUT has a high voltage value, any one of the NMOS transistors M1, M2 can function as a resistive element to give a resistance value between the first and second terminals IN, OUT.

Description

  The present invention relates to a high resistance circuit using a MOS transistor.

  A MEMS sensor that detects a change in external force such as acceleration based on a change in capacitance value has been proposed (Non-Patent Document 1, etc.). In order to extract a change in capacitance value obtained by such a MEMS sensor as a signal, a so-called CV conversion circuit that converts the change in capacitance value into a change in voltage value and outputs the change is used.

As shown in FIG. 2, the CV conversion circuit includes a differential input terminal including non-inverting and inverting input terminals to which variable capacitance elements CDP and CDN included in the MEMS sensor are connected, and an inverting and non-inverting output terminal. A so-called fully differential amplifier having a differential output terminal is provided. Feedback capacitance elements Cfp and Cfn are connected between the non-inverting input terminal and the inverting output terminal and between the inverting input terminal and the non-inverting output terminal of the fully differential amplifier. The differential output voltage signals VOP and VON are output from the differential output terminal with a gain set by the capacitance ratio of the variable capacitance elements CDP and CDN and the feedback capacitance elements Cfp and Cfn. As a result, a change in capacitance values of the variable capacitance elements CDP and CDN provided in the MEMS sensor is extracted as a change in voltage value of the differential output voltage signals VOP and VON.

  Here, in the CV conversion circuit, a feedback resistance element is connected between the differential input terminal and the differential output terminal of the fully differential amplifier. This is to bias the virtual ground potential at the differential input terminal of the fully differential amplifier to a predetermined potential. By connecting the feedback resistance element, the voltage value corresponding to the differential output voltage signals VOP and VON is biased to the differential input terminal, and the voltage value of the virtual ground is determined. In this case, the feedback resistance element forms a feedback circuit together with the feedback capacitance elements Cfp and Cfn. This feedback circuit has a high-pass filter characteristic, and has a characteristic that a phase delay occurs in a band below the cutoff frequency. Therefore, it is necessary to increase the resistance value of the feedback resistance element so that a frequency lower than the band of the detection signal output from the MEMS sensor becomes the cutoff frequency. When the cut-off frequency is high, gain reduction and phase shift occur in the response between input and output signals. As a result, the differential output voltage signals VOP and VON are attenuated and the phase is shifted, and the original CV conversion operation may not be performed. PMOS transistors MP1p and MP1n are used to make the feedback resistance element have a sufficiently high resistance value.

Mikko Saukoski, “System and Circuit Design for a Capacitive MEMS Gyroscope”, p. 155-160, [online], 2008/4/18, Helsinki University of Technology, [searched September 4, 2013], Internet <URL: http://lib.tkk.fi/Diss / 2008 / isbn9789512292974 / ＞

  In Non-Patent Document 1, between the non-inverting input terminal and the inverting output terminal of the fully differential amplifier and between the inverting input terminal and the non-inverting output terminal, which are connected by the PMOS transistors MP1p and MP1n, It is not uniquely determined which terminal has a high voltage and which terminal has a low voltage. That is, if the inverting output terminal has a higher voltage than the non-inverting input terminal, the non-inverting output terminal has a lower voltage than the inverting input terminal, and the inverting output terminal has a lower voltage than the non-inverting input terminal. In the case of voltage, the non-inverting output terminal is higher than the inverting input terminal. Therefore, the source terminals of the PMOS transistors MP1p and MP1n connected to the differential input terminal of the fully differential amplifier and the drain terminals of the PMOS transistors MP1p and MP1n connected to the differential output terminal of the fully differential amplifier are: In some cases, the voltage may be high. In the configuration of FIG. 2, the resistance values of the PMOS transistors MP1p and MP1n differ depending on the terminal that becomes a high voltage. In FIG. 2, the bulk of the PMOS transistors MP1p and MP1n is connected to the source terminal, and the source terminal is connected to the differential input terminal. In this connection, a differential output terminal having a voltage relationship opposite to that in the case where the differential output terminal side is a low voltage (the differential input terminal side is a high voltage) and current flows from the differential input terminal toward the PMOS transistors MP1p and MP1n. When the current flows from the PMOS transistors MP1p and MP1n toward the differential input terminal when the side is a high voltage (the differential input terminal side is a low voltage), the resistance value becomes smaller when compared at the same current value. The decrease in resistance value in response to the increase is also abrupt.

When the bulk of the PMOS transistors MP1p and MP1n is connected to a differential output voltage signal or a power supply voltage, the differential input terminal side is a high voltage (the differential output terminal side is a low voltage) and the differential input terminal is connected to the PMOS transistor MP1p When the current flows toward the source terminal of MP1n, the current flowing into the source terminal flows through the bulk and does not flow into the drain terminal. A current cannot flow between the source and drain terminals of the PMOS transistors MP1p and MP1n, so that it does not function as a feedback resistor. For this reason, the virtual ground potential of the differential input terminal of the fully-differential amplifier cannot be biased as a feedback resistance element.

In the PMOS transistors MP1p and MP1n described in Non-Patent Document 1, the magnitude of the voltage value applied to the bulk and the voltage value between the differential input terminal and the differential output terminal of the fully-differential amplifier is determined. The resistance values are greatly different, and a stable operation as a CV conversion circuit cannot be achieved.

  The technology disclosed in the present application has been proposed in view of the above problems, and provides a resistance circuit using a MOS transistor that provides a resistance element having a stable resistance value regardless of a voltage difference between terminals. With the goal.

  The resistance circuit according to the technique disclosed in the present application is a resistance circuit connected as a resistance element between a first terminal and a second terminal. The first to fifth MOS transistors and a first current source are provided. In the first and second MOS transistors, the source terminals connected to the bulk are connected to each other, and the drain terminals are connected to the first and second terminals, respectively. The third MOS transistor has a drain terminal and a gate terminal connected to the gate terminals of the first and second MOS transistors, and a source terminal connected to the bulk. The fourth MOS transistor has a drain terminal and a gate terminal connected to the source terminal of the third MOS transistor. The fifth MOS transistor has a gate terminal connected to the source terminals of the first and second MOS transistors, and a source terminal connected to the source terminal of the fourth MOS transistor. The first current source is connected to the drain terminal of the third MOS transistor.

  In the resistance circuit according to the technique disclosed in the present application, the first and second MOS transistors function as a resistance element between the first and second terminals. The source terminals are commonly connected, and the drain terminals of the first and second MOS transistors are connected to the first and second terminals, respectively. If the first and second MOS transistors are NMOS transistors, one of the first and second MOS transistors connected to the high voltage side terminal of the first and second terminals functions as a resistance element. . At this time, the other of the first and second MOS transistors has a PN junction (diode) formed between the bulk (P-type semiconductor) connected to the source terminal and the drain terminal (N-type semiconductor). Current flows through. For this reason, the current that flows from the source terminal to the drain terminal becomes a current that forward biases the diode, and this transistor does not function as a resistance element. If the first and second MOS transistors are PMOS transistors, one of the first and second MOS transistors connected to the low voltage value side terminal of the first and second terminals functions as a resistance element. At this time, the other of the first and second MOS transistors has a PN junction (diode) formed between the bulk (N-type semiconductor) connected to the source terminal and the drain terminal (P-type semiconductor). Current flows through. For this reason, the current that flows from the source terminal to the drain terminal becomes a current that forward biases the diode, and this transistor does not function as a resistance element. Whichever of the first and second terminals has a high voltage value, one of the first and second MOS transistors functions as a resistance element. A resistance value can be given between the terminals with respect to a voltage difference in any direction between the first and second terminals.

  Further, the fourth and fifth MOS transistors constitute a differential pair. For this reason, if an equivalent current flows through each of the fourth and fifth MOS transistors, the voltages applied to the gate terminals of both transistors can be assumed to be substantially the same potential. As a result, the voltage at the source terminal of the first and second MOS transistors and the voltage at the source terminal of the third MOS transistor can be set to the same potential. The differential pair composed of the fourth and fifth MOS transistors constitutes a feedback circuit in which the voltage at the source terminal of the first and second MOS transistors is the voltage at the source terminal of the third MOS transistor.

  In addition to the voltage at the source terminal of the first and second MOS transistors being equal to the voltage at the source terminal of the third MOS transistor, the gate terminals of the first and second MOS transistors and the third MOS transistor are connected in common. Therefore, each gate terminal has the same potential. Therefore, the voltage between the gate and source terminals of the first and second MOS transistors is the same as the voltage between the gate and source terminals of the third MOS transistor. The voltage between the gate and source terminals is determined by the current supplied by the first current source connected to the drain terminal in the third MOS transistor operating in the saturation region where the drain terminal and the gate terminal are connected. If the current supplied from the first current source is limited, a voltage corresponding to the limited current value is applied between the gate and source terminals of the third MOS transistor, and the voltage is applied to the gate and source terminals of the first and second MOS transistors. It becomes the voltage between. In addition to the voltage between the gate and source terminals, the first and second MOS transistors have a β value determined in proportion to the ratio (W / L) of the gate width (W) to the gate length (L). Therefore, by supplying a limited current from the first current source and selecting the β value of the first and second MOS transistors, the current flowing in the first and second MOS transistors is limited and drained. -The resistance value of the source terminal can be set to a large value. Specifically, a high resistance can be obtained by limiting the current supplied by the first current source and increasing the gate length (L) of the first and second MOS transistors.

  In the resistance circuit disclosed in the present application, the first and second MOS transistors may be configured such that the channel length and the channel width are the same between the transistors. As a result, the β values in the MOS transistor characteristics can be made equal between the first MOS transistor and the second MOS transistor. Thereby, when the first terminal is at a high voltage compared to the second terminal, the resistance value by the first MOS transistor that functions as a resistance element, and vice versa, the second terminal is at a high voltage. In some cases, the resistance value of the second MOS transistor functioning as a resistance element is equivalent to the resistance value. Regardless of the direction of the voltage difference between the first terminal and the second terminal, the terminals can be connected with the same resistance value.

  In the resistance circuit disclosed in the present application, the first and second MOS transistors may be configured to have a channel length longer than that of the third MOS transistor. Thereby, the first and second MOS transistors can have a characteristic having a smaller β value than the third MOS transistor, and can have a large resistance value.

  In the resistor circuit disclosed in the present application, the fourth and fifth MOS transistors may be configured with the same channel length and channel width. Thereby, in the differential pair constituted by the fourth and fifth MOS transistors, the voltages at the gate terminals of both transistors can be made to coincide with each other with high accuracy. The conduction state of the first and second MOS transistors and the conduction state of the third MOS transistor can be made to coincide with each other with high accuracy, and the resistance value between the first and second terminals can be adjusted with high accuracy.

  The resistor circuit disclosed in the present application further includes a second current source connected to the source terminals of the fourth and fifth MOS transistors, and the second current source has a current value twice that of the first current source. You may comprise as. As a result, in the differential pair constituted by the fourth and fifth MOS transistors, the current flowing through the fourth MOS transistor and the current flowing through the fifth MOS transistor can be matched, and the voltages at the gate terminals of both transistors can be accurately matched. Can be made. The conduction state of the first and second MOS transistors and the conduction state of the third MOS transistor can be made to coincide with each other with high accuracy, and the resistance value between the first and second terminals can be adjusted with high accuracy.

  According to the resistance element according to the technique disclosed in the present application, the resistance value between the terminals can be maintained at a high resistance value between the first and second terminals regardless of which terminal is at a high voltage. it can.

It is a circuit diagram showing an example of a resistance circuit using a MOS transistor of an embodiment. It is a CV conversion circuit using an example of a resistance circuit using a MOS transistor of the background art.

  FIG. 1 is a resistor circuit 1 according to an embodiment. An NMOS transistor is used. The first terminal IN and the second terminal OUT are connected with high resistance. Here, the first terminal IN and the second terminal OUT correspond to, for example, the differential input terminals INP and INN and the differential output terminals VON and VOP of the CV conversion circuit (FIG. 2) in the background art. That is, the resistor circuit 1 is a resistor circuit that substitutes for the PMOS transistors MP1p and MP1n.

  An NMOS transistor M1 whose drain terminal is connected to the first terminal IN and an NMOS transistor M2 whose drain terminal is connected to the second terminal OUT are connected in series between the first terminal IN and the second terminal OUT. Has been. The source terminals of the NMOS transistor M1 and the NMOS transistor M2 are connected by a contact M. The channel lengths (L1, L2) are the same length (L1 = L2 = L), and the channel widths (W1, W2) are also the same length.

  The drain terminal of the NMOS transistor M3 is connected to the power supply voltage AVDD via the current source IS1. A constant current I1 is supplied from the current source IS1 to the drain terminal of the NMOS transistor M3. The drain terminal of the NMOS transistor M3 is connected to its own gate terminal and the gate terminals of the NMOS transistor M1 and the NMOS transistor M2. The source terminal of the NMOS transistor M3 is connected to the bulk of the NMOS transistor M3. The channel length (L3) of the NMOS transistor M3 is shorter than the channel lengths (L1 = L2 = L) of the NMOS transistors M1 and M2 (L3 <L).

  The NMOS transistor M4 and the NMOS transistor M5 have the same channel length (L4 = L5) and channel width (W), and their source terminals are both connected to the contact n2. The NMOS transistors M4 and M5 operate in the saturation region and constitute a differential pair. The drain terminal of the NMOS transistor M4 is connected to the source terminal of the NMOS transistor M3. It is also connected to its own gate terminal. The drain terminal of the NMOS transistor M5 is connected to the power supply voltage AVDD. The gate terminal of the NMOS transistor M5 is connected to the contact M. A current source IS2 is connected between a contact point n2 to which the source terminals of the NMOS transistors M4 and M5 are connected and the ground potential. A constant current I2 from the contact point n2 flows into the current source IS2. The constant current I2 has a current value twice that of the constant current I1.

  Here, if the channel length (L3) of the NMOS transistor M3 is the same as the channel length (L4 = L5) of the NMOS transistors M4 and 5 (L3 = L4 = L5), the NMOS transistors M3 to M5 are placed on the silicon chip. Therefore, it is possible to obtain an efficient layout in which the occupied area is suppressed. Further, in the relationship (L3 <L) between the channel length (L1 = L2 = L) of the NMOS transistors M1 and M2 and the channel length (L3) of the NMOS transistor M3, the NMOS is compared with the channel length (L3) of the NMOS transistor M3. The longer the channel length (L1 = L2 = L) of the transistors M1 and M2, the higher the resistance between the first terminal IN and the second terminal OUT.

  Next, the operation of the resistance circuit 1 will be described. The constant current I1 supplied from the current source IS1 flows into the current source IS2 through the NMOS transistors M3 and M4. Here, the constant current I2 of the current source IS2 has a current value twice that of the constant current I1. Therefore, the constant current I1 further flows from the other NMOS transistor M5 of the differential pair into the current source IS2 into which the constant current I1 flows from one NMOS transistor M4 of the differential pair. In other words, the constant current I1 flows through the NMOS transistors M4 and M5 constituting the differential pair. Since the source terminals of the NMOS transistors M4 and M5 constituting the differential pair are connected to the contact point n2 and are common, if the currents flowing through both transistors are both constant current I1, the voltages at the gate terminals of each other are the same voltage. . As a result, the voltage Vn1 (same as the gate voltage of the NMOS transistor M4) of the contact n1 between the drain terminal of the NMOS transistor M4 and the source terminal of the NMOS transistor M3 and the contact between the source terminals of the NMOS transistors M1 and M2 are connected. The voltage VM of M (the same as the gate voltage of the NMOS transistor M5) is the same voltage (Vn1 = VM). The voltage VM at the contact M, which is connected between the source terminals of the NMOS transistors M1 and M2, by the NMOS transistors M4 and M5 and the current source IS2 is changed to the voltage at the contact n1 between the drain terminal of the NMOS transistor M4 and the source terminal of the NMOS transistor M3. A feedback circuit that matches the voltage Vn1 is configured.

As a result, the voltages between the gate and source terminals of the NMOS transistors M1, M2, and M3 become the same voltage. Here, this voltage is determined by the characteristics of the NMOS transistor M3 in accordance with the constant current I1 flowing from the drain terminal of the NMOS transistor M3 operating in the saturation region with the drain and gate terminals connected. That is, the relational expression between the gate-source voltage (VGS (3)) and the drain current (IDS (3) = I1) of the NMOS transistor M3 operating in the saturation region is as the following expression (I).
IDS (3) = I1 = (β3 / 2) · (VGS (3) −VTH) ² (I)

From the formula (I), when the gate-source voltage (VGS (3)) is derived,
VGS (3) = VTH + √ (2I1 / β3) (II)
It is. On the other hand, since the NMOS transistor M1 operates in the linear region, the relational expression between the gate-source voltage (VGS (1)) and the drain current (IDS (1)) is as shown in the following expression (III). Since the characteristics of the NMOS transistor M2 are the same, it is represented by the NMOS transistor M1.
IDS (1) = β1 · (VGS (1) −VTH) · VDS (1) (III)

From the formula (III), when the gate-source voltage (VGS (1)) is derived,
VGS (1) = VTH + IDS (1) / (β1 · VDS (1)) (IV)

Here, since VGS (1) = VGS (3), from Formula (II) and Formula (IV),
√ (2I1 / β3) = IDS (1) / (β1 · VDS (1)),
R (1) = VDS (1) / IDS (1)
= 1 / (β1 · √ (2I1 / β3) (V)
Relationship is found.

  Here, I1 is a current supplied from the current source IS1, and β1 and β3 are β values of the NMOS transistors M1 and M3, respectively. Here, the β value is a characteristic value based on the carrier mobility on the semiconductor device constituting the NMOS transistor, the gate capacitance of the MOS transistor, etc. (W / L) (where L is the gate length, W is the gate length) (Width). Since the former characteristic value is fixed in the semiconductor process, it is (W / L) that can be adjusted in the circuit design. Accordingly, the resistance value R (1) can be increased by setting the constant current I1 of the current source IS1 to a small value and increasing the gate lengths (L1, L2, L3) of the NMOS transistors M1 to M3. Here, since the constant current I1 of the current source IS1 and the β value (β3) of the NMOS transistor M3 are within the square root, in particular, the channel lengths (L1, L2) of the NMOS transistors M1 and M2 are increased to increase the β value ( In order to obtain a high resistance value, it is effective to reduce β1).

  In order to increase the channel length (L1, L2) of the NMOS transistors M1, M2, in addition to increasing the channel length (L1, L2) of the NMOS transistors M1, M2, the NMOS transistors M1, M2 are paired, It is effective to connect a plurality of pairs in series. In this case, the configuration of the NMOS transistors M3 to M5 is also provided for each pair, and the NMOS transistors M1 and M2 of each pair are biased.

  Here, the NMOS transistors M1 to M5 are examples of first to fifth MOS transistors, and the current sources IS1 and IS2 are examples of first and second current sources, respectively.

  As described above in detail, the resistance circuit 1 according to the present embodiment has the NMOS transistors M1 and M2 connected between the first terminal IN and the second terminal OUT, and the source terminals of the resistors 1 and M2 are connected by the contact M. Each drain terminal is connected to the first terminal IN and the second terminal OUT to form a resistance element. As a result, the NMOS transistor (either M1 or M2) connected to the terminal on the high voltage side of the first and second terminals IN and OUT functions as a resistance element. At this time, either the NMOS transistor M1 or M2 is connected via a PN junction (diode) formed between the bulk (P-type semiconductor) connected to the source terminal and the drain terminal (N-type semiconductor). Current flows and does not function as a resistance element. Regardless of which of the first and second terminals IN, OUT is a high voltage terminal, one of the NMOS transistors M1, M2 functions as a resistance element, and the first and second terminals A resistance value can be given between IN and OUT.

  The NMOS transistors M4 and M5 have the same channel length (L) and channel width (W) to form a differential pair. The constant current I2 of the current source IS2 connected to the contact point n2 to which the source terminals of the NMOS transistors M4 and M5 are connected is the constant current I1 of the current source IS1 connected to the drain terminal side of the NMOS transistor M4. The current value is twice that of the current value. For this reason, an equivalent constant current I1 also flows through the NMOS transistor M5. As a result, the voltages applied to the gate terminals of both transistors have the same potential (Vn1 = VM). As a result, the voltages (VM) of the source terminals of the NMOS transistors M1 and M2 and the voltage (Vn1) of the source terminal of the NMOS transistor M3. ) And the same potential. The NMOS transistors M4 and M5 and the current source IS2 constitute a feedback circuit.

  The gate terminals of the NMOS transistors M1, M2 and NMOS transistor M3 are connected in common, and the voltage applied to the gate terminal in addition to the source terminal is also at the same potential. Therefore, the voltage between the gate and source terminals of the NMOS transistors M1 and M2 is the same as the voltage between the gate and source terminals of the NMOS transistor M3. The voltage between the gate and source terminals is determined by a constant current I1 supplied from the current source IS1 connected to the drain terminal in the NMOS transistor M3 operating in the saturation region where the drain terminal and the gate terminal are connected. If the constant current I1 is limited, a voltage corresponding to the limited constant current I1 is applied between the gate and source terminals of the NMOS transistor M3, and this voltage is the voltage between the gate and source terminals of the NMOS transistors M1 and M2. Become. In addition, since the current corresponding to the β value determined in proportion to the ratio (W / L) of the gate length (L) to the gate width (W) flows through the NMOS transistors M1 and M2, the current source IS1 If the constant current I1 to be supplied and the β value of the NMOS transistors M1 and M2 are selected, the current flowing through the NMOS transistors M1 and M2 is controlled to set the resistance value between the first and second terminals IN and OUT to a large value. can do. Specifically, a high resistance can be obtained by limiting the constant current I1 supplied from the current source IS1 and increasing the gate lengths (L1, L2) of the NMOS transistors M1, M2. The resistance values of the NMOS transistors M1 and M2 are the resistance values represented by the formula (V).

  In the resistance circuit 1, the NMOS transistors M1 and M2 preferably have the same channel length (L1, L2) and channel width (W1, W2) between the transistors. Thereby, the β values in the MOS transistor characteristics can be made equal between the NMOS transistor M1 and the NMOS transistor M2. As a result, the resistance value of the NMOS transistor M1 that functions as a resistance element when the first terminal IN is at a higher voltage than the second terminal OUT and the second terminal OUT compared to the opposite first terminal IN. The resistance value by the NMOS transistor M2 functioning as a resistance element when is high is equal to the resistance value. Regardless of the voltage level between the first terminal IN and the second terminal OUT, the terminals can be connected with the same resistance value.

  In the resistance circuit 1, the NMOS transistors M1 and M2 have a channel length longer than that of the NMOS transistor M3 (L3 <L1 = L2 = L). Thereby, the NMOS transistors M1 and M2 can have a characteristic having a smaller β value than the NMOS transistor M3, and can have a large resistance value.

  In the resistance circuit 1, the NMOS transistors M4 and M5 have the same channel length and channel width. Thereby, a differential pair with a small offset voltage can be configured. The voltages at the gate terminals of both transistors can be made to coincide with each other with high precision (Vn1 = VM). The conduction state of the NMOS transistors M1 and M2 and the conduction state of the NMOS transistor M3 can be matched with high accuracy, and the resistance value between the first and second terminals IN and OUT can be adjusted with high accuracy.

  In the resistor circuit 1, the constant current I2 of the current source IS2 connected to the contact point n2 to which the source terminals of the NMOS transistors M4 and M5 are connected has a current value twice that of the constant current I1 of the current source IS1. doing. As a result, the flowing current can be made to coincide between the NMOS transistor M4 and the NMOS transistor M5 constituting the differential pair. The voltages at the gate terminals of both transistors can be made to coincide with each other with high precision (Vn1 = VM). The conduction state of the NMOS transistors M1 and M2 and the conduction state of the NMOS transistor M3 can be matched with high accuracy, and the resistance value between the first and second terminals IN and OUT can be adjusted with high accuracy.

  The resistor circuit 1 according to the embodiment can connect a high resistance between the terminals regardless of the voltage levels of the first and second terminals IN and OUT. Therefore, it can be used also when the voltage value is reversed appropriately between the first and second terminals IN and OUT. For example, it can be used as a feedback resistor for a fully differential amplifier. In a CV conversion circuit that converts a detection value due to a change in capacitance into a voltage value, such as an acceleration sensor that outputs a change in capacitance value, it is convenient to use as a feedback resistor that connects between differential input / output terminals of a fully differential amplifier. It is.

  Since the resistance element is a resistance element utilizing the linear operation region of the NMOS transistors M1 and M2, a high resistance with excellent resistance linearity in a wide voltage difference range between the first and second terminals IN and OUT. Can be realized.

Needless to say, the present invention is not limited to the above-described embodiment, and various modifications and changes can be made without departing from the spirit of the present invention.
For example, the resistor circuit 1 according to the embodiment has been described by way of example with an NMOS transistor, but the present application is not limited to this. A resistance circuit having the same configuration can also be configured by a PMOS transistor.
In the embodiment, the voltage VM of the contact M to which the source terminals of the NMOS transistors M1 and M2 are connected and the voltage Vn1 of the contact n1 between the drain terminal of the NMOS transistor M4 and the source terminal of the NMOS transistor M3 are the same voltage. In order to achieve this, the case of using a differential pair composed of NMOS transistors M4 and M5 and a current source IS2 has been described. However, the present application is not limited to this. The circuit configuration is not limited to the configuration of the embodiment as long as it includes a configuration in which the constant current I1 is supplied to the NMOS transistor M3.

DESCRIPTION OF SYMBOLS 1 Resistance circuit AVDD Power supply voltage I1, I2 Constant current IN 1st terminal IS1, IS2 Current source M1-M5 NMOS transistor OUT 2nd terminal

Claims (5)

A resistance circuit connected as a resistance element between a first terminal and a second terminal,
First and second MOS transistors having source terminals connected to the bulk connected to each other and drain terminals connected to each of the first and second terminals;
A third MOS transistor having a drain terminal and a gate terminal connected to the gate terminals of the first and second MOS transistors and a source terminal connected in bulk;
A fourth MOS transistor having a drain terminal and a gate terminal connected to a source terminal of the third MOS transistor;
A fifth MOS transistor having a gate terminal connected to a source terminal of the first and second MOS transistors and a source terminal connected to a source terminal of the fourth MOS transistor;
A resistance circuit comprising: a first current source connected to a drain terminal of the third MOS transistor.   2. The resistance circuit according to claim 1, wherein the first and second MOS transistors have the same channel length and channel width.   3. The resistance circuit according to claim 1, wherein the first and second MOS transistors have a channel length longer than that of the third MOS transistor.   4. The resistance circuit according to claim 1, wherein the fourth and fifth MOS transistors have the same channel length and channel width. 5. A second current source connected to the source terminals of the fourth and fifth MOS transistors;
5. The resistance circuit according to claim 1, wherein the second current source has a current value that is twice that of the first current source. 6.

Images