JP2015079874A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- JP2015079874A JP2015079874A JP2013216505A JP2013216505A JP2015079874A JP 2015079874 A JP2015079874 A JP 2015079874A JP 2013216505 A JP2013216505 A JP 2013216505A JP 2013216505 A JP2013216505 A JP 2013216505A JP 2015079874 A JP2015079874 A JP 2015079874A
- Authority
- JP
- Japan
- Prior art keywords
- coating material
- mpa
- substrate
- semiconductor chip
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 239000000463 material Substances 0.000 claims abstract description 99
- 239000011248 coating agent Substances 0.000 claims abstract description 93
- 238000000576 coating method Methods 0.000 claims abstract description 93
- 229920005989 resin Polymers 0.000 claims abstract description 29
- 239000011347 resin Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims description 34
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 229920002614 Polyether block amide Polymers 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 239000004962 Polyamide-imide Substances 0.000 claims description 2
- 239000004697 Polyetherimide Substances 0.000 claims description 2
- 229920002312 polyamide-imide Polymers 0.000 claims description 2
- 229920001601 polyetherimide Polymers 0.000 claims description 2
- 230000009545 invasion Effects 0.000 abstract 1
- 238000005187 foaming Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 8
- 239000010949 copper Substances 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000007789 sealing Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910000881 Cu alloy Inorganic materials 0.000 description 4
- 239000004033 plastic Substances 0.000 description 4
- 229920003023 plastic Polymers 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000005489 elastic deformation Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 239000004734 Polyphenylene sulfide Substances 0.000 description 2
- 229920000122 acrylonitrile butadiene styrene Polymers 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 230000009477 glass transition Effects 0.000 description 2
- 229920001707 polybutylene terephthalate Polymers 0.000 description 2
- 229920000069 polyphenylene sulfide Polymers 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XECAHXYUAAWDEL-UHFFFAOYSA-N acrylonitrile butadiene styrene Chemical compound C=CC=C.C=CC#N.C=CC1=CC=CC=C1 XECAHXYUAAWDEL-UHFFFAOYSA-N 0.000 description 1
- 239000004676 acrylonitrile butadiene styrene Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920006122 polyamide resin Polymers 0.000 description 1
- -1 polybutylene terephthalate Polymers 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229920002803 thermoplastic polyurethane Polymers 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
本発明は、半導体装置に関し、特に樹脂封止型の半導体装置に関する。 The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device.
樹脂封止型半導体装置の信頼性、特に半導体チップに対する耐湿性の向上を図るため、モールド樹脂で成形する前の段階で、基板上にマウントされた半導体チップの表面を耐湿性の高いコーティング材（ジャンクション・コーティング・レジン）で覆うことが実施されている（例えば特許文献１参照）。 In order to improve the reliability of the resin-encapsulated semiconductor device, especially the moisture resistance of the semiconductor chip, the surface of the semiconductor chip mounted on the substrate is coated with a high moisture resistance before the molding with the mold resin ( Covering with a junction coating resin) (see, for example, Patent Document 1).
このコーティング材は、溶剤を加えて流動性を付与した状態で、ディスペンサにより半導体チップの上にポッティングされ、乾燥させて硬化させることにより、半導体チップの表面全体がコーティングされるようになっている。 The coating material is potted on the semiconductor chip by a dispenser in a state where fluidity is imparted by adding a solvent, and the entire surface of the semiconductor chip is coated by drying and curing.
近年、自動車分野などで、例えばエンジンルームといった高湿・高温である過酷な環境下でも信頼性の高い樹脂封止型の半導体装置を用いる需要が高まってきていることから、前述のコーティング材にもより高い高湿・高温特性が求められるようになってきている。一方で従来のコーティング材を高湿・高温下に適用した場合、以下のような課題が発生することが本発明者の鋭意研究により明らかとなった。模式図を図７に示す。 In recent years, the demand for using highly reliable resin-encapsulated semiconductor devices in harsh environments with high humidity and high temperature, such as engine rooms, has increased in the automotive field. Higher humidity and high temperature characteristics have been demanded. On the other hand, when the conventional coating material is applied under high humidity and high temperature, it has been clarified by the present inventors that the following problems occur. A schematic diagram is shown in FIG.
コーティング材１０１の内部に水分１０２が入った状態で（図７（ａ）、図７（ｂ））高温下にさらされると、水分１０２が気化し膨張する結果、コーティング材１０１の内部に気泡１０３が発生する（図７（ｃ））。この時、従来のコーティング材１０１の高温下の変形は弾性変形ではなく塑性変形が支配的であるため、常温に戻ったとしても気泡１０３が残留してしまう（図７（ｄ））。このコーティング材１０１の内部に残留した気泡１０３が新たな水分侵入経路となり、半導体チップ表面の腐食など信頼性に悪影響を及ぼすことになる。 When moisture 102 enters the inside of the coating material 101 (FIGS. 7A and 7B), when exposed to a high temperature, the moisture 102 vaporizes and expands. As a result, bubbles 103 are formed inside the coating material 101. Occurs (FIG. 7C). At this time, the deformation at a high temperature of the conventional coating material 101 is not the elastic deformation but the plastic deformation, so that the bubbles 103 remain even when the temperature returns to room temperature (FIG. 7D). The bubbles 103 remaining inside the coating material 101 become a new moisture intrusion path, which adversely affects reliability such as corrosion of the semiconductor chip surface.
本発明はこのような点に鑑みてなされたものであり、高湿・高温な環境でもコーティング材内部の水分による気泡発生を抑制し、またコーティング材内部に気泡が発生した場合でも常温下での気泡の残留を抑制することができる半導体装置を提供するものである。 The present invention has been made in view of these points, and suppresses the generation of bubbles due to moisture inside the coating material even in a high humidity and high temperature environment, and even when bubbles are generated inside the coating material, A semiconductor device capable of suppressing the remaining of bubbles is provided.
前記の目的を達成するために、この発明の一態様では、基板と、前記基板の主面に載置されている半導体チップと、前記基板に載置された前記半導体チップを覆うように配置されているコーティング材と、前記コーティング材を覆うように配置されている樹脂とを備え、前記コーティング材は２６０℃以下の貯蔵弾性率（１Ｈｚ）が５０ＭＰａ以上１０００ＭＰａ以下である構成とする。 In order to achieve the above object, according to one aspect of the present invention, a substrate, a semiconductor chip placed on a main surface of the substrate, and a semiconductor chip placed on the substrate are arranged to cover the substrate. The coating material is disposed so as to cover the coating material, and the coating material has a storage elastic modulus (1 Hz) of 260 ° C. or lower of 50 MPa or higher and 1000 MPa or lower.
また別の一態様では、半導体装置は、基板と、前記基板の主面に載置されている半導体チップと、前記基板に載置された前記半導体チップを覆うように配置されているコーティング材と、前記コーティング材を覆うように配置されている樹脂とを備え、前記コーティング材は２６０℃以下の損失弾性率（１Ｈｚ）が１．１ＭＰａ以上１０ＭＰａ以下である構成とする。 In another aspect, the semiconductor device includes a substrate, a semiconductor chip placed on the main surface of the substrate, and a coating material arranged to cover the semiconductor chip placed on the substrate. And a resin arranged so as to cover the coating material, and the coating material has a loss elastic modulus (1 Hz) of 260 ° C. or less of 1.1 MPa or more and 10 MPa or less.
さらに別の一態様では、半導体装置は、基板と、前記基板の主面に載置されている半導体チップと、前記基板に載置された前記半導体チップを覆うように配置されているコーティング材と、前記コーティング材を覆うように配置されている樹脂とを備え、前記コーティング材は２６０℃以下の貯蔵弾性率（１Ｈｚ）が５０ＭＰａ以上１０００ＭＰａ以下であり、前記コーティング材は２６０℃以下の損失弾性率（１Ｈｚ）が１．１ＭＰａ以上１０ＭＰａ以下である構成とする。 In yet another aspect, the semiconductor device includes a substrate, a semiconductor chip placed on the main surface of the substrate, and a coating material arranged to cover the semiconductor chip placed on the substrate. And a resin arranged so as to cover the coating material, the coating material has a storage elastic modulus (1 Hz) of 260 ° C. or lower of 50 MPa or higher and 1000 MPa or lower, and the coating material has a loss elastic modulus of 260 ° C. or lower. (1 Hz) is 1.1 MPa or more and 10 MPa or less.
上記の手段によれば、樹脂封止型の半導体装置において、高湿・高温な環境でもコーティング材内部の水分による気泡発生を抑制し、さらにコーティング材内部に気泡が発生した場合でも常温下での気泡の残留を抑制することができ、高い耐湿性を有する半導体装置が実現できる。 According to the above means, in a resin-encapsulated semiconductor device, generation of bubbles due to moisture inside the coating material is suppressed even in a high humidity and high temperature environment, and even when bubbles are generated inside the coating material, Residual air bubbles can be suppressed, and a semiconductor device having high moisture resistance can be realized.
以下に、本発明の好適な実施形態（実施例）を図面に基づいて説明する。
実施の形態を通して共通の構成には同一の符号を付すものとし、重複する説明は省略する。
DESCRIPTION OF EMBODIMENTS Preferred embodiments (examples) of the present invention will be described below with reference to the drawings.
Throughout the embodiments, common components are denoted by the same reference numerals, and redundant description is omitted.
なおこの実施例は、説明された実施形態に限定されるものではなく、本発明の技術的思想の範囲を逸脱しない限り様々な形態に変更することができる。
[実施例１]
図１は、この発明の実施例１に係る樹脂封止型の半導体装置５０の構成図であり、同図（ａ）は上面図、同図（ｂ）はＩ−Ｉ’断面図である。
It should be noted that this example is not limited to the described embodiment, and can be modified in various forms without departing from the scope of the technical idea of the present invention.
[Example 1]
1A and 1B are configuration diagrams of a resin-encapsulated semiconductor device 50 according to Embodiment 1 of the present invention, where FIG. 1A is a top view and FIG. 1B is a cross-sectional view taken along line II ′.
図示する半導体装置５０は、半導体チップ１と、金属基板２と、コーティング材３と、封止樹脂４と、ボンディングワイヤ５と、外部端子６と、接合材７などで構成されている。 The illustrated semiconductor device 50 includes a semiconductor chip 1, a metal substrate 2, a coating material 3, a sealing resin 4, a bonding wire 5, an external terminal 6, a bonding material 7, and the like.
半導体チップ１は、例えばＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）、パワーＭＯＳＦＥＴ、ＦＷＤ（Ｆｒｅｅ Ｗｈｅｅｌｉｎｇ Ｄｉｏｄｅ）等の縦型のパワー半導体素子が該当する。これらの半導体チップ１は動作時に高温を発生させるため、隣接するコーティング材３も高温下にさらされることになる。 The semiconductor chip 1 corresponds to a vertical power semiconductor element such as, for example, an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET, or a FWD (Free Wheeling Diode). Since these semiconductor chips 1 generate a high temperature during operation, the adjacent coating material 3 is also exposed to a high temperature.
金属基板２は、縦型のパワー半導体素子である半導体チップ１の裏面電極（例えばコレクタ電極）を、はんだなどの導電性の接合材７を経由して付随する端子部へと電気的に接続させる機能を有する。また半導体チップ１から発生する高温を効果的に放熱する機能も求められている。このように金属基板２には高い電気伝導率と熱伝導率が必要とされることから、例えば銅や銅合金などで構成されている。 The metal substrate 2 electrically connects a back surface electrode (for example, a collector electrode) of the semiconductor chip 1 that is a vertical power semiconductor element to an associated terminal portion via a conductive bonding material 7 such as solder. It has a function. A function for effectively radiating the high temperature generated from the semiconductor chip 1 is also required. Thus, since the metal substrate 2 needs high electrical conductivity and thermal conductivity, it is made of, for example, copper or copper alloy.
金属基板２は、例えば外部端子６と一体でリードフレームから成形され、最終的に外部端子６と切り離されることにより形成されている。
コーティング材３は、半導体チップ１の耐湿性を確保することを目的として、半導体チップ１の表面および側面を覆うように配置されている。コーティング材３は、例えば、ポリイミド、ポリエーテルアミド、ポリエーテルイミド、ポリアミドイミドなどの有機材料で構成されている。
The metal substrate 2 is formed by, for example, being formed from a lead frame integrally with the external terminal 6 and finally being separated from the external terminal 6.
The coating material 3 is disposed so as to cover the surface and side surfaces of the semiconductor chip 1 for the purpose of ensuring the moisture resistance of the semiconductor chip 1. The coating material 3 is made of an organic material such as polyimide, polyether amide, polyether imide, or polyamide imide.
銅や銅合金などの金属で構成された外部端子６と、半導体チップ１の表面電極（例えばエミッタ電極やゲート電極）は、アルミニウムやアルミニウム合金などで構成されたボンディングワイヤ５を用いて電気的に接続されている。 An external terminal 6 made of a metal such as copper or copper alloy and a surface electrode (for example, an emitter electrode or a gate electrode) of the semiconductor chip 1 are electrically connected using a bonding wire 5 made of aluminum or an aluminum alloy. It is connected.
封止樹脂４は、半導体チップ１やコーティング材３、ボンディングワイヤ５などを外部環境から保護することを目的として、それらを覆うように配置されている。封止樹脂４は、例えば、エポキシ樹脂などで構成されている。 The sealing resin 4 is disposed so as to cover the semiconductor chip 1, the coating material 3, the bonding wire 5 and the like for the purpose of protecting them from the external environment. The sealing resin 4 is made of, for example, an epoxy resin.
実施例１に係る半導体装置５０の製造工程の概略図を図２に示す。
まず銅や銅合金で構成された金属板を所定形状のリードフレームに加工して、金属基板２や図示しない外部端子を形成し、はんだなどの接合材７を用いて金属基板２上に半導体チップ１を固定する。さらに必要に応じて、半導体チップ１と外部端子との間に図示しないボンディングワイヤを接合する（図２（ａ））。
FIG. 2 shows a schematic diagram of a manufacturing process of the semiconductor device 50 according to the first embodiment.
First, a metal plate made of copper or a copper alloy is processed into a lead frame having a predetermined shape to form a metal substrate 2 or an external terminal (not shown), and a semiconductor chip is formed on the metal substrate 2 using a bonding material 7 such as solder. 1 is fixed. Further, if necessary, a bonding wire (not shown) is bonded between the semiconductor chip 1 and the external terminal (FIG. 2A).
続いて溶剤を加えて流動性を付与したコーティング材３を、半導体チップ１の上方からディスペンサを用いてポッティングし、コーティング材３の材質に応じて最適な温度で熱処理して硬化させて、半導体チップ１をコーティングする（図２（ｂ））。例えばコーティング材３としてポリエーテルアミドを用いた場合は、約１８０〜２６０℃の硬化温度が適している。またポリイミドを用いた場合には、約２５０℃の硬化温度が適している。 Subsequently, the coating material 3 to which fluidity is imparted by adding a solvent is potted from above the semiconductor chip 1 using a dispenser, and is heat-treated and cured at an optimum temperature according to the material of the coating material 3. 1 is coated (FIG. 2B). For example, when polyether amide is used as the coating material 3, a curing temperature of about 180 to 260 ° C. is suitable. When polyimide is used, a curing temperature of about 250 ° C. is suitable.
続いて構成部材を所定の金型に投入し、トランスファーモールド成形を行うことにより、封止樹脂４を形成する（図２（ｃ））。最後にリードフレームの不要な部分を切除することにより、半導体装置５０が完成する。 Subsequently, the constituent member is put into a predetermined mold, and transfer molding is performed to form the sealing resin 4 (FIG. 2C). Finally, unnecessary portions of the lead frame are cut away to complete the semiconductor device 50.
実施例１が前述の従来例と異なる点としては、高温下でコーティング材３内部の水分が気化し、膨張することを防止するため、コーティング材３の貯蔵弾性率を最適化した点である。コーティング材３の貯蔵弾性率と、気泡が発生する確率の相関を図３に示す。 Example 1 is different from the above-described conventional example in that the storage elastic modulus of the coating material 3 is optimized in order to prevent moisture inside the coating material 3 from vaporizing and expanding at high temperatures. FIG. 3 shows a correlation between the storage elastic modulus of the coating material 3 and the probability that bubbles are generated.
このグラフは、６種類の様々な貯蔵弾性率を持つコーティング材を適用した半導体装置を、温度８５℃、湿度８５％の条件下に１６８時間さらしてコーティング材に吸湿させ、さらに２６０℃で１０秒間の高温処理を行った後のコーティング材内部の発泡の有無を評価したデータである。 This graph shows that a semiconductor device to which six kinds of coating materials having various storage elastic moduli are applied is exposed to a temperature of 85 ° C. and a humidity of 85% for 168 hours so that the coating material absorbs moisture, and further at 260 ° C. for 10 seconds. It is the data which evaluated the presence or absence of the foaming in the coating material after performing high temperature processing.
なお本実験で用いたコーティング材の硬化前の粘度は４５〜４７．５（Ｐａ・ｓ）、硬化後のガラス転移点温度は２００〜２５０（℃）、熱膨張係数は３６〜６０（ｐｐｍ／℃）である。 The viscosity of the coating material used in this experiment before curing is 45 to 47.5 (Pa · s), the glass transition temperature after curing is 200 to 250 (° C.), and the thermal expansion coefficient is 36 to 60 ppm / ppm. ° C).
コーティング材の貯蔵弾性率は動的粘弾性測定装置（日立ハイテクサイエンス社製動的粘弾性測定装置）を用い、温度２６０℃、荷重７０ｍＮ、周波数１Ｈｚの条件で測定したものである。 The storage elastic modulus of the coating material is measured using a dynamic viscoelasticity measuring device (dynamic viscoelasticity measuring device manufactured by Hitachi High-Tech Science Co., Ltd.) under the conditions of a temperature of 260 ° C., a load of 70 mN, and a frequency of 1 Hz.
なおコーティング材に対する上記試験において、２６０℃という処理温度及び測定温度を定義した理由は、この温度が本発明が適用される半導体装置がさらされうる最も高い温度であるため、この温度での発泡特性、粘弾性特性が本発明においては重要であるからである。つまり、本発明が適用される半導体装置では、コーティング材が１８０℃〜２６０℃で硬化させるので、この温度での貯蔵弾性率と損失弾性率が重要となる。 In the above test for the coating material, the reason why the processing temperature and measurement temperature of 260 ° C. are defined is the highest temperature to which the semiconductor device to which the present invention is applied can be exposed. This is because viscoelastic properties are important in the present invention. That is, in the semiconductor device to which the present invention is applied, since the coating material is cured at 180 ° C. to 260 ° C., the storage elastic modulus and loss elastic modulus at this temperature are important.
上記６種類のコーティング材の貯蔵弾性率を測定した結果、それぞれ３８ＭＰａ、４１ＭＰａ、４８ＭＰａ、５９ＭＰａ、７８ＭＰａ及び１００ＭＰａであった。またそれぞれのコーティング材の発泡の有無を評価したところ、貯蔵弾性率が３８ＭＰａ及び４１ＭＰａのコーティング材では発泡が発生（発泡発生率＞０）していたのに対し、貯蔵弾性率が４８ＭＰａ、５９ＭＰａ、７８ＭＰａ及び１００ＭＰａのコーティング材では発泡が発生していない（発泡発生率＝０）ことが明らかとなった。 As a result of measuring the storage elastic modulus of the six types of coating materials, they were 38 MPa, 41 MPa, 48 MPa, 59 MPa, 78 MPa, and 100 MPa, respectively. Further, when the presence or absence of foaming of each coating material was evaluated, foaming occurred in the coating materials having a storage modulus of 38 MPa and 41 MPa (foaming rate> 0), whereas the storage modulus was 48 MPa, 59 MPa, It became clear that foaming did not occur in the coating materials of 78 MPa and 100 MPa (foaming rate = 0).
すなわち、これはコーティング材３の貯蔵弾性率（１Ｈｚ）を５０ＭＰａ以上に設定することにより、高温高湿下においても気泡の発生を防止することが可能であることを示している。これにより図７に示したような気泡の残留による新たな水分侵入経路の形成を防止することができ、半導体チップ表面の腐食などを防止することが可能となった。 That is, this indicates that by setting the storage elastic modulus (1 Hz) of the coating material 3 to 50 MPa or more, the generation of bubbles can be prevented even under high temperature and high humidity. Accordingly, it is possible to prevent formation of a new moisture intrusion path due to residual bubbles as shown in FIG. 7, and it is possible to prevent corrosion of the surface of the semiconductor chip.
またコーティング材３の貯蔵弾性率（１Ｈｚ）を１０００ＭＰａ以上にした場合、コーティング材３自体の製造コストが非常に高くなるため、コーティング材３の貯蔵弾性率（１Ｈｚ）は１０００ＭＰａ以下が望ましい。
[実施例２]
実施例２に関して、本実施例に係る半導体装置の構成自体は実施例１と同様である。
Further, when the storage elastic modulus (1 Hz) of the coating material 3 is set to 1000 MPa or more, the manufacturing cost of the coating material 3 itself becomes very high. Therefore, the storage elastic modulus (1 Hz) of the coating material 3 is desirably 1000 MPa or less.
[Example 2]
Regarding the second embodiment, the configuration of the semiconductor device according to the second embodiment is the same as that of the first embodiment.
実施例２が前述の従来例と異なる点としては、高温下でコーティング材３内部の水分が気化し、膨張した際に塑性変形して気泡が残留することを防止するため、コーティング材３の損失弾性率を最適化した点である。コーティング材３の損失弾性率と、気泡が発生する確率の相関を図４に示す。 Example 2 is different from the above-described conventional example in that moisture inside the coating material 3 is vaporized at high temperatures and plastic deformation is prevented when it expands, so that the loss of the coating material 3 is prevented. This is the point where the elastic modulus is optimized. FIG. 4 shows a correlation between the loss elastic modulus of the coating material 3 and the probability that bubbles are generated.
このグラフは、７種類の様々な損失弾性率を持つコーティング材を適用した半導体装置を、温度８５℃、湿度８５％の条件下に１６８時間さらしてコーティング材に吸湿させ、さらに２６０℃で１０秒間の高温処理を行った後のコーティング材内部の発泡の有無を評価したデータである。 This graph shows that a semiconductor device to which seven kinds of coating materials having various loss elastic moduli are applied is exposed to a temperature of 85 ° C. and a humidity of 85% for 168 hours so that the coating material absorbs moisture, and further at 260 ° C. for 10 seconds. It is the data which evaluated the presence or absence of the foaming in the coating material after performing high temperature processing.
なお本実験で用いたコーティング材の硬化前の粘度は４５〜４７．５（Ｐａ・ｓ）、硬化後のガラス転移点温度は２００〜２５０（℃）、熱膨張係数は３６〜６０（ｐｐｍ／℃）である。 The viscosity of the coating material used in this experiment before curing is 45 to 47.5 (Pa · s), the glass transition temperature after curing is 200 to 250 (° C.), and the thermal expansion coefficient is 36 to 60 ppm / ppm. ° C).
コーティング材の貯蔵弾性率は動的粘弾性測定装置（日立ハイテクサイエンス社製動的粘弾性測定装置）を用い、温度２６０℃、荷重７０ｍＮ、周波数１Ｈｚの条件で測定したものである。 The storage elastic modulus of the coating material is measured using a dynamic viscoelasticity measuring device (dynamic viscoelasticity measuring device manufactured by Hitachi High-Tech Science Co., Ltd.) under the conditions of a temperature of 260 ° C., a load of 70 mN, and a frequency of 1 Hz.
上記７種類のコーティング材の損失弾性率を測定した結果、それぞれ１．１ＭＰａ、２．０ＭＰａ、２．２ＭＰａ、２．５ＭＰａ、１０ＭＰａ、１９ＭＰａ及び２７ＭＰａであった。またそれぞれのコーティング材の発泡の有無を評価したところ、貯蔵弾性率が１９ＭＰａ及び２７ＭＰａのコーティング材では発泡が発生（発泡発生率＞０）していたのに対し、貯蔵弾性率が１．１ＭＰａ、２．０ＭＰａ、２．２ＭＰａ、２．５ＭＰａ及び１０ＭＰａのコーティング材では発泡が発生していない（発泡発生率＝０）ことが明らかとなった。 As a result of measuring the loss elastic modulus of the seven types of coating materials, they were 1.1 MPa, 2.0 MPa, 2.2 MPa, 2.5 MPa, 10 MPa, 19 MPa, and 27 MPa, respectively. Further, when the presence or absence of foaming of each coating material was evaluated, foaming occurred in the coating materials having a storage elastic modulus of 19 MPa and 27 MPa (foaming rate> 0), whereas the storage elastic modulus was 1.1 MPa, It became clear that foaming did not occur in the coating materials of 2.0 MPa, 2.2 MPa, 2.5 MPa, and 10 MPa (foaming rate = 0).
すなわち、これはコーティング材３の損失弾性率（１Ｈｚ）を１０ＭＰａ以下に設定することにより、高温高湿下において気泡が発生した際に、コーティング材の変形モードを塑性変形ではなく弾性変形に維持することが可能であることを示している。これにより図７に示したような気泡の残留による新たな水分侵入経路の形成を防止することができ、半導体チップ表面の腐食などを防止することが可能となった。 That is, by setting the loss elastic modulus (1 Hz) of the coating material 3 to 10 MPa or less, when bubbles are generated under high temperature and high humidity, the deformation mode of the coating material is maintained to be elastic deformation instead of plastic deformation. It shows that it is possible. Accordingly, it is possible to prevent formation of a new moisture intrusion path due to residual bubbles as shown in FIG. 7, and it is possible to prevent corrosion of the surface of the semiconductor chip.
またコーティング材３の損失弾性率（１Ｈｚ）を１．１ＭＰａ以下にした場合、コーティング材３自体の製造コストが非常に高くなるため、コーティング材３の損失弾性率（１Ｈｚ）は１．１ＭＰａ以上が望ましい。 Further, when the loss elastic modulus (1 Hz) of the coating material 3 is set to 1.1 MPa or less, the manufacturing cost of the coating material 3 itself becomes very high. Therefore, the loss elastic modulus (1 Hz) of the coating material 3 is 1.1 MPa or more. desirable.
また、実施例１にて記した貯蔵弾性率の良好な範囲と、実施例２で示した損失弾性率の良好な範囲を共に満たすコーティング材３を用いることにより、さらに信頼性の高い半導体装置を実現することができる。
[実施例３]
図５は、この発明の実施例３に係る樹脂封止型の半導体装置６０の要部断面図である。
Further, by using the coating material 3 that satisfies both the good range of the storage elastic modulus described in the first embodiment and the good range of the loss elastic modulus shown in the second embodiment, a more reliable semiconductor device can be obtained. Can be realized.
[Example 3]
FIG. 5 is a cross-sectional view of an essential part of a resin-encapsulated semiconductor device 60 according to Embodiment 3 of the present invention.
実施例３が実施例１と大きく異なる点としては、構成部材として樹脂ケース１３が用いられていることと、半導体チップ１が固定されている基板が金属基板でなく絶縁回路基板であることがあげられる。絶縁回路基板８は、金属パターン層９、絶縁層１０及び下部金属層１１の３層構造で構成されている。 The third embodiment is significantly different from the first embodiment in that the resin case 13 is used as a constituent member and that the substrate on which the semiconductor chip 1 is fixed is not a metal substrate but an insulating circuit substrate. It is done. The insulated circuit board 8 has a three-layer structure of a metal pattern layer 9, an insulating layer 10, and a lower metal layer 11.
絶縁回路基板８の一様態としては、絶縁層１０は、例えばアルミナ（Ａｌ２Ｏ３）焼結体、窒化シリコン（Ｓｉ３Ｎ４）等のセラミックで構成されている。金属パターン層９及び下部金属層１１は銅（Ｃｕ）を主成分とする金属で構成され、ＤＣＢ（Ｄｉｒｅｃｔ Ｃｏｐｐｅｒ Ｂｏｎｄｉｎｇ）法などを用いて絶縁層１０のそれぞれの面に形成されている。また金属パターン層９は選択的にパターン形成され、半導体装置６０に必要な回路が形成されている。 As an embodiment of the insulating circuit board 8, the insulating layer 10 is made of ceramic such as alumina (Al 2 O 3 ) sintered body, silicon nitride (Si 3 N 4 ), or the like. The metal pattern layer 9 and the lower metal layer 11 are made of a metal having copper (Cu) as a main component, and are formed on each surface of the insulating layer 10 by using a DCB (Direct Copper Bonding) method or the like. Further, the metal pattern layer 9 is selectively patterned, and a circuit necessary for the semiconductor device 60 is formed.
また絶縁回路基板８の別の一様態としては、アルミニウム板などで構成された下部金属層１１の表面にエポキシ系樹脂で絶縁層１０を形成し、さらにその表面に金属パターン層９を選択的にパターン形成して、絶縁回路基板８が構成されている。先の様態と比較した場合、コスト面で有利である。 As another embodiment of the insulating circuit board 8, an insulating layer 10 is formed of an epoxy resin on the surface of a lower metal layer 11 made of an aluminum plate, and a metal pattern layer 9 is selectively formed on the surface. The insulating circuit board 8 is configured by pattern formation. Compared to the previous mode, it is advantageous in terms of cost.
また、半導体装置６０には、半導体チップ１の動作を制御するための制御チップ１２が搭載されている。図５では、制御チップ１２は外部端子６上に固定されているが、絶縁回路基板８上に固定されてももちろん良い。 The semiconductor device 60 is equipped with a control chip 12 for controlling the operation of the semiconductor chip 1. In FIG. 5, the control chip 12 is fixed on the external terminal 6, but may of course be fixed on the insulating circuit board 8.
実施例３に係る半導体装置６０の製造工程の概略図を図６に示す。
まず銅や銅合金で構成された金属板を所定形状のリードフレームに加工して外部端子６を形成し、
あらかじめ準備した絶縁回路基板８と共に所定の金型に投入して、トランスファーモールド成形により樹脂ケース１３を形成する（図６（ａ））。樹脂ケース１３は、例えばポリフェニレンサルファイド樹脂（ＰＰＳ樹脂）、ポリブチレンテレフタレート樹脂（ＰＢＴ樹脂）、ポリアミド樹脂（ＰＡ樹脂）又はアクリロニトリルブタジエンスチレン樹脂（ＡＢＳ樹脂）などで構成されている。また樹脂ケース１３の成形後に、リードフレームの不要部分が切除される。
FIG. 6 shows a schematic diagram of a manufacturing process of the semiconductor device 60 according to the third embodiment.
First, an external terminal 6 is formed by processing a metal plate made of copper or a copper alloy into a lead frame having a predetermined shape,
The resin case 13 is formed by transfer molding to be put into a predetermined mold together with the insulating circuit board 8 prepared in advance (FIG. 6A). The resin case 13 is made of, for example, polyphenylene sulfide resin (PPS resin), polybutylene terephthalate resin (PBT resin), polyamide resin (PA resin), acrylonitrile butadiene styrene resin (ABS resin), or the like. Further, after the resin case 13 is molded, unnecessary portions of the lead frame are cut off.
続いてはんだなどの接合材７を用いて絶縁回路基板８上に半導体チップ１を、外部端子６上に制御チップ１２を固定する。さらに必要に応じて、半導体チップ１と制御チップ１２、外部端子６との間にボンディングワイヤ５を接合する（図６（ｂ））。 Subsequently, the semiconductor chip 1 is fixed on the insulating circuit substrate 8 and the control chip 12 is fixed on the external terminal 6 using a bonding material 7 such as solder. Further, if necessary, a bonding wire 5 is bonded between the semiconductor chip 1, the control chip 12, and the external terminal 6 (FIG. 6B).
続いて溶剤を加えて流動性を付与したコーティング材３を、半導体チップ１の上方からディスペンサを用いてポッティングし、コーティング材３の材質に応じて最適な温度で熱処理して硬化させて、半導体チップ１をコーティングする（図６（ｃ））。例えばコーティング材３としてポリエーテルアミドを用いた場合は、約１８０〜２６０℃の硬化温度が適している。またポリイミドを用いた場合には、約２５０℃の硬化温度が適している。 Subsequently, the coating material 3 to which fluidity is imparted by adding a solvent is potted from above the semiconductor chip 1 using a dispenser, and is heat-treated and cured at an optimum temperature according to the material of the coating material 3. 1 is coated (FIG. 6C). For example, when polyether amide is used as the coating material 3, a curing temperature of about 180 to 260 ° C. is suitable. When polyimide is used, a curing temperature of about 250 ° C. is suitable.
続いてエポキシ樹脂やシリコーン樹脂、ウレタン樹脂などから成る樹脂を樹脂ケース１３内に注入して、固化することにより封止樹脂４が形成される（図６（ｄ））。これにより半導体装置６０が完成する。 Subsequently, a resin made of epoxy resin, silicone resin, urethane resin, or the like is injected into the resin case 13 and solidified to form the sealing resin 4 (FIG. 6D). Thereby, the semiconductor device 60 is completed.
本実施例においても、実施例１と同様にコーティング材３の貯蔵弾性率（１Ｈｚ）を５０ＭＰａ以上、１０００ＭＰａ以下に設定することにより、高温高湿下においても気泡の発生を防止することが可能である。 Also in this example, by setting the storage modulus (1 Hz) of the coating material 3 to 50 MPa or more and 1000 MPa or less as in Example 1, it is possible to prevent the generation of bubbles even under high temperature and high humidity. is there.
また、本実施例においても実施例２と同様にコーティング材３の損失弾性率（１Ｈｚ）を１．１ＭＰａ以上、１０ＭＰａ以下に設定することにより、高温高湿下において気泡が発生した際に、コーティング材の変形モードを塑性変形ではなく弾性変形に維持することが可能である。 Also, in this example, similarly to Example 2, the loss elastic modulus (1 Hz) of the coating material 3 is set to 1.1 MPa or more and 10 MPa or less, so that when bubbles are generated under high temperature and high humidity, the coating is performed. It is possible to maintain the deformation mode of the material not as plastic deformation but as elastic deformation.
さらに、本実施例においても、コーティング材３の貯蔵弾性率と損失弾性率は基本的に独立で制御可能であることから、上記貯蔵弾性率の良好な範囲と、上記損失弾性率の良好な範囲を共に満たすコーティング材３を用いることにより、さらに信頼性の高い半導体装置を実現することができる。 Furthermore, also in this embodiment, the storage elastic modulus and loss elastic modulus of the coating material 3 are basically independently controllable, so that the above storage elastic modulus has a good range and the above loss elastic modulus has a good range. By using the coating material 3 that satisfies both of the requirements, a more reliable semiconductor device can be realized.
これらにより図７に示したような気泡の発生・残留による新たな水分侵入経路の形成を防止することができ、半導体チップ表面の腐食などを防止することが可能となる。
また本実施例では、図５で示すように制御チップ１２の表面はコーティング材３で保護されていない。これは制御チップ１２は半導体チップ３に比べ、動作時に高温が発生しないためである。しかしながら、高い信頼性を確保する目的で、制御チップ１２にも今回適用したコーティング材を適用してもよい。
Accordingly, it is possible to prevent the formation of a new moisture intrusion path due to the generation and residual of bubbles as shown in FIG. 7, and it is possible to prevent the surface of the semiconductor chip from being corroded.
In this embodiment, the surface of the control chip 12 is not protected by the coating material 3 as shown in FIG. This is because the control chip 12 does not generate a higher temperature during operation than the semiconductor chip 3. However, the coating material applied this time may also be applied to the control chip 12 in order to ensure high reliability.
１ 半導体チップ
２ 金属基板
３ コーティング材
４ 封止樹脂
５ ボンディングワイヤ
６ 外部端子
７ 接合材
８ 絶縁回路基板
９ 金属パターン層
１０ 絶縁層
１１ 下部金属層
１２ 制御チップ
１３ 樹脂ケース
５０、６０ 半導体装置
DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Metal substrate 3 Coating material 4 Sealing resin 5 Bonding wire 6 External terminal 7 Bonding material 8 Insulating circuit board 9 Metal pattern layer 10 Insulating layer 11 Lower metal layer 12 Control chip 13 Resin case 50, 60 Semiconductor device
Claims (7)
前記基板の主面に載置されている半導体チップと、
前記基板に載置された前記半導体チップを覆うように配置されているコーティング材と、
前記コーティング材を覆うように配置されている樹脂と、
を備え、
前記コーティング材は２６０℃以下の貯蔵弾性率（１Ｈｚ）が５０ＭＰａ以上１０００ＭＰａ以下であることを特徴とする半導体装置。 A substrate,
A semiconductor chip mounted on the main surface of the substrate;
A coating material arranged to cover the semiconductor chip placed on the substrate;
A resin arranged to cover the coating material;
With
The coating material has a storage elastic modulus (1 Hz) of 260 ° C. or less of 50 MPa or more and 1000 MPa or less.
前記基板の主面に載置されている半導体チップと、
前記基板に載置された前記半導体チップを覆うように配置されているコーティング材と、
前記コーティング材を覆うように配置されている樹脂と、
を備え、
前記コーティング材は２６０℃以下の損失弾性率（１Ｈｚ）が１．１ＭＰａ以上１０ＭＰａ以下であることを特徴とする半導体装置。 A substrate,
A semiconductor chip mounted on the main surface of the substrate;
A coating material arranged to cover the semiconductor chip placed on the substrate;
A resin arranged to cover the coating material;
With
The coating material has a loss elastic modulus (1 Hz) of 260 ° C. or less of 1.1 MPa or more and 10 MPa or less.
前記基板の主面に載置されている半導体チップと、
前記基板に載置された前記半導体チップを覆うように配置されているコーティング材と、
前記コーティング材を覆うように配置されている樹脂と、
を備え、
前記コーティング材は２６０℃以下の貯蔵弾性率（１Ｈｚ）が５０ＭＰａ以上１０００ＭＰａ以下であり、
前記コーティング材は２６０℃以下の損失弾性率（１Ｈｚ）が１．１ＭＰａ以上１０ＭＰａ以下であることを特徴とする半導体装置。 A substrate,
A semiconductor chip mounted on the main surface of the substrate;
A coating material arranged to cover the semiconductor chip placed on the substrate;
A resin arranged to cover the coating material;
With
The coating material has a storage elastic modulus (1 Hz) of 260 ° C. or less of 50 MPa or more and 1000 MPa or less,
The coating material has a loss elastic modulus (1 Hz) of 260 ° C. or less of 1.1 MPa or more and 10 MPa or less.
The semiconductor device according to claim 1, wherein the semiconductor chip is a vertical power semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013216505A JP6314416B2 (en) | 2013-10-17 | 2013-10-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013216505A JP6314416B2 (en) | 2013-10-17 | 2013-10-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2015079874A true JP2015079874A (en) | 2015-04-23 |
| JP6314416B2 JP6314416B2 (en) | 2018-04-25 |
Family
ID=53011066
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013216505A Active JP6314416B2 (en) | 2013-10-17 | 2013-10-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP6314416B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013033972A (en) * | 2007-12-04 | 2013-02-14 | Hitachi Chemical Co Ltd | Semiconductor device and manufacturing method of the same |
| JP2013038410A (en) * | 2011-07-13 | 2013-02-21 | Ajinomoto Co Inc | Semiconductor package |
-
2013
- 2013-10-17 JP JP2013216505A patent/JP6314416B2/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013033972A (en) * | 2007-12-04 | 2013-02-14 | Hitachi Chemical Co Ltd | Semiconductor device and manufacturing method of the same |
| JP2013038410A (en) * | 2011-07-13 | 2013-02-21 | Ajinomoto Co Inc | Semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP6314416B2 (en) | 2018-04-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8674492B2 (en) | Power module | |
| KR100723454B1 (en) | Power module package with high thermal dissipation capability and method for manufacturing the same | |
| US7936054B2 (en) | Multi-chip package | |
| KR101068703B1 (en) | Power semiconductor module with connection elements electrically insulated from one another | |
| US8629538B2 (en) | Power module package | |
| US9530754B2 (en) | Chip package and chip assembly | |
| JP6127837B2 (en) | Semiconductor device | |
| US9524929B2 (en) | Semiconductor module package and method of manufacturing the same | |
| US9728484B2 (en) | Power module package and method for manufacturing the same | |
| US20130069213A1 (en) | Power module package | |
| US20140001613A1 (en) | Semiconductor package | |
| US9589904B2 (en) | Semiconductor device with bypass functionality and method thereof | |
| KR101237566B1 (en) | Power Module Package and Method for Manufacturing the same | |
| US20130154123A1 (en) | Semiconductor Device and Fabrication Method | |
| US10163752B2 (en) | Semiconductor device | |
| US9257376B2 (en) | Semiconductor package and method of manufacturing the same | |
| JP2016181536A (en) | Power semiconductor device | |
| US20150270201A1 (en) | Semiconductor module package and method of manufacturing the same | |
| US20130001759A1 (en) | Semiconductor package and method of manufacturing the semiconductor package | |
| US9161479B2 (en) | Power module package and method for manufacturing the same | |
| US8810014B2 (en) | Semiconductor package including conductive member disposed between the heat dissipation member and the lead frame | |
| US9099451B2 (en) | Power module package and method of manufacturing the same | |
| JP6314416B2 (en) | Semiconductor device | |
| US10381283B2 (en) | Power semiconductor module | |
| US20140001611A1 (en) | Semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20151005 |
|
| RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20151005 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20160913 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20170413 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170425 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170619 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20171031 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20171226 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20180227 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20180312 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 6314416 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |