JP2015077213A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine which can favorably read out information from memory means.SOLUTION: In an audio light emission control board 101, an audio light SOC 102 and an audio light ROM 103 are provided. The audio light SOC 102 includes a control core 111 which determines an execution content of a performance according to a command received from a main control unit, and executes a light emission control of a display light emission part 53 according to the determined performance content; a sound output core 112 which executes an audio output control of a speaker part 54 according to the performance content determined by the control core 111; and a memory controller 114 which executes the read-out of data from the audio light ROM 103 according to address data transmitted from a DMA 123 of the control core 111 and address data transmitted from a data transfer part 134 of the sound output core 112. Here, program data used in the control core 111 is integrally read out at the start of operation power supply.

Description

  The present invention relates to a gaming machine.

  As a kind of gaming machine, a pachinko gaming machine, a slot machine, and the like are known. These gaming machines are equipped with general-purpose control elements such as a CPU and read-only storage elements such as a ROM, and a series of processes are executed by the general-purpose control elements according to a program read from the read-only storage elements. Are controlled (see, for example, Patent Document 1). It is also known that a general-purpose control element, a read-only memory element, etc. are integrated into one chip.

  A configuration using a dedicated control element as a control element for performing sound output control and display control is also known. In this case, the operation of the control target device is controlled based on the processing performed by the dedicated control element according to the data read from the read-only storage element.

JP 2009-261415 A

  Here, in the gaming machine such as the above-described example, it is necessary to suitably read out information from the storage means, and there is still room for improvement in this respect.

  The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a gaming machine capable of suitably reading information from a storage unit.

In order to solve the above-mentioned problem, the invention according to claim 1 includes a storage means for storing information in advance,
First control means for executing first control using information stored in the storage means;
Second control means for executing second control using information stored in the storage means;
With
In the storage means,
Program information necessary for executing the program in the first control means;
First control information necessary for determining a control mode of a control target when executing the first control according to the program;
Second control information necessary for determining the control mode of the control target when the second control means executes the second control;
Is at least remembered,
The first control means includes a reading means for reading the program information to the first storage means during a period in which an instruction for reading the first control information and the second control information is not generated. To do.

  According to the present invention, it is possible to suitably read information from the storage unit.

It is a perspective view which shows the pachinko machine in 1st Embodiment. It is a perspective view which decomposes | disassembles and shows the main structures of a pachinko machine. It is a front view which shows the structure of a game board. It is a block diagram which shows the electric constitution of a pachinko machine. It is explanatory drawing for demonstrating the content of the various counters used for a success or failure lottery. It is a flowchart which shows the main process performed in MPU of a main controller. It is a flowchart which shows the timer interruption process performed in MPU of a main controller. It is a block diagram which shows the electrical structure for performing execution control of an effect. It is explanatory drawing for demonstrating the data structure of a register | resistor. It is explanatory drawing for demonstrating an example of sequence data. It is explanatory drawing for demonstrating the data structure of ROM for sound light. It is a flowchart which shows the main process performed with CPU of a control core. 6 is a time chart for explaining a relationship between a period during which power-on wait processing is executed in the MPU of the main control unit and a period during which data is read when power is turned on in the control core. It is explanatory drawing for demonstrating the data structure of RAM. It is a flowchart which shows the process for normal determination performed with CPU of a control core. It is a time chart which shows a mode that normal determination is performed. It is a flowchart which shows the timer interruption process performed with CPU of a control core. It is a flowchart which shows the operation | movement in DMA. It is a time chart which shows a mode that data are read from ROM for sound light with respect to transmission of the address data from DMA. It is a flowchart which shows the operation | movement in a data transfer part. It is a flowchart which shows the operation | movement in a memory controller. 10 is a time chart for explaining a data read mode when a period in which a read instruction is issued from a DMA and a period in which a read instruction is issued from a data transfer unit overlap. It is explanatory drawing for demonstrating the unit reading period in case the sound data for the largest channel is read in each of HWD and SCM. It is a flowchart which shows the process for normality determination performed with CPU of the control core in 2nd Embodiment. (A) It is a flowchart which shows the operation | movement in DMA, (b) It is a flowchart which shows the operation | movement in a data transfer part. It is a block diagram which shows the electrical structure for performing execution control of the effect in 3rd Embodiment. It is explanatory drawing for demonstrating the data structure of direct attachment ROM. It is a flowchart which shows the main process performed with CPU of a control core. (A) It is a flowchart which shows the command interruption process performed with CPU of a control core, (b) It is a flowchart which shows the timer interruption process performed with CPU of a control core. It is a flowchart which shows the process for normal determination performed with CPU of a control core. It is a flowchart which shows the operation | movement in DMA. It is a time chart for demonstrating the reading aspect of various data. It is explanatory drawing for demonstrating the relationship between the execution period of the process for normal determination, and the execution period of various processes.

<First Embodiment>
Hereinafter, a first embodiment of a pachinko gaming machine (hereinafter referred to as “pachinko machine”), which is a type of gaming machine, will be described in detail with reference to the drawings. FIG. 1 is a perspective view of the pachinko machine 10, and FIG. 2 is an exploded perspective view showing the main configuration of the pachinko machine 10. As shown in FIG. In FIG. 2, the configuration in the game area of the pachinko machine 10 is omitted for convenience.

  As shown in FIG. 1, the pachinko machine 10 includes an outer frame 11 that forms an outer shell of the pachinko machine 10, and a gaming machine body 12 that is rotatably attached to the outer frame 11. . The outer frame 11 is configured by connecting wooden plates to four sides and has a rectangular frame shape. The pachinko machine 10 is installed in the game hall by attaching and fixing the outer frame 11 to the island facility. In the pachinko machine 10, the outer frame 11 is not an essential configuration, and may be configured such that the outer frame 11 is provided in the island facility of the game hall.

  As shown in FIG. 2, the gaming machine main body 12 includes an inner frame 13, a front door frame 14 disposed in front of the inner frame 13, and a back pack unit 15 disposed behind the inner frame 13. ing. The inner frame 13 of the gaming machine main body 12 is supported so as to be rotatable with respect to the outer frame 11. Specifically, the inner frame 13 can be rotated forward with the left side as a rotation base end side and the right side as a rotation front end side in front view.

  A front door frame 14 is rotatably supported by the inner frame 13 and can be rotated forward with the left side as a rotation base end side and the right side as a rotation front end side in a front view. Further, the back pack unit 15 is rotatably supported on the inner frame 13, and can be rotated backward with the left side as a rotation base end side and the right side as a rotation front end side in a front view.

  The gaming machine main body 12 is provided with a locking device at the rotating tip, and has a function of locking the gaming machine main body 12 to the outer frame 11 so that it cannot be opened. The door frame 14 has a function of locking the door frame 14 to the inner frame 13 so as not to be opened. Each of these locked states is released by performing an unlocking operation using the unlocking key on the cylinder lock 17 that is exposed on the front surface of the pachinko machine 10.

  Next, the configuration of the front side of the gaming machine body 12 will be described.

  The inner frame 13 is mainly composed of a resin base 21 whose outer shape is substantially the same as that of the outer frame 11. A substantially elliptical window hole 23 is formed at the center of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and the game area PA formed on the front surface of the game board 24 is exposed to the front surface side of the inner frame 13 through the window hole 23 of the resin base 21.

  Here, the structure of the game board 24 is demonstrated based on FIG. FIG. 3 is a front view of the game board 24.

  An inner rail portion 25 and an outer rail portion 26 are attached to the game board 24 so as to partition a part of the outer edge of the game area PA. The inner rail portion 25 and the outer rail portion 26 provide guidance means. As a guide rail, it is configured. A game ball launched from a game ball launching mechanism 27 (see FIG. 2) attached below the window hole 23 in the resin base 21 is guided to the upper part of the game area PA by a guide rail.

  Incidentally, the game ball launching mechanism 27 includes a launch rail 27a extending toward the guide rail, a ball feeding device 27b for supplying game balls stored in an upper plate 55a, which will be described later, onto the launch rail 27a, and the launch rail 27a. And a solenoid 27c which is an electric actuator for firing the game ball supplied to the guide rail. When the launch operation device (or operation handle) 28 provided on the front door frame 14 is rotated, the solenoid 27c is driven and controlled, and a game ball is launched.

  The game board 24 has a plurality of large and small openings penetrating in the front-rear direction. Each opening is provided with a general winning port 31, a special electricity winning device 32, a first operating port 33, a second operating port 34, a through gate 35, a variable display unit 36, a special drawing unit 37, a universal drawing unit 38, and the like. ing.

  Even if a ball enters the through gate 35, the game ball is not paid out. On the other hand, when a ball enters the general winning port 31, the special electricity winning device 32, the first operating port 33, and the second operating port 34, a predetermined number of game balls are paid out. Specifically, with respect to the number of prize balls, when a ball enters the first working port 33 or a ball enters the second working port 34, three prize balls are paid out. When a ball is entered into the general winning port 31, 10 prize balls are paid out. When a ball is entered into the special electric prize device 32, 15 prize balls are paid out. Executed.

  The number of prize balls may be arbitrary. For example, the second actuation port 34 may have a smaller number of prize balls than the first actuation port 33, and the second actuation port 34 may be configured as the first actuation port. The number of prize balls may be larger than 33.

  In addition, an out port 24a is provided at the bottom of the game board 24, and game balls that have not entered various winning ports etc. are discharged from the game area PA through the out port 24a. In addition, the game board 24 is provided with a large number of nails 24b and various members such as a windmill in order to disperse and adjust the falling direction of the game ball as appropriate.

  Here, the entry ball means that the game ball passes through a predetermined opening, and not only the mode of discharging from the game area PA after passing through the opening, but also from the game area PA after passing through the opening. A mode in which the game area PA continues to flow down without being discharged is also included. However, in the following description, in order to clearly distinguish the game ball from entering the out port 24a, the general winning port 31, the special prize winning device 32, the first operating port 33, the second operating port 34, and the through gate 35 are provided. Entering a game ball into is also expressed as a prize.

  The first operating port 33 and the second operating port 34 are unitized as operating port devices and are installed in the game board 24. Both the first working port 33 and the second working port 34 are opened upward. Further, both the operation ports 33 and 34 are arranged in the vertical direction so that the first operation port 33 is located on the upper side. The second operating port 34 is provided with a general electric utility 34a as a guide piece composed of a pair of left and right movable pieces. In the closed state of the utility wire 34a, the game ball cannot win the second operating port 34, and the winning of the second operating port 34 becomes possible when the universal power 34a is opened.

  A through gate 35 is provided on the upstream side in the flow-down direction of the game ball from the second working port 34. The through gate 35 has a through hole (not shown) penetrating in the vertical direction, and the game ball that has won the through gate 35 flows down the game area PA after winning. As a result, the game ball that has won the through gate 35 can win the second working port 34.

  Based on the winning of the through gate 35, the common utility 34 a of the second operating port 34 is switched from the closed state to the open state. Specifically, an internal lottery is performed with a winning at the through gate 35 as a trigger, and a normal display of a general-purpose unit 38 provided at the lower right corner, which is a region where game balls do not pass in the game region PA, is displayed. In the part 38a, the change display of the pattern is performed. Then, when the result of the internal lottery is the electrification opening winning, the stop result corresponding to the result is displayed, and the fluctuation display of the general map display unit 38a is finished, the state shifts to the public power open state. In the public power open state, the general electric utility 34a is opened in a predetermined manner.

  The general map display unit 38a is constituted by a segment display in which a plurality of segment light emitting units are arranged in a predetermined manner, but is not limited to this, and is not limited to this. A liquid crystal display device, an organic EL display device , Or other types of display devices such as CRT or dot matrix display. In addition, as a pattern variably displayed on the general map display unit 38a, a configuration in which a plurality of types of characters are variably displayed, a configuration in which a plurality of types of symbols are variably displayed, a configuration in which a plurality of types of characters are variably displayed, or A configuration in which a plurality of colors are switched and displayed is conceivable.

  In the universal map unit 38, a universal map hold display section 38b is provided at a position adjacent to the universal map display section 38a. A maximum of four game balls won in the through gate 35 are reserved, and the number of the reserved balls is displayed by turning on the general-purpose display unit 38b.

  A lottery is performed with the winning of the first working port 33 or the second working port 34 as a trigger. The lottery result is clearly shown through display effects in the symbol display device 41 of the special figure unit 37 and the variable display unit 36.

  Specifically, the special figure unit 37 is provided with a special figure display unit 37a. The display area of the special figure display unit 37 a is narrower than the display surface 41 a of the symbol display device 41. In the special figure display part 37a, a winning change to the first working port 33 or a winning to the second working port 34 is used as a trigger, and a lottery is performed to display a variation display or a predetermined display. Then, a result corresponding to the lottery result is displayed. In addition, although the special figure display part 37a is comprised by the segment display by which several segment light emission parts are arranged in the predetermined | prescribed aspect, it is not limited to this, A liquid crystal display device, an organic electroluminescence display device , Or other types of display devices such as CRT or dot matrix display. In addition, as a picture displayed on the special figure display unit 37a, a configuration in which a plurality of types of characters are displayed, a configuration in which a plurality of types of symbols are displayed, a configuration in which a plurality of types of characters are displayed, or a plurality of types of colors A configuration in which is displayed is conceivable.

  In the special figure unit 37, a special figure holding display part 37b is provided at a position adjacent to the special figure display part 37a. A maximum of four game balls won in the first operation port 33 or the second operation port 34 are reserved, and the reserved number is displayed by lighting the special figure reservation display portion 37b.

  Specifically, the symbol display device 41 is configured as a liquid crystal display device including a liquid crystal display, and the display content is controlled by a display control device described later. The symbol display device 41 is not limited to a liquid crystal display device, and may be another display device having a display screen such as a plasma display device, an organic EL display device, or a CRT, and is a dot matrix display. May be.

  In the symbol display device 41, when a special symbol display unit 37a displays a change or predetermined display of a pattern based on a winning in the first operating port 33 or a winning in the second operating port 34, the symbol is displayed accordingly. A variable display or a predetermined display is performed. For example, on the display surface 41a of the symbol display device 41, three symbol rows of upper, middle, and lower rows are set as a plurality of display areas, and numbers “1” to “9” are attached to the symbol rows. The symbols are scrolled and displayed with the symbols arranged in ascending or descending order. In this scroll display, the scroll display in all the symbol sequences is started first, and the display is switched from the scroll display to the standby display in the order of the upper symbol sequence → the lower symbol sequence → the middle symbol sequence. The process ends with the symbols still displayed. For example, in the game times in which the game result is a jackpot result, a predetermined combination of symbols is stopped and displayed on the active line set in advance on the display surface 41a of the symbol display device 41.

  In addition, the symbol display device 41 performs not only a display effect triggered by winning a prize to the first operating port 33 or the second operating port 34, but also a display effect in the opening / closing execution mode that shifts after winning the winning combination. Is called. In addition, based on the winning in one of the operation ports 33 and 34, the display is started on the special symbol display unit 37a and the symbol display device 41, and until a predetermined result is displayed and ended, the game number is 1 Equivalent to times. Further, the variation display mode of the symbol in the symbol display device 41 is not limited to the above, and is arbitrary, such as the number of symbol columns, the direction of symbol variation display in the symbol column, the number of symbols in each symbol column, etc. Can be appropriately changed. Also, the pattern that is variably displayed on the symbol display device 41 is not limited to the above-described pattern, and for example, only numbers may be variably displayed as the pattern.

  When the big win is won in the winning lottery based on the winning to the first operating port 33 or the winning to the second operating port 34, the mode shifts to an opening / closing execution mode in which the special electric winning device 32 can be won. The special electric prize winning device 32 is provided with a large winning opening (not shown) leading to the back side of the game board 24 and an open / close door 32a for opening and closing the large winning opening. The open / close door 32a is arranged in either a closed state or an open state. Specifically, the open / close door 32a is normally in a closed state in which game balls cannot be won, and can be switched to an open state in which game balls can be won when winning the transition to the open / close execution mode in the internal lottery. It has become. Incidentally, the opening / closing execution mode is a mode that shifts when a hit result is obtained. Note that, in the closed state, winning may not be impossible, but it may be configured such that winning is less likely to occur than in the open state.

  As shown in FIG. 2, the front door frame 14 is provided so as to cover the entire front side of the inner frame 13 in which the game board 24 having the above configuration is attached to the resin base 21. As shown in FIG. 1, the front door frame 14 is formed with a window portion 51 so that almost the entire game area PA can be viewed from the front. The window part 51 has a substantially elliptical shape, and the window panel 52 is fitted therein. The window panel 52 is formed of colorless and transparent with glass, but is not limited to this, and may be formed of colorless and transparent with synthetic resin. The game area PA is defined through the window panel 52 from the front of the pachinko machine 10. As long as it is visible, it may be colored and transparent.

  A display light emitting unit 53 is provided above the window unit 51. In addition, a pair of left and right speaker portions 54 that output sound effects according to the gaming state are provided. Further, below the window portion 51, an upper bulging portion 55 and a lower bulging portion 56 that bulge to the near side are arranged in parallel vertically. An upper plate 55a that opens upward is provided inside the upper bulge portion 55, and a lower plate 56a that also opens upward is provided inside the lower bulge portion 56. The upper plate 55a has a function of temporarily storing game balls paid out from a payout device described later and guiding them to the game ball launching mechanism 27 side while aligning them in a row. In addition, the lower tray 56a has a function of storing game balls that are surplus in the upper tray 55a.

  Next, the configuration on the back side of the gaming machine main body 12 will be described.

  As shown in FIG. 2, a main controller 60 that controls the main game is mounted on the back of the inner frame 13 (specifically, the game board 24). The main control device 60 has a main control board accommodated in a board box. In addition, you may provide the trace structure for giving the trace means for leaving the trace of the opening to the board | substrate box, or leaving the trace of the open. As the trace means, a plurality of case bodies constituting the substrate box are unseparably coupled, and a configuration of a coupling portion that requires destruction of a predetermined part at the time of separation, or an adhesive layer that remains on an adhesion target at the time of peeling is peeled off. A configuration is conceivable in which a seal seal that leaves a trace of what has been done is pasted so as to straddle the boundaries between the plurality of case bodies. Moreover, as a trace structure, the structure which apply | coats an adhesive agent with respect to the boundary between the some case bodies which comprise a board | substrate box can be considered.

  The back pack unit 15 is installed so as to cover the back side of the inner frame 13 including the main controller 60. The back pack unit 15 includes a back pack 72 formed of a synthetic resin having transparency, and a payout mechanism unit 73 and a controller assembly unit 74 are attached to the back pack 72.

  The payout mechanism unit 73 includes a tank 75 in which game balls supplied from the island equipment of the game hall are sequentially replenished, and a payout device 76 for paying out the game balls stored in the tank 75. The game balls paid out from the payout device 76 are discharged to the upper plate 55a or the lower plate 56a through a payout passage provided on the downstream side of the payout device 76. The payout mechanism unit 73 is provided with a backpack substrate having a power switch for performing ON and OFF operations of the power supply, for example, while supplying a main power of AC 24 volts.

  The control device assembly unit 74 generates and outputs predetermined power required by the payout control device 77 having a function of controlling the payout device 76 and various control devices, and is accompanied by an operation of the launch operation device 28 by the player. And a power source / launch control device 78 for controlling the launch of the game ball. The payout control device 77 and the power supply / launch control device 78 are arranged so as to overlap each other so that the payout control device 77 is behind the pachinko machine 10.

<Electric configuration of pachinko machine 10>
FIG. 4 is a block diagram showing an electrical configuration of the pachinko machine 10.

  The main control device 60 includes a main control board 61 that controls the main control of the game, and a power failure monitoring board 65 that monitors the power supply. An MPU 62 is mounted on the main control board 61. The MPU 62 includes a ROM 63 that stores various control programs executed by the MPU 62 and fixed value data, and a memory that temporarily stores various data when the control program stored in the ROM 63 is executed. A RAM 64, an interrupt circuit, a timer circuit, a data input / output circuit, various counter circuits as a random number generator, and the like are incorporated. Note that it is not essential that the ROM 63 and the RAM 64 are made into one chip with respect to the MPU 62, but each may be made into a chip individually. The same applies to the MPUs of control devices other than the main control device 60.

  The MPU 62 is provided with an input port and an output port. A power failure monitoring board 65 and a payout control device 77 provided in the main control device 60 are connected to the input side of the MPU 62. The power failure monitoring board 65 is connected to a power source / launch control device 78 having a function of supplying operating power, and the MPU 62 is supplied with power via the power failure monitoring board 65.

  Various sensors such as various winning detection sensors 66 a to 66 e are connected to the input side of the MPU 62. Each of the various winning detection sensors 66a to 66e is provided on a one-to-one basis with respect to the winning-corresponding pitching portions such as the general winning port 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the through gate 35. The detection sensor is included, and the MPU 62 makes a winning determination for each winning part. Further, in the MPU 62, various lotteries are executed on the basis of winning in the first operating port 33, and various lotteries are executed on the basis of winning in the second operating port 34.

  A power failure monitoring board 65, a payout control device 77, and a sound emission control device 80 are connected to the output side of the MPU 62. For example, a prize ball command is output to the payout control device 77 based on a winning determination result for the winning-corresponding winning part. Various commands such as a change command, a type command, and an opening command are output to the sound emission control device 80. Details of these various commands will be described later. The MPU 62 transmits a command to the sound emission control device 80 by parallel communication.

  Further, on the output side of the MPU 62, a special electric drive unit 32b for opening and closing the open / close door 32a of the special electric prize winning device 32, and a general electric drive unit 34b for opening and closing the general electric utility 34a of the second operating port 34 are provided. The special figure unit 37 and the universal figure unit 38 are connected. Incidentally, the special figure unit 37 is provided with a special figure display part 37 a and a special figure holding display part 37 b, all of which are connected to the output side of the MPU 62. Similarly, the universal map unit 38 is provided with a universal map display unit 38 a and a universal map hold display unit 38 b, all of which are connected to the output side of the MPU 62. The main control board 61 is provided with various driver circuits, and the MPU 62 performs drive control of various drive units and various display units through the driver circuits.

  That is, in the opening / closing execution mode, the MPU 62 performs drive control of the special electricity driving unit 32b so that the special electricity prize winning device 32 is opened and closed. In addition, when the power utility item 34a is won, the MPU 62 performs drive control of the power unit 34b so that the power utility item 34a is opened and closed. In each game round, the display control of the special figure display unit 37a is executed in the MPU 62. In addition, when the lottery result indicating whether or not to open the electric utility item 34a is clearly indicated, the MPU 62 performs display control of the normal display portion 38a. In addition, when winning is awarded to the first working port 33 or the second working port 34, or when the variable display is started in the special figure display unit 37a, the display control of the special figure holding display unit 37b is executed in the MPU 62. When the winning to the through gate 35 is generated or when the variable display is started in the general map display unit 38a, the display control of the general map hold display unit 38b is executed in the MPU 62.

  The power failure monitoring board 65 relays between the main control board 61 and the power / fire control device 78, and monitors a DC stable voltage of 24 volts, which is the maximum voltage output from the power / fire control device 78. The payout control device 77 performs payout control of prize balls and rental balls by the payout device 76 based on the prize ball command received from the main control device 60.

  The power / launch control device 78 is connected to, for example, a commercial power source (external power source) in a game hall or the like. And based on the external electric power supplied from the commercial power supply, necessary operating power is generated for each of the main control board 61, the payout control device 77, etc., and the generated operating power is supplied. Incidentally, the power supply / launch control device 78 is provided with a power supply unit for power interruption such as a backup capacitor, and even when the power of the pachinko machine 10 is in an OFF state, the power supply unit for power interruption is connected to the main power supply unit. Power for storing and holding is supplied to the RAM 64 of the control device 60. In addition, the power source / launch control device 78 is responsible for launch control of the game ball launch mechanism 27, and the game ball launch mechanism 27 is driven when predetermined launch conditions are met.

  The sound light emission control device 80 controls the display control device 90 while driving and controlling the display light emitting portion 53 and the speaker portion 54 provided on the front door frame 14 based on various commands received from the main control device 60. It is. The display control device 90 executes display control of the symbol display device 41 based on the command received from the sound emission control device 80.

<Electrical configuration for performing various lotteries in the MPU 62 of the main controller 60>
Next, an electrical configuration for performing various lotteries in the MPU 62 of the main controller 60 will be described with reference to FIG.

  The MPU 62 uses lots of counter information in the game to perform jackpot occurrence lottery, display setting of the special symbol display unit 37a, symbol display setting of the symbol display device 41, display setting of the general symbol display unit 38a, and the like. More specifically, as shown in FIG. 5, when the winning random number counter C1 used for winning lottery, the big hit type counter C2 used for determining the big hit type, and the symbol display device 41 fluctuate and change. Reach random number counter C3 used for the reach generation lottery, random number initial value counter CINI used for setting the initial value of the hit random number counter C1, and the variation type for determining the display duration in the special figure display unit 37a and the symbol display unit 41 The counter CS is used. Further, the utility power release counter C4 used for the lottery to determine whether or not the utility power item 34a of the second working port 34 is set to the utility power release state is used. The counters C1 to C3, CINI, CS, and C4 are provided in various counter areas 64b of the RAM 64.

  Each of the counters C1 to C3, CINI, CS, and C4 is a loop counter that adds 1 to the previous value every time it is updated and returns to 0 after reaching the maximum value. Each counter is updated at short intervals. Information corresponding to the hit random number counter C1, the big hit type counter C2 and the reach random number counter C3 is provided as an acquisition information storage means in the RAM 64 when a winning to the first operating port 33 or the second operating port 34 occurs. It is stored in the reserved storage area 64a.

  The holding storage area 64a includes a holding area RE and an execution area AE. The holding area RE includes a first holding area RE1, a second holding area RE2, a third holding area RE3, and a fourth holding area RE4. In the winning history to the first operating port 33 or the second operating port 34, In addition, combinations of numerical information of the hit random number counter C1, the big hit type counter C2, and the reach random number counter C3 are stored as hold information in any of the hold areas RE1 to RE4.

  In this case, in the first reservation area RE1 to the fourth reservation area RE4, when a winning to the first operation port 33 or the second operation port 34 occurs continuously a plurality of times, the first reservation area RE1 → second Each numerical information is stored in time series in the order of the reserved area RE2 → the third reserved area RE3 → the fourth reserved area RE4. By providing the four holding areas RE1 to RE4 as described above, up to four game balls winning histories to the first operating port 33 or the second operating port 34 are stored and stored. .

  Note that the number that can be reserved and stored is not limited to four, but may be any other number such as two, three, or five or more.

  The execution area AE is an area for moving each numerical information stored in the first holding area RE1 of the holding area RE when starting the variable display of the special figure display section 37a, and starting one game round At this time, determination of success or failure is performed based on various numerical information stored in the execution area AE.

  Each of the counters will be described in detail.

  First, the general electric utility release counter C4 will be described. For example, the utility power release counter C4 is incremented by 1 in the range of 0 to 250, and returns to 0 after reaching the maximum value. The general electric utility release counter C4 is periodically updated and stored in the general electric power holding area 64c of the RAM 64 at a timing when a game ball wins the through gate 35. Then, at a predetermined timing, a lottery is performed as to whether or not to control the general utility 34a to the open state based on the stored value of the general utility release counter C4.

  In the pachinko machine 10, a plurality of types of support modes are set so that the modes of support by the electric utility 34 a are different from each other. Specifically, in the support mode, when compared with a situation in which a game ball is continuously being fired in the same manner with respect to the game area, the power utility 34a of the second working port 34 is per unit time. The high frequency support mode and the low frequency support mode are set so that the frequency of the open state is relatively high.

  In the high frequency support mode and the low frequency support mode, the probability of winning the electric power open state in the electric power open lottery using the electric power utility opening counter C4 is the same (for example, both 4/5). In the high frequency support mode, the number of times that the power utility 34a is in the open state is set more frequently than in the low frequency support mode, and one open time is set longer. Has been. In this case, in the high frequency support mode, when the open state of the public electric power is selected and the open state of the general electric utility 34a is generated a plurality of times, from the end of one open state to the start of the next open state. The closing time is set shorter than one opening time. Furthermore, in the high frequency support mode, the minimum reserved time (i.e., the normal map) is required for the next open train lottery after the first open train lottery than in the low frequency support mode. The display duration time for the display unit 38a is set short.

  As described above, in the high frequency support mode, the probability of winning a prize to the second operating port 34 is higher than in the low frequency support mode. In other words, in the low frequency support mode, there is a higher probability of winning the first operating port 33 than in the second operating port 34, but in the high frequency support mode, the second operation is performed more than in the first operating port 33. The probability of winning a prize in the mouth 34 is increased. When a winning is made to the second operation port 34, a predetermined number of game balls are paid out. Therefore, in the high frequency support mode, the player plays a game while not reducing the number of possessed balls so much. It can be carried out.

  Note that the configuration for increasing the frequency at which the high frequency support mode is set to the normal power open state per unit time as compared to the low frequency support mode is not limited to the above, for example, in the general power open lottery It is good also as a structure which raises the probability that it will be elected in an open state of a public train. In addition, a reserved time (for example, executed in the general map display unit 38a based on a winning to the through gate 35) is secured after the next public train opening lottery is performed. In a configuration in which a plurality of types of variable display time) are prepared, the high frequency support mode is set so that a short securing time is easily selected or the average secure time is shorter than the low frequency support mode. Also good. Furthermore, increase the number of times of opening, lengthen the opening time, and shorten the reserved time that will be secured when the next public train opening lottery is performed after the first public train opening lottery is performed, the reserved time concerned The advantage of the high-frequency support mode over the low-frequency support mode may be increased by applying any one condition or any combination of conditions among shortening the average time and increasing the winning probability.

  Next, the winning random number counter C1 will be described. For example, the winning random number counter C1 is incremented one by one within a range of 0 to 599, and after reaching the maximum value, returns to 0. In particular, when the winning random number counter C1 makes one round, the value of the initial random number counter CINI at that time is read as the initial value of the winning random number counter C1. The random number initial value counter CINI is a loop counter similar to the winning random number counter C1 (value = 0 to 599). The winning random number counter C1 is periodically updated, and stored in the holding storage area 64a of the RAM 64 at the timing when the game ball wins the first operation port 33 or the second operation port 34.

  The random number value for winning the jackpot is stored in the ROM 63 as a success / failure table. As the success / failure table, a success / failure table for the low probability mode and a success / failure table for the high probability mode are set. That is, in the pachinko machine 10, the low probability mode and the high probability mode are set as the lottery modes in the success / failure lottery means.

  In the gaming state in which the winning / failing table for the low probability mode is referred to at the time of the lottery, the number of random numbers that win the jackpot is two. On the other hand, in the gaming state in which the winning / failing table for the high probability mode is referred to at the time of the lottery, the number of random numbers that will win the jackpot is 20. If the winning probability in the high probability mode is higher than that in the low probability mode, the number of random numbers to be won is arbitrary.

  The jackpot type counter C2 is configured so that 1 is added in order within a range of 0 to 29, and after reaching the maximum value, it returns to 0. The big hit type counter C2 is periodically updated and stored in the holding storage area 64a at the timing when the game ball wins the first operation port 33 or the second operation port 34.

  In the pachinko machine 10, a plurality of jackpot results are set. The plurality of jackpot results are as follows: (1) a mode of opening / closing control of the special prize winning device 32 in the opening / closing execution mode, (2) lottery mode in the winning lottery means after the opening / closing execution mode ends, (3) A plurality of jackpot results are set by making a difference in the three conditions of the support mode in the general electric utility 34a of the two operation ports 34.

  As an aspect of the opening / closing control of the special electricity prize winning device 32 in the opening / closing execution mode, the occurrence frequency of winning in the special electricity prize winning device 32 from the start to the end of the opening / closing execution mode is relatively high. A frequency winning mode and a low frequency winning mode are set. Specifically, in any of the high-frequency winning mode and the low-frequency winning mode, the game is executed with a predetermined number of round games as an upper limit.

  Here, the round game is continued until either one of a predetermined upper limit continuation time elapses and a predetermined upper limit number of game balls win the special electric prize winning device 32 is satisfied. It is a game to play. In addition, the number of round games in the opening / closing execution mode triggered by the jackpot result is the same for a fixed number of rounds regardless of the type of jackpot result triggered by the transition. Specifically, the upper limit number of round games is set to 15 rounds regardless of which jackpot result is obtained.

  Moreover, in this pachinko machine 10, a plurality of types of opening modes of the special electricity prize winning device 32 are set with different opening durations from when the special electricity prize winning device 32 is opened until it is closed. Specifically, a long-time mode set to 29 sec, which is a long open duration, and a short-time mode set to 0.06 sec, which is a short duration shorter than the above long time, are set. Has been.

  In the present pachinko machine 10, when the launch operation device 28 is operated by the player, the game ball launching mechanism 27 is driven and controlled so that one game ball is launched toward the game area every 0.6 sec. The In the round game, the upper limit number of end conditions is set to nine. Then, in the long time mode among the above open modes, the open duration time is set longer than the product of the game ball firing period and one round game. On the other hand, in the short-time mode, an opening continuation time is set that is shorter than the product of the game ball launch cycle and one round game, more specifically, shorter than the game ball launch cycle. Therefore, when the opening is performed once in the long-time mode, it is expected that the special electric prize winning device 32 will receive the maximum number of winnings in one round game. When the number of times is released, it is expected that no prize will be given to the special electric prize winning device 32 or that there will be about one even if a prize is generated.

  In the high-frequency winning mode, the special electric prize winning device 32 is opened once in a long-time manner in each round game. On the other hand, in the low-frequency winning mode, the special prize winning device 32 is opened once in each round game in a short time mode.

  In addition, the number of times of opening / closing the special electric prize device 32 in the high frequency winning mode and the low frequency winning mode, the number of round games, the opening duration for one opening, and the upper limit number in one round game are those in the high frequency winning mode. However, the value is not limited to the above value as long as the occurrence frequency of the winning to the special electricity winning device 32 is higher than the low-frequency winning mode until the opening / closing execution mode starts and ends. It is.

  The game result distribution destination for the big hit type counter C2 is stored in the ROM 63 as a distribution table. And as such a distribution destination, a low probability big hit result, a low winning high probability big hit result, and the most advantageous big hit result are set.

  The low probability big hit result is a big hit result in which the open / close execution mode becomes the high-frequency winning mode, and after the open / close execution mode ends, the win / fail lottery mode becomes the low probability mode and the support mode becomes the high frequency support mode. However, the high-frequency support mode shifts to the low-frequency support mode when the number of games reaches the end reference number (specifically, 100 times) after the shift.

  The low-winning high-probability jackpot result is a jackpot result in which the opening / closing execution mode becomes the low-frequency winning mode, and after the opening / closing execution mode ends, the success / failure lottery mode becomes the high probability mode and the support mode becomes the high-frequency support mode. is there. These high-probability mode and high-frequency support mode are continued until the lottery result in the success / failure lottery becomes a big hit state win and shifts to the big win state by that.

  The most advantageous jackpot result is a jackpot result in which the opening / closing execution mode becomes the high-frequency winning mode, and after the opening / closing execution mode ends, the winning / raising lottery mode becomes the high probability mode and the support mode becomes the high-frequency support mode. These high-probability mode and high-frequency support mode are continued until the lottery result in the success / failure lottery becomes a big hit state win and shifts to the big win state by that.

  Note that the normal game state in relation to each of the above-described game states refers to a state in which the success / failure lottery mode is the low probability mode and the support mode is the low frequency support mode, not the open / close execution mode. Moreover, it is good also as a structure in which the low prize-winning high probability hit result is not set as a game result.

  In the distribution table, among the values of the big hit type counter C2 of “0 to 29”, “0 to 9” corresponds to the low probability big hit result, and “10 to 14” corresponds to the low winning high probability big hit result. “15 to 29” corresponds to the most favorable jackpot result.

  Next, the reach random number counter C3 will be described. For example, the reach random number counter C3 is incremented one by one within a range of 0 to 238, for example, and reaches a maximum value and then returns to 0. Here, in the pachinko machine 10, an expected effect is set as a kind of display effect in the symbol display device 41. The expected effect includes a symbol display device 41 that can display a variation of symbols, and in a gaming machine in which a final stop result is an assignment corresponding result in a game round that results in a predetermined jackpot result, the symbol display device 41 This is a display state for making the player think that it is a variable display state that is likely to be the above-mentioned giving correspondence result at the stage before the stop result is derived and displayed after the symbol variable display is started. In addition, about the provision corresponding | compatible result, the combination of the symbol to which the same number was attached | subjected on one of the effective lines is stopped and displayed.

  In the expected effect, two types of reach display and a notice display for expecting the occurrence of reach display and the generation of the result of giving correspondence at a stage before the reach display occurs are set.

  In the reach display, a combination of reach symbols is displayed by displaying symbols for a part of a plurality of symbol sequences displayed on the display surface 41a of the symbol display device 41, and the remaining combinations in that state are displayed. A display state in which a variable display of symbols is displayed in the symbol row is included. In addition, in the state where the combination of reach symbols is displayed as described above, the variation of the symbols is displayed in the remaining symbol rows, and a predetermined character or the like is displayed as a moving image on the background screen, and the reach effect is performed. In addition, there are those that perform a reach effect by displaying a predetermined character or the like as a moving image on substantially the entire display surface 41a after reducing or not displaying a combination of reach symbols.

  The notice display includes a plurality of symbol strings in a situation where symbols are variably displayed in all symbol columns after the symbol variable display is started on the display surface 41a of the symbol display device 41. In the situation where the symbols are variably displayed in the symbol row, a mode in which the character is displayed separately from the symbols on the symbol row is included. Moreover, what makes a background screen the predetermined aspect different from the previous aspect, and what makes the symbol on a symbol row the predetermined aspect different from the previous aspect are also included. Such a notice display can occur in any game times when reach display is performed and when reach display is not performed, but the case where reach display is performed is higher than the case where reach display is not performed. It is set to occur with probability.

  The reach display is executed regardless of the value of the reach random number counter C3 in the game times in which the combination of the same symbols is finally stopped. In addition, the game times corresponding to the jackpot result in which the same symbol combination is not stopped and displayed are not executed regardless of the value of the reach random number counter C3. Also, in the game times corresponding to the result of losing, it is executed when the reach random number counter C3 acquired at a predetermined timing with reference to the reach table stored in the ROM 63 corresponds to the occurrence of reach display.

  On the other hand, the determination as to whether or not to perform the notice display is performed not by the main control device 60 but by the sound emission control device 80. In this case, the sound emission control device 80 is more likely to generate a notice display and a notice display with a low appearance rate in the game times corresponding to any of the jackpot results compared to the game times corresponding to the missed results. A lottery process for displaying a notice is executed so as to satisfy at least one of the conditions of being easily generated. Incidentally, the lottery result is reflected when the game display effect is executed on the symbol display device 41.

  Next, the variation type counter CS will be described. The variation type counter CS is, for example, incremented by 1 within a range of 0 to 198, and returns to 0 after reaching the maximum value. The variation type counter CS is used when the MPU 62 determines the display continuation time in the special symbol display section 37a and the symbol display continuation time in the symbol display device 41. The variation type counter CS is updated once every time a normal process to be described later is executed once, and is repeatedly updated even within the remaining time in the normal process. Then, the buffer value of the variation type counter CS is acquired when the variation pattern is determined at the start of variation display in the special symbol display unit 37a and at the time of symbol variation start by the symbol display device 41.

<Processing configuration of main controller 60>
Next, each process performed in order to advance a game in MPU62 of the main controller 60 is demonstrated. The processing of the MPU 62 is roughly divided into main processing that is started when the power is turned on and timer interrupt processing that is started periodically (in the present embodiment at a cycle of 4 msec).

<Main processing>
First, the main process will be described with reference to the flowchart of FIG.

  In step S101, power-on wait processing is executed. In the power-on wait process, for example, the process waits without progressing to the next process until a predetermined time for wait (specifically 1 sec) elapses after the main process is activated. The operation start and initial setting of the symbol display device 41 are completed during the execution period of the power-on wait process. In the subsequent step S102, access to the RAM 64 is permitted, and in step S103, the internal function register of the MPU 62 is set.

  Thereafter, in step S104, it is determined whether or not the RAM erase switch provided in the power / fire control device 78 is manually operated. In subsequent step S105, whether or not “1” is set in the power failure flag of the RAM 64 is determined. Determine whether. In step S106, a checksum calculation process for calculating a checksum is executed. In subsequent step S107, whether or not the checksum matches the checksum stored when the power is turned off, that is, the validity of the stored data is checked. judge.

  In the pachinko machine 10, for example, when RAM data is initialized when the power is turned on, such as when a game hall starts business, the power is turned on while the RAM erase switch is pressed. Therefore, if the RAM erase switch is pressed, the process proceeds to step S108. Similarly, when the information on occurrence of power shutdown is not set, or when an abnormality of data stored and held is confirmed by the checksum, the process proceeds to step S108. In step S108, the RAM 64 is cleared. Thereafter, the process proceeds to step S109.

  On the other hand, if the RAM erase switch has not been pressed, step S109 is executed without executing step S108 on condition that the power failure flag is set to “1” and the checksum is normal. Proceed to In step S109, a power-on setting process is executed. In the power-on setting process, a predetermined area of the RAM 64 such as initialization of a power failure flag is set to an initial value, and a command corresponding to the current gaming state is transmitted to the sound emission control device 80 in order to recognize the current gaming state. To do.

  Thereafter, the process proceeds to the remaining process of steps S110 to S113. That is, the MPU 62 is configured to periodically execute the timer interrupt process, but a remaining time is generated between one timer interrupt process and the next timer interrupt process. The remaining time varies depending on the processing completion time of each timer interrupt process, but the remaining processes in steps S110 to S113 are repeatedly executed using such irregular time. In this regard, it can be said that the remaining processes in steps S110 to S113 are non-periodic processes that are performed irregularly.

  In the remaining process, first, in step S110, an interrupt prohibition setting is performed in order to prohibit the generation of the timer interrupt process. In the subsequent step S111, a random number initial value update process for updating the random number initial value counter CINI is executed, and a change counter update process for updating the change type counter CS is executed in step S112. In these update processes, the current numerical information is read from the corresponding counter of the RAM 64, the process of adding 1 to the read numerical information is executed, and then the process of overwriting the read-out counter is executed. In this case, each counter value is cleared to “0” when it reaches the maximum value. Thereafter, in step S113, an interrupt permission setting for switching from a state in which the generation of the timer interrupt process is prohibited to a state in which the timer interrupt process is permitted is performed. If the process of step S113 is performed, it will return to step S110 and will repeat the process of step S110-step S113.

<Timer interrupt processing>
Next, timer interrupt processing will be described with reference to the flowchart of FIG. The timer interrupt process is executed periodically (for example, at a cycle of 4 msec).

  First, in step S201, a power failure information storage process is executed. In the power outage information storage process, it is monitored whether or not a power outage signal corresponding to the occurrence of power interruption is received from the power outage monitoring board 65, and when the occurrence of a power outage is specified, the process during power outage is executed.

  In subsequent step S202, a lottery random number update process is executed. In the lottery random number update process, the big hit random number counter C1, the big hit type counter C2, the reach random number counter C3, and the universal utility release counter C4 are updated. Specifically, the current numerical information is sequentially read from the jackpot random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the universal utility release counter C4, and a process of adding 1 to each of the read numerical information is executed. Later, a process of overwriting the reading source counter is executed. In this case, each counter value is cleared to “0” when it reaches the maximum value.

  Thereafter, in step S203, the random number initial value update process is executed in the same manner as in step S111, and in step S204, the variation counter update process is executed in the same manner as in step S112.

  In subsequent step S205, a fraud detection process for monitoring whether or not a predetermined event set as a fraud monitoring target has occurred is executed. In the fraud detection process, occurrence of a plurality of types of events is monitored, and by confirming that a predetermined event has occurred, “1” is set to a game stop flag provided in the RAM 64.

  In the subsequent step S206, it is determined whether or not the progress of the game is stopped by determining whether or not “1” is set in the game stop flag. If a negative determination is made in step S206, the processing after step S207 is executed.

  In step S207, port output processing is executed. In the port output process, when output information is set in the previous timer interrupt process, a process for performing output corresponding to the output information to the various drive units 32b and 34b is executed. For example, when information for switching the special electric prize winning device 32 to the open state is set, output of a drive signal to the special electric drive unit 32b is started, and information for switching to the closed state is set. Stops the output of the drive signal. In addition, when the information for switching the general utility 34a of the second working port 34 to the open state is set, output of the drive signal to the general power drive unit 34b is started, and the closed state should be switched to. When the information is set, the output of the drive signal is stopped.

  In a succeeding step S208, a reading process is executed. In the reading process, signals other than the power failure signal and the winning signal are read, and the read information is stored for use in future processing.

  In subsequent step S209, a winning detection process is executed. In the winning detection process, the signals received from the winning detection sensors 66a to 66e are read, and the general winning port 31, the special prize winning device 32, the first operating port 33, the second operating port 34, and the through gate 35 are read. A process for specifying the presence or absence of winning is executed.

  In the subsequent step S210, timer update processing for updating the numerical information of a plurality of types of timer counters provided in the RAM 64 is executed. In this case, the timer counter that is updated by subtracting the stored numerical information is handled in an integrated manner. However, both the updating of the subtracting timer counter and the updating of the adding timer counter are performed collectively. It is good also as a structure.

  In the subsequent step S211, a launch control process for controlling the launch of the game ball is executed. In a situation where the launch operation to the launch operation device 28 is continued, as described above, one game ball is launched at a predetermined launch period of 0.6 sec.

  In the subsequent step S212, as input state monitoring processing, disconnection confirmation of the winning detection sensors 66a to 66e and opening confirmation of the gaming machine body 12 and the front door frame 14 are confirmed based on the information read in the reading processing in step S208. Do.

  In the subsequent step S213, a special figure special electric control process for performing execution control of the game times and execution control of the opening / closing execution mode is executed. In the special figure special power control process, when a winning to the first operation port 33 or the second operation port 34 occurs in a situation where the number of the hold information stored in the hold storage area 64a is less than the upper limit number, A process of storing the numerical information of the jackpot random number counter C1, the jackpot type counter C2 and the reach random number counter C3 at the time as the hold information in the hold storage area 64a in time series is executed. Also, in the special figure special electric control process, whether or not the hold information corresponds to the big win is determined on the condition that the hold information is not stored during the game rotation and the opening / closing execution mode and is stored. If it corresponds to the process and the jackpot winning, a distribution determination process for determining which jackpot result the hold information corresponds to is executed. In addition, in the special figure special power control process, not only the success / failure determination process and the distribution determination process, but if the hold information does not correspond to the big win, whether the hold information corresponds to the occurrence of reach. A reach determination process is performed, and a process of selecting a game time duration using the numerical information of the variation type counter CS at that time is executed. Then, the change command including the duration information according to the result of each process and the type command including the game result information are transmitted to the sound emission control device 80, and the pattern in the special figure display unit 37a is displayed. Start the variable display. As a result, one game round is started, and an effect for game round is started on the special figure display unit 37a and the symbol display device 41.

  Also, in the special figure special electric control process, during the execution of one game round, it is determined whether or not it is the end timing of that game round. Then, the process of ending the game round is executed. In this case, a final stop command indicating that the game round should be ended is transmitted to the sound emission control device 80. Further, in the special figure special electric control process, when the result of the game times is a result corresponding to the transition to the opening / closing execution mode, a process for starting the opening / closing execution mode is executed. At the start, an opening command indicating that the opening / closing execution mode is started is transmitted to the sound emission control device 80. In the special figure special electric control process, a process for starting each round game and a process for ending each round game are executed. In each of these processes, an open command indicating that the round game is started is transmitted to the sound emission control device 80, and a close command indicating that the round game is ended is transmitted to the sound emission control device 80. Further, in the special figure special electric control process, when the opening / closing execution mode is ended, an ending command indicating that is sent to the sound emission control device 80, and the success / failure lottery mode and the support mode after the opening / closing execution mode are set. Execute the process.

  After executing the special figure special electric control process of step S213 in the timer interruption process, the normal figure electric power control process is executed in step S214. In the ordinary map / electric power control process, when a winning to the through gate 35 is generated, a process for acquiring the retained information on the ordinary map side is executed and the retained information on the ordinary map side is stored. In addition, a release determination is performed on the hold information, and a process for performing an effect for a normal diagram is executed using the release determination as a trigger. Further, based on the result of the opening determination, a process for opening and closing the utility wire 34a of the second working port 34 is executed.

  In the subsequent step S215, based on the processing results of the immediately preceding steps S213 and S214, output information is set for reflecting the increase / decrease number of the hold information related to the special figure display unit 37a in the special figure hold display unit 37b. The output information for reflecting the increase / decrease number of the hold information related to the general map display unit 38a to the general map hold display unit 38b is set. In step S215, the output information for updating the display content of the special figure display unit 37a is set based on the processing results of the immediately preceding steps S213 and S214, and the display content of the general map display unit 38a is set. Set the output information to be updated.

  In the following step S216, the contents of the command and signal received from the payout control device 77 are confirmed, and a payout state receiving process for performing a process corresponding to the confirmation result is executed. In step S217, a payout output process for setting a prize ball command as an output target is executed. In the subsequent step S218, an external information setting process for controlling the start and end of the output of the external signal according to the processing results of the various processes executed in the current timer interrupt process is executed. Thereafter, the timer interrupt process is terminated.

<Electrical configuration related to production execution control>
Next, an electrical configuration for performing execution control will be described with reference to the block diagram of FIG.

  A sound emission control device 80 is provided as a control device for controlling the execution of the effect based on an instruction from the main control device 60. As shown in FIG. 8, the sound emission control device 80 includes a sound emission control board 101 on which a sound light SOC 102, a sound light ROM 103, and an amplifier circuit 104 are mounted. The sound light SOC 102 includes a control core 111, a sound output core 112, a sound data processing unit 113, and a memory controller 114, and the sound light SOC 102 is configured by integrating these elements into one chip.

  The control core 111 determines the specific content of the effect based on the command received from the main control device 60 and executes the light emission control of the display light emitting unit 53 according to the determined content. Further, the control core 111 performs data setting according to the determined content of the effect on the register 131 provided in the sound output core 112, and displays a command according to the determined content of the display on the display control device 90. Send to. As a result, the sound output core 112 performs sound output control in a manner in accordance with the content instructed from the control core 111, and the display control device 90 performs display control in a manner in accordance with the content instructed from the control core 111. Run. Incidentally, the data setting for the register 131 of the sound output core 112 by the control core 111 is performed through the data bus SL that electrically connects the control core 111 and the sound output core 112 in the sound light SOC 102. Note that the control core 111 and the sound output core 112 are capable of bidirectional communication through the data bus SL, and data setting is performed from the control core 111 to the sound output core 112 as described above. A signal indicating that sound is being output is transmitted from 112 to the control core 111.

  In addition to the CPU 121, which is a central processing unit including a control unit and a calculation unit, the control core 111 is used when reading program data and control data stored in the sound ROM 103 in advance and executing programs. In this case, a RAM 122 for temporarily storing necessary data is incorporated. The RAM 122 is configured to use a memory (that is, a volatile storage unit) that requires an external power supply for storage and retention, such as SRAM and DRAM, for both reading and writing. The time required for reading out is faster than that of the sound and light ROM 103 when compared with the data capacities. The data capacity of the RAM 122 has a data capacity of many bytes so that a plurality of data can be stored and held simultaneously, and has a data capacity in units of kilobytes or megabytes. Specifically, it has a data capacity of about 4 megabytes. The data capacity is smaller than the data capacity of the sound light ROM 103. However, the data capacity of the RAM 122 is not limited to this, and is arbitrary as long as the control core 111 can suitably execute control.

  The control core 111 also has a built-in DMA 123 that instructs the memory controller 114 to read data from the sound ROM 103 based on an instruction from the CPU 121. When data corresponding to the data read instruction is written into the internal register of the DMA 123 by the CPU 121, the DMA 123 instructs the memory controller 114 to read the data until all of the data corresponding to the read instruction is read to the RAM 122. Send address data. The address data is transmitted in synchronization with a clock signal periodically transmitted from a clock circuit built in the DMA 123 (for example, 4 MHz).

  The sound output core 112 performs sound output control of the speaker unit 54 in accordance with the contents of the effect determined by the control core 111. The sound output core 112 includes a register 131, an HWD 132, an SCM 133, and a data transfer unit 134.

  The register 131 has a function as a storage means for temporarily storing various data used in the sound output core 112, and a memory that requires an external power supply for storing and holding is used for both reading and writing. It is configured to be used. In addition, random access is possible, and when compared with the same data capacity, the time required for reading is faster than that of the sound ROM 103. The register 131 has a data capacity of many bytes so that a plurality of data can be stored and held simultaneously, and has a data capacity in units of kilobytes or megabytes. Specifically, it has a data capacity of about 2 megabytes. The data capacity is smaller than the data capacity of the sound ROM 103 and smaller than the data capacity of the RAM 122 of the control core 111. However, the data capacity of the register 131 is not limited to this, and is arbitrary as long as the sound output core 112 can suitably execute control.

  The HWD 132 and the SCM 133 have a function of creating digital musical tone data using sound data read from the sound ROM 103 according to sequence data and parameter data transmitted from the control core 111 and stored in the register 131. The sequence data includes time data indicating the output start timing and output order of a series of sounds, and the parameter data includes data that determines the pitch, volume and tone of the sound at a predetermined timing. Yes. These sequence data and parameter data are set as a set of data corresponding to each other, and a series of sound outputs is possible by using the set of sequence data and parameter data. The period of sound output determined by a set of sequence data and parameter data is constant for a specific time regardless of the type of sequence data and parameter data. For example, one game and one opening / closing are executed. It is 2.1 sec shorter than the mode. However, it is not limited to this, and may be shorter or longer than 2.1 sec. In addition, the sound output period determined by the sequence data and parameter data may vary depending on the type of the data.

  The HWD 132 creates digital musical sound data for reproducing pre-sampled recording data, and creates sine wave data by using the HWD recording data stored in the sound ROM 103 in advance. The recorded data can be played back. Note that the recording data may be compressed data such as MP3 or non-compressed data. The SCM 133 does not create digital musical tone data from recording data for a predetermined time, but creates digital musical tone data by combining the rectangular wave data stored in advance in the sound ROM 103 in time series. Sound (so-called pico-pico sound) can be reproduced.

  Here, the configuration of the register 131 used for creating digital musical tone data in the HWD 132 and the SCM 133 will be described with reference to the explanatory diagram of FIG. The register 131 is provided with a sequence area 141, a parameter area 142, an HWD area 143, and an SCM area 144. The sequence data already described is written in the sequence area 141, and the parameter data already described is written in the parameter area 142.

  The HWD 132 reads the recording data stored in the sound ROM 103 into the HWD area 143 by referring to the sequence data written in the sequence area 141 and the parameter data written in the parameter area 142, and the recording The recording sound can be output by creating digital musical sound data from the data. The HWD area 143 is provided with a first CH area 143a to a 16th CH area 143p, and digital musical tone data based on different recording data can be created in each of the CH areas 143a to 143p. As a result, sounds corresponding to a plurality of different recording data can be output simultaneously.

  By referring to the sequence data written in the sequence area 141 and the parameter data written in the parameter area 142, the SCM 133 reads the rectangular wave data stored in the sound ROM 103 into the SCM area 144, and the rectangular data Electronic musical sound can be output by creating digital musical sound data from wave data. The SCM area 144 is provided with a first CH area 144a to a 16th CH area 144p, and different digital musical tone data can be created in each of the CH areas 144a to 144p. Thereby, a plurality of different electronic sounds can be output simultaneously.

  Each of the first CH area 143a to the 16th CH area 143p of the HWD area 143 and the first CH area 144a to the 16th CH area 144p of the SCM area 144 is an area where two created digital musical tone data can be stored. In the middle of performing sound output control using digital musical sound data created in one storable area, digital corresponding to the next execution period with respect to the execution period of the sound output control Musical sound data is created in the other storable area. This makes it possible to create necessary digital musical sound data in parallel during the next sound output control execution period while outputting sound, and to continuously output sound.

  Returning to the description of FIG. 8, the sound data processing unit 113 of the sound light SOC 102 has a function as a digital / analog converter, and the digital musical sound data and SCM area created in the HWD area 143 of the register 131. The digital musical tone data created in 144 is converted into an analog sound signal and output to the amplifier circuit 104 formed on the sound emission control board 101. The amplifier circuit 104 amplifies the output level of the analog sound signal to a level corresponding to the volume set by the volume, and outputs the amplified sound signal to the speaker unit 54. Thereby, a predetermined sound is output from the speaker unit 54. The sound data processing unit 113 synthesizes the digital musical sound data when the digital musical sound data is simultaneously created in the plurality of CH areas 143a to 143p in the HWD area 143, and also in the SCM area 144. When digital musical tone data is simultaneously created in a plurality of CH areas 144a to 144p, the digital musical tone data is synthesized. When digital musical tone data is created in each of the HWD area 143 and the SCM area 144, the digital musical tone data is synthesized. When the synthesis is performed in this way, the synthesized digital musical tone data is converted into an analog sound signal, amplified by the amplifier circuit 104 as described above, and then output to the speaker unit 54. Thereby, a plurality of different sounds can be simultaneously output from the speaker unit 54.

  As described above, when outputting sound, sound data, which is either recording data or rectangular wave data, is read out from the sound ROM 103 to the register 131. The sound data is read out in the sequence area 141 of the register 131. Is performed by the data transfer unit 134 of the sound output core 112 based on the sequence data stored in

  Specifically, referring to the explanatory diagram of FIG. 10 showing an example of the sequence data, the sequence data SD has pointer data set corresponding to the processing timing of the sound output core 112 defined therein. The contents data of the sound output and the contents data of the data transfer are determined in correspondence with each pointer data. The processing timing of the sound output core 112 is generated in synchronization with a clock signal periodically transmitted from a clock circuit (not shown) built in the sound output core 112. In this case, the cycle of the clock signal is shorter than the cycle of the clock signal of the DMA 123, specifically 10 MHz. When the processing timing of the sound output core 112 is reached, the HWD 132, the SCM 133, and the data transfer unit 134 perform operations corresponding to the sequence data and parameter data, respectively.

  The content data of the sound output in the sequence data SD is used to create digital musical sound data for each channel in the HWD 132 and the SCM 133. In this case, the content data of the sound output is set corresponding to the pointer data, and the creation of the digital musical sound data based on the content data of the sound output set corresponding to each pointer data is transferred to the register 131 in advance. This is performed using the sound data.

  The content data of the data transfer in the sequence data SD is used by the data transfer unit 134 to specify the data read timing from the sound ROM 103, and in the area of the sound ROM 103 in which the data to be read is stored. Used to specify address data. The content data of the data transfer is such that a plurality of predetermined pointer data exist between the read timing of sound data corresponding to one channel and the read timing of sound data corresponding to the next channel. Read instruction data is set. In the data read instruction data, data for reading out sound data having a data amount capable of outputting sound for a predetermined time is set, and the sound data is 1 for either the HWD 132 or the SCM 133. It corresponds to the number of channels. Therefore, when a plurality of digital musical tone data is synthesized and a sound is output, a data read instruction corresponding to the number of digital musical tone data is issued. The sound data read based on one data read instruction corresponds to data that enables a sound output for 700 μsec as the predetermined time in the corresponding channel. In this case, the HWD 132 and the SCM 133 each have 16 channels, and the time required to read out sound data for 700 μsec for all of these 16 channels is shorter than 700 μsec. Accordingly, it is possible to create digital musical sound data for enabling output of the sound for the next predetermined time continuous with respect to the predetermined time while outputting the sound for the predetermined time.

  Each of the DMA 123 of the control core 111 and the data transfer unit 134 of the sound output core 112 reads data from the common sound light ROM 103. The sound ROM 103 is configured to use, as a read-only memory, a memory (that is, a non-volatile storage means) that does not require external power supply for storing and holding. Specifically, a NOR flash memory is used as the sound ROM 103, but a NAND flash memory may be used. The sound ROM 103 stores various control programs and fixed value data used when executing processing according to the programs.

  The data structure of the sound light ROM 103 will be described in detail with reference to FIG. In the sound ROM 103, program data (1), program data (2),..., Program data (L) for executing the effect control processing by the CPU 121 of the control core 111 are stored in advance. It is remembered. By using these program data, the CPU 121 executes main processing and timer interrupt processing, which will be described later. The sound ROM 103 stores processing data (1), processing data (2),..., Processing data (M) in advance. These processing data include a data table used for executing each effect, sequence data and parameter data for providing to the sound output core 112. The sound ROM 103 stores command data (1), command data (2),..., Command data (N) in advance. These command data are used by the CPU 121 of the control core 111 to instruct the display control device 90 about the contents of the effect.

  In the sound ROM 103, in addition to the data used for executing the processing by the CPU 121 of the control core 111 as described above, light emission data (1), light emission data (2),. (P) is stored, and sound data (1), sound data (2),..., Sound data (Q) are stored. In each light emission data, information on the type, lighting period, and lighting order of the light emitting units to be turned on among the display light emitting units 53 is set in a predetermined production period. It differs depending on the type of light emission data. Each light emission data stored in the sound ROM 103 has different light emission control periods and different light emission pattern contents. Each sound data includes recording data composed of a sine wave and rectangular wave data used for outputting an electronic sound.

  As shown in FIG. 8, the sound light ROM 103 is electrically connected to the memory controller 114 of the sound light SOC 102 via the address bus SL1 and the data bus SL2. The memory controller 114 is electrically connected to the control core 111 via the address bus SL3 and the data bus SL4, and is also electrically connected to the sound output core 112 via the address bus SL5 and the data bus SL6. .

  Address data to be read is sent from the DMA 123 of the control core 111 to the memory controller 114 via the address bus SL3. The memory controller 114 includes a control-side address buffer 114a for storing the address data received from the DMA 123. When new address data is received from the DMA 123 in a situation where unprocessed address data is not stored, Address data is stored in the control-side address buffer 114a. At this time, a normal reception signal indicating that the address data has been normally received is transmitted from the memory controller 114 to the DMA 123 via the data bus SL4, thereby specifying that the address data has been normally received by the DMA 123. The On the other hand, when new address data is received from the DMA 123 while unprocessed address data is stored in the control-side address buffer 114a, the address data is not stored in the control-side address buffer 114a. In this case, since the normal acceptance signal is not transmitted to the DMA 123, the DMA 123 specifies that the same address data needs to be transmitted again.

  In the case of corresponding to the address data transmitted from the DMA 123, the memory controller 114 transmits the address data via the address bus SL1 to the sound ROM 103, and the data corresponding to the address data via the data bus SL2 is transmitted to the sound light. Received from the ROM 103. Then, the received data is transmitted to the RAM 122 of the control core 111 or the internal register of the CPU 121 via the data bus SL4.

  Address data to be read out is transmitted from the data transfer unit 134 of the sound output core 112 to the memory controller 114 via the address bus SL5. The memory controller 114 includes a sound output side address buffer 114b for storing the address data received from the data transfer unit 134, and a new address is received from the data transfer unit 134 in a situation where unprocessed address data is not stored. When data is received, the address data is stored in the sound output side address buffer 114b. At this time, a normal reception signal indicating that the address data has been normally received is transmitted from the memory controller 114 to the data transfer unit 134 via the data bus SL6, whereby the address data is normally received by the data transfer unit 134. It has been identified. On the other hand, when new address data is received from the data transfer unit 134 in a state where unprocessed address data is stored in the sound output side address buffer 114b, the address data is not stored in the sound output side address buffer 114b. In this case, since the normal acceptance signal is not transmitted to the data transfer unit 134, the data transfer unit 134 specifies that the same address data needs to be transmitted again.

  When corresponding to the address data transmitted from the data transfer unit 134, the memory controller 114 transmits the address data to the sound ROM 103 via the address bus SL1, and data corresponding to the address data via the data bus SL2. Are received from the sound ROM 103. Then, the received data is transmitted to the register 131 of the sound output core 112 via the data bus SL6.

  The memory controller 114 includes a clock circuit, and processing in the memory controller 114 is performed in synchronization with a clock signal periodically transmitted from the clock circuit. In this case, the cycle of the clock signal is shorter than the cycle of the clock signal of the DMA 123 and the cycle of the clock signal of the sound output core 112, specifically, 15 MHz.

<Various types of processing executed in the acoustic light SOC 102>
Next, various processes executed in the sound light SOC 102 will be described. First, processing executed by the CPU 121 of the control core 111 will be described. The CPU 121 executes a main process that is activated at a timing when the supply of operating power to the CPU 121 is started, and a timer interrupt process that is activated by periodically interrupting the main process.

<Main processing of CPU 121>
FIG. 12 is a flowchart showing the main process. First, in step S301, initialization processing of the RAM 122 is executed. Specifically, each area of the RAM 122 is cleared to “0”. Thereafter, in step S302, the DMA 123 is instructed to read data when the power is turned on. Note that a program for executing the processing of step S301 and step S302 is stored in advance in a boot buffer (not shown) provided in the control core 111, and the CPU 121 can execute the boot buffer when the supply of operating power is started. Steps S301 and S302 are executed by executing a process corresponding to the program stored in step S301. Further, the processing in step S303 described later is also performed according to the program stored in the boot buffer.

  The DMA 123 receives the data read instruction when the power is turned on, and transmits the corresponding address data to the memory controller 114. By receiving the address data, the memory controller 114 receives program data (1), program data (2),..., Program data (L) stored in the sound ROM 103 in advance, Reads processing data (1), processing data (2), ..., processing data (M), command data (1), command data (2), ..., command data (N) Then, the data is transferred to the RAM 122 of the control core 111. As a result, the entire program data for executing the processing after step S304 and the timer interrupt processing in the CPU 121 is written into the RAM 122. Therefore, the CPU 121 uses the program data written in the RAM 122 when executing the processing after step S304 and the timer interrupt processing. In addition, all data necessary for executing these processes, except for the light emission data, is written in advance in the RAM 122.

  Thereafter, in step S303, the CPU 121 determines whether the data read completion signal is received from the DMA 123, thereby determining whether the data read corresponding to the data read instruction at power-on is completed. judge. If the reading of the data is not completed, the process waits in step S303.

  Here, referring to the time chart of FIG. 13, the relationship between the period during which the power-on wait process is executed in the MPU 62 of the main controller 60 and the period during which the control core 111 reads data at power-on. explain. FIG. 13A shows a period during which the power-on wait process is executed in the MPU 62 of the main controller 60, and FIG. 13B shows the timing at which the data read instruction at the time of power-on is executed in the CPU 121 of the control core 111. FIG. 13C shows a period required for data corresponding to the data read instruction to be read from the sound light ROM 103.

  When the supply of operating power to the MPU 62 of the main control device 60 is started at the timing t1, the power-on wait process is executed in the MPU 62 as shown in FIG. As a result, the MPU 62 of the main control device 60 waits without proceeding to the next process until the wait time (specifically, 1 sec) has elapsed.

  Immediately after the operation power supply to the MPU 62 of the main controller 60 is started, the operation power supply to the control core 111 is started, and at the timing t2, as shown in FIG. The CPU 121 issues a data read instruction when the power is turned on. As a result, as shown in FIG. 13C, data corresponding to the data read instruction is transferred from the sound ROM 103 to the RAM 122 of the control core 111. The data transfer is completed at a timing t3 that is a timing before a timing t4 that is a timing at which the power-on wait process is completed in the MPU 62 of the main controller 60.

  With the above-described configuration, all the program data, processing data, and command data required in the CPU 121 of the control core 111 are utilized (using the period during which the power-on wait process is executed in the MPU 62 of the main control device 60 ( Hereinafter, these data are referred to as a series of data corresponding to the program). As a result, when it is time to transmit a command from the MPU 62 of the main control device 60, the CPU 121 of the control core 111 executes all processing using the data written in the RAM 122 of the control core 111. Is possible. Note that reading of a series of data corresponding to a program requires about 8 msec at the longest.

  Returning to the description of the main process (FIG. 12), when data reading is completed (step S303: YES), an interrupt permission is set in step S304. As a result, a periodic interruption of the timer interruption process (FIG. 17) is permitted. Thereafter, in step S305, it is determined whether or not the normal determination is being executed by determining whether or not “1” is set in the normal determination execution flag provided in the RAM 122. To do.

  The normal determination is a determination for specifying whether or not a series of program-corresponding data read to the RAM 122 of the control core 111 when the power is turned on is abnormal data due to electrical noise or the like. . In the normality determination, a series of program-corresponding data is read again from the sound ROM 103 to the RAM 122 of the control core 111, and the read program-corresponding series of data and the program-corresponding program already read to the RAM 122 are read. Whether or not the series of data matches is specified. That is, as shown in the explanatory diagrams of FIGS. 14A and 14B, the RAM 122 of the control core 111 has a program-corresponding area 122a as a dedicated area for reading a series of data corresponding to the program when the power is turned on. Apart from that, a general-purpose area 122b for temporarily storing and holding data for light emission control and other processing is provided. As shown in FIG. 14A, a series of program-corresponding data is read into the program-corresponding area 122a when the power is turned on. On the other hand, when the normality determination is started, as shown in FIG. 14 (b), the program corresponding to the general-purpose area 122b in the state where the series of data corresponding to the program has already been read to the program corresponding area 122a. Are newly read out from the sound ROM 103. Then, it is determined whether or not the corresponding bits of the series data corresponding to these programs all match.

  Specifically, regarding the processing configuration for performing the normal determination, if “1” is not set in the normal determination executing flag (step S305: NO), is the normal determination start timing in step S306? Determine whether or not. The start timing of normality determination occurs when 32 msec has elapsed since the affirmative determination was made in step S303, or when 32 msec had elapsed since the previous affirmative determination was made in step S306.

  If it is the normal determination start timing, a normal determination data read instruction is issued to the DMA 123 in step S307. The DMA 123 receives an instruction to read data for normality determination, and transmits address data corresponding to the instruction to the memory controller 114, so that a series of data corresponding to the program to the general-purpose area 122b of the RAM 122 is transmitted to the memory controller 114. Start reading. After that, in step S308, “1” is set in the normal determination execution flag in the RAM 122, and then the process returns to step S304. When “1” is set in the normal determination execution flag, the normal determination process is executed in step S309. When the normal determination processing is completed for all of the series of program-compatible data having a data capacity of 512 bytes, the normal determination in-progress flag is cleared to “0”.

<Normal determination processing of CPU 121>
FIG. 15 is a flowchart showing normality determination processing.

  When the reading of the series data corresponding to the program to the general-purpose area 122b is completed (step S401: YES), the data collation process is executed in step S402. In the data collation processing, 4-byte data corresponding to each other is read from each of the series of data corresponding to the program stored in the program corresponding area 122a of the RAM 122 and the series of data corresponding to the program stored in the general-purpose area 122b. By executing logical operation processing such as XOR processing, it is determined whether or not these 4-byte data match.

  If all the bits of the 4-byte data match (step S403: YES), the normality determination process is terminated as it is. In other words, when the normality is determined, the data matching process is not executed for the entire series of 512-byte data corresponding to the program, but is performed in units of 4 bytes that are the bytes to be checked. Here, since the interrupt of the timer interrupt process (FIG. 17) is not prohibited when the data collation process is started, the timer interrupt process (FIG. 17) occurs even during the data collation process.

  If some of the 4 bytes of data do not match (step S403: NO), the data rewriting process shown in steps S404 to S407 is executed. Specifically, execution of timer interrupt processing (FIG. 17) is prohibited in step S404, and a data rewrite instruction is issued to DMA 123 in step S405. Upon receiving the data rewrite instruction, the DMA 123 transmits address data corresponding to the instruction to the memory controller 114, thereby reading the program corresponding series data to the program corresponding area 122 a of the RAM 122 to the memory controller 114. Let it begin. In this case, a series of newly read program-corresponding data is overwritten on the program-corresponding area 122a. Note that the program for executing the process is excluded from overwriting so that the process of step S406 can be executed even during the overwriting, and the excluded program is not included in the execution of the process of step S407. Cleared.

  When rewriting of a series of program-corresponding data for the program-corresponding area 122a is completed (step S406: YES), the execution of the timer interrupt process (FIG. 17) is permitted in step S407, and then the normality determination process is terminated.

  A state in which the normality determination is executed will be described with reference to the time chart of FIG. 16A shows the start timing of normality determination, FIG. 16B shows the period during which data is read from the general-purpose area 122b, and FIG. 16C shows normality determination being executed. FIG. 16D shows a period in which overwriting to the program corresponding area 122a is executed.

  When the normal determination start timing is reached as shown in FIG. 16A at the timing t1, reading of a series of data corresponding to the program to the general-purpose area 122b of the RAM 122 is started as shown in FIG. 16B. . Thereafter, when the reading of the series of data corresponding to the program is completed at the timing t2, normality determination is started as shown in FIG. Then, the normality determination is completed at the timing t3 without causing a data mismatch. In this case, the program corresponding area 122a is not overwritten as shown in FIG.

  On the other hand, when the data mismatch occurs as shown in the example of the timing from t4 to t7, it is the timing when the mismatch is found as shown in FIGS. 16 (c) and 16 (d). At the timing of t6, overwriting of a series of data to the program corresponding area 122a is started. As a result, in the configuration in which various processes are executed by the CPU 121 of the control core 111 using the series of data corresponding to the program read to the RAM 122 when the power is turned on, the series of data remains in an abnormal state. It is possible to prevent various processes in the CPU 121 from continuing.

  In addition, in the normal determination, the collation process is not executed for the entire series of data corresponding to the program at once, but the collation process is executed in units of 4 bytes that are the bytes to be collated. It is possible to start rewriting of a series of data corresponding to a program at the timing when the collation process in units of 4 bytes is completed. As a result, when an abnormality occurs in a series of data corresponding to a program, the rewriting can be started at an early stage.

<Timer interrupt processing of CPU 121>
Next, a timer interrupt process that is executed periodically (for example, by a period of 2 msec) by the CPU 121 of the control core 111 will be described with reference to the flowchart of FIG.

  First, in step S501, it is determined whether a new command has been received from the MPU 62 of the main controller 60. This command includes the combination of the variation command and the type command, the final stop command, the opening command, the opening command, the closing command, and the ending command that have already been described.

  The RAM 122 of the control core 111 is provided with a ring buffer for enabling storage and reading of commands received from the MPU 62 of the main control device 60, and the commands received from the MPU 62 of the main control device 60 are stored in the ring buffer. And sequentially read out in accordance with the stored order. In this case, the command storage process for the ring buffer is performed in a command receiving circuit provided separately from the CPU 121 in the control core 111. The command reception circuit is activated when a new command is received from the MPU 62 of the main control device 60, regardless of whether or not the interrupt prohibition is set in the CPU 121 of the control core 111, and the newly received command Is stored in the ring buffer. In this way, by storing the command regardless of whether or not the interrupt prohibition is set, for example, the occurrence of data abnormality is identified in the above-described normal determination, and the series of data corresponding to the command is rewritten. Even in a situation where the command is received, the command received from the MPU 62 of the main control device 60 can be stored and held in the RAM 122 without invalidating the command. Then, after rewriting the series of data is completed, the CPU 121 of the control core 111 can execute processing corresponding to the command.

  If an unprocessed command is stored in the ring buffer of the RAM 122 (step S501: YES), a data table for enabling the presentation or notification corresponding to the command to be read this time in step S502 is stored in the RAM 122. The program is read from the program corresponding area 122a to the general-purpose area 122b and set as an execution target. Thereafter, in step S503, a display command corresponding to the data table read this time is transmitted to the display control device 90. Thereby, the display control device 90 controls the display of the symbol display device 41 so that a display effect corresponding to the data table is performed.

  If a negative determination is made in step S501, or if the process of step S503 is executed, the light emission data read instruction timing is referred to in step S504 by referring to the data table set as the execution target in the RAM 122. It is determined whether or not. If it is the read instruction timing of the light emission data, the read instruction of the light emission data is issued to the DMA 123 in step S505. When the DMA 123 receives a light emission data read instruction and transmits the corresponding address data to the memory controller 114, the memory controller 114 causes the memory controller 114 to start reading light emission data to the general-purpose area 122b of the RAM 122.

  If a negative determination is made in step S504, or if the process of step S505 is executed, in step S506, the data table set as the execution target in the RAM 122 is referred to at the execution timing of the light emission control. It is determined whether or not there is. If it is the execution timing of the light emission control, the light emission control of the display light emitting unit 53 is performed using the light emission data already read into the general-purpose area 122b of the RAM 122 in step S507.

  If a negative determination is made in step S506, or if the process of step S507 is executed, the sound output control instruction timing is determined by referring to the data table set as the execution target in the RAM 122 in step S508. It is determined whether or not. If it is the sound output control instruction timing, in step S509, the sequence data and parameter data corresponding to the current sound output control instruction are read from the program corresponding area 122a of the RAM 122, and the read sequence data and parameter data are read out. Is written in the register 131 of the sound output core 112.

<DMA123>
Next, a processing configuration for reading data from the sound ROM 103 will be described. First, with reference to the flowchart of FIG. 18, a flow of processing for instructing data reading in the DMA 123 of the control core 111 will be described. The DMA 123 repeatedly executes the following processing flow in a relatively short cycle. Specifically, it is repeatedly executed at a cycle of 3 μsec, but a specific cycle is arbitrary.

  When the reading of data in response to the read instruction received from the CPU 121 of the control core 111 is not completed, the read instruction flag provided in the DMA 123 is set to “1”. If “1” is set in the read instruction flag (step S601: YES), the address data is sent to the memory controller 114 on condition that the address data to be transmitted exists (step S602: YES). Transmit (step S603). In this case, the address data is data corresponding to reading of 1-byte data, which is the minimum unit as a data reading unit.

  Here, when a read instruction is received from the CPU 121 of the control core 111, data to be read is 2 bytes or more with respect to one read instruction. In addition, the data group to be read for one read instruction is set continuously on the address of the sound ROM 103. When the CPU 121 of the control core 111 instructs the DMA 123 to read data, the CPU 121 transmits the data of the start address and the data of the end address of the data group to be read to the DMA 123. When receiving a read instruction from the CPU 121 of the control core 111, the DMA 123 reads the data group included in the data of the end address from the data of the start address. A read instruction is given in units of 1 byte among the included multiple bytes of data.

  When the address data corresponding to 1-byte data is transmitted to the memory controller 114 but the address data is received by the memory controller 114, a normal reception signal is sent from the memory controller 114 to the DMA 123. Sent. When the DMA 123 receives the normal acceptance signal (step S604: YES), the DMA 123 reads out to the memory controller 114 on condition that the address data transmitted this time is not data corresponding to the end address (step S605: YES). The address data for giving the instruction is updated to the address data corresponding to the next 1 byte (step S606). Thereby, when the DMA 123 subsequently instructs the memory controller 114 to read, the updated address data is transmitted to the memory controller 114. If the address data transmitted this time is data corresponding to the end address, it means that the transmission of the address data corresponding to the current read instruction from the CPU 121 of the control core 111 has been completed. Does not transmit new address data to the memory controller 114 until a new read instruction is issued from the CPU 121.

  When the DMA 123 receives 1-byte data from the memory controller 114 (step S607: YES), the DMA 123 transmits the received 1-byte data to the RAM 122 of the control core 111 or the internal register of the CPU 121 (step S608). Then, when the reading of all data that has been instructed from the CPU 121 of the control core 111 is completed (step S609: YES), the DMA 123 transmits a signal indicating the completion of reading to the CPU 121 of the control core 111 (step S610). . As a result, the CPU 121 of the control core 111 specifies that the reading of the light emission data subject to the read instruction has been completed, and the light emission control using the light emission data is executed. When the DMA 123 transmits a signal indicating the completion of reading to the CPU 121 of the control core 111, the DMA 123 clears the reading instruction flag “0” (step S611).

  Here, referring to the time chart of FIG. 19, the manner in which data is read from the sound ROM 103 in response to the transmission of address data from the DMA 123 will be described. FIG. 19A shows the transmission timing of address data from the DMA 123, FIG. 19B shows the period during which unprocessed address data is stored in the control-side address buffer 114a, and FIG. 19C shows control. A period during which data is transmitted toward the core 111 is shown.

  As shown in FIG. 19A, when a read instruction is issued from the CPU 121 of the control core 111 to the DMA 123, the DMA 123 keeps the memory controller 114 until the data group corresponding to the read instruction is completely read. Send address data to. Specifically, the address data is transmitted at each of the timing t1, timing t3, timing t5, timing t7, timing t9, timing t11, timing t13, and timing t15.

  As shown in FIG. 19B, the address data transmitted at the timings t1, t3, t7, t11, and t15 are not processed in the control side address buffer 114a. Since the address data is not stored, it is stored in the control-side address buffer 114a. When there is unprocessed address data in a state where data is not read from the sound light ROM 103, data is read from the sound light ROM 103 (timing from t2 to t4). , Timings t6 to t8 and timings t10 to t12).

  On the other hand, the address data transmitted at the timing t5, the timing t9, and the timing t13 has unprocessed address data stored in the control-side address buffer 114a at each timing, as shown in FIG. 19B. Therefore, transmission of the address data is invalidated without being stored in the control-side address buffer 114a. The invalidated address data is transmitted to the memory controller 114 at each address data transmission timing until it is stored in the control-side address buffer 114a.

<Data transfer unit 134>
Next, a flow of processing for instructing data reading in the data transfer unit 134 of the sound output core 112 will be described with reference to the flowchart of FIG. The data transfer unit 134 repeatedly executes the following process flow at a cycle shorter than the cycle of a series of processes in the DMA 123. Specifically, it is repeatedly executed at a cycle of 2 μsec, but a specific cycle is arbitrary.

  When the data reading in response to the read instruction set in the sequence data is not completed, the read execution flag provided in the data transfer unit 134 is set to “1”. If “1” is not set in the read execution flag (step S701: NO), the data transfer content data corresponding to the current pointer data in the sequence data read to the register 131 of the sound output core 112 is used. On condition that the data corresponding to the read instruction is set (step S702: YES), the address data of the data group to be read is read to the internal register of the data transfer unit 134 (step S703). If the address data is read, “1” is set to the read execution flag (step S704).

  Here, the data to be read with respect to one read instruction in the sequence data is 2 bytes or more. In addition, the data group to be read for one read instruction is set continuously on the address of the sound ROM 103. When read instruction data is set in sequence data, the data includes start address data and end address data of a data group to be read. The data transfer unit 134 reads the data group included in the end address data from the start address data when the read instruction data is set in the sequence data. Performs a read instruction in units of one byte among data of a plurality of bytes included in the data group.

  When “1” is set in the read execution flag (step S701: YES), the address data is transmitted to the memory controller 114 on condition that the address data to be transmitted exists (step S705: YES). (Step S706). In this case, the address data is data corresponding to reading of 1-byte data.

  When the address data corresponding to 1-byte data is sent to the memory controller 114 but the memory controller 114 accepts the address data, a normal acceptance signal is transferred from the memory controller 114. Is transmitted to the unit 134. When the data transfer unit 134 receives the normal acceptance signal (step S707: YES), the data transfer unit 134 determines that the address data transmitted this time is not data corresponding to the end address (step S708: YES). Address data for giving a read instruction is updated to address data corresponding to the next 1 byte (step S709). Thus, when the data transfer unit 134 subsequently instructs the memory controller 114 to read, the updated address data is transmitted to the memory controller 114. If the address data transmitted this time is data corresponding to the end address, it means that transmission of the address data corresponding to the current read instruction in the sequence data has been completed. Until a read instruction is issued, new address data is not transmitted to the memory controller 114.

  When the data transfer unit 134 receives 1-byte data from the memory controller 114 (step S710: YES), the data transfer unit 134 uses the received 1-byte data for the CH corresponding to the current read instruction in the register 131 of the sound output core 112. Write to the area (step S711). When the data transfer unit 134 completes reading all the data instructed in the sequence data (step S712: YES), the data transfer unit 134 reads out to the side corresponding to the current read instruction in the HWD 132 and the SCM 133 of the sound output core 112. A signal indicating completion is transmitted (step S713). Thereby, it is specified that the reading of the sound data that is the target of the read instruction is completed on the side corresponding to the current read instruction of the HWD 132 and the SCM 133, and the sound output control using the sound data is executed. When the data transfer unit 134 transmits a signal indicating the completion of reading, the data transfer unit 134 clears the reading execution flag to “0” (step S714).

  As described above, when data is read from the sound ROM 103 for transmission of address data from the data transfer unit 134, data is read from the sound ROM 103 for transmission of address data from the DMA 123. Similarly, the data transfer unit 134 periodically transmits address data to the memory controller 114 until the reading of the data group corresponding to the read instruction set in the sequence data is completed. When the address data is transmitted and the unprocessed address data is not stored in the sound output side address buffer 114b, the address data is stored in the sound output side address buffer 114b, and the address data is stored in the address data. Reading of the corresponding data is started. On the other hand, when address data is transmitted and unprocessed address data is stored in the sound output side address buffer 114b, the transmission of the address data is invalidated. The invalidated address data is transmitted to the memory controller 114 every time the address data is transmitted until it is stored in the sound output side address buffer 114b.

<Memory controller 114>
Next, the flow of processing for reading data in the memory controller 114 will be described with reference to the flowchart of FIG. The memory controller 114 repeatedly executes the following processing flow at a cycle shorter than the repetition cycle of a series of processes in the DMA 123 and the data transfer unit 134. Specifically, it is repeatedly executed at a cycle of 1 μsec, but a specific cycle is arbitrary.

  If the memory controller 114 receives address data from the DMA 123 (step S801 and step S802: YES), the memory controller 114 is conditioned on the condition that unprocessed address data is not stored in the control-side address buffer 114a (step S803: NO). The received address data is stored in the control-side address buffer 114a (step S804). At this time, a normal acceptance signal indicating that the address data has been accepted is transmitted to the DMA 123 (step S805).

  If the memory controller 114 has received address data from the data transfer unit 134 (step S801: YES, step S802: NO), the condition is that unprocessed address data is not stored in the sound output side address buffer 114b. (Step S806: NO), the received address data is stored in the sound output side address buffer 114b (Step S807). At this time, a normal acceptance signal indicating that the address data has been accepted is transmitted to the data transfer unit 134 (step S808).

  When the address data is received as described above, the memory controller 114 reads data corresponding to the address data from the sound ROM 103. Specifically, when data is not being read from the sound ROM 103 (step S809: NO), it is a condition that unprocessed address data is stored in the sound output side address buffer 114b (step S810: YES), the address data is transmitted to the sound ROM 103, and reading of data corresponding to the address data is started (step S811). Thereby, reading of 1-byte data corresponding to the address data is started. When data reading is started, data setting is performed so that the memory controller 114 can specify that the address data stored in the sound output side address buffer 114b has been processed.

  On the other hand, in a situation where the unprocessed address data is not stored in the sound output side address buffer 114b (step S810: NO), the unprocessed address data is stored in the control side address buffer 114a (step S810). (S812: YES), by transmitting the address data to the sound ROM 103, reading of 1-byte data corresponding to the address data is started (step S813). Thereby, reading of 1-byte data corresponding to the address data is started. When data reading is started, data setting is performed so that the memory controller 114 can specify that the address data stored in the control-side address buffer 114a has been processed.

  When the memory controller 114 starts reading 1-byte data (step S809: YES), the memory controller 114 executes the reading completion process on condition that the reading of the 1-byte data is completed (step S814: YES) (step S814: YES). Step S815). By executing the read completion process, the 1-byte data read this time is transferred to the control core 111 (that is, DMA 123) and the sound output core 112 (that is, the data transfer unit 134) on the side from which the data is read. Sent.

  Next, with reference to the time chart of FIG. 22, a data read mode when a period in which a read instruction is issued from the DMA 123 and a period in which a read instruction is issued from the data transfer unit 134 will be described. 22A shows a period in which address data is periodically transmitted from the DMA 123, FIG. 22B shows a period in which address data is periodically transmitted from the data transfer unit 134, and FIG. Indicates the period during which the data read from the sound ROM 103 is transferred to the control core 111, and FIG. 22D shows the period during which the data read from the sound ROM 103 is transferred to the sound output core 112. Show.

  When a read instruction from the CPU 121 of the control core 111 to the DMA 123 is generated at the timing t1, transmission of periodic address data from the DMA 123 to the memory controller 114 is started as shown in FIG. In this case, since reading of data from the sound ROM 103 is not performed, reading of 1 byte of data from the sound ROM 103 to the control core 111 is started as shown in FIG. Is done.

  When a read instruction is issued in the sequence data read to the register 131 of the sound output core 112 at the timing t2 during which the reading of the 1-byte data is being performed, FIG. As shown in FIG. 4, transmission of address data from the data transfer unit 134 of the sound output core 112 to the memory controller 114 is started. However, since the data is being read from the control core 111 at the timing t2, the data reading for the transmission of the address data from the data transfer unit 134 is not started. Thereafter, as shown in FIG. 22C, the data reading to the control core 111 started at the timing t1 is completed at the timing t3.

  By the timing t3, address data is newly transmitted from the DMA 123 to the memory controller 114, and address data is transmitted from the data transfer unit 134 to the memory controller 114. Therefore, unprocessed address data is stored in both the control-side address buffer 114a and the sound output-side address buffer 114b of the memory controller 114. In this case, since the memory controller 114 processes the read instruction from the data transfer unit 134 in preference to the read instruction from the DMA 123, at the timing t4, as shown in FIG. Reading of 1-byte data to the sound output core 112 is started. Further, as shown in FIG. 22B, since the period in which the address data is periodically transmitted from the data transfer unit 134 continues until the timing t8, the timings t5, t6, t7, and t8 Reading of 1-byte data from the sound light ROM 103 to the sound output core 112 is started at each timing.

  When reading of data started at the timing t8 is completed, unprocessed address data is not stored in the sound output side address buffer 114b, and unprocessed address data is stored in the control side address buffer 114a. It becomes a state. Therefore, at the timing of t9, reading of 1-byte data from the sound ROM 103 to the control core 111 is started as shown in FIG. Further, as shown in FIG. 22A, since the period in which the address data is periodically transmitted from the DMA 123 continues until the timing t11, the sound core 103 controls the control core at each of the timing t10 and the timing t11. Reading of 1-byte data to 111 is started.

  Next, a device for shortening the time for waiting for data reading in the control core 111 in a configuration in which the sound output core 112 has priority over the control core 111 for data reading will be described.

  As already described, each of the HWD 132 and the SCM 133 of the sound output core 112 has 16 channels, and it is possible to output a sound corresponding to digital synthesized musical sound data that is a result of synthesizing the digital musical sound data created in each channel. It is. However, the sound for 16 channels is not always synthesized, but only the sound for 1 channel may be output, or it may be a part of 16 channels such as 5 or 8 In some cases, the synthesized sound of the channels is output.

  When the sound data is read, the sound data for the number of channels to be output is read. In addition, since the digital musical sound data created by each of the HWD 132 and the SCM 133 may be synthesized and output a sound, in this case, the sound data for the number of channels to be output in the HWD 132 and the output target in the SCM 133 Sound data for the number of channels to be read out is read out before the output timing of the synthesized sound.

  The sound data read instruction is defined in the sequence data, but the sound data read in response to one read instruction defined in the sequence data corresponds to one channel and is further predetermined in that channel. The sound output for the time (700 μsec) is set to be possible. The predetermined time is a time obtained by adding the sum of the maximum number of channels of the HWD 132 and the maximum number of channels of the SCM 133 to the longest time expected to read one sound data having a data structure of a plurality of bytes. Even set as a long time. The amount of data of sound data stored in advance in the sound light ROM 103 is set so as to enable sound output for a predetermined time. Therefore, even if the total number of channels of sound output at one time is “32” for the HWD 132 and the SCM 133, or less than that, the sound data that enables sound output for a predetermined time. Is read out.

  As described above, in the configuration in which the sound data enabling sound output for a predetermined time is read in this way, the first CH area 143a to the 16th CH area 143p of the HWD area 143 in the register 131 of the sound output core 112 is described. Each of the first CH area 144a to the 16th CH area 144p of the SCM area 144 includes an area capable of storing two pieces of created digital musical tone data. Therefore, when sound output from the speaker unit 54 is continuously performed, in a situation where sound output corresponding to the unit sound output period for a predetermined time is performed, the unit sound output period corresponding to the next predetermined time is supported. When the sound data for enabling sound output is read out and the unit sound output period on the front side ends, the unit sound output period on the rear side is started using the read sound data It becomes. That is, the unit readout period for reading out the sound data for the predetermined time is repeated regardless of the number of channels of sound output at a time.

  FIG. 23 is an explanatory diagram for explaining a unit readout period when sound data for the maximum channels is read out in each of the HWD 132 and the SCM 133. FIGS. 23A and 23B are explanatory diagrams for explaining a sound data reading mode for the HWD 132. FIGS. 23C and 23D are sound data reading modes for the SCM 133. FIG. It is explanatory drawing for demonstrating.

  The unit readout period during which the sound data for a predetermined time is read coincides with the unit sound output period for the predetermined time, and therefore “unit readout period = predetermined time”. In the unit readout period, since the sound data for the HWD 132 and the sound data for the SCM 133 are read out, half the unit readout period can be used to read out the sound data for the HWD 132. The remaining half of the period is available for reading sound data for SCM 133.

  As already described, the unit readout period is set as a time longer than the time required to read out sound data for the maximum channel. Therefore, as shown in FIG. 23 (a), the period T1 during which the sound light ROM 103 is accessed to read out sound data for 16 channels for the HWD 132 is shorter than the half of the unit read period. A period T2 during which the ROM 103 is not accessed occurs. Similarly, as shown in FIG. 23 (c), the period T3 during which the sound light ROM 103 is accessed to read out sound data for 16 channels for the SCM 133 is shorter than the half of the unit read period. A period T4 during which the ROM 103 is not accessed will occur.

  Here, if the period for reading the sound data for the HWD 132 and the period for reading the sound data for the SCM 133 are collected in the unit reading period, the memory controller 114 issues a read instruction from the sound output core 112 as described above. Since priority is given to the reading instruction from the control core 111, a situation occurs in which the period of waiting for data reading in the control core 111 becomes longer. On the other hand, as described above, the unit reading period is divided into the period T1 for reading the sound data for the HWD 132 and the period T3 for reading the sound data for the SCM 133, and no access is made between the reading periods T1 and T3. Periods T2 and T4 exist. Thereby, the control core 111 shortens the period of waiting for data reading.

  In the above configuration, in the pachinko machine 10, as shown in FIGS. 23B and 23D, the period T1 for reading the sound data for the HWD 132 and the period T3 for reading the sound data for the SCM 133 are divided in units of channels. The channel unit periods T5 and T7 are set so as to sandwich the non-access unit periods T6 and T8.

  Specifically, since the data volume of sound data for a predetermined time is the same on the HWD 132 side, the channel unit period T5 is constant. Accordingly, a period obtained by dividing the period T1 for reading the sound data for the HWD 132 into 16 equal parts corresponds to the channel unit period T5. A non-access unit period T6 is set between each channel unit period T5, and all the non-access unit periods T6 are constant.

  On the other hand, on the SCM 133 side, the channel unit period T7 is not constant because the data volume of the sound data for a predetermined time differs depending on the type of the sound data. Therefore, the channel unit period T7 varies depending on the type of sound data. On the other hand, the non-access unit period T8 set during each channel unit period T7 is all constant.

  The channel unit periods T5 and T7 and the non-access unit periods T6 and T8 are determined at the design stage of the pachinko machine 10. The data transfer content in the sequence data is set so that the determined unit periods T5 to T8 occur. Further, the number of channel unit periods varies according to the number of channels included in the unit readout period, and the length of the non-access unit period varies accordingly. Specifically, the smaller the number of channels, the longer the non-access unit period.

  According to the embodiment described in detail above, the following excellent effects are obtained.

  In the configuration in which the program data and control data used in the control core 111 and the control data used in the sound output core 112 are stored together in the sound ROM 103, the sound ROM 103 When the memory controller 114 that manages the reading of data from both the control core 111 and the sound output core 112 has received the address data, the address controller receives the address data received from the sound output core 112 regardless of the reception order. The address data received from the control core 111 is prioritized as a data read execution target. As a result, delay in reading out the sound data is suppressed, and sound can be output suitably. On the other hand, since it is basically emission data that can occur in the control core 111 in duplicate with the reading of the sound data, even if the reading of the emission data is slightly delayed, it is slightly delayed in the emission timing of the display light emitting unit 53. It is harder to give the player a sense of incongruity than the sound output shifts.

  Even when the DMA 123 of the control core 111 receives a read instruction of a data group consisting of a plurality of bytes from the CPU 121 of the control core 111, a read instruction of 1 byte of data is transmitted by one transmission of address data to the memory controller 114. I do. As a result, when address data is transmitted from the sound output core 112 to the memory controller 114 even while a data group consisting of a plurality of bytes is being read, the data corresponding to the address data is read. Is possible.

  Even when the data transfer unit 134 of the sound output core 112 receives an instruction to read a data group consisting of a plurality of bytes in the sequence data, it reads 1 byte of data by transmitting address data to the memory controller 114 once. Give instructions. As a result, when the memory controller 114 receives the address data, the memory controller 114 may read 1-byte data regardless of whether the transmission source is the control core 111 or the sound output core 112. Therefore, the processing configuration of the memory controller 114 can be simplified.

  Even if the memory controller 114 receives address data from the sound output core 112 during the reading of 1-byte data, the memory controller 114 completes the reading of the 1-byte data during the reading. As a result, while it is possible to preferentially read sound data in the sound output core 112, it is possible to prevent the memory controller 114 from complicating the process for reading data.

  The memory controller 114 is provided with a control side address buffer 114a and a sound output side address buffer 114b. When address data is transmitted from the control core 111 or the sound output core 112 during reading of 1-byte data, Address data is stored in the corresponding address buffers 114a and 114b. Thus, when the data reading is completed, it is possible to immediately start reading the next data.

  In particular, the memory controller 114 receives address data from the sound output core 112 in advance during the reading of 1-byte data by providing the sound output side address buffer 114b which is a priority side for reading. Is possible. As a result, a situation in which the address data received from the sound output core 112 already exists at the time when the reading of 1 byte of data is completed, and preferential data reading to the sound output core 112 is facilitated. Become.

  Further, the memory controller 114 is provided with a control side address buffer 114a and a sound output side address buffer 114b so that the memory controller 114 receives the address data on the read priority side depending on the type of the address buffers 114a and 114b. It becomes possible to determine whether or not. Therefore, simplification of processing when the memory controller 114 determines a data read execution target is achieved.

  When the data transfer unit 134 of the sound output core 112 reads sound data that enables sound output for a predetermined time, the sound data corresponding to the next channel is read after the sound data corresponding to one channel is completely read. The address data is transmitted so that a non-access unit period, which is a period during which no sound data is read, is generated before the reading of the sound data is started. As a result, even when the data reading in the sound output core 112 is prioritized over the data reading in the control core 111, it is possible to cause a period for the data reading in the control core 111. Therefore, it is possible to prevent the waiting period for data reading in the control core 111 from becoming long.

  Further, the data transfer unit 134 transmits the address data in such a manner that the non-access unit period is not actively generated while the sound data corresponding to one channel is read. As a result, the sound data corresponding to one channel can be continuously read out, and the data transfer unit 134 or the memory controller 114 can designate or determine the transfer destination of the read sound data. Can be suitably performed.

  The data transfer unit 134 generates the non-access unit period by transmitting address data in accordance with the sequence data SD. This simplifies the processing configuration for generating the non-access unit period.

  The setting mode of the read instruction data in the sequence data SD is adjusted so that the non-access unit periods are equal in a predetermined continuous period. As a result, the non-access unit period is set evenly, and it becomes possible to evenly generate data read opportunities in the control core 111.

  Even when both the HWD 132 and the SCM 133 create digital musical tone data of the maximum number of channels, each sound data is read so that a non-access unit period occurs in a unit reading period for a predetermined time. This makes it possible to generate a non-access unit period regardless of the number of channels to be output simultaneously.

  Used in a unit sound output period after the corresponding unit sound output period in the unit readout period in a configuration in which the total time for reading out sound data of the corresponding number of channels in the unit readout period is shorter than the unit readout period. No sound data is read out. As a result, it is possible to maximize the non-access unit period in the unit reading period.

  The unit readout period and the amount of sound data are set so that the non-access unit period occurs regardless of whether the digital musical tone data is created by the HWD 132 or the digital musical tone data is created by the SCM 133. . This makes it possible to generate a non-access unit period regardless of the type of digital musical tone data to be created.

  In the sound output core 112, the transmission timing of the address data is adjusted so that the non-access unit period occurs, whereas in the control core 111, the transmission timing for positively generating such a non-access unit period. Is not adjusted. As a result, the processing configuration can be simplified as compared with the configuration in which the transmission timing of the address data is adjusted in both the control core 111 and the sound output core 112.

  When the DMA 123 of the control core 111 receives a read instruction from the CPU 121 of the control core 111, it simply transmits address data periodically until the reading of data corresponding to the read instruction is completed. Is achieved.

  Program data (1) to program data (L), processing data (1) to processing data (M), command data (1) to command data (N) used in the CPU 121 of the control core 111 are: When the supply of operating power to the control core 111 is started, the data is read to the RAM 122 of the control core 111. Thereby, when the light emission data (1) to the light emission data (P) and the sound data (1) to the sound data (Q) are read, it is basically unnecessary to read a series of data corresponding to the program. Therefore, a series of data corresponding to the program is read during a period in which the reading instruction of the light emission data (1) to the light emission data (P) and the sound data (1) to the sound data (Q) is not generated, and the program data (1) ~ Program data (L), processing data (1) ~ processing data (M), command data (1) ~ command data (N) need not wait for reading. .

  Whether or not there is an abnormality in the program-corresponding series of data is periodically checked. If there is an abnormality, the program-corresponding series of data is read out from the program corresponding area 122a of the RAM 122 again. As a result, it is possible to prevent the CPU 121 from continuously using a series of data corresponding to an abnormal program.

  When a series of data corresponding to the program is read again, execution of the timer interrupt process is prohibited, and thus generation of a new reading instruction of the light emission data and sound data to the DMA 123 and the data transfer unit 134 is prohibited. This makes it possible to prioritize rereading of a series of data corresponding to a program.

  When a command is received from the MPU 62 of the main controller 60 even when a series of data corresponding to the program is being read again, the command is stored in the ring buffer of the RAM 122. This makes it possible to prevent the command transmitted from the MPU 62 of the main control device 60 from being invalidated even during re-reading of the series data corresponding to the program.

<Second Embodiment>
In this embodiment, in the normality determination process in the CPU 121 of the control core 111, when it is determined that there is an abnormality in the program-corresponding series of data read to the RAM 122, data other than the program-corresponding series of data is read. It will be prohibited. A processing configuration for performing the prohibition will be specifically described. The description of the same configuration as that of the first embodiment is basically omitted.

  FIG. 24 is a flowchart showing normality determination processing in the present embodiment. In steps S901 to S905 and steps S907 to S908, steps of normality determination processing (FIG. 15) in the first embodiment are performed. The same processing as S401 to step S407 is executed. On the other hand, in the normality determination process in the present embodiment, if some of the 4-byte data does not match as a result of the data collation process (step S902) (step S903: NO), a data rewrite instruction is issued. In addition to the setting for the DMA 123 (step S905), the rewriting priority setting is performed for the sound output core 112. Specifically, “1” is set to the rewrite priority flag provided in the register 131 of the sound output core 112.

  FIG. 25A is a flowchart showing a flow of processing for issuing a data read instruction in the DMA 123 of the control core 111. When a data rewrite instruction is received from the CPU 121 of the control core 111 (step S1001: YES). Then, the interrupt process to be read (step S1002) is executed. Thereby, regardless of whether or not the reading of the data group corresponding to the read instruction received from the CPU 121 has been completed, priority is given to the data read instruction for overwriting the program-corresponding series data on the program-corresponding area 122a of the RAM 122. Set up interrupts so that they can be performed. Thereafter, the processing shown in steps S601 to S611 of the processing of the DMA 123 (FIG. 18) in the first embodiment is executed. Note that if a rewrite instruction for a series of data corresponding to a program occurs in a situation where reading of another data group has not been completed, the data group that was in the process of being read after the completion of reading of the series of data corresponding to the program has been completed. Resume reading.

  FIG. 25B is a flowchart showing a flow of processing for instructing data read in the data transfer unit 134 of the sound output core 112, and when “1” is set in the rewrite priority flag of the register 131 ( Step S1101: YES), “1” is set to the read stop flag provided in the data transfer unit 134 (Step S1102). If “1” is not set in the read stop flag (step S1103: NO), the data transfer unit 134 proceeds to steps S701 to S714 in the processing of the data transfer unit 134 in the first embodiment (FIG. 20). The other process shown (step S1104) is executed, and when the read stop flag is set to “1” (step S1103: YES), the other process is not executed. That is, when a series of program-corresponding data is overwritten on the program-corresponding area 122a of the RAM 122, the data output in the sound output core 112 is stopped.

  According to the embodiment described in detail above, when there is an abnormality in the program-corresponding series of data and an instruction to rewrite the program-corresponding series of data to the program-corresponding area 122a of the RAM 122 is generated, reading of other data is stopped. Is done. Accordingly, it is possible to prioritize reading of a series of data corresponding to a program over reading of other data, and rewriting of the series of data corresponding to the program can be terminated early.

<Third Embodiment>
In the present embodiment, the processing configuration of the CPU 121 of the control core 111 is different from that of the first embodiment. Hereinafter, the different configuration will be described. The description of the same configuration as that of the first embodiment is basically omitted.

  FIG. 26 is a block diagram showing an electrical configuration for performing execution control in the present embodiment.

  In the present embodiment, a direct ROM 201 is provided in addition to the CPU 121, RAM 122, and DMA 123 in the control core 111 of the sound and light SOC 102. The direct ROM 201 is electrically connected to the CPU 121 via an address bus and a data bus, and data stored in advance in the direct ROM 201 can be read by the CPU 121. That is, the CPU 121 uses not only the data stored in the sound ROM 103 but also the data stored in the direct ROM 201.

  The direct ROM 201 is configured to use a memory (that is, a non-volatile storage unit) that does not require external power supply for storage and holding as a read-only memory. Specifically, a NOR flash memory is used as the direct ROM 201, but a NAND flash memory may be used. The direct ROM 201 stores various control programs and fixed value data used when executing processes according to the programs.

  The data structure of the direct ROM 201 will be described in detail with reference to FIG. In the direct ROM 201, initial startup data (1), initial startup data (2),..., Initial startup data (R) are stored in advance. These initial activation data are directly read from the direct ROM 201 by the CPU 121 when the supply of operating power to the CPU 121 is started. The CPU 121 executes a process according to the program data and the control data included in the initial startup data, thereby executing the first process after the start of the supply of the operating power, and stored in the sound light ROM 103. Instructs reading of a series of data corresponding to the program. After all of the program-corresponding series data is read to the program-corresponding area 122a of the RAM 122, the CPU 121 performs processing using the program-corresponding series data from a state in which processing is executed using the initial activation data. Switch to the state to execute.

  The direct ROM 201 stores command interrupt data (1), command interrupt data (2),..., Command interrupt data (S) in addition to initial startup data. The command interrupt data includes program data and control data for executing command interrupt processing in the CPU 121. The command interrupt process is a process that is started by interrupting another process by the CPU 121 when it is specified by a latch circuit (not shown) provided in the control core 111 that a command has been transmitted from the MPU 62 of the main controller 60. It is. By executing the command interrupt process, the command received from the MPU 62 of the main controller 60 can be used in the subsequent process.

  The direct ROM 201 stores data for rewriting (1), data for rewriting (2),..., Data for rewriting (T) in addition to initial start-up data and command interrupt data. ing. These rewriting data are used to execute a rewrite instruction for a series of data corresponding to the program when it is determined that an abnormality has occurred in the series of data corresponding to the program read to the program corresponding area 122a of the RAM 122. Program data and control data. When rewriting of a series of data corresponding to a program is started and during execution of rewriting, the CPU 121 directly reads out rewriting data from the direct ROM 201 and executes processing corresponding thereto.

  Of the program data and control data necessary for executing various processes in the CPU 121, data other than the initial start data, command interrupt data, and rewrite data are stored in the sound ROM 103 in advance. .

<Main processing of CPU 121>
Next, the main processing of the CPU 121 in this embodiment will be described with reference to the flowchart of FIG.

  When the supply of operating power is started, the CPU 121 reads the initial activation data directly from the direct ROM 201, thereby executing the processes of steps S1201 to S1203. Specifically, first, initialization processing of the RAM 122 is executed in step S1201, thereby clearing each area of the RAM 122 to "0". Thereafter, in step S1202, a data read instruction at power-on is given to the DMA 123. As in the first embodiment, the DMA 123 receives a data read instruction when the power is turned on, so that a series of program-corresponding data stored in advance in the sound ROM 103 is read to the program-corresponding area 122a of the RAM 122. The address data is transmitted to the memory controller 114.

  Thereafter, in step S1203, it is determined whether or not the data read completion signal at the time of power-on is completed by determining whether or not the data read completion signal is received from the DMA 123. If the data reading has not been completed, the process waits in step S1203.

  When the CPU 121 determines that the data reading has been completed (step S1203: YES), the CPU 121 refers to the program-corresponding series of data read to the program-corresponding area 122a of the RAM 122, and executes the processing after step S1204. Specifically, in step S1204, execution of command interrupt processing and timer interrupt processing is permitted.

  In a succeeding step S1205, it is determined whether or not a command is received from the MPU 62 of the main controller 60. Here, when a command is received from the MPU 62 of the main control device 60, the command interrupt processing is started in the CPU 121 of the control core 111 by the command being latched by the latch circuit of the control core 111 as already described. The command interrupt process is executed by directly reading the command interrupt data from the direct ROM 201. That is, the CPU 121 switches from reading the program-corresponding series of data read to the program-corresponding area 122 a of the RAM 122 to reading the command interrupt data directly from the direct ROM 201.

  In the command interrupt process, as shown in the flowchart of FIG. 29A, first, the execution of the timer interrupt process is prohibited in step S1301. After that, by updating the write pointer of the ring buffer 122c in step S1302, the area to which the command received this time in the area of the ring buffer 122c is to be written is updated in the next order with respect to the currently set area. Change to area. When the value of the write pointer reaches the maximum value, the pointer is cleared to “0”. Therefore, when the area to be written goes around once, the newly received command is overwritten on the area where the command has already been written. Thereafter, in step S1303, the command received this time is written in the area corresponding to the updated write pointer. In step S1304, execution of timer interrupt processing is permitted. When the command interrupt process is completed, the CPU 121 switches from a state in which the command interrupt data is directly read from the direct ROM 201 to a state in which the program corresponding series data read in the program corresponding area 122a of the RAM 122 is read out. Then, by referring to the series of data corresponding to the program, the process executed immediately before the command interrupt process is started is resumed.

  Returning to the description of the main process (FIG. 28), in step S1205, it is determined whether or not an unprocessed command is stored in the ring buffer 122c of the RAM 122. If an unprocessed command is stored, a data table for enabling execution of an effect or notification corresponding to the command to be read this time is read from the program corresponding area 122a of the RAM 122 to the general-purpose area 122b in step S1206. Set as execution target. In this case, the data table includes a data transmission table in which the sequence data and parameter data are transmitted to the sound output core 112, and a combination type of the sequence data and parameter data. Data for enabling to specify the timing to be given to the DMA 123 and the type of light emission data to be read is set, and the light emission control execution timing is set based on the light emission data read in advance. There exists a table. One set of the data transmission table and the light emission control table is provided in correspondence with the contents of various effects, and the light emitting mode of the display light emitting unit 53 and the speaker are referred to by the CPU 121 referring to the corresponding tables. It is possible to associate the sound output mode from the unit 54 with each other. Thereafter, in step S1207, a display command corresponding to the data table read this time is transmitted to the display control device 90. Thereby, the display control device 90 controls the display of the symbol display device 41 so that a display effect corresponding to the data table is performed.

  If a negative determination is made in step S1205, or if the process of step S1207 is executed, it is determined in step S1208 whether the value of the first interrupt counter provided in the RAM 122 is “0”. The first interrupt counter is a counter for the CPU 121 to specify the execution cycle of the data transmission process in step S1209.

  Here, the timer interrupt process is periodically started at a cycle of 500 μsec. In the timer interrupt process, as shown in the flowchart of FIG. 29B, first, 1 is subtracted from the value of the first interrupt counter in the RAM 122 in step S1401. A numerical value is set in the first interrupt counter so that the value of the first interrupt counter becomes “0” in a cycle of 2 msec. In step S1402, the value of the second interrupt counter provided in the RAM 122 is decremented by 1. The second interrupt counter is a counter for the CPU 121 to specify the execution cycle of the light emission control process in step S1211 in the main process (FIG. 28). A numerical value is set in the second interrupt counter so that the value of the second interrupt counter becomes “0” in a cycle of 4 msec.

  Returning to the description of the main process (FIG. 28), when the value of the first interrupt counter is “0” (step S1208: YES), the data transmission process is executed in step S1209. In the data transmission process, it is determined whether or not it is the transmission timing of the sequence data and parameter data by referring to the data transmission table that is the object of use this time. The kind of sequence data and parameter data are written into the register 131 of the sound output core 112.

  If a negative determination is made in step S1208, or if the process of step S1209 is executed, it is determined in step S1210 whether the value of the second interrupt counter in the RAM 122 is “0”. If the value of the second interrupt counter is “0”, the light emission control process is executed in step S1211. In the light emission control process, by referring to the light emission control table that is the object of use this time, it is determined whether or not it is the timing for instructing to read out the light emission data. The corresponding light emission data read instruction is given to the DMA 123. Further, in the light emission control process, it is specified whether or not it is the light emission control timing of the display light emitting unit 53 by referring to the light emission control data. Execute light emission control.

  If a negative determination is made in step S1210, or if the process of step S1211 is executed, it is confirmed that “1” is not set in the normal determination execution flag of the RAM 122 and that the normal determination start timing is reached. As a condition (step S1212: NO, step S1213: YES), a data read instruction for normality determination is given to the DMA 123 in step S1214. After that, in step S1215, “1” is set to the normal determination execution flag of the RAM 122, and the process returns to step S1204. Note that the processing content of steps S1212 to S1215 is the same as that of steps S305 to S308 of the main processing (FIG. 12) in the first embodiment. On the other hand, if “1” is set in the normal determination execution flag (step S1212: YES), the normal determination process is executed in step S1216, and then the process returns to step S1204. When the normal determination processing is completed for all of the series of program-compatible data having a data capacity of 512 bytes, the normal determination in-progress flag is cleared to “0”.

<Normal determination processing of CPU 121>
FIG. 30 is a flowchart showing normality determination processing.

  When the reading of the series data corresponding to the program to the general-purpose area 122b has been completed (step S1501: YES), data collation processing is executed in step S1502. In the data collation processing, 4-byte data corresponding to each other is read from each of the series of data corresponding to the program stored in the program corresponding area 122a of the RAM 122 and the series of data corresponding to the program stored in the general-purpose area 122b. By executing logical operation processing such as XOR processing, it is determined whether or not these 4-byte data match.

  If all the bits of the 4-byte data match (step S1503: YES), the normality determination process is terminated as it is. In other words, when the normality is determined, the data matching process is not executed for the entire series of 512-byte data corresponding to the program, but is performed in units of 4 bytes that are the bytes to be checked. Here, since the interrupt of the command interrupt process (FIG. 29A) and the interrupt of the timer interrupt process (FIG. 29B) are not prohibited when the data collation process is started, the data collation process is being executed. However, command interrupt processing (FIG. 29A) and timer interrupt processing (FIG. 29B) occur.

  If some bits of the 4-byte data do not match (step S1503: NO), the data rewriting process shown in steps S1504 to S1508 is executed. Here, the data rewriting process is executed by directly reading the rewriting data from the direct ROM 201. That is, the CPU 121 switches from a state in which a series of program-corresponding data read to the program corresponding area 122 a of the RAM 122 is read to a state in which the rewriting data is directly read from the direct ROM 201.

  In the data rewriting process, the execution of the timer interrupt process (FIG. 29B) is prohibited in step S1504. Thereby, even if it becomes the execution period of a timer interruption process, the interruption of the said timer interruption process does not generate | occur | produce. On the other hand, even when the data rewriting process is executed, the execution of the command interrupt process (FIG. 29A) is not prohibited. This makes it possible to store the command received from the MPU 62 of the main control device 60 in the ring buffer 122c of the RAM 122 even in a situation where the data rewriting process is being executed, so as not to invalidate the reception of the command. It becomes possible to.

  In a succeeding step S1505, a data rewrite instruction is issued to the DMA 123. Upon receiving the data rewrite instruction, the DMA 123 transmits address data corresponding to the instruction to the memory controller 114, thereby reading the program corresponding series data to the program corresponding area 122 a of the RAM 122 to the memory controller 114. Let it begin. In this case, a series of newly read program-corresponding data is overwritten on the program-corresponding area 122a. In step S1506, rewrite priority setting is performed for the sound output core 112. Specifically, “1” is set to the rewrite priority flag provided in the register 131 of the sound output core 112. The operation of the sound output core 112 when the rewrite priority flag is set to “1” is the same as that in the second embodiment.

  Thereafter, in step S1507, it is determined whether or not rewriting of the series of data corresponding to the program for the program corresponding area 122a has been completed. If the rewriting has not been completed, the process stands by in step S1507. When the rewriting of the series data corresponding to the program is completed, the execution of the timer interrupt process (FIG. 29B) is permitted in step S1508. As a result, the interrupt is permitted from the state in which the periodic interrupt of the timer interrupt process is prohibited. When the data rewriting process is completed, the CPU 121 switches from a state in which the rewriting data is directly read from the direct ROM 201 to a state in which the program corresponding series data read in the program corresponding area 122a of the RAM 122 is read out. Then, the process of step S1204 in the main process (FIG. 28) is executed by referring to the series of data corresponding to the program.

<DMA123>
Next, a processing configuration for reading data from the sound ROM 103 will be described. The process flow for instructing data reading in the data transfer unit 134 of the sound output core 112 is the same as the process flow (FIG. 25B) shown in the second embodiment, and the memory controller 114. The flow of processing for reading data is the same as the processing flow (FIG. 21) shown in the first embodiment. On the other hand, the flow of processing for instructing data reading in the DMA 123 of the control core 111 is different from those in the above embodiments. Therefore, the flow of processing in this embodiment for instructing data reading in the DMA 123 will be described with reference to the flowchart of FIG.

  When the DMA 123 receives a data read instruction from the CPU 121 of the control core 111 (step S1601: YES), the DMA 123 executes a process for storing address data corresponding to the read instruction in the internal register of the DMA 123 (step S1602). ). Specifically, the data of the start address and the data of the end address corresponding to the current read instruction are stored in the internal register. In this case, when another data group is being read, the data setting process is executed without erasing the data at the start address and the data at the end address for the data group being read. Further, “1” is set to the read instruction flag provided in the internal register of the DMA 123 (step S1603).

  When the DMA 123 newly receives a light emission data read instruction from the CPU 121 in a situation where the normal determination data corresponding to the read instruction from the CPU 121 has not been read (step S1604 and step S1605: YES), the DMA 123 Is executed (step S1606). Specifically, the state in which the instruction for reading out the data for normality determination is temporarily interrupted, and the light emission data reading instruction corresponding to the current reading instruction is started. As a result, when a light emission data read instruction is issued during the normal determination data read, it is possible to prioritize the read of the light emission data, and to prevent delays in the light emission control timing. .

  On the other hand, also when a data rewrite instruction is newly received from the CPU 121 in a situation where the data read corresponding to the read instruction from the CPU 121 is not completed (step S1607 and step S1608: YES), the interrupt process to be read is performed. It executes (step S1606). Specifically, the current instruction for reading data to be read is temporarily suspended, and a read instruction for rewriting a series of data corresponding to the program is started. This makes it possible to prioritize the rewriting of a series of data corresponding to a program over the reading of any data, and when the occurrence of data abnormality is specified in the normality determination process, the rewriting of the series of data corresponding to a program is performed. It can be completed early.

  The DMA 123 executes the read process regardless of whether a new read instruction is received from the CPU 121 (step S1609). In the read process, the processes shown in steps S601 to S611 of the process of the DMA 123 (FIG. 18) in the first embodiment are executed. In this case, when the interrupt process to be read (step S1606) has occurred, the read instruction for the data group set as the interrupt target is prioritized, and is interrupted during the execution after the reading of the data group is completed. The reading instruction of the data group that has been stored is resumed.

<Data read mode>
Next, how to read various data will be described with reference to the time chart of FIG. FIG. 32A shows the timing at which the CPU 121 gives an instruction to read normality data to the DMA 123, and FIG. 32B shows the timing at which the CPU 121 gives an instruction to read the light emission data to the DMA 123. ) Shows the timing at which a rewrite instruction of a series of data corresponding to the program is given from the CPU 121 to the DMA 123, FIG. 32 (d) shows the reading period of the data for normality determination, and FIG. 32 (e) shows the reading period of the light emission data. FIG. 32 (f) shows a period in which a series of data corresponding to a program is read for rewriting, and FIG. 32 (g) shows a period in which sound data is being read by the data transfer unit 134 of the sound output core 112. .

  First, a case will be described in which a light emission data read instruction is generated during normality determination data read.

  As shown in FIG. 32A, when the CPU 121 gives an instruction to read normal determination data to the DMA 123 at the timing t1, reading of the normal determination data is started as shown in FIG. After that, since the sound data read instruction data is set in the sequence data read to the register 131 of the sound output core 112 at the timing t2, as shown in FIG. The data transfer unit 134 starts reading the sound data. In this case, in FIG. 32D and FIG. 32G, the normal determination data read period and the sound data read period are shown to overlap. While giving priority to the reading of the sound data, the normality determination data is read between the readings of the sound data.

  Thereafter, at timing t3, a read instruction of light emission data is given from the CPU 121 to the DMA 123 as shown in FIG. In this case, since the reading of the light emission data is prioritized over the reading of the normal determination data as already described, the reading of the normal determination data is temporarily interrupted as shown in FIG. The reading of the light emission data is started as shown in FIG. On the other hand, the reading of the sound data is continued as shown in FIG. In this case, the memory controller 114 reads the light emission data between reading of the sound data while giving priority to reading of the sound data.

  Thereafter, at the timing of t4, the reading of the light emission data is completed as shown in FIG. 32E, and the reading of the data for normality determination is resumed as shown in FIG. 32D. In this case, reading of the normal determination data is not started from the beginning, but reading of the normal determination data is resumed from a state in the middle of being interrupted at the timing t3.

  Next, a case where a rewrite instruction is generated during the reading of the light emission data will be described.

  At the timing of t5, as shown in FIG. 32 (b), a light emission data read instruction is given from the CPU 121 to the DMA 123, whereby reading of the light emission data is started as shown in FIG. 32 (e). After that, since the sound data read instruction data is set in the sequence data read to the register 131 of the sound output core 112 at the timing of t6, as shown in FIG. The data transfer unit 134 starts reading the sound data. In this case, in FIGS. 32 (e) and 32 (g), the light emission data read period and the sound data read period are shown to overlap, but actually the memory controller 114 uses the sound data. The light emission data is read between the reading of the sound data while giving priority to the reading of the sound data.

  Thereafter, a rewrite instruction for a series of data corresponding to the program is given from the CPU 121 to the DMA 123 as shown in FIG. In this case, as already described, rewriting of a series of data corresponding to a program has priority over reading of any data, so reading of light emission data is temporarily interrupted as shown in FIG. The reading of the sound data is temporarily interrupted as shown in g), and rewriting of the series data corresponding to the program is started as shown in FIG.

  Thereafter, at the timing of t8, the rewriting of the series data corresponding to the program is completed as shown in FIG. 32 (f), so that the reading of the light emission data is resumed as shown in FIG. 32 (e). Reading of sound data is resumed as shown in (g). In this case, the reading of the light emission data and the sound data is not started from the beginning, but the reading of the light emission data and the sound data is resumed from a state in the middle of being interrupted at the timing t7.

<Relationship between execution cycle of normality determination process and execution period of various processes>
Next, the relationship between the execution cycle of the normal determination process and the execution period of various processes will be described with reference to the explanatory diagram of FIG.

  As described above, in the normality determination process, all of the series of data (for example, 512 bytes) corresponding to the program stored in the sound ROM 103 is read to the general-purpose area 122b of the RAM 122 of the control core 111. This reading takes about 8 msec at the longest. After the series of data corresponding to the program is read to the general-purpose area 122b, the series of data corresponding to the program stored in the program-corresponding area 122a of the RAM 122 and the program corresponding to the program currently read to the general-purpose area 122b of the RAM 122 are read. Are matched in units of 4 bytes, and when it is determined that the two data do not match, the series of data corresponding to the program is read again from the program corresponding area 122a.

  The execution period Ta of the normality determination process is 32 msec. This execution cycle Ta is the shortest period Ta1 required to execute the data transmission process (step S1209) of the main process (FIG. 28) in the execution cycle Ta, and the light emission control of the main process (FIG. 28) in the execution cycle Ta. The shortest period Ta2 required to execute the process (step S1211), the shortest period Ta3 required to execute the timer interrupt process (FIG. 29B) in the execution cycle Ta, and the data comparison result in the execution cycle Ta The period is set to be longer than the sum of the shortest periods Ta4 required for executing the normality determination process (FIG. 30) in a situation where no abnormality occurs. In addition, Ta1 is derived by “the minimum execution period of the data transmission process” × Ta / “the execution period of the data transmission process”, and Ta2 is “the minimum execution period of the light emission control process” × Ta / “execution of the light emission control process. "Ta3" is derived from "Minimum execution period of timer interrupt processing" x Ta / "Period of timer interrupt processing", and Ta4 is a data collation for 512 bytes in a situation where no data collation result error occurs This corresponds to the period required to execute the process.

  Since Ta> (Ta1 + Ta2 + Ta3 + Ta4), the remaining period Ta5 can occur in the execution cycle Ta of the normality determination process. As a result, even if the collation result becomes abnormal in the normality determination process and the series of data corresponding to the program needs to be rewritten, the rewriting can be performed using the remaining period Ta5. However, the period Tb required for rewriting the data is longer than the remainder period Ta5. Therefore, although depending on the timing at which the collation result becomes abnormal, when a data rewrite instruction is issued, rewriting of a series of data corresponding to a program may not be completed within a range of 32 msec. The normality determination process is not executed.

  According to the embodiment described above in detail, the following excellent effects are obtained in addition to the effects described in the first embodiment.

  The control core 111 is provided with a direct ROM 201, and program data and control data are directly read from the direct ROM 201 when the initial activation process and the data rewriting process are executed. As a result, when reading the series of data corresponding to the program from the sound ROM 103 to the RAM 122, it is only necessary to use the data stored in the direct ROM 201, and it is possible to suitably read the series of data corresponding to the program. Become.

  The direct ROM 201 also stores and holds command interrupt data for executing command interrupt processing. This makes it possible to execute command interrupt processing regardless of whether or not a series of data corresponding to a program is being read, and to reliably receive a command transmitted from the MPU 62 of the main control device 60. It becomes possible.

  In a configuration in which the DMA 123 executes read control of light emission data and normality determination data in accordance with a read instruction from the CPU 121 of the control core 111 and also executes rewrite control of a series of data corresponding to the program, rewriting of the series of data corresponding to the program is performed. Priority is given to reading of light emission data and normality determination data. This makes it possible to complete rewriting of a series of data corresponding to the program at an early stage when a collation result abnormality occurs in the normality determination process. Furthermore, when rewriting the series of data corresponding to the program, the reading of the sound data is interrupted in the data transfer unit 134 of the sound output core 112. Also from this point, it is possible to complete rewriting of the series data corresponding to the program at an early stage.

<Other embodiments>
In addition, it is not limited to the description content of embodiment mentioned above, A various deformation | transformation improvement is possible within the range which does not deviate from the meaning of this invention. For example, you may change as follows. Incidentally, the following configuration of another embodiment may be applied individually or in combination to the configuration of the above embodiment.

  (1) The memory controller 114 is not limited to the configuration in which the sound output core 112 is prioritized over the control core 111 as a data read target, and the control core 111 is prioritized over the sound output core 112. It is good. The priority object may be switched depending on the situation. For example, when a series of data corresponding to a program is read by the control core 111, the control core 111 is prioritized over the sound output core 112 as a data read object, and the light emission data Is read out by the control core 111, the sound output core 112 may be prioritized over the control core 111 as a data read target.

  (2) The configuration in which the address data is transmitted to the memory controller 114 is not limited to the two control means of the control core 111 and the sound output core 112, and may be one control means. Even in this case, the address data corresponding to the read instruction for the data other than the sound data among the address data transmitted from the one control means is stored in the control-side address buffer 114a, and the read instruction for the sound data is received. By storing the corresponding address data in the sound output side address buffer 114b, it is possible to prioritize the reading of the sound data as in the above embodiments.

  Further, three or four or more control means may transmit address data to the memory controller 114. In this case, by setting the data read priority among the plurality of control means in advance, even if the address data is simultaneously transmitted from the plurality of control means, the data can be read according to the priority. It becomes possible.

  (3) The type of the control means for reading data from the common ROM such as the sound light ROM 103 is not limited to the control core 111 and the sound output core 112. For example, the display of images on the symbol display device 41 is controlled. The display control means and the sound output control means such as the sound output core 112 may be configured to read data from the common ROM. Even in this case, the memory controller 114 that manages the reading of data from the common ROM performs reading according to a predetermined priority when address data is simultaneously received from the display control means and the sound output control means. A configuration may be adopted in which target address data is determined.

  For example, by giving priority to data reading to the display control means over data reading to the sound output control means, it is possible to prevent a delay in displaying an image on the symbol display device 41. In particular, it is considered that the player plays the game paying attention to the display effect on the symbol display device 41 rather than the effect sound and the sound effect. Therefore, it is preferable to prioritize the data reading to the display control means. Further, in this configuration, display control is performed after the reading of one image data of the image data group necessary for displaying an image in a predetermined period is completed until reading of the next image data is started. By generating the non-access unit period of the means, the sound output control means can read out the sound data using the non-access unit period.

  (4) The sound light ROM 103 may not store sound data, and the sound data may be stored in another ROM. In this case, the memory controller 114 is provided with a ring buffer capable of storing a plurality of address data transmitted from the control core 111. When the memory controller 114 starts reading data corresponding to the address data, the ring buffer It is also possible to adopt a configuration in which the read execution target is determined from the address data having a high priority instead of determining the read execution target in the order of reception among the address data stored in. For example, when the address data for reading the production data and the address data for reading the abnormality notification data are stored in the ring buffer at the same time, the reading of the abnormality notification data has priority over the reading of the production data. It is good also as a structure. Thereby, it is possible to prioritize the abnormality notification over the execution of the effect. In addition, in the configuration in which address data having a high priority is selected from a plurality of address data stored in the ring buffer as described above, data indicating the priority is attached to each address data to be a read execution target. In selecting address data, it is preferable to compare and determine data indicating the priority.

  (5) At least one of the control-side address buffer 114a and the sound output-side address buffer 114b of the memory controller 114 may be a ring buffer capable of storing a plurality of address data according to the reception order. For example, in a configuration in which the sound output side address buffer 114b is a ring buffer, a plurality of address data transmitted from the sound output core 112 can be stored simultaneously, and the address data is read out in accordance with the order received. It becomes possible to make it an execution target.

  (6) The memory controller 114 may not be provided with the control side address buffer 114a corresponding to the non-priority side control means.

  (7) When the memory controller 114 reads data corresponding to the address data received from one of the control core 111 and the sound output core 112, the memory controller 114 reads data corresponding to the address data received from the other. A configuration in which a large amount of data is read may be employed. For example, when reading data corresponding to the address data received from the sound output core 112 which is a priority-side control means, 2-byte data is read and received from the control core 111 which is a non-priority control means. When data corresponding to the address data is read, 1-byte data may be read. As a result, it is possible to read data to the priority-side control means earlier.

  (8) When the memory controller 114 receives one piece of address data from the sound output core 112, the memory controller 114 reads all sound data of a plurality of bytes for one channel, which is a read instruction target in the sound output core 112, and When one address data is received from 111, a configuration may be adopted in which some bytes of the plurality of bytes of light emission data to be read by the control core 111 are read.

  (9) The data read from the sound ROM 103 to the RAM 122 of the control core 111 when the supply of operating power to the control core 111 is started are the program data (1) to the program data (L) and the processing data (1). The processing data (M) and the command data (1) to the command data (N) are not limited, and all of the program data (1) to the program data (L) are to be read. May be read when it is necessary for executing the program. Also, all of the program data (1) to program data (L) and the processing data (1) to processing data (M) are to be read, and other cases are necessary when executing the program. It is good also as a structure read. Also, all of the program data (1) to program data (L) and command data (1) to command data (N) are to be read, and other data are read when necessary for program execution. It is good also as a structure. Also, all of the program data (1) to program data (L) and at least one of the processing data (1) to processing data (M) and the command data (1) to command data (N). The configuration may be such that the unit is read out.

  (10) The unit reading period for a predetermined period is divided into a unit reading period for the HWD 132 and a unit reading period for the SCM 133, and the sound data is read so that the non-access unit period is evenly generated in each unit reading period. The configuration is not limited to the configuration in which the period is adjusted, and the non-access unit period is uniformly generated in the entire unit reading period without being divided into the unit reading period for the HWD 132 and the unit reading period for the SCM 133. In this way, the sound data read period may be adjusted. However, even in this configuration, the length of the non-access unit period that is evenly distributed varies depending on the number of channels for which digital musical tone data needs to be created.

  (11) The sound data corresponding to a plurality of channels is not limited to a configuration in which sound data corresponding to one channel is read out in one reading period of sound data existing across the non-access unit period. May be read, or a part of sound data corresponding to one channel may be read.

  (12) When the memory controller 114 receives address data corresponding to a data read instruction having a higher priority than the data being read while reading 1-byte data, the memory controller 114 stops reading the data being executed. Or it is good also as a structure which interrupts and starts reading of the data corresponding to the newly received address data.

  (13) Of the DMA 123 and the data transfer unit 134, the configuration is not limited to the configuration in which data is read while the non-access unit period is generated only in the data transfer unit 134. The non-access unit period is generated only in the DMA 123. However, the data may be read out, or the data may be read out while the non-access unit period is generated in both the DMA 123 and the data transfer unit 134.

  (14) In the third embodiment, instead of the configuration in which the remainder period Ta5 is shorter than the period Tb required for data rewrite, the remainder period Ta5 may be longer than the period Tb required for data rewrite. . As a result, it is possible to reduce the influence on the execution cycle of the normal determination process when rewriting of a series of data corresponding to the program occurs.

  (15) When determining whether or not the program-corresponding series of data read to the program-corresponding area 122a of the RAM 122 is normal, after first reading all the program-corresponding series of data to the general-purpose area 122b of the RAM 122, The collation between the program-corresponding series of data read into the program-corresponding area 122a and the program-corresponding series of data read into the general-purpose area 122b is performed in units of 4 bytes. In addition, instead of reading all of the series data corresponding to the program to the general-purpose area 122b, it is possible to read only 4 bytes corresponding to the data to be collated when performing the collation processing, and perform the collation processing.

  (16) The collation processing for specifying whether or not the program-corresponding series of data read to the program-corresponding area 122a is normal is not limited to a configuration in which the collation processing is performed in units of 4 bytes, or 1 byte or The configuration may be performed in units of bytes less than 4 bytes, such as 2 bytes, or may be configured in units of bytes greater than 4 bytes, such as 5 bytes or 6 bytes. Moreover, it is good also as a structure by which the whole series of program corresponding | compatible data are made into the execution object of one collation process.

  (17) When rewriting of a series of program-corresponding data read to the program corresponding area 122a of the RAM 122 occurs, processing other than processing for waiting for completion of rewriting of the series of data corresponding to the program is executed. It is good also as a structure to be made. For example, it is monitored whether or not an abnormality notification command is received from the MPU 62 of the main control device 60, and when the command is received, a processing program and control data for starting the abnormality notification are directly updated. It is good also as a structure which can be beforehand memorize | stored in the attached ROM 201 and can start abnormality alert | reporting also in the condition where the rewriting of the series data corresponding to a program is performed.

  (18) As in the case where a series of data corresponding to a program is rewritten, reading of data for normal determination to the general-purpose area 122b of the RAM 122 has priority over reading of light emission data and reading of sound data. Also good.

  (19) A configuration that periodically monitors whether data read from the ROM to the RAM is normal may be applied to data other than a series of data corresponding to a program.

  For example, the MPU 62 of the main control device 60 having the low probability mode and the high probability mode as the success / failure lottery mode refers to the success / failure lottery table for the low probability mode stored in advance in the ROM 63 if the low probability mode is selected. Then, in the configuration in which the high / low probability mode determination lottery table stored in advance in the ROM 63 is referenced, the corresponding random determination table is stored in the RAM 64 while at least one of the low probability mode and the high probability mode is stored, and Whether or not the winning lottery table stored in the RAM 64 is normal is checked periodically. And when it is specified that there is an abnormality in the data of the success / failure lottery table read to the RAM 64, the success / failure lottery table is re-read. Thereby, the possibility that an abnormal winning / raising table is used is reduced while suppressing the frequency of reading the winning / raising table from the ROM 63.

  Further, for example, the control core 111 is not configured to read all program-corresponding series data to the program-corresponding area 122 a of the RAM 122, but is configured to read all data tables for determining the execution contents of the effect to the RAM 122 in advance. In this case, whether or not these data tables are normal is periodically checked. When it is specified that there is an abnormality in the data table read into the RAM 122, the data table is excluded from the use target, and another data table is used as an alternative. This reduces the possibility of using an abnormal data table while eliminating the need to re-read the data table.

  (20) Instead of the configuration in which the display control device 90 is controlled by the sound emission control device 80 based on the command transmitted from the main control device 60, the display control is performed based on the command transmitted from the main control device 60. The device 90 may be configured to control the sound emission control device 80. Further, instead of the configuration in which the sound emission control device 80 and the display control device 90 are separately provided, both the control devices may be provided as one control device, and one of the two control devices has a function. May be integrated into the main control device 60, and both functions of these two control devices may be integrated into the main control device 60. The configuration of the command transmitted from the main control device 60 to the sound emission control device 80 and the configuration of the command transmitted from the sound emission control device 80 to the display control device 90 are also arbitrary.

  (21) Other types of pachinko machines different from the above-described embodiments, such as pachinko machines that release a predetermined number of times when a game ball enters a specific area of a special device, or game balls in a specific area of a special device The present invention can also be applied to a pachinko machine that generates a right if a player enters, a pachinko machine equipped with other objects, an arrangement ball machine, a sparrow ball, and other gaming machines.

  Also, a non-ball-type gaming machine, for example, a plurality of reels with a plurality of types of symbols attached in the circumferential direction, starts rotation of the reel by inserting a medal and operating a start lever, and a stop switch is operated. If a specific symbol or a combination of specific symbols is established on the active line visible from the display window after the reel has stopped after a predetermined time has passed, a privilege such as paying out medals is given to the player The present invention can also be applied to a slot machine.

  In addition, the gaming machine main body that is supported by the outer frame so as to be openable and closable is provided with a storage unit and a capture device, and the start lever is operated after a predetermined number of game balls stored in the storage unit are captured by the capture device. Thus, the present invention can also be applied to a gaming machine in which a pachinko machine and a slot machine are fused, which starts rotating the reel.

<Invention Group Extracted from Each Embodiment>
Hereinafter, the characteristics of the invention group extracted from each of the above-described embodiments will be described while showing effects and the like as necessary. In the following, for easy understanding, the corresponding configuration in each of the above embodiments is appropriately shown in parentheses, but is not limited to the specific configuration shown in parentheses.

<Feature A group>
Feature A1. Storage means (sound light ROM 103) for storing information in advance;
A management unit (memory controller 114) that reads information corresponding to the read instruction information from the storage unit when the read instruction information is received;
With
When the management unit receives a plurality of read instruction information, the management unit determines the read instruction information to be read out according to a predetermined priority different from the reception order of the read instruction information. A gaming machine comprising means (function for executing the processing of steps S810 to S813 in the memory controller 114).

  According to the feature A1, the read instruction information to be read out of information is determined according to the priority different from the reception order of the read instruction information. Therefore, information with high priority can be quickly transmitted regardless of the reception order. It can be read out.

Feature A2. A request response means (DMA 123, data transfer unit 134) for transmitting the read instruction information to the management means on condition that an information read request has been made;
When the management means receives the read instruction information, the management means reads unit information having an information amount smaller than an information amount of information corresponding to the read request,
The determination of the read instruction information to be read by the determining means can occur after the reading of the unit information is completed even when the reading of the information corresponding to the reading request is not completed. The gaming machine according to Feature A1, characterized by:

  According to the feature A2, the amount of information to be read is suppressed for one transmission of the read instruction information, and even if the information corresponding to the read request is not completely read, When the reading of information in response to the transmission of the read instruction information is completed, the read instruction information to be executed is determined according to the priority, so that information with a high priority can be read at an early stage.

  Feature A3. The gaming machine according to Feature A2, wherein the unit information is information of a minimum unit that is possible when information is read.

  According to the feature A3, since the information to be read is the minimum unit information that can be read for one transmission of the read instruction information, the frequency of determining the read instruction information to be executed is increased. Is possible.

Feature A4. A request response means (DMA 123, data transfer unit 134) for transmitting the read instruction information to the management means on condition that an information read request has been made;
Any of the features A1 to A3, wherein the request handling means instructs reading of information having a smaller amount of information than information corresponding to the read request by transmitting the read instruction information to the management means. The gaming machine according to 1.

  According to the feature A4, the request handling unit is configured to instruct reading of information with a smaller information amount than information corresponding to the reading request by transmitting the read instruction information once. In a configuration in which the management is positively performed, the management unit need only read information according to the read instruction information.

  Feature A5. Even if the management means receives read instruction information having a higher priority than the read instruction information that triggered the reading of the information during the reading of the information, the management means continues to read the information that is being executed. A gaming machine according to any one of features A1 to A4.

  According to the feature A5, when reading of information corresponding to the read instruction information is started in the management unit, reading of the information is completed regardless of the subsequent reception status of the read instruction information. As a result, it is possible to prevent the processing for reading information from becoming complicated while enabling high-priority information to be read early.

  Feature A6. The management means includes instruction information storage means (control side address buffer 114a, sound output side address buffer 114b) for storing the received read instruction information. The gaming machine described.

  According to the feature A6, even when new read instruction information is received in the middle of reading information, the new read instruction information can be stored in the instruction information storage means, so that the information reading is completed. In this case, it is possible to start reading new information at an early stage. Further, if the read instruction information is stored in the instruction information storage means, and if the read instruction information having a high priority is stored in the instruction information storage means until the reading of the information is completed, the read with the high priority is performed. The instruction information is an execution target of information reading. Therefore, it is possible to increase the chance that information corresponding to read instruction information with high priority is read.

Feature A7. First control means (control core 111) for executing first control using information stored in the storage means;
Second control means (sound output core 112) for executing second control using information stored in the storage means;
With
The determination means executes the reading of information from the read instruction information received from the non-priority control means with respect to the read instruction information received from the priority control means of the first control means and the second control means. The gaming machine according to any one of features A1 to A6, wherein priority is given to determining a target.

  According to the feature A7, it is possible to prioritize the reading of information by the priority control means of the first control means and the second control means over the reading of information by the non-priority control means.

Feature A8. The first control means includes first request response means (DMA123) for transmitting the read instruction information to the management means on condition that an information read request has been made,
The second control means includes second request response means (data transfer unit 134) for transmitting the read instruction information to the management means on condition that an information read request has been made,
The management means, when receiving the read instruction information from at least the side corresponding to the non-priority control means of the first request response means and the second request response means, from information corresponding to the read request Read unit information that is a small amount of information,
The determination of the read instruction information to be read by the determining means can occur after the reading of the unit information is completed even when the reading of the information corresponding to the reading request is not completed. A gaming machine according to Feature A7, characterized in that

  According to the feature A8, at least for the non-priority control means, the amount of information to be read is reduced with respect to one transmission of read instruction information, and reading of information corresponding to the read request is completed. Even if not, when reading of information for one transmission of read instruction information is completed, determination of read instruction information to be executed is performed while giving priority to the control means on the priority side, It becomes possible to read out information in the priority-side control means at an early stage.

  Feature A9. The gaming machine according to Feature A8, wherein the unit information is information of a minimum unit that can be read when reading information.

  According to feature A9, at least for the non-priority control means, the information to be read is the minimum unit of information that can be read for one transmission of read instruction information, so the read instruction to be executed It is possible to increase the frequency with which information is determined.

Feature A10. The first control means includes first request response means (DMA123) for transmitting the read instruction information to the management means on condition that an information read request has been made,
The second control means includes second request response means (data transfer unit 134) for transmitting the read instruction information to the management means on condition that an information read request has been made,
Of the first request handling means and the second request handling means, at least the side corresponding to the non-priority control means sends the read instruction information to the management means from the information corresponding to the read request. The gaming machine according to any one of features A7 to A9, which instructs to read out information with a small amount of information.

  According to feature A10, at least the non-priority control means is configured to instruct reading of information with a smaller amount of information than information corresponding to a read request by transmitting read instruction information once. In a configuration in which the amount of information is positively read, the management unit need only read the information according to the read instruction information.

  Feature A11. Even if the management means receives read instruction information having a higher priority than the read instruction information that triggered the reading of the information during the reading of the information, the management means continues to read the information that is being executed. The gaming machine according to any one of features A7 to A10, wherein:

  According to the feature A11, when reading of information corresponding to the read instruction information is started in the management unit, reading of the information is completed regardless of the subsequent reception status of the read instruction information. As a result, it is possible to prevent the processing for reading information from becoming complicated while enabling high-priority information to be read early.

Feature A12. The management means includes instruction information storage means (control side address buffer 114a, sound output side address buffer 114b) for storing the read instruction information,
When the read instruction information received from the priority-side control means is stored in the instruction information storage means at the information read start timing, the determining means sets the read instruction information as an information read execution target. The gaming machine according to any one of features A7 to A11, wherein:

  According to the feature A12, for example, even when new read instruction information is received from the priority control means during the reading of information to the non-priority control means, the new read instruction information is stored in the instruction information storage means. Therefore, when the reading of information is completed, the reading of information toward the priority control means can be started at an early stage.

Feature A13. The management means includes
Priority storage means (sound output side address buffer 114b) for storing the read instruction information received from the priority control means;
Non-priority storage means (control-side address buffer 114a) for storing the read instruction information received from the non-priority control means;
The gaming machine according to any one of features A7 to A12, comprising:

  According to the feature A13, the storage means for storing the read instruction information received from the priority control means and the read instruction information received from the non-priority control means are different. As a result, when the read instruction information is stored in the priority storage means, the management means sets the read instruction information as an information read execution target, and the read instruction information is not stored in the priority storage means. In this case, the read instruction information stored in the non-priority storage means may be the information read execution target. That is, since it is possible to distinguish the priority side and the non-priority side according to the type of the storage means, it is possible to simplify the process in the case where the management means determines the information read execution target.

  Feature A14. When at least one of the priority-side control means and the non-priority-side control means reads out the predetermined correspondence information for use in a predetermined period, the partial information of the predetermined correspondence information is read out. Adjustment means (data transfer unit 134, sequence data SD) that adjusts the transmission timing of the read instruction information so that a non-read period occurs after the completion of the reading of other partial information in the predetermined correspondence information. The gaming machine according to any one of features A7 to A13, wherein:

  According to the feature A14, even when the predetermined correspondence information for use in a predetermined period is read, the read instruction information is transmitted so that the read is performed in units of some information, and one piece of information The read instruction information is transmitted so that a non-read period occurs between the completion of the read operation and the read instruction information corresponding to the reading of the next partial information. Thereby, it is possible to prevent the waiting period for reading information in the other control unit from becoming long.

  Feature A15. The gaming machine according to Feature A14, wherein the one control means is the priority-side control means.

  Since the priority-side control means is prioritized over the non-priority-side control means when determining the information read-out execution target, the information is read out to the priority-side control means at an early stage, while the priority-side control means. If the transmission of the read instruction information from the means is continued, the non-priority control means is not given an opportunity to read information, and the non-priority control means waits for information to be read for a long time. There is a possibility that On the other hand, since the non-reading period is positively set in the priority-side control means, an opportunity for reading information in the non-priority-side control means is secured, and a long period of time for waiting for information reading Is suppressed.

Feature A16. The adjustment means is information for adjustment in which the transmission timing of the read instruction information for each partial information included in the predetermined correspondence information is predetermined,
The gaming machine according to A14 or A15, wherein the one control means transmits the read instruction information in accordance with the transmission timing defined in the adjustment information.

  According to the feature A16, it is possible to cause the non-reading period only by transmitting the read instruction information according to the adjustment information.

  Feature A17. The gaming machine according to any one of features A14 to A16, wherein the adjustment is performed by the adjustment means so that the non-reading period is uniform in a predetermined continuous period.

  According to the feature A17, since the non-reading period is set evenly, it is possible to evenly generate information reading opportunities in the other control means.

Feature A18. The one control means includes
A plurality of sound information storage means (CH areas 143a to 143p, 144a to 144p) for storing sound information created using information read from the storage means;
Output execution means (sound data processing unit 113, HWD132, SCM 133) for controlling the sound output means so that sounds corresponding to the sound information stored in the plurality of sound information storage means are simultaneously output;
With
The predetermined correspondence information is information for creating a plurality of sound information to be output simultaneously in the predetermined period,
Any one of the features A14 to A17, wherein the partial information is information used to create partial sound information among a plurality of pieces of sound information corresponding to the predetermined correspondence information. Game machines.

  According to the feature A18, in the configuration in which information is read in units of partial information when reading information for use in a predetermined period, the partial information is one of a plurality of pieces of sound information to be output simultaneously. This is information used for creating sound information of a part. That is, the information for creating one piece of sound information is divided in units of partial information without being divided. Thereby, even when information is read out in units of partial information, the read information can be easily handled.

  Feature A19. The gaming machine according to Feature A18, wherein the partial sound information is sound information stored in one of the sound information storage means.

  According to the feature A19, since the unit of information is divided by the unit of sound information, the frequency of occurrence of the non-reading period is increased while disabling division reading of information for creating one sound information. Is possible.

  Feature A20. Information used to create the predetermined period and each sound information so that the non-reading period occurs even when sound output is performed using the maximum number of sound information that can be output simultaneously. The gaming machine according to Feature A18 or A19, characterized in that is set.

  According to the feature A20, it is possible to cause a non-reading period regardless of the type of sound information to be output at the same time.

  Feature A21. In the configuration that does not require the predetermined period to read out the information necessary for outputting the sound for the predetermined period, the information necessary for performing the sound output for the predetermined period is read out during the predetermined period. The gaming machine according to any one of features A18 to A20, wherein information necessary to output a sound exceeding the limit is not read.

  According to the feature A21, since information read out in a predetermined period for performing sound output is limited to information necessary for performing sound output for a predetermined period, the non-reading period can be generated to the maximum in the predetermined period. It becomes possible.

Feature A22. The one control means includes
First sound information is created by using the information created in the first mode, and the first sound information is stored in the first sound information storage means of the sound information storage means (HWD132). When,
The second sound information is created using the information created in the second mode, and the second sound information is stored in the second sound information storage means of the sound information storage means (SCM 133). When,
With
The predetermined period and the non-reading period are generated so that the non-reading period occurs regardless of whether the information for generating the first sound information is read or the information for generating the second sound information is read. The gaming machine according to any one of features A18 to A21, wherein information used to create each sound information is set.

  According to the feature A22, the non-reading period occurs in any case where the information for creating the first sound information is read out and the information for creating the second sound information is read out. Regardless of the type of sound information to be output, it is possible to suppress the lengthening of the period of waiting for information reading in the other control means.

  Feature A23. When the other control unit of the priority-side control unit and the non-priority-side control unit reads out the specific correspondence information to be used in a specific period, the specific correspondence is determined with respect to the transmission timing of the read instruction information. No adjustment is made so that a non-reading period occurs after reading of partial information of information is completed until reading of other partial information in the specific correspondence information is started. The gaming machine according to any one of A14 to A22.

  According to feature A23, in the configuration in which the transmission timing of the read instruction information is adjusted by one control means, the transmission timing of the read instruction information is not adjusted by the other control means. The processing configuration can be simplified compared to the configuration in which the process is performed.

  Feature A24. The other control means periodically transmits read instruction information corresponding to each piece of information included in the specific correspondence information when the specific correspondence information is read. The gaming machine described in 1.

  According to feature A24, since the other control unit only needs to periodically transmit read instruction information corresponding to some information until the reading of the specific correspondence information is completed, the other control unit reads the information. This simplifies the processing configuration.

Feature A25. In the storage means,
Program information (program data (1) to program data (L), processing data (1) to processing data (M), command data (1) required for executing a program in the first control means ) To command data (N)),
First control information (light emission data (1) to light emission data (P)) necessary for determining the control mode of the control object when executing the first control according to the program,
Second control information (sound data (1) to sound data (Q)) necessary for determining the control mode of the control target when the second control means executes the second control;
Is at least remembered,
The first control means reads out the program information to the first storage means (RAM 122) during a period in which no instruction to read the first control information and the second control information occurs (step S302 in the CPU 121). A gaming machine according to any one of features A7 to A24, wherein the gaming machine is provided with a function of executing the process (DMA123).

  According to the feature A25, the program information is read in a period in which the instruction for reading the first control information and the second control information is not generated, so that the program information can be read at an early stage.

  Feature A26. The gaming machine according to Feature A25, wherein the reading unit reads the program information into the first storage unit when supply of operating power to the first control unit is started.

  According to feature A26, when supply of operating power to the first control means is started, all of the program information is read out to the first storage means, and thereafter the first control information and the second control information It is possible to make it unnecessary to read the program information at the timing when the information read instruction is generated.

Feature A27. The first control means includes
After the program information is read to the first-side storage means by the read-out means, a re-readout means (in the first embodiment, the step in the CPU 121) that reads the program information again into the first-side storage means. A function for executing the process of S405 and the DMA 123; in the second embodiment, a function for executing the process of step S905 in the CPU 121 and the DMA 123);
When the program information is newly read by the re-reading means, means for restricting reading of the first control information and the second control information (CPU 121 in the first embodiment). A function for executing the process of step S404 in the second embodiment, a function for executing the process of step S906 in the CPU 121 in the second embodiment, and a function for executing the process of step S1506 in the CPU 121 in the third embodiment.
A gaming machine according to Feature A26, comprising:

  According to the feature A27, by reading the program information again, the first control unit can execute the program using the normal program information. In this case, when the program information is read again, the reading of the first control information and the second control information is limited, so that the program information can be read again at an early stage.

Feature A28. The first control means comprises storage execution means for storing the information in storage means (ring buffer of the RAM 122) when information is received from outside the first control means, and the information stored in the storage means is stored in the information stored in the storage means. It is a configuration that executes the corresponding control,
Any of the features A25 to A27, wherein the information is stored in the storage unit by the storage execution unit even when the program information is being read by the first storage unit. A gaming machine according to claim 1.

  According to feature A28, even when information is received from the outside of the first control means in a situation where the program information is being read out to the first side storage means, the information is stored in the storage means. Therefore, the information can be prevented from being invalidated.

Feature A29. The first control means includes
When the information confirmation timing comes after reading the program information to the first storage means, confirmation means for confirming whether or not the program information has been rewritten (step S402 in the CPU 121 in the first embodiment). And the function of executing the process of step S403, the function of executing the processes of step S902 and step S903 in the CPU 121 in the second embodiment, and the function of executing the processes of step S1502 and step S1503 in the CPU 121 in the third embodiment. When,
Re-reading means (first embodiment) that causes the first-side storage means to newly read the program information when it is confirmed by the checking means that rewriting of the program information has occurred. In the second embodiment, the function of executing the process of step S405 in the CPU 121 and the DMA 123, in the second embodiment, the function of executing the process of step S905 in the CPU 121 and the DMA 123, and in the third embodiment, the function of executing the process of step S1505 in the CPU 121. DMA123),
The gaming machine according to any one of features A25 to A28, comprising:

  According to feature A29, when the program information read to the first storage unit is abnormal, the program information is read again to the first storage unit, so the program information is abnormal. Nevertheless, the possibility that the program is executed in the first control means is reduced.

  In addition, with respect to any one of the features A1 to A29, any one or more of the features A1 to A29, the features B1 to B10, the features C1 to C5, the features D1 to D8, and the features E1 to E11 are used. You may apply. Thereby, it becomes possible to produce a synergistic effect by the combined configuration.

<Feature B group>
Feature B1. Storage means (sound light ROM 103) for storing information in advance;
First control means (control core 111) for executing first control using information stored in the storage means;
Second control means (sound output core 112) for executing second control using information stored in the storage means;
A management unit (memory controller 114) that reads information corresponding to the read instruction information from the storage unit when the read instruction information is received;
With
When one of the first control means and the second control means reads out the predetermined correspondence information for use in a predetermined period, after the partial information of the predetermined correspondence information has been read out, Adjustment means (data transfer unit 134, sequence data SD) for adjusting the transmission timing of the read instruction information so that a non-read period occurs before reading of some other information in the predetermined correspondence information is started,
When the other control unit of the first control unit and the second control unit reads the specific correspondence information for use in the specific period, the specific control information is transmitted with respect to the transmission timing of the read instruction information. A gaming machine, characterized in that no adjustment is made so that a non-reading period occurs after reading of partial information is completed and reading of other partial information in the specific correspondence information is started.

  According to the feature B1, even when the predetermined correspondence information for use in a predetermined period is read, the read instruction information is transmitted so that the read is performed in units of some information, and one piece of information The read instruction information is transmitted so that a non-read period occurs between the completion of the read operation and the read instruction information corresponding to the reading of the next partial information. As a result, it is possible to prevent the waiting period for reading information in the other control unit from becoming long.

  Further, in the configuration in which the transmission timing of the read instruction information is adjusted by one control means, the transmission timing of the read instruction information is not adjusted by the other control means, and therefore the transmission timing is adjusted by both control means. Compared to the above, the processing configuration can be simplified.

  Feature B2. The management means determines the read instruction information received from the one control means over the read instruction information received from the other control means when determining an execution target of information reading (memory controller 114). The gaming machine according to Feature B1, further comprising: a function of executing the processing of Steps S810 to S813.

  According to the feature B2, it is possible to prioritize the reading of information by the priority control means of the first control means and the second control means over the reading of information by the non-priority control means.

  In this case, since the priority-side control means is prioritized over the non-priority-side control means in determining the information read-out execution target, the information is read out to the priority-side control means at an early stage. When transmission of the read instruction information from the priority control means is continued, the non-priority control means is not given an opportunity to read information, and the non-priority control means waits for information read May become longer. On the other hand, since the non-reading period is positively set in the priority-side control means, an opportunity for reading information in the non-priority-side control means is secured, and a long period of time for waiting for information reading Is suppressed.

Feature B3. The adjustment means is information for adjustment in which the transmission timing of the read instruction information for each partial information included in the predetermined correspondence information is predetermined,
The gaming machine according to the feature B1 or B2, wherein the one control means transmits the read instruction information in accordance with the transmission timing defined in the adjustment information.

  According to the feature B3, it is possible to generate the non-reading period only by transmitting the read instruction information according to the adjustment information.

  Feature B4. The gaming machine according to any one of the characteristics B1 to B3, wherein the adjustment is performed by the adjustment unit so that the non-reading period is uniform in a predetermined continuous period.

  According to the feature B4, since the non-reading period is set evenly, it is possible to evenly generate information reading opportunities in the other control means.

  Feature B5. The other control means, when reading the specific correspondence information, periodically transmits read instruction information corresponding to each piece of information included in the specific correspondence information. Thru | or the game machine of any one of B4.

  According to the feature B5, since the other control unit only needs to periodically transmit read instruction information corresponding to some information until the reading of the specific correspondence information is completed, the other control unit reads the information. This simplifies the processing configuration.

Feature B6. The one control means includes
A plurality of sound information storage means (CH areas 143a to 143p, 144a to 144p) for storing sound information created using information read from the storage means;
Output execution means (sound data processing unit 113, HWD132, SCM 133) for controlling the sound output means so that sounds corresponding to the sound information stored in the plurality of sound information storage means are simultaneously output;
With
The predetermined correspondence information is information for creating a plurality of sound information to be output simultaneously in the predetermined period,
Any one of the characteristics B1 to B5, wherein the partial information is information used to create a part of sound information among a plurality of pieces of sound information corresponding to the predetermined correspondence information. Game machines.

  According to the feature B6, in the configuration in which information is read in units of partial information when reading information for use in a predetermined period, the partial information is one of a plurality of pieces of sound information to be output simultaneously. This is information used for creating sound information of a part. That is, the information for creating one piece of sound information is divided in units of partial information without being divided. Thereby, even when information is read out in units of partial information, the read information can be easily handled.

  Feature B7. The gaming machine according to Feature B6, wherein the partial sound information is sound information stored in one of the sound information storage means.

  According to the feature B7, since the unit of the information is divided by the unit of the sound information, the frequency of occurrence of the non-reading period is increased while disabling the divided reading of the information for creating one sound information. Is possible.

  Feature B8. Information used to create the predetermined period and each sound information so that the non-reading period occurs even when sound output is performed using the maximum number of sound information that can be output simultaneously. The gaming machine according to Feature B6 or B7, characterized in that is set.

  According to the feature B8, it is possible to cause a non-reading period regardless of the type of sound information to be output at the same time.

  Feature B9. In the configuration that does not require the predetermined period to read out the information necessary for outputting the sound for the predetermined period, the information necessary for performing the sound output for the predetermined period is read out during the predetermined period. The game machine according to any one of features B6 to B8, wherein information necessary to output a sound exceeding the limit is not read.

  According to the feature B9, since information read out in a predetermined period for performing sound output is limited to information necessary for sound output for a predetermined period, the non-reading period can be generated to the maximum in the predetermined period. It becomes possible.

Feature B10. The one control means includes
First sound information is created by using the information created in the first mode, and the first sound information is stored in the first sound information storage means of the sound information storage means (HWD132). When,
The second sound information is created using the information created in the second mode, and the second sound information is stored in the second sound information storage means of the sound information storage means (SCM 133). When,
With
The predetermined period and the non-reading period are generated so that the non-reading period occurs regardless of whether the information for generating the first sound information is read or the information for generating the second sound information is read. The gaming machine according to any one of features B6 to B9, wherein information used to create each sound information is set.

  According to the feature B10, the non-reading period occurs in any of the case where the information for creating the first sound information is read and the case where the information for creating the second sound information is read. Regardless of the type of sound information to be output, it is possible to suppress the lengthening of the period of waiting for information reading in the other control means.

  In addition, with respect to any one of the features B1 to B10, any one or more of the features A1 to A29, the features B1 to B10, the features C1 to C5, the features D1 to D8, and the features E1 to E11 are used. You may apply. Thereby, it becomes possible to produce a synergistic effect by the combined configuration.

<Feature C group>
Feature C1. Storage means (sound light ROM 103) for storing information in advance;
First control means (control core 111) for executing first control using information stored in the storage means;
Second control means (sound output core 112) for executing second control using information stored in the storage means;
With
In the storage means,
Program information (program data (1) to program data (L), processing data (1) to processing data (M), command data (1) required for executing a program in the first control means ) To command data (N)),
First control information (light emission data (1) to light emission data (P)) necessary for determining the control mode of the control object when executing the first control according to the program,
Second control information (sound data (1) to sound data (Q)) necessary for determining the control mode of the control target when the second control means executes the second control;
Is at least remembered,
The first control means reads out the program information to the first storage means (RAM 122) during a period in which no instruction to read the first control information and the second control information occurs (step S302 in the CPU 121). A game machine characterized by having a function of executing the process (DMA123).

  According to the feature C1, it is possible to read out the program information at an early stage by reading out the program information in a period in which an instruction to read out the first control information and the second control information is not generated.

  Feature C2. The gaming machine according to claim C1, wherein the reading unit reads the program information into the first storage unit when supply of operating power to the first control unit is started.

  According to the feature C2, since all of the program information is read out to the first storage unit when the supply of the operating power to the first control unit is started, the first control information and the second control information are thereafter It is possible to make it unnecessary to read the program information at the timing when the information read instruction is generated.

Feature C3. The first control means includes
After the program information is read to the first-side storage means by the read-out means, a re-readout means (in the first embodiment, the step in the CPU 121) that reads the program information again into the first-side storage means. A function for executing the process of S405 and the DMA 123; in the second embodiment, a function for executing the process of step S905 in the CPU 121 and the DMA 123);
When the program information is newly read by the re-reading means, means for restricting reading of the first control information and the second control information (CPU 121 in the first embodiment). The function of executing the process of step S404 in the second embodiment, the function of executing the process of step S906 in the CPU 121 in the second embodiment),
The gaming machine according to Feature C2, further comprising:

  According to the feature C3, by reading the program information again, the first control unit can execute the program using the normal program information. In this case, when the program information is read again, the reading of the first control information and the second control information is limited, so that the program information can be read again at an early stage.

Feature C4. The first control means comprises storage execution means for storing the information in storage means (ring buffer of the RAM 122) when information is received from outside the first control means, and the information stored in the storage means is stored in the information stored in the storage means. It is a configuration that executes the corresponding control,
Any of the features C1 to C3, wherein the information is stored in the storage unit by the storage execution unit even when the program information is being read by the first storage unit A gaming machine according to claim 1.

  According to the feature C4, even when information is received from the outside of the first control unit in a situation where the program information is read to the first side storage unit, the information is stored in the storage unit. Therefore, the information can be prevented from being invalidated.

Feature C5. The first control means includes
When the information confirmation timing comes after reading the program information to the first storage means, confirmation means for confirming whether or not the program information has been rewritten (step S402 in the CPU 121 in the first embodiment). And a function of executing the process of step S403, a function of executing the processes of step S902 and step S903 in the CPU 121 in the second embodiment),
Re-reading means (first embodiment) that causes the first-side storage means to newly read the program information when it is confirmed by the checking means that rewriting of the program information has occurred. In the second embodiment, the function of executing the process of step S405 in the CPU 121 and the DMA 123, and in the second embodiment, the function of executing the process of step S905 in the CPU 121 and the DMA 123),
The gaming machine according to any one of features C1 to C4, comprising:

  According to the feature C5, when the program information read to the first storage unit is abnormal, the program information is read to the first storage unit again, so the program information is abnormal. Nevertheless, the possibility that the program is executed in the first control means is reduced.

  In addition, with respect to any one of the features C1 to C5, any one or more of the features A1 to A29, features B1 to B10, features C1 to C5, features D1 to D8, and features E1 to E11 are used. You may apply. Thereby, it becomes possible to produce a synergistic effect by the combined configuration.

<Feature D group>
Feature D1. Storage means (sound light ROM 103) for storing information in advance;
A management unit (memory controller 114) that reads information corresponding to the read instruction information from the storage unit when the read instruction information is received;
A plurality of sound information storage means (CH areas 143a to 143p, 144a to 144p) for storing sound information created using the information read from the storage means;
Output execution means (sound data processing unit 113, HWD132, SCM 133) for controlling the sound output means so that sounds corresponding to the sound information stored in the plurality of sound information storage means are simultaneously output;
When reading the predetermined correspondence information for creating a plurality of sound information to be output at the same time in a predetermined period, among the plurality of sound information corresponding to the predetermined correspondence information by transmitting the one read instruction information Read instruction means (data) for reading a part of information used for creating a part of sound information and for reading the whole of the predetermined correspondence information by transmitting the read instruction information a plurality of times. Transfer unit 134);
A gaming machine characterized by comprising:

  According to the feature D1, when the predetermined correspondence information is read, the read instruction information is transmitted so that the reading is performed in units of some information. It is possible to generate an opportunity to receive read instruction information of information different from the information in the management means.

  In addition, in the configuration in which information is read in units of some information when reading information for use in a predetermined period, the partial information is a part of sound information among a plurality of sound information to be output simultaneously. Information used to create That is, some information units are divided without dividing information for creating one sound information. Thereby, even when information is read out in units of partial information, the read information can be easily handled.

  Feature D2. The read instructing unit is configured to read the instructed read information so that a non-reading period is generated after reading of the partial information of the predetermined correspondence information is completed until reading of the other partial information in the predetermined correspondence information is started. The game machine according to Feature D1, further comprising adjusting means (sequence data SD) for adjusting the transmission timing of the game.

  According to the feature D2, it is possible to ensure a period during which reading instruction information of information different from the information included in the predetermined correspondence information can be received even during the reading of the predetermined correspondence information.

Feature D3. The adjustment means is information for adjustment in which the transmission timing of the read instruction information for each partial information included in the predetermined correspondence information is predetermined,
The game machine according to claim D2, wherein the read instruction means transmits the read instruction information in accordance with the transmission timing defined in the adjustment information.

  According to the feature D3, it is possible to generate the non-reading period only by transmitting the read instruction information according to the adjustment information.

  Feature D4. The gaming machine according to feature D2 or D3, wherein the adjustment is performed by the adjustment means so that the non-reading period is equal in a predetermined continuous period.

  According to the feature D4, since the non-reading period is set evenly, it is possible to evenly read information different from the predetermined correspondence information.

  Feature D5. Information used to create the predetermined period and each sound information so that the non-reading period occurs even when sound output is performed using the maximum number of sound information that can be output simultaneously. Is set, The gaming machine according to any one of features D2 to D4.

  According to the feature D5, it is possible to cause a non-reading period regardless of the type of sound information to be output at the same time.

  Feature D6. In the configuration that does not require the predetermined period to read out the information necessary for outputting the sound for the predetermined period, the information necessary for performing the sound output for the predetermined period is read out during the predetermined period. The game machine according to any one of features D2 to D5, wherein information necessary to output a sound exceeding the limit is not read.

  According to the feature D6, since information read out in a predetermined period for performing sound output is limited to information necessary for performing sound output for a predetermined period, the non-reading period can be generated to the maximum in the predetermined period. It becomes possible.

Feature D7. The one control means includes
First sound information is created by using the information created in the first mode, and the first sound information is stored in the first sound information storage means of the sound information storage means (HWD132). When,
The second sound information is created using the information created in the second mode, and the second sound information is stored in the second sound information storage means of the sound information storage means (SCM 133). When,
With
The read instruction means is one read instruction information regardless of whether the information for creating the first sound information is read out or the information for creating the second sound information is read out. The gaming machine according to any one of features D1 to D6, wherein the partial information is read out by transmitting.

  According to the feature D7, reading of information different from the predetermined correspondence information is performed regardless of whether the information for creating the first sound information is read or the information for creating the second sound information is read. An opportunity to receive the instruction information in the management means can be generated.

  Feature D8. The gaming machine according to any one of features D1 to D7, wherein the partial sound information is sound information stored in one of the sound information storage means.

  According to the feature D8, since the unit of the information is divided by the unit of the sound information, it is impossible to divide and read the information for creating one sound information, and the information about the information different from the predetermined correspondence information It is possible to generate many opportunities to accept read instruction information.

  In addition, with respect to any one of the features D1 to D8, any one or more of the features A1 to A29, features B1 to B10, features C1 to C5, features D1 to D8, and features E1 to E11 are used. You may apply. Thereby, it becomes possible to produce a synergistic effect by the combined configuration.

<Feature E group>
Feature E1. A first storage means (sound light ROM 103) for storing information in advance;
Second storage means (program corresponding area 122a) in which predetermined information read from the first storage means is written;
Predetermined control means (CPU 121) for executing predetermined control using write information (program-compatible series data) written in the second storage means;
When the information confirmation timing comes, confirmation means for confirming whether or not the written information written in the second storage means is normal (in the first embodiment, the processing of steps S402 and S403 in the CPU 121 is performed). A function to be executed, a function to execute the processes of steps S902 and S903 in the CPU 121 in the second embodiment, a function to execute the processes of steps S1502 and S1503 in the CPU 121 in the third embodiment), and
A gaming machine characterized by comprising:

  According to the feature E1, in the configuration in which the predetermined control is executed using the write information written from the first storage means to the second storage means, the write information written in the second storage means is normal. This is performed when confirmation of whether or not there is a confirmation timing. As a result, if the write information written in the second storage means is abnormal, it is possible to take some measures, and the predetermined control may continue to be executed as it is using the abnormal write information. Is reduced.

  Feature E2. When the confirmation means confirms that the write information is not normal, the rewrite means for newly writing the write information in the second storage means (in the first embodiment, in step S405 in the CPU 121) A function for executing the process and the DMA 123, a function for executing the process of step S905 in the CPU 121 and the DMA 123 in the second embodiment, and a function for executing the process of step S1505 in the CPU 121 and the DMA 123 in the third embodiment are provided. The gaming machine according to Feature E1, characterized in that:

  According to the feature E2, when there is an abnormality in the write information written in the second storage means, the write information is written to the second storage means again, so the write information is abnormal. Therefore, the possibility that the write information is continuously used in the predetermined control means is reduced.

  Feature E3. When the write information is newly written by the rewrite means, means for restricting reading of information different from the write information from the first storage means (in the first embodiment, step S404 in the CPU 121). A function of executing the process of step S906 in the CPU 121 in the second embodiment, and a function of executing the process of step S1506 in the CPU 121 in the third embodiment). The gaming machine according to feature E2.

  According to the feature E3, when the write information is written again, reading of information different from the write information is restricted, so that the write information can be rewritten early.

Feature E4. The write information includes program information (program data (1) to program data (L), processing data (1) to processing data (M), necessary for executing the program in the predetermined control means, Command data (1) to command data (N)),
When the write information is newly written by the rewrite means, the predetermined control means uses the information stored in the third storage means (direct ROM 201) to perform a process during writing (steps S1504 to S1504 in the CPU 121). The gaming machine according to feature E2 or E3, characterized in that the function of executing the process of step S1508 is executed.

  According to the feature E4, when the program is executed by the predetermined control means, the program information written in the second storage means may be referred to, so that the program information is directly read from the first storage means when the program is executed. There is no need.

  In this case, a third storage unit is provided separately from the first storage unit and the second storage unit, and the information stored in the third storage unit is used in the situation where the rewrite of the write information is performed. Then, the process during writing is executed. This eliminates the need to perform rewriting in such a manner as to enable execution of processing during writing when rewriting the writing information. Therefore, it is possible to rewrite the write information satisfactorily.

  Feature E5. Whether the writing information is normal by reading out the same information as the writing information from the first storage unit and identifying whether the read information matches the writing information. The gaming machine according to any one of features E1 to E4, characterized in that it is confirmed whether or not.

  According to feature E5, when determining whether or not the write information written in the second storage means is normal, information corresponding to the write information stored in the first storage means is directly read out. Since the information is collated, it is possible to accurately determine whether the information is normal.

Feature E6. Means for reading out the same information as the write information from the first storage means and writing it into the confirmation storage means (general-purpose area 122b) (in the first embodiment, the function of executing the processing of step S307 in the CPU 121 and the DMA 123, the third In the embodiment, the CPU 121 has a function of executing the processing of step S1214 in the CPU 121,
The confirmation unit performs a process for confirming whether or not the write information is normal after all the writing of the same information as the write information to the confirmation storage unit is completed. The gaming machine according to feature E5.

  According to feature E6, when determining whether or not the write information written in the second storage means is normal, all of the same information as the write information is first read from the first storage means and confirmed. Whether the write information is normal or not is determined using the information written in the storage unit for storage and then written in the storage unit for confirmation. This makes it possible to collectively write information to the confirmation storage unit as compared to a configuration in which information is sequentially written to the confirmation storage unit according to the progress of the determination as to whether or not it is normal. It is possible to simplify the processing configuration for instructing to write information to the confirmation storage means.

  Feature E7. Even if the same information is read out in a situation where information different from the same information is being read, the writing of the different information is prioritized. A gaming machine according to E6.

  According to the feature E7, it is possible to prioritize reading of other information rather than information for performing normal determination. Thereby, it is possible to execute the normal determination while giving priority to the execution of processing different from the normal determination.

  Feature E8. The features E5 to E7 are characterized in that, when the same information is being read out, when it is time to read out information different from the same information, the reading out of the different information is prioritized. The gaming machine according to any one of the above.

  According to the feature E8, it is possible to prioritize reading of other information over information for performing normal determination. Thereby, it is possible to execute the normal determination while giving priority to the execution of processing different from the normal determination.

  Feature E9. The gaming machine according to any one of features E1 to E8, wherein the confirmation unit confirms whether or not the part of the write information is normal in one confirmation process.

  According to the feature E9, since it is determined whether or not a part of the writing information is normal in one confirmation process, whether or not the writing information is normal after all the writing information is confirmed. It is possible to cope with the occurrence of an abnormality earlier than the configuration in which the determination is performed.

Feature E10. The predetermined control means comprises storage execution means (function for executing command interrupt processing in the CPU 121) for storing the information in the storage means (ring buffer 122c) when information is received from outside the predetermined control means, It is a configuration that executes control corresponding to the information stored in the storage means,
Any of the features E1 to E9, wherein the storage execution unit stores information in the storage unit even when the write information is being written to the second storage unit A gaming machine according to claim 1.

  According to the feature E10, even when information is received from the outside of the predetermined control means in a situation where writing information is written to the second storage means, the information is stored in the storage means and can be used. Therefore, it is possible to prevent the information from being invalidated.

  Feature E11. The gaming machine according to any one of features E1 to E10, wherein the write information includes program information necessary for executing the program in the predetermined control means.

  According to the feature E11, when the program is executed by the predetermined control means, the program information written in the second storage means may be referred to, so that the program information is directly read from the first storage means when the program is executed. There is no need.

  In addition, with respect to any one of the features E1 to E11, any one or more of the features A1 to A29, features B1 to B10, features C1 to C5, features D1 to D8, and features E1 to E11 are used. You may apply. Thereby, it becomes possible to produce a synergistic effect by the combined configuration.

  The invention of the group A, the invention of the group B, the invention of the group C, the invention of the group D and the group E can solve the following problems.

  As a kind of gaming machine, a pachinko gaming machine, a slot machine, and the like are known. These gaming machines are equipped with general-purpose control elements such as a CPU and read-only storage elements such as a ROM, and a series of processes are executed by the general-purpose control elements according to a program read from the read-only storage elements. The game is controlled. It is also known that a general-purpose control element, a read-only memory element, etc. are integrated into one chip.

  A configuration using a dedicated control element as a control element for performing sound output control and display control is also known. In this case, the operation of the control target device is controlled based on the processing performed by the dedicated control element according to the data read from the read-only storage element.

  Here, in the gaming machine such as the above-described example, it is necessary to suitably read out information from the storage means, and there is still room for improvement in this respect.

  The basic configuration of the gaming machine to which the above features can be applied or applied to each feature is shown below.

  Pachinko gaming machine: operation means operated by a player, game ball launching means for launching a game ball based on the operation of the operation means, a ball path for guiding the launched game ball to a predetermined game area, and a game A gaming machine that includes each gaming component arranged in an area, and gives a bonus to a player when a gaming ball passes through a predetermined passing portion of each gaming component.

  Revolving type gaming machine such as a slot machine: equipped with a picture display device for variably displaying a plurality of pictures, variably starting display of the plurality of pictures due to the operation of the start operation means, and due to the operation of the stop operation means In addition, the game machine is configured such that the variable display of the plurality of patterns is stopped when a predetermined time elapses and a privilege is given to the player according to the pattern after the stop.

  DESCRIPTION OF SYMBOLS 10 ... Pachinko machine, 103 ... ROM for sound light, 111 ... Control core, 112 ... Sound output core, 113 ... Sound data processing part, 114 ... Memory controller, 114a ... Control side address buffer, 114b ... Sound output side address buffer, 121 ... CPU, 122 ... RAM, 122a ... Program corresponding area, 122b ... General purpose area, 122c ... Ring buffer, 123 ... DMA, 132 ... HWD, 133 ... SCM, 134 ... Data transfer unit, 143a to 143p, 144a to 144p ... CH area, 201 ... Direct ROM, SD ... Sequence data.

Claims (5)

Storage means for storing information in advance;
First control means for executing first control using information stored in the storage means;
Second control means for executing second control using information stored in the storage means;
With
In the storage means,
Program information necessary for executing the program in the first control means;
First control information necessary for determining a control mode of a control target when executing the first control according to the program;
Second control information necessary for determining the control mode of the control target when the second control means executes the second control;
Is at least remembered,
The first control means includes a reading means for reading the program information to the first storage means during a period in which an instruction for reading the first control information and the second control information is not generated. To play.   2. The gaming machine according to claim 1, wherein the reading unit reads the program information into the first storage unit when supply of operating power to the first control unit is started. The first control means includes
After the program information is read to the first side storage means by the read means, a reread means for reading the program information to the first side storage means again;
Means for restricting reading of the first control information and the second control information when the program information is newly read by the reread means;
The gaming machine according to claim 2, further comprising: The first control means includes storage execution means for storing the information in the storage means when information is received from outside the first control means, and executes control corresponding to the information stored in the storage means. Configuration,
4. The information is stored in the storage unit by the storage execution unit even when the program information is being read by the first storage unit. The gaming machine according to any one of the above. The first control means includes
Confirmation means for confirming whether or not the program information has been rewritten when the information confirmation timing comes after reading the program information to the first-side storage means;
Re-reading means for causing the first-side storage means to newly read the program information when it is confirmed by the checking means that rewriting of the program information has occurred;
The gaming machine according to any one of claims 1 to 4, further comprising:

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