JP2015076801A - Limiter amplifier circuit and driver circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a limiter amplifier circuit that improves reception sensitivity and response characteristic by setting an appropriate DC offset amount to an input amplitude.SOLUTION: A differential amplification circuit 11 amplifies differential input signals. Differential amplification circuits 12, 13 amplify differential output signals of the differential amplification circuit 11. An offset adjustment circuit 18 adjusts a DC offset voltage of differential output signals of the differential amplification circuit 12 in accordance with a DC component of one of differential output signals of the differential amplification circuit 13 and a reference voltage. In the offset adjustment circuit 18, a peak detection circuit 19 detects the DC component of one of the differential output signals of the differential amplification circuit 13. A differential amplification circuit 20 amplifies a voltage difference between an output of the peak detection circuit 19 and the reference voltage REF. A resistor R1 is connected between an output terminal of the peak detection circuit 19 and an input terminal of the differential amplification circuit 20. An external adjustment circuit 30 adjusts a voltage of a junction of the input terminal of the differential amplification circuit 20 and the resistor R1.

Description

  The present invention relates to a limiter amplifier circuit and a driver circuit that can set an appropriate DC offset amount with respect to an input amplitude and can improve reception sensitivity and response characteristics.

  As an optical transmission system that enables high-speed data transmission, an optical transmission system that time-multiplexes a plurality of data signal packets is known. In this system, an optical receiving circuit is used to receive a burst signal.

  FIG. 1 is a diagram showing a conventional optical receiving circuit. The photodiode 100 converts a minute optical signal into a current signal. A transimpedance amplifier 101 (TIA: Trans Impedance Amplifier) converts this current signal into a voltage signal and amplifies it. The limiter amplifier circuit 102 amplifies the output signal of the transimpedance amplifier 101 to a constant amplitude.

  In the optical receiver circuit having such a configuration, a DC offset is generated between the positive phase side IP and the negative phase side IN of the differential output of the transimpedance amplifier 101. The DC offset of the input signal is amplified by the gain of the transimpedance amplifier 101. The magnitude of the DC offset varies depending on the individual difference of the transimpedance amplifier 101. However, when the DC offset is large, there is a problem that the burst response of the limiter amplifier circuit 102 is degraded and good response characteristics cannot be obtained.

  FIG. 2 is a diagram showing a conventional optical receiver circuit having an AC coupling configuration. Coupling capacitors C 1 and C 2 are provided between the transimpedance amplifier 101 and the limiter amplifier circuit 102. Thereby, the influence of the DC offset of the optical receiver circuit of FIG. 1 can be eliminated. However, there is a problem that it takes time until the DC level changes due to the time constant determined by the coupling capacitors C1 and C2 and the input impedance of the limiter amplifier circuit 102, and an appropriate DC offset is obtained. Furthermore, when a differential input signal is not input, the DC output levels of the positive phase output signal and the negative phase output signal are equal, noise is output when there is no signal, and the characteristics of the receiving device at the subsequent stage are affected. There is also.

  In order to solve these problems, an improved limiter amplifier circuit has been proposed (for example, see Patent Document 1). FIG. 3 is a diagram showing an improved conventional limiter amplifier circuit. The differential amplifier circuit 11 amplifies a differential input signal composed of a normal phase input signal IP and a negative phase input signal IN. The differential amplifier circuits 12 and 13 amplify the differential output signal of the differential amplifier circuit 11.

  The offset adjustment circuit 14 includes peak detection circuits 15 and 16 and a differential amplifier circuit 17. The peak detection circuit 15 detects and holds the DC component of the positive phase input signal IP. The peak detection circuit 16 detects and holds the direct current component of the negative phase input signal IN. The differential amplifier circuit 17 negatively feeds back the voltage difference between the DC component of the positive phase input signal IP detected by the peak detection circuits 15 and 16 and the DC component of the negative phase input signal IN to the differential amplifier circuit 11, and this potential difference. Accordingly, the DC offset voltage of the differential output signal of the differential amplifier circuit 11 is adjusted.

  The offset adjustment circuit 18 includes a peak detection circuit 19 and a differential amplifier circuit 20. The peak detection circuit 19 detects and holds the DC component of one of the differential output signals of the differential amplifier circuit 13 that is saturated. The differential amplifier circuit 20 positively feeds back the voltage difference between the DC component of one of the differential output signals of the differential amplifier circuit 13 detected by the peak detection circuit 19 and the reference voltage REF to the differential amplifier circuit 12, The DC offset voltage of the differential output signal of the differential amplifier circuit 12 is adjusted according to this potential difference.

  The reference voltage REF is adjusted to a predetermined value. When a differential signal is input to the input of the limiter amplifier circuit 102, the offset adjustment circuit 18 does not add a DC offset to the DC offset voltage of the differential output signal of the differential amplifier circuit 13, but the input of the limiter amplifier circuit 102. When a differential signal is not input to the signal, a DC offset is added to the DC offset voltage of the differential output signal of the differential amplifier circuit 13. For this reason, when the differential signal is not input to the input of the limiter amplifier circuit 102, it is possible to prevent the DC output levels of the positive phase output signal and the negative phase output signal from being equal, and obtain good response characteristics. Can do.

  FIG. 4 is a diagram showing input signal response characteristics of the limiter amplifier circuit of FIG. FIG. 4A shows an input signal of the limiter amplifier circuit. The input signal is a 10 (1 zero) alternating signal of 10 Gbps. As an input signal, a preamble signal and a payload signal are input from a state of no input. FIG. 4B shows a transient response waveform of the output of the differential amplifier circuit 12 in the limiter amplifier circuit 102. FIG. 4C is a transient response waveform of the output OP and ON of the limiter amplifier circuit 102, and shows a waveform in which the time width of the initial response characteristic is enlarged. The waveform shown in FIG. 4C is a transient response characteristic under conditions when a DC offset is given to an appropriate value when a differential input signal is input to the limiter amplifier circuit 102.

JP 2009-38556 A

  In the limiter amplifier circuit of FIG. 3, the DC offset amount when no differential signal is input to the circuit input is a constant value determined by the value of the predetermined reference voltage REF. Therefore, when an optical signal is input, the operating point (DC offset) given by the reference voltage REF with respect to the input amplitude determined by the PD conversion efficiency (photodiode light-current conversion efficiency) and the gain of the transimpedance amplifier is not necessarily limited. It is not always an appropriate value. Therefore, as can be seen from FIG. 4C, there is a problem that the duty ratio of the differential output of the differential amplifier circuit 12 does not transiently become 50%, the reception sensitivity is lowered, and the response characteristics are also deteriorated. .

  The present invention has been made to solve the above-described problems, and the object thereof is to set an appropriate DC offset amount for the input amplitude, and to improve reception sensitivity and response characteristics. A limiter amplifier circuit that can be obtained is obtained.

  A limiter amplifier circuit according to the present invention includes a first differential amplifier circuit that amplifies a differential input signal composed of a positive phase input signal and a negative phase input signal, and a differential output signal of the first differential amplifier circuit. A differential output signal of the first differential amplifier circuit according to a voltage difference between a DC component of the positive phase input signal and a DC component of the negative phase input signal. A difference between the first offset adjustment circuit for adjusting the DC offset voltage and the second differential amplifier circuit according to the DC component of one of the differential output signals of the second differential amplifier circuit and the reference voltage. A second offset adjustment circuit for adjusting a DC offset voltage of the dynamic output signal; and an external adjustment circuit, wherein the reference voltage is adjusted to a predetermined value, and the second offset adjustment circuit Is input, the difference of the second differential amplifier circuit If no DC offset is added to the DC offset voltage of the output signal and the differential input signal is not input, a DC offset is added to the DC offset voltage of the differential output signal of the second differential amplifier circuit; The second offset adjustment circuit includes: a first peak detection circuit that detects a direct current component of one of the differential output signals of the second differential amplifier circuit; and an output of the first peak detection circuit. A third input terminal configured to amplify a voltage difference between an output of the first peak detection circuit and the reference voltage, the first input terminal being input; and a second input terminal to which the reference voltage is input. A differential amplifier circuit; a first resistor connected between an output terminal of the first peak detection circuit and the first input terminal of the third differential amplifier circuit; The adjustment circuit includes the first differential amplifier circuit of the first differential amplifier circuit. And adjusting the voltage of the connection point between the first resistor and the input terminal.

  According to the present invention, an appropriate DC offset amount can be set with respect to the input amplitude, and the reception sensitivity and response characteristics can be improved.

It is a figure which shows the conventional optical receiver circuit. It is a figure which shows the conventional optical receiver circuit of AC coupling structure. It is a figure which shows the conventional limiter amplifier circuit improved. It is a figure which shows the input signal response characteristic of the limiter amplifier circuit of FIG. It is a figure which shows the limiter amplifier circuit which concerns on embodiment of this invention. It is a figure for demonstrating operation | movement of a 2nd offset adjustment circuit. It is a figure which shows the example of calculation of the optical input level dependence of the output amplitude of the transimpedance amplifier input into a limiter amplifier circuit. FIG. 6 is a diagram illustrating a voltage PKs for giving an optimum DC offset amount (a DC level amount equal to the input amplitude) with respect to an input amplitude of a limiter amplifier circuit in relation to a value of an external adjustment resistor. It is a figure which shows the example of calculation which displayed the optical input level of FIG. 7 per mW. It is a figure which shows the output waveform of the 2nd differential amplifier circuit with respect to the output amplitude of a transimpedance amplifier. It is a figure which shows the input signal response characteristic of the limiter amplifier circuit which concerns on embodiment of this invention. It is a figure which shows the packet transmitter to which the limiter amplifier circuit which concerns on embodiment of this invention is applied.

  FIG. 5 is a diagram showing a limiter amplifier circuit according to the embodiment of the present invention. The photodiode 100 converts an optical signal into an electrical signal. The electrical signal is amplified by the transimpedance amplifier 101. The limiter amplifier circuit 102 amplifies the differential output signal of the transimpedance amplifier 101.

  In the limiter amplifier circuit 102, the differential amplifier circuit 11 amplifies the differential input signal composed of the positive phase input signal IP and the negative phase input signal IN. The differential amplifier circuits 12 and 13 amplify the differential output signal of the differential amplifier circuit 11. The differential output signal of the differential amplifier circuit 13 becomes the positive phase output signal OP and the negative phase output signal ON of the limiter amplifier circuit 102.

  The offset adjustment circuit 18 adjusts the DC offset voltage of the differential output signal of the differential amplifier circuit 12 according to the DC component of one of the differential output signals of the differential amplifier circuit 13 that is saturated and the reference voltage REF. To do. The reference voltage REF is adjusted to a predetermined value. The offset adjustment circuit 18 constitutes a positive feedback loop and automatically adjusts the DC offset voltage of the differential amplifier circuit 12. Specifically, when a differential input signal is input to the limiter amplifier circuit 102, the offset adjustment circuit 18 does not add a DC offset to the DC offset voltage of the differential output signal of the differential amplifier circuit 12, and differential When no input signal is input, a DC offset is added to the DC offset voltage of the differential output signal of the differential amplifier circuit 12.

  The offset adjustment circuit 18 includes a peak detection circuit 19, a differential amplifier circuit 20, and a resistor R1. The peak detection circuit 19 detects and holds the DC component of one of the differential output signals of the differential amplifier circuit 13 that is saturated. The differential amplifier circuit 20 has a first input terminal to which the output of the peak detection circuit 19 is input and a second input terminal to which a reference voltage is input. The output of the peak detection circuit 19 and the reference voltage Amplify the voltage difference of. The resistor R <b> 1 is connected between the output terminal of the peak detection circuit 19 and the first input terminal of the differential amplifier circuit 20.

  The external adjustment circuit 30 includes a resistor R2 connected between the first input terminal of the differential amplifier circuit 20 and the ground (GND), a first input terminal of the differential amplifier circuit 20, and a power supply terminal (constant voltage). And a resistor R3 connected between the source VEE). The external adjustment circuit 30 adjusts the voltage PKs at the connection point between the first input terminal of the differential amplifier circuit 20 and the resistor R1. Accordingly, the differential amplifier circuit 20 positively feeds back the voltage difference between the DC component adjusted by the resistors R1, R2, and R3 and the reference voltage REF to the differential amplifier circuit 12, and the differential amplifier circuit 12 according to the potential difference. The DC offset voltage of the differential output is adjusted.

  The offset adjustment circuit 14 adjusts the DC offset voltage of the differential output signal of the differential amplifier circuit 11 according to the voltage difference between the direct current component of the positive phase input signal IP and the direct current component of the negative phase input signal IN. Specifically, the offset adjustment circuit 14 includes a peak detection circuit 15 that detects and holds the DC component of the positive phase input signal IP, and a peak detection circuit 16 that detects and holds the DC component of the negative phase input signal IN. A differential amplifier circuit 17 that amplifies the voltage difference between the output of the peak detector circuit 15 and the output of the peak detector circuit 16, and between the output terminal of the peak detector circuit 15 and one of the differential inputs of the differential amplifier circuit 17. And a resistor R5 connected between the output terminal of the peak detection circuit 16 and the other differential input of the differential amplifier circuit 17. The differential amplifier circuit 17 amplifies the voltage difference between the DC component of the positive phase input signal IP and the DC component of the negative phase input signal IN detected by the peak detection circuits 15 and 16 and negatively feeds back to the differential amplifier circuit 11. The DC offset voltage of the differential output signal of the differential amplifier circuit 11 is adjusted according to this voltage difference.

  Here, the resistance values of the resistors R4 and R5 are equal to the resistance value of the resistor R1. Thereby, the response time of the offset adjustment circuits 14 and 18 can be matched by making the circuit configuration and circuit constants of the offset adjustment circuits 14 and 18 the same.

  FIG. 6 is a diagram for explaining the operation of the second offset adjustment circuit. When an optical burst signal is input to the photodiode 100, as shown in FIG. 6A, the input IP ′ of the differential amplifier circuit 12 has a waveform upward from the stable point of the DC potential by an amplitude as shown in FIG. appear. Further, the waveform of the input IN ′ of the differential amplifier circuit 12 appears on the lower side of the amplitude. The IP ′ and IN ′ signals become stable because the offset voltages of both signals coincide with each other at a time determined by the offset adjustment circuit 14. In other words, the initial offset becomes a value corresponding to the input amplitude of IP ′ or IN ′, and the offset decreases in a time determined by the offset adjustment circuit 14. The offset adjustment circuit 18 operates to adjust the input DC offset voltage of the differential amplifier circuit 20 so as to follow the change in the offset.

  Here, the reference voltage REF is set so that the voltage difference (corresponding to the offset voltage) between the reference voltage REF applied to the input of the differential amplifier circuit 20 and the voltage PKs becomes a value corresponding to the input amplitude of the initial IP ′, for example. give. Then, when the burst signal is input, the differential amplifier circuit 12 operates so that the DC level of the signal IP ′ decreases by the input amplitude and matches the DC level of the signal IN ′.

  The peak detection circuit 19 is generally composed of a rectifying diode and a capacitor for charging a charge corresponding to the peak value. While the input signal is being input, the peak value of the limit amplitude of the differential amplifier circuit 13 is detected, and the capacitor is charged until the output voltage of the peak detection circuit 19 reaches the peak value of the limit amplitude. Hold. Therefore, with the passage of time, the voltage PKs that is the output of the peak detection circuit 19 increases, and the voltage difference between the reference voltage REF and the voltage PKs decreases. 6B and 6C show the operation of the voltage PKs in the offset adjustment circuit 18 and the operation of the DC offset voltage between the outputs of the differential amplifier circuit 12 at this time.

  FIG. 6B shows the operation of the conventional example without the external resistors R2 and R3, and FIG. 6C shows the operation of this embodiment with the external resistors R2 and R3 added. Here, REF1 indicates a case where a DC offset voltage equal to the input amplitude of IP ′ is applied to the voltage of REF from the voltage PKs at the time of no input, and REF2 is a time during which the first offset adjustment circuit becomes stable. The case where it is adjusted to a voltage equal to the voltage PKs is shown.

  In FIG. 6B, in the case of REF1, an appropriate offset is given to the differential amplifier circuit 12 at the beginning of the burst signal input, and the DC offset voltage between the outputs of the differential amplifier circuit 12 becomes zero. As the IP ′ and IN ′ signals approach a stable state, the voltage of PKs exceeds the voltage of REF1 (the differential amplifier circuit 12 used in the circuit simulation has a gain of 1, and differential amplification Since the gain of the circuit 13 is 5 and the limiter operation is performed), the differential amplifier circuit 12 is finally at a time when the first offset adjustment circuit becomes stable (IP ′ and IN ′ signals are stable). Is given an offset voltage Vof. For this reason, the differential DC operating DC voltage of the differential amplifier circuit is different, the duty ratio of the output signal does not become 50%, and the reception sensitivity deteriorates. In the case of REF2, an appropriate offset is not given to the differential amplifier circuit 12 at the beginning of the burst signal input (the offset voltage of Vof is given to the DC voltages of IP 'and IN'), and differential amplification is performed. The duty ratio of the output signal of the circuit 12 does not become 50%, and the reception sensitivity is deteriorated. FIG. 4 shows operation waveforms in this state. Therefore, in the conventional circuit, the duty ratio of the output signal can be set to an output waveform of 50% in all periods even after the IP ′ and IN ′ signals become stable from the beginning of the burst signal input only by adjusting the voltage REF. First, it will lead to deterioration of reception sensitivity.

  FIG. 6C shows the operation of the PKs terminal voltage when the external resistors R2 and R3 are added in the present embodiment. As in the case of REF1, the voltage REF gives a DC offset voltage having a value corresponding to the input amplitude of IP ′ to the voltage PKs at the beginning of the burst signal input, and the values of the external resistors R2 and R3 are times when the offset adjustment circuit 14 becomes stable The voltage PKs at is given so as to be equal to the voltage REF. For this reason, an appropriate offset is given to the voltage REF at the beginning of the burst signal input, the DC offset voltage between the outputs of the differential amplifier circuit 12 is ideally 0, and the time during which the offset adjustment circuit 14 becomes stable is elapsed. Then, follow up so that an appropriate offset is given by positive feedback.

  Further, since the voltage PKs is applied by the external resistors R2 and R3 so that the voltage PKs becomes equal to the voltage REF when the signals IP ′ and IN ′ are stabilized, the DC offset voltage between the outputs of the differential amplifier circuit 12 is set to zero. be able to. Accordingly, the DC offset voltage between the outputs of the differential amplifier circuit 12 can be set to 0 even after the IP ′ and IN ′ signals become stable from the beginning of the burst signal input. % Output waveform, and waveform response characteristics and reception sensitivity can be improved.

  Hereinafter, specific adjustment of the DC offset amount and input signal response characteristics depending on the conditions will be described. FIG. 7 is a diagram illustrating a calculation example of the optical input level dependence of the output amplitude of the transimpedance amplifier input to the limiter amplifier circuit. The output amplitude of the transimpedance amplifier 101 is obtained from the PD conversion efficiency of the photodiode 100 and the transimpedance gain (Zt) of the transimpedance amplifier 101. In the calculation, the PD conversion efficiency was 0.9 A / W and Zt = 700Ω.

  FIG. 8 shows the change width of the voltage PKs for giving the optimum DC offset amount (DC level amount equal to the input amplitude) to the input amplitude of the limiter amplifier circuit (voltage PKs when there is no input signal and when there is no input signal). Is a diagram showing the relationship between the values of external adjustment resistors. For the combination of resistance values of the external resistors R2 and R3, the horizontal axis indicates the resistance value of the resistor R2 between PKs and GND, and the vertical axis on the left side indicates the change width of the voltage PKs. Specifically, the R2 / R3 resistor for determining the change width of the DC offset voltage and the voltage PKs at which the duty ratio of the transient response waveform of the limiter amplifier output corresponding to the input amplitude of the limiter amplifier circuit is 50% from the packet head. The value was obtained by simulation. It is a simulation result when the differential amplifier circuit 31 with a gain of 5 is inserted between the differential amplifier circuits 11 and 12, and the converted value to the input amplitude on the right side of the vertical axis is the gain of 5 and the value of the change width of the voltage PKs. Divided value. The gain of the differential amplifier circuit 31 is G = 5, and the gain of the differential amplifier circuit 31 can be appropriately designed and added according to the specifications of the optical receiver.

  Here, in order to make the DC potential determined by the external resistors R2 and R3 constant at the connection point between the resistor R1 and the differential amplifier circuit 20, the ratio of the external resistors R2 and R3 is constant, and each of the external resistors R2 and R3 is fixed. The resistance value of was changed. The resistance values of the resistors R1, R4, and R5 were set to a constant value of 500Ω.

  An appropriate DC offset amount for maintaining the minimum receiving sensitivity of the optical receiving circuit is equal to the output amplitude of the transimpedance amplifier 101 corresponding to the minimum receiving sensitivity (corresponding to the input amplitude of the limiter amplifier circuit 102). In FIG. 7, when the minimum reception sensitivity of the transimpedance amplifier 101 is −18 dBm, the output amplitude of the transimpedance amplifier 101 is about 20 mVpp. In FIG. 8, by adjusting the resistance ratio R2 / R3 = 5 KΩ / 10 KΩ, a DC offset amount of 105 mV is obtained with an input amplitude of 21 mVpp close to the input amplitude of the minimum reception sensitivity. This value is input to the differential amplifier circuit 20. As a result of experimentally examining the reception sensitivity characteristics of the optical reception circuit under these conditions, the reception sensitivity was about -17.5 dBm with an error rate of 1E-12, and a value close to the minimum reception sensitivity was obtained.

  Next, waveform response characteristics will be described. FIG. 9 is a diagram showing a calculation example in which the optical input level of FIG. 7 is displayed in mW units. In this calculation example, the output amplitude of the transimpedance amplifier 101 is calculated up to the saturation output.

  FIG. 10 is a diagram showing an output waveform of the differential amplifier circuit 12 with respect to the output amplitude of the transimpedance amplifier. FIG. 10A shows an output waveform of the differential amplifier circuit 12 when the output amplitude of the transimpedance amplifier 101 corresponding to the minimum reception level indicated by a circle in FIG. 9 is input to the limiter amplifier circuit 102. FIG. The differential amplifier circuit 12 is given a DC offset equal to the minimum reception level. In this case, the duty ratio of the waveform is 50%, and high reception sensitivity is obtained.

  FIG. 10B shows an output waveform of the differential amplifier circuit 12 when the output amplitude of the transimpedance amplifier 101 before saturation indicated by a circle in FIG. 9 is input to the limiter amplifier circuit 102. Is given a DC offset equal to the minimum reception level. Although the amplitude is large relative to the DC offset amount, reception is possible. This is because the output of the transimpedance amplifier 101 is a linear output up to the pre-saturation level, so that the duty of 50% is maintained. As the optical input level increases, the noise component relative to the signal component decreases, and the subsequent CDR (clock data recovery) circuit can tolerate a transient duty change generated in the limiter amplifier at the time of high input.

  Further, when the transimpedance amplifier 101 reaches an input level equal to or higher than the saturation point, a change in the duty ratio of the transimpedance amplifier 101 is added, so that packet reception cannot be performed. Therefore, the reception range by the packet signal input can be a high input range from the minimum reception level to the saturation level.

  FIG. 11 is a diagram showing input signal response characteristics of the limiter amplifier circuit according to the embodiment of the present invention. FIG. 11A shows an input signal of the limiter amplifier circuit. The input signal is a 10 (1 zero) alternating signal of 10 Gbps. As an input signal, a preamble signal and a payload signal are input from a state of no input. FIG. 11B shows a transient response waveform of the output of the differential amplifier circuit 12 in the limiter amplifier circuit 102. FIG. 11C is a transient response waveform of the output OP and ON of the limiter amplifier circuit, and shows a waveform in which the time width of the initial response characteristic is enlarged.

  In the limiter amplifier circuit according to the present embodiment, the differential amplifier circuit 12 is given a DC offset equal to the minimum reception level. Therefore, when an optical input signal is input, the operating point (DC offset) of the differential amplifier circuit 12 is appropriately set with respect to the input amplitude determined by the light-current conversion efficiency of the photodiode 100 and the gain of the transimpedance amplifier 101. Can be set to any value. Therefore, the duty ratio of the output of the peak detection circuit is 50% even at the initial stage of the transient response when the burst signal is input, and the reception sensitivity is improved as compared with the conventional circuit. Further, a faster response characteristic can be obtained as compared with the circuit of FIG.

  As described above, the limiter amplifier circuit according to the present embodiment can adjust the DC offset amount of the offset adjustment circuit 18 by the resistance values of the external resistors R2 and R3. It can be set, and the reception sensitivity and response characteristics can be improved.

  Next, FIG. 12 is a diagram showing a packet transmitter to which the limiter amplifier circuit according to the embodiment of the present invention is applied. The multiplexing circuit 41, the attenuator 42, the limiter amplifier circuit 102, and the driver amplifier circuit 43 are driver circuits that drive the EA-DFB laser diode 44.

  The multiplexing circuit 41 multiplexes N packet signals. The attenuator 42 attenuates the output of the multiplexing circuit 41 input through the capacitors C1 and C2. The output of the attenuator 42 is input to the limiter amplifier circuit 102. A driver amplifier circuit 43 amplifies the output of the limiter amplifier circuit 102. The driver amplifier circuit 43 amplifies the output signal of the limiter amplifier circuit 102 to a voltage amplitude that can drive the EA-DFB laser diode 44. The EA-DFB laser diode 44 outputs an optical packet signal according to the input packet electric signal. Here, the output of the multiplexing circuit 41, the input / output of the attenuator 42 and the limiter amplifier circuit 102, and the input of the driver amplifier circuit 43 are performed differentially.

  A positive power source is used for the multiplexing circuit 41 and a negative power source is used for the driver amplifier circuit 43. In the packet signal, since the peak value gradually changes due to the effect of CR during AC coupling, signal degradation increases. In addition, in DC coupling, a plurality of stages are necessary for level shift to satisfy the withstand voltage, and output jitter increases. Therefore, the limiter amplifier circuit 102 according to the present embodiment that can give an appropriate offset to the input burst signal is applied to the packet transmitter.

  However, when the limiter amplifier circuit 102 is used on the transmitter side, the output amplitude of the multiplexing circuit 41 is large, and the offset necessary for the limiter amplifier circuit 102 to operate properly is an offset amount that can be adjusted by the limiter amplifier circuit 102. It will exceed. Therefore, the packet signal input to the limiter amplifier circuit 102 is attenuated by the attenuator 42 to the same extent as the input signal level when used as a receiver. As a result, the limiter amplifier circuit 102 can give an appropriate offset amount, and a limiter output signal without waveform deterioration can be obtained. As a result, the packet transmitter according to the present embodiment can obtain an optical packet output signal without waveform deterioration.

11, 12, 13, 17, 20 Differential amplification circuit, 14, 18 Offset adjustment circuit, 15, 16, 19 Peak detection circuit, 30 External adjustment circuit, 41 Multiplexing circuit, 42 Attenuator, 43 Driver amplification circuit, 102 Limiter amplifier circuit, C1, C2 capacitance, R1, R2, R3, R4, R5 resistance

Claims (5)

A first differential amplifier circuit for amplifying a differential input signal composed of a normal phase input signal and a negative phase input signal;
A second differential amplifier circuit for amplifying a differential output signal of the first differential amplifier circuit;
A first offset adjustment circuit that adjusts a DC offset voltage of a differential output signal of the first differential amplifier circuit according to a voltage difference between a DC component of the positive phase input signal and a DC component of the negative phase input signal. When,
A second offset for adjusting a DC offset voltage of the differential output signal of the second differential amplifier circuit according to a DC component of one signal of the differential output signal of the second differential amplifier circuit and a reference voltage An adjustment circuit;
With an external adjustment circuit,
When the reference voltage is adjusted to a predetermined value and the differential input signal is input, the second offset adjustment circuit converts the DC offset voltage of the differential output signal of the second differential amplifier circuit to DC. If the differential input signal is not input without adding an offset, a DC offset is added to the DC offset voltage of the differential output signal of the second differential amplifier circuit,
The second offset adjustment circuit includes:
A first peak detection circuit for detecting a DC component of one of the differential output signals of the second differential amplifier circuit;
A first input terminal to which an output of the first peak detection circuit is input; and a second input terminal to which the reference voltage is input; the output of the first peak detection circuit and the reference voltage A third differential amplifier circuit for amplifying the voltage difference between
A first resistor connected between an output terminal of the first peak detection circuit and the first input terminal of the third differential amplifier circuit;
The limiter amplifier circuit, wherein the external adjustment circuit adjusts a voltage at a connection point between the first input terminal of the third differential amplifier circuit and the first resistor. The external adjustment circuit is
A second resistor connected between the first input terminal of the third differential amplifier circuit and ground;
The limiter amplifier circuit according to claim 1, further comprising a third resistor connected between the first input terminal and a power supply terminal of the third differential amplifier circuit. The first offset adjustment circuit includes:
A second peak detection circuit for detecting a DC component of the positive phase input signal;
A third peak detection circuit for detecting a DC component of the negative phase input signal;
A fourth differential amplifier circuit for amplifying a voltage difference between the output of the second peak detection circuit and the output of the third peak detection circuit;
A fourth resistor connected between the output terminal of the second peak detection circuit and one of the differential inputs of the fourth differential amplifier circuit;
A fifth resistor connected between the output terminal of the third peak detection circuit and the other differential input of the fourth differential amplifier circuit;
The limiter amplifier circuit according to claim 2, wherein resistance values of the fourth and fifth resistors are equal to a resistance value of the first resistor.   The limiter amplifier circuit according to claim 1, wherein the differential output of the second differential amplifier circuit is saturated. A multiplexing circuit for multiplexing N signals;
An attenuator for attenuating the output of the multiplexing circuit input via a capacitor;
The limiter amplifier circuit according to any one of claims 1 to 4, wherein an output of the attenuator is input;
A driver circuit comprising a driver amplifier circuit for amplifying the output of the limiter amplifier circuit.

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