JP2015072584A - Detection device and signal detection module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a detection device of which reading of a detection signal is fast, and a signal detection module capable of efficiently performing reading operation as a whole module.SOLUTION: A detection device includes a signal detection circuit 1 of a semiconductor substrate (IC chip) 10, and a control circuit 2 which controls permission of output of the detection signal to the outside of the substrate. The control circuit includes an address circuit 3 which comprises data of bit number n (n is positive integer) and holds an address for IC chip discrimination, a counter circuit 4 of bit number n for counting a clock number of a clock signal CLK that is supplied from the outside of the semiconductor integrated circuit, and a gate circuit 5 which sequentially compares the discrimination address with a value that has changed by counting of the counter circuit and permits outputting of the detection signal to the outside of the IC chip when they agree with each other.

Description

  The present invention relates to a detection device that can quickly read out a detection signal generated by a signal detection circuit, and a signal detection module that includes a plurality of such detection devices.

Japanese Patent Application Laid-Open No. 2004-151561 discloses means for selecting a main device such as a CPU from a plurality of peripheral devices such as memory devices. That is, in an information processing device including a plurality of peripheral devices each including a memory cell array and a common main device connected to each of these peripheral devices, each of the peripheral devices has a register in which device-specific address information is stored. The address information output from the main device is compared with the unique address information, and has a selection means for selecting only the peripheral device whose information matches. . This information processing device
A circuit for selecting a peripheral device by the main device can be simplified, and it is not necessary to manufacture a variety of peripheral devices for each device number.

  Patent Document 2 discloses a multi-chip photoelectric conversion device that aims to reduce the photoelectric conversion sensitivity difference between individual chips in the multi-chip photoelectric conversion device. This is configured by arranging a plurality of photoelectric conversion elements and a plurality of image sensor chips each having a scanning circuit for sequentially reading out optical signals and an output processing circuit for outputting the read signals to the outside. In each of the photoelectric conversion devices, each of the image sensor chips can have two or more different settings, including a set value, for the gain setting of the output circuit, and this setting is controlled by using an externally taken out pad as an input. It is set through the output of the circuit. In addition, the multichip integrated circuit includes a gain-settable output circuit arranged in each chip for each chip, and compares the photoelectric conversion sensitivity of the chip with the photoelectric conversion sensitivity of the other chip to thereby increase the output level of the chip. The output levels of the other chips are almost the same. Since the level of photoelectric conversion output of each chip of a multi-chip arranged in large numbers can be made substantially the same, the difference in photoelectric conversion sensitivity between individual chips can be reduced.

JP-A-1-217529 JP-A-9-214700

As described above, when reading a conventional detection signal, an address corresponding to each detection device is sent, and output is performed in synchronization with the clock signal only when the corresponding address is provided (see Patent Document 1). Therefore, there is a problem that the time for sending the address is lost. Further, when the detectors are used in an array, there is a problem that a loss corresponding to the number of the detectors occurs, and the increase in readout time becomes remarkable.
The present invention has been made for such a situation, and a detection device that can quickly read out a detection signal, or a signal that can be efficiently read out as a whole module when a plurality of detection devices are arranged to form a signal detection module. A detection module is provided.

  The detection device of the present invention includes a signal detection circuit formed in a semiconductor integrated circuit, and a control circuit that controls whether a detection signal generated by the signal detection circuit is output to the outside of the semiconductor integrated circuit, The control circuit includes an address circuit configured of data of bit number n (n is a positive integer) and holding an identification address of the semiconductor integrated circuit, and a clock number of a clock signal supplied from the outside of the semiconductor integrated circuit. A counter circuit with n bits to count, the identification address held by the address circuit and the value changed by the counting in the counter circuit are sequentially compared, and when both match, the detection signal is the semiconductor integrated And a gate circuit that permits output to the outside of the circuit. The output of the detection signal to the outside of the semiconductor integrated circuit is permitted on condition that an output enable signal is given from the outside of the semiconductor integrated circuit, and the counter circuit is initialized after the value is initialized by the output. Counting may be started.

  The signal detection module of the present invention is a signal detection module in which a plurality of the detection devices are arranged and the counter circuit included in each of the detection devices performs counting synchronized with the same clock signal. Of these, the first detection device has the address composed of first data, the second detection device has the address composed of second data, and the number of clocks of the clock signal increases. The detection signals are sequentially output from the first and second detection devices.

    In the detection apparatus of the present invention, the output operation is performed in synchronization with the count result of the predetermined number of clocks included in the clock signal, so that the detection signal is read out quickly. In addition, when a plurality of detection devices are arranged to form a signal detection module, detection signals are sequentially output from each detection device in the process of increasing the number of clock signals, so that the entire module can be efficiently read out. Done and the time is reduced.

1 is a plan view of an IC chip on which a signal detection circuit according to Embodiment 1 is formed. FIG. 2 is a waveform diagram illustrating an output enable signal (OE) and a clock signal (CLK) that control the signal detection circuit of FIG. 1. Circuit diagram of the signal detection circuit described in this embodiment FIG. 6 is a block diagram of a signal detection module according to a second embodiment. The figure which shows the address of the IC chip used for the signal detection module of FIG. The figure explaining the state of the component at each timing in the signal detection module of FIG.

  Hereinafter, embodiments of the invention will be described with reference to examples.

The first embodiment will be described with reference to FIGS.
FIG. 1 shows a semiconductor chip such as silicon on which a detection device is formed. In this embodiment, the semiconductor chip is represented by an IC chip (sensor IC1). This IC chip has a signal detection circuit 1 formed on a semiconductor substrate 10 and a control circuit 2 for controlling whether or not a detection signal generated by the signal detection circuit 1 is output from an external terminal 7. 1 and an external terminal 7 are provided with a switch 6 for on / off control of the output. The signal detection circuit 1 and the control circuit 2 are connected to an external terminal 7 via a switch 6.
The signal detection circuit 1 will be described using, for example, a photoelectric conversion circuit shown in FIG. This photoelectric conversion circuit includes a current-voltage conversion circuit 11, an amplification circuit 12, an output circuit 13, an optical signal detection means 14, and an output terminal 15.

The current-voltage conversion circuit 11 includes an operational amplifier 17 having a first input terminal (+), a second input terminal (−), and an output terminal, a capacitor C having both ends connected to the second input terminal and the output terminal, and a capacitor C. The reset switch 16 is connected in parallel and resets the current-voltage conversion circuit 11. The reference voltage Vref is input to the first input terminal (+) of the operational amplifier 17 and the light is input to the second input terminal (−). The output voltage of the signal detection means 14 is input.
The amplifier circuit 12 is connected between an operational amplifier 18 having a first input terminal (+), a second input terminal (−) and an output terminal, an output terminal of the operational amplifier 17, and a second input terminal (−) of the operational amplifier 18. And the resistor R2 connected between the second input terminal (−) and the output terminal of the operational amplifier 17, and the reference voltage Vref is input to the first input terminal (+) of the operational amplifier 18. The output of the operational amplifier 17 is input to the two input terminals (−) via the resistor R1.
The output circuit 13 includes an operational amplifier 19 having a first input terminal (+), a second input terminal (−), and an output terminal. The first input terminal (+) is connected to the output of the operational amplifier 18 and has a second input. The end (−) is connected to the output end, and the output end is connected to the output terminal 15.

Next, the control circuit 2 will be described.
The control circuit 2 is composed of data of bit number n (n is a positive integer), and holds an address circuit 3 for holding an identification address for identifying the IC chip (sensor IC1), and from the outside of the IC chip (sensor IC1). The counter circuit 4 having n bits for counting the number of clocks of the supplied clock signal (CLK), the identification address held by the address circuit 3 and the value changed by counting in the counter circuit 4 are sequentially compared, And the gate circuit 5 that permits the detection signal generated by the signal detection circuit 1 to be output to the outside of the IC chip (sensor IC1).

When the output enable signal (OE) is given from the outside of the IC chip (sensor IC1), the detection signal is output to the outside of the IC chip (sensor IC1) according to the counting result of the number of clocks of the clock signal (CLK). Output is allowed. The counter circuit 4 starts counting after its value is initialized by the output.
The address circuit 3 is composed of data of n bits (n is a positive integer) (in this embodiment, n = 3), and holds an identification address of the IC chip (sensor IC1). In this case, it has an address (001) (see FIG. 5). The counter circuit 4 is a circuit having a bit number n (n = 3 in this embodiment) for counting the number of clocks of the clock signal (CLK) supplied from the outside.
The gate circuit 5 sequentially compares the identification address held by the address circuit 3 and the value changed by the count in the counter circuit 4, and outputs the detection signal output from the signal detection circuit 1 when the two match. It is a circuit that permits output to. The gate circuit 5 is composed of five logic circuits. The logic circuits 51-53 are EXCLUSIVE NOR circuits (hereinafter abbreviated as EX-NOR), which outputs 1 when the two inputs match, and outputs 0 when they do not match. The logic circuits 54 and 55 are 3-input and 2-input AND circuits (AND), and output 1 only when all inputs are 1.

The IC chip (sensor IC1) holds the address (001), and a 3-bit signal is output from the address circuit 3 based on an address signal (ADD) from the outside. The first output line is a first digit signal line and is connected to the first input terminal of the logic circuit 51 (EX-NOR). The second output line is a second-digit signal line and is connected to the first input terminal of the logic circuit 52 (EX-NOR). The third output line is a third digit signal line, and is connected to the first input terminal of the logic circuit 53 (EX-NOR).
On the other hand, the counter circuit 4 counts the number of clocks of the clock signal (CLK) supplied from the outside, and the count (counter) value is output from the counter circuit 4. The first output line is a first digit signal line and is connected to the second input terminal of the logic circuit 51 (EX-NOR). The second output line is a signal line for the second digit and is connected to the second input terminal of the logic circuit 52 (EX-NOR). The third output line is a third digit signal line, and is connected to the second input terminal of the logic circuit 53 (EX-NOR).
The output signal lines of the logic circuits 51-53 (EX-NOR) are respectively connected to the input terminals of the logic circuit 54 (AND). An output enable (OE) signal line is connected to the first input terminal of the logic circuit 55 (AND), and an output line of the logic circuit 54 (AND) is connected to the second input terminal.
The output line of the logic circuit 55 (AND) is connected to a switch 6 provided between the signal detection circuit 1 and the external terminal 7, and this output controls on / off of this switch.

Next, the operation of the IC chip (sensor IC1) shown in FIG. 1 will be described. FIG. 2 shows the relationship between the output enable signal (OE) and the clock signal (CLK). The address value for the IC chip (sensor IC1) is set in advance in the address circuit 3 so as to be effective from the time of power-on. At the time of output, since the output enable signal (OE) is inputted, a signal corresponding to the identification address (001) is outputted from the address circuit 3 to the gate circuit 5, and at the same time, the counter circuit 4 inputs the clock signal (CLK). The number is counted and the counter value is output from the counter circuit 4 to the gate circuit 5.
The output signal from the address circuit 3 is “1” output from the first digit signal line and is input to the first input terminal of the logic circuit 51 (EX-NOR), and “0” is output from the second digit signal line. Is output to the first input terminal of the logic circuit 52 (EX-NOR), “0” is output from the third digit signal line, and input to the first input terminal of the logic circuit 53 (EX-NOR). To do.
In this embodiment, the number of input clocks 1 is counted. Then, the counter value 001 is counted, and this value is output from the counter circuit 4. The output signal from the counter circuit 4 is “1” output from the first digit signal line and is input to the second input terminal of the logic circuit 51 (EX-NOR), and “0” is output from the second digit signal line. Is output to the second input terminal of the logic circuit 52 (EX-NOR), “0” is output from the third digit signal line, and input to the second input terminal of the logic circuit 53 (EX-NOR). To do.

Signals from the address circuit 3 and the counter circuit 4 are input, and the input values of the logic circuits 51-53 (EX-NOR) are compared. Since these three logic circuits have the same input value for each pair, the outputs are all “1”. Since this output is input to the logic circuit 54 (NAND) having three input terminals, the output is “1” and is input to the second input terminal of the logic circuit 55 (NAND). Since the output enable signal is input to the first input terminal and is “1”, the output of the logic circuit 55 (NAND) is “1”. Therefore, this output signal turns on the switch 6 and sends the output signal of the signal detection circuit 1 from the external terminal 7 to the outside.
Next, a case where the counter circuit 4 counts the number of input clocks 2 in the IC chip (sensor IC1) (count value 010) will be described.
The output from the address circuit 3 is the same as in the case of the input clock number 1 described above, and is input to the first input terminal of the logic circuit 51-53 (EX-NOR). The counter (counter) value counted by the counter circuit 4 is (010) and is input to the second input terminal of the logic circuits 51-53 (EX-NOR).

Signals from the address circuit 3 and the counter circuit 4 are input, and the input values of the logic circuits 51-53 (EX-NOR) are compared. Among these, the input values of the respective pairs of the logic circuits 51-52 (EX-NOR) do not match, so the output values of the two logic circuits are “0”. Since the input pair of the logic circuit 53 (EX-NOR) matches, the output value is “1”. Therefore, the input values of the logic circuit 54 to which these outputs are input do not match and “0” is output. The output of the logic circuit 54 is input to the second input terminal of the logic circuit 55 (NAND). Since the output enable signal is input to the first input terminal and is “1”, the output of the logic circuit 55 (NAND) is “0”. Therefore, this output signal turns off the switch 6 and stops sending the output signal of the signal detection circuit 1 from the external terminal 7 to the outside.
As described above, according to this embodiment, the output operation is performed in synchronization with the count result of the predetermined number of clocks included in the clock signal, so that the detection signal can be read quickly.

Next, Embodiment 2 will be described with reference to FIGS.
The signal detection module shown in FIG. 4 includes a plurality of detection devices including the IC chip (sensor IC1) described in the first embodiment.
The IC chips (sensor IC2, sensor IC3) have the same configuration as that shown in FIG. 1, but have different identification addresses. The address of the sensor IC2 is (010), and the address of the sensor IC3 is (011) (see FIG. 5).
The IC chip has first and second input ends and output ends, and each output end is connected to an external terminal OUT of the module by wiring.
An output enable (OE) signal line is connected to the first input terminal of each IC chip, and a clock (CLK) signal line is connected to the second input terminal.
Each IC chip operates the output enable signal (OE), then inputs the clock signal (CLK) from the outside, and outputs a signal corresponding to the identification address from the address circuit to the gate circuit. At the same time, the counter circuit Then, the number of input clocks is counted, and the counter value is compared with the identification address by the gate circuit.

Next, the operation of the signal detection module in accordance with the timing will be described with reference to FIG.
First, at timing t0, the counter is in a reset state, and the count (counter) value of the counter circuit is (000). At the next timing t1, a counter value (001) is obtained. This counter value matches the address of the IC chip (sensor IC1) as the first detection device, and as a result, the detection signal of the first detection device is output to the outside. Since the addresses of the other second detection devices (sensor IC2) and third detection device (sensor IC3) do not match this counter value, the output of the detection signal to the outside is not permitted.
At the next timing t2, the number of input clocks is counted to obtain a counter value (010). This counter value matches the address of the IC chip (sensor IC2) as the second detection device, and as a result, the detection signal of the second detection device is output to the outside, and the detection signal of the first detection device is external The output to can be stopped. Since the address of the third detection device (sensor IC3) does not match this counter value, output of the detection signal to the outside is not permitted.

At the next timing t3, the number of input clocks is counted to obtain a counter value (011). This counter value coincides with the address of the IC chip (sensor IC3) which is the third detection device. As a result, the detection signal of the third detection device is output to the outside, and the detection signal of the second detection device is external. Output to is stopped. Since the address of the first detection device (sensor IC1) does not match this counter value, output of the detection signal to the outside is not permitted.
As described above, when a plurality of detection devices are arranged to form a signal detection module, detection signals are sequentially output from each detection device in the process of increasing the number of clock signals, so that the entire module can be read efficiently and the time Is shortened.

DESCRIPTION OF SYMBOLS 1 ... Signal detection circuit 2 ... Control circuit 3 ... Address circuit 4 ... Counter circuit 5 ... Gate circuit 6 ... Switch 7 ... External terminal 10 ... Semiconductor substrate 11. .. Current-voltage conversion circuit 12... Amplifier circuit 13... Output circuit 14... Optical signal detection means 15... Output terminal 16 .. Reset switch 17-19.・ Logic circuit

Claims (3)

A signal detection circuit formed in the semiconductor integrated circuit; and a control circuit that controls whether or not a detection signal generated by the signal detection circuit is output to the outside of the semiconductor integrated circuit. an address circuit configured of n (n is a positive integer) data and holding an identification address of the semiconductor integrated circuit, and a bit number n for counting the number of clocks of a clock signal supplied from the outside of the semiconductor integrated circuit The counter circuit and the identification address held by the address circuit are sequentially compared with the value changed by the count in the counter circuit, and when the two match, the detection signal is output outside the semiconductor integrated circuit. And a gate circuit that permits the detection.   The output of the detection signal to the outside of the semiconductor integrated circuit is permitted on condition that an output enable signal is given from the outside of the semiconductor integrated circuit, and the counter circuit is initialized after the value is initialized by the output. 2. The detection apparatus according to claim 1, wherein counting is started. A signal detection module in which a plurality of detection devices according to claim 1 are arranged and the counter circuit included in each of the detection devices performs counting synchronized with the same clock signal. In the process of increasing the number of clocks of the clock signal, the first detection device has the address including the first data, and has the address including the second data among the plurality of detection devices. The signal detection module, wherein the detection signals are sequentially output from the first and second detection devices.

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