JP2015064718A - Signal processor, signal analysis system, signal generation system, signal analysis method, and signal generation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal processor, a signal analysis system, a signal generation system, a signal analysis method, and a signal generation method capable of, when simultaneously performing signal processing in parallel by using a plurality of daisy chain-connected signal processors, achieving synchronism between the plurality of signal processors with high accuracy.SOLUTION: The signal processor includes a delay correction value calculation part 19d for calculating a delay correction value as a time until an internal trigger signal output from a trigger signal generation part 19a is transmitted via a switching part 19c, a trigger signal output terminal 11 and a cable c1, and detected by a trigger signal detection part 19b in a state that the trigger signal output terminal 11 is connected to the output side of the trigger signal generation part 19a by the switching part 19c, and that the trigger signal output terminal 11 is connector-connected via the cable c1 to a trigger signal input terminal 10.

Description

  The present invention relates to a signal processing device, a signal analysis system, a signal generation system, a signal analysis method, and a signal generation method, and more particularly to a daisy chain connectable signal processing device, a signal analysis system, a signal generation system, a signal analysis method, and The present invention relates to a signal generation method.

  In recent years, with the spread of large-capacity content services and the like, there has been a demand for a significant improvement in transmission speed (throughput). For example, in LTE-A (LTE-Advanced) based on 3GPP (Third Generation Partnership Project), carrier aggregation, MIMO (Multi Input Multi Output) system, etc. are adopted as technologies that meet such requirements.

  Carrier aggregation is a technique for virtually creating a larger frequency band by aggregating a plurality of different frequency bands (component carriers). By this carrier aggregation, for example, two carriers of 2 GHz band and 800 MHz band having different propagation environments can be aggregated, thereby realizing improvement in communication stability in addition to improvement in throughput.

  The MIMO scheme is a scheme for performing high-speed data communication using M × N paths formed between a plurality of M antennas on the transmission side and a plurality of N antennas on the reception side.

  Thus, for a communication system that simultaneously transmits and receives a plurality of different signals, a signal analyzer is used when evaluating the quality of a signal on the transmission side (see, for example, Patent Document 1).

JP 2009-250719 A

  For example, when measuring a plurality of signals to be measured with different frequencies, such as 2 GHz band and 800 MHz band, with a signal analyzer, the measurement band of one signal analyzer is limited, so one signal It is difficult to analyze a plurality of signals under measurement using an analyzer. In that case, it is necessary to perform measurement in parallel using a plurality of signal analyzers.

  As a method of connecting a plurality of signal analyzers with cables when performing measurement by synchronizing a plurality of signal analyzers with a trigger signal, star connection and daisy chain connection can be mentioned.

  In the case of star connection, a plurality of signal analyzers are connected by cables around a branch circuit (hub). At this time, in order to trigger each signal analyzer simultaneously, the lengths of the cables after the branch circuit need to be exactly the same.

  However, as the number of signal analyzers increases, the distance from the branch point to each device increases, so the lengths of all cables must be increased accordingly. In particular, when branch circuits are provided over several stages, it is necessary to sandwich a buffer in order to prevent a voltage drop, and there is a problem that cable wiring becomes complicated.

  On the other hand, daisy chain connection is a method of connecting a plurality of signal analyzers in a daisy chain, so that no branch circuit is required, and even when the number of signal analyzers is large, cable wiring between the devices can be easily performed. There are advantages. On the other hand, since the length of a cable cannot be made the same, it becomes difficult to trigger each signal analyzer simultaneously.

  For this reason, in the case of daisy chain connection, the length of the cable connecting a plurality of signal analyzers is accurately measured, and the delay time of the trigger signal is set in advance as a trigger delay in each signal analyzer. There is a need.

  The cable length is obtained, for example, by measuring the group delay characteristic of the cable using a network analyzer, but this measurement is complicated. Moreover, since the delay in the path inside the apparatus is not considered only by measuring the cable length, there is a problem that this delay remains as an error.

  The present invention has been made to solve such a conventional problem, and uses an external measuring instrument when performing signal processing in parallel using a plurality of signal processing devices connected in a daisy chain. Signal processing device, signal analysis system, and signal generation capable of measuring the propagation delay time caused by the connection cable and the internal path of the device, and capable of synchronizing the plurality of signal processing devices with high accuracy It is an object to provide a system, a signal analysis method, and a signal generation method.

  In order to solve the above-described problems, a signal processing device according to claim 1 of the present invention is a signal processing device that can be connected in a daisy chain, and includes a trigger signal generating unit that generates an internal trigger signal and a trigger signal input terminal. A trigger signal detector that detects the external trigger signal or the internal trigger signal that is input and outputs the external trigger signal; and a trigger signal output terminal that is one of the trigger signal detector and the trigger signal generator. By selectively connecting to the output side, either the external trigger signal output from the trigger signal detection unit or the internal trigger signal output from the trigger signal generation unit is connected to the trigger signal output terminal. The trigger signal output terminal is connected to the output side of the trigger signal generator by the switching unit. In addition, the internal trigger signal output from the trigger signal generation unit is connected to the trigger signal output terminal and the trigger signal input terminal with a cable connected to the trigger signal output terminal. And a delay correction value calculation unit that calculates a delay correction value as a time until detection by the trigger signal detection unit via the terminal and the cable.

  With this configuration, when performing signal processing in parallel using multiple signal processing devices connected in a daisy chain, the propagation delay time due to the connection cable and the path inside the device is measured without using an external measuring instrument. Therefore, it is possible to realize a signal processing device capable of synchronizing a plurality of signal processing devices with high accuracy.

  Also, in the signal processing device according to claim 2 of the present invention, the delay correction value calculation unit includes a time when the internal trigger signal is output from the trigger signal generation unit, and the internal trigger signal is the trigger signal detection unit. The delay correction value is calculated by taking the difference from the time detected in.

  With this configuration, it is possible to easily measure the propagation delay time caused by the connection cable and the path inside the apparatus without using an external measuring instrument.

  According to a third aspect of the present invention, there is provided a signal analysis system comprising a plurality (N units) of the signal processing devices and a control device for controlling the N signal processing devices, and the switching unit configured to trigger the trigger. A signal output terminal is connected to the output side of the trigger signal detector, and a cable is connected between the trigger signal output terminal of the nth signal processing device and the trigger signal input terminal of the n + 1th signal processing device. A signal analysis system for performing signal analysis on an input RF signal in a state where the connector is connected to the delay correction value calculation unit of the nth signal processing device, wherein the cable is connected to the nth signal processing device. A connector is connected between the trigger signal input terminal and the trigger signal output terminal of the nth signal processing device, and the trigger signal is generated by the switching unit. The delay correction value is calculated with a power terminal connected to the output side of the trigger signal generation unit, and the control device calculates the delay correction value calculated by the delay correction value calculation unit of each signal processing device. And a delay time calculation unit for calculating a delay time to be set in each signal processing device.

  With this configuration, it is possible to measure the propagation delay time due to the connection cable and the path inside the device without using an external measuring instrument, and to synchronize a plurality of signal processing devices with high accuracy. An analysis system can be realized.

  In the signal analysis system according to claim 4 of the present invention, each of the signal processing devices displays a signal analysis unit that performs signal analysis processing on the input RF signal, and a signal analysis result of the signal analysis unit. A display unit, and the display unit displays the signal analysis result on the basis of a time shifted by the delay time from the time when the external trigger signal is detected by the trigger signal detection unit. doing.

  With this configuration, the data of the signal under measurement to be displayed on the plurality of signal processing devices can be regarded as almost the same timing, so that it is possible to perform extremely accurate measurement.

  In the signal analysis system according to claim 5 of the present invention, each signal processing device further includes a signal analysis unit that performs signal analysis processing on the input RF signal, and the signal analysis unit includes the trigger The signal analysis processing is configured to perform the signal analysis processing based on a time that is shifted by the delay time from the time when the external trigger signal is detected by the signal detection unit.

  With this configuration, since the processing on the signal under measurement in the plurality of signal processing devices is performed at substantially the same timing, it is possible to perform extremely accurate measurement.

  In the signal analysis system according to claim 6 of the present invention, the absolute value of the delay time of the (n + 1) th signal processing device calculated by the delay time calculation unit is the first to nth signal processing. It has a configuration equal to the absolute value of the sum of the delay correction values calculated by the delay correction value calculation unit of the apparatus.

  With this configuration, synchronization between a plurality of signal processing devices can be achieved with high accuracy.

  A signal generation system according to a seventh aspect of the present invention includes a plurality (N) of signal processing devices according to the first or second aspect and a control device that controls the N signal processing devices. The trigger signal output terminal is connected to the output side of the trigger signal detection unit by the switching unit, and the trigger signal output terminal of the nth signal processing device and the trigger of the (n + 1) th signal processing device A signal generation system for generating an output RF signal in a state where a connector is connected to a signal input terminal by a cable, wherein the delay correction value calculation unit of the nth signal processing device includes the nth cable And a connector connected between the trigger signal input terminal of the signal processing device and the trigger signal output terminal of the nth signal processing device, The delay correction value is calculated with a trigger signal output terminal connected to the output side of the trigger signal generation unit, and the control device calculates the delay calculated by the delay correction value calculation unit of each signal processing device. Based on the correction value, it has a configuration having a delay time calculation unit for calculating a delay time to be set in each signal processing device.

  With this configuration, it is possible to measure the propagation delay time due to the connection cable and the path inside the device without using an external measuring instrument, and to synchronize a plurality of signal processing devices with high accuracy. A generation system can be realized.

  In the signal generation system according to claim 8 of the present invention, each of the signal processing devices includes baseband signal output means for outputting a baseband signal, and a local portion for generating a local oscillation signal having a predetermined local oscillation frequency. An oscillation signal generating means; a radio frequency signal generating means for generating a radio frequency signal by performing quadrature modulation and frequency conversion by multiplying the baseband signal and the local oscillation signal; and a signal level of the radio frequency signal. A signal level setting means for setting and outputting a predetermined signal level; and a step attenuator for attenuating and outputting the radio frequency signal set to the predetermined signal level with a predetermined attenuation value. , Based on the time deviated by the delay time from the time when the external trigger signal is detected by the trigger signal detector. It has a configuration which outputs the baseband signal Te.

  With this configuration, output RF signals can be output from a plurality of signal processing devices at substantially the same timing.

  In the signal generation system according to claim 9 of the present invention, the absolute value of the delay time of the (n + 1) th signal processing device calculated by the delay time calculation unit is from the first to the (N-1) th. The delay correction calculated by the delay correction value calculators of the first to nth signal processing devices from the absolute value of the sum of the delay correction values calculated by the delay correction value calculator of the signal processing device. It has a structure equal to the value obtained by subtracting the absolute value of the sum of the values.

  With this configuration, synchronization between a plurality of signal processing devices can be achieved with high accuracy.

  A signal analysis method according to claim 10 of the present invention is a signal analysis method for performing signal analysis on an input RF signal using the signal analysis system described above, wherein a cable is connected to the trigger of the nth signal processing device. A cable connection stage for connecting a connector between a signal input terminal and the trigger signal output terminal of the n-th signal processing device; and the switching unit connects the trigger signal output terminal to the output side of the trigger signal generation unit. In the state where the trigger signal output terminal is connected to the output side of the trigger signal generation unit by the switching step, the internal trigger signal is switched by the trigger signal generation unit to the switching unit, the trigger signal output terminal, And an internal trigger signal output stage that outputs to the trigger signal detector via the cable, and an internal trigger signal output stage. An internal trigger signal detecting step of detecting the input internal trigger signal by the trigger signal detecting unit; a time when the internal trigger signal is detected by the internal trigger signal detecting step; and an internal trigger signal outputting step A delay correction value calculation stage that calculates a delay correction value based on a difference from the time when the trigger signal is output, and each signal processing device based on the delay correction value calculated by the delay correction value calculation stage. A delay time calculating step for calculating a delay time to be set.

  A signal generation method according to an eleventh aspect of the present invention is a signal generation method for generating an output RF signal using the above-described signal generation system, wherein a cable is connected to the trigger signal output of the nth signal processing device. A cable connecting step of connecting a connector between the terminal and the trigger signal input terminal of the nth signal processing device, and a switching step of connecting the trigger signal output terminal to the output side of the trigger signal generating unit by the switching unit And in the state where the trigger signal output terminal is connected to the output side of the trigger signal generating unit by the switching step, the internal trigger signal is switched by the trigger signal generating unit, the trigger signal output terminal, and the An internal trigger signal output stage that outputs to the trigger signal detection unit via a cable, and the output before the internal trigger signal output stage. An internal trigger signal detection stage for detecting an internal trigger signal by the trigger signal detection unit, a time when the internal trigger signal is detected by the internal trigger signal detection stage, and the internal trigger signal output by the internal trigger signal output stage A delay correction value calculating step for calculating a delay correction value based on a difference from the time that has been set, and a delay to be set for each signal processing device based on the delay correction value calculated by the delay correction value calculating step A delay time calculating step of calculating time.

  The present invention measures the propagation delay time caused by the connection cable and the path inside the device without using an external measuring device when performing signal processing in parallel using a plurality of signal processing devices connected in a daisy chain. It is possible to provide a signal processing device, a signal analysis system, a signal generation system, a signal analysis method, and a signal generation method that can be synchronized between a plurality of signal processing devices with high accuracy.

It is a block diagram which shows the structure of the signal analysis system as the 1st Embodiment of this invention. It is a block diagram which shows an example of a detailed structure of the signal analysis apparatus with which the signal analysis system as the 1st Embodiment of this invention is provided. It is a timing chart which shows the waveform of the trigger signal in each point of the signal analysis system as the 1st embodiment of the present invention. It is a block diagram for demonstrating the signal analysis method using the signal analysis system as the 1st Embodiment of this invention. It is a block diagram which shows the structure of the signal generation system as the 2nd Embodiment of this invention. It is a block diagram which shows the detailed structure of the signal generator with which the signal generation system as the 2nd Embodiment of this invention is provided.

  Hereinafter, embodiments of a signal processing device, a signal analysis system, a signal generation system, a signal analysis method, and a signal generation method according to the present invention will be described with reference to the drawings.

(First embodiment)
First, the configuration of the signal analysis system 1 as the first embodiment of the present invention will be described.

  As shown in FIG. 1, the signal analysis system 1 according to the present embodiment includes a plurality of units (N units) that can be daisy chained by a plurality of cables c0, c1, c2, c3,. , SAN, and a control device 100 for controlling the N signal analyzers SA1, SA2,..., SAN.

  The cable c0 is for inputting an external trigger signal output from an external trigger signal generator to the trigger signal input terminal 10. The cable cn (n is a natural number) is a trigger signal of the nth signal analyzer SAn when signal analysis is performed on the input RF signal by each signal analyzer SA1,..., SAN (in the RF signal measurement mode). This is for connector connection between the output terminal 11 and the trigger signal input terminal 10 of the (n + 1) th signal analyzer SA (n + 1).

  The cable cn (n is a natural number) is also used for connector connection between the trigger signal output terminal 11 of the nth signal analyzer SAn and the trigger signal input terminal 10 of the nth signal analyzer SAn. .

  Further, the control device 100 and each signal analysis device SA1,..., SAN are connected via a control terminal 12 included in each signal analysis device SA1,.

  FIG. 2 shows an example of a detailed configuration of the signal analyzer SA1. The configurations of the other signal analyzers SA2,..., SAN are the same as the configuration of the signal analyzer SA1. The signal analysis apparatus SA1 includes an RF unit 13, an A / D conversion unit 14, a signal analysis unit 15, a display unit 16, an operation unit 17, a control unit 18, and a trigger control unit 19 in a housing 20.

  The housing 20 includes a trigger signal input terminal 10, a trigger signal output terminal 11, a control terminal 12, a reference frequency signal input terminal 21, and an RF signal input terminal 22.

  The RF unit 13 includes a sweep unit 13a, a local signal generation unit 13b, and a mixer unit 13c.

The local signal generation unit 13b receives an instruction of the center frequency fc of the measurement frequency from the control unit 18 through the sweep unit 13a, oscillates a local signal of the local frequency (fc + f _IF ), and sends it to the mixer unit 13c. ing.

The local signal generator 13b uses the reference frequency signal of the oscillation frequency (fc + f _IF ) output from the local signal generator 13b of another signal analyzer SA2,..., SAN or an external signal generator as a reference frequency. The signal is received via the signal input terminal 21, and the received reference frequency signal can be sent to the mixer unit 13c instead of the local signal of the local frequency (fc + f _IF ) generated by itself. With this configuration, the signal analysis device SA1 can perform frequency synchronization with the other signal analysis devices SA2,..., SAN.

The mixer unit 13c mixes the input RF signal input from the RF signal input terminal 22 and the local signal (or reference frequency signal) of the local frequency (fc + f _IF ) to obtain an intermediate frequency (f _IF ± ΔF _Max / 2). The signal is converted into a signal and the intermediate frequency signal is sent to the A / D converter 14.

The A / D conversion unit 14 converts the intermediate frequency signal (frequency: f _IF ± ΔF _Max / 2) output from the RF unit 13 into digital data with a predetermined clock from the control unit 18.

  The trigger control unit 19 includes a trigger signal generation unit 19a, a trigger signal detection unit 19b, a switching unit 19c, and a delay correction value calculation unit 19d. Here, the trigger control part 19 is comprised by logic circuits, such as FPGA (Field Programmable Gate Array) and ASIC (Application Specific Integrated Circuit), for example.

The trigger signal generator 19a generates an internal trigger signal. The trigger signal generating unit 19a is configured to output the information of the time T ₀ which generates an internal trigger signal to the delay correction value calculating unit 19d.

The trigger signal detector 19b detects the trigger signal input via the trigger signal input terminal 10 and outputs the trigger signal. The trigger signal detecting unit 19b is configured to output the information of the time T ₁ that has detected the trigger signal to the delay correction value calculating unit 19d.

  Here, the trigger signal indicates either an external trigger signal output from an external device such as another signal analyzer or an internal trigger signal output from the trigger signal generator 19a.

  In the “RF signal measurement mode”, the switching unit 19c selectively connects the trigger signal output terminal 11 to the output side of the trigger signal detection unit 19b, and outputs the trigger signal output from the trigger signal detection unit 19b to the trigger signal output terminal. 11 to output to the outside.

  In the RF signal measurement mode, the connector between the trigger signal output terminal 11 of the nth signal analyzer SAn and the trigger signal input terminal 10 of the (n + 1) th signal analyzer SA (n + 1) is connected by a cable cn (see FIG. 1). Connected.

  In the “delay correction value calculation mode”, the switching unit 19c selectively connects the trigger signal output terminal 11 to the output side of the trigger signal generation unit 19a, and connects the internal trigger signal output from the trigger signal generation unit 19a. The signal is output to the outside via the trigger signal output terminal 11.

  In the delay correction value calculation mode, the trigger signal output terminal 11 of the nth signal analyzer SAn and the trigger signal input terminal 10 of the nth signal analyzer SAn are connected by a cable cn. Yes.

In the delay correction value calculation mode, the delay correction value calculation unit 19d has a time T ₀ when the internal trigger signal is output from the trigger signal generation unit 19a and a time T ₁ when the internal trigger signal is detected by the trigger signal detection unit 19b. The delay correction value as a difference (T ₁ −T ₀ ) is calculated.

  That is, the delay correction value is the time until the trigger signal detection unit 19b detects the internal trigger signal output from the trigger signal generation unit 19a via the switching unit 19c, the trigger signal output terminal 11, and the cable cn. is there.

  Based on the delay correction value calculated by the delay correction value calculation unit 19d of each signal analysis device SA1,..., SA (N−1), the control device 100 detects each signal analysis device SA1,. A delay time calculation unit 110 that calculates a delay time to be set to

  Here, the absolute value of the delay time of the (n + 1) th signal analyzer SA (n + 1) calculated by the delay time calculator 110 is the delay correction of the first to nth signal analyzers SA1,. This is equal to the absolute value of the sum of the delay correction values calculated by the value calculation unit 19d.

  The control device 100 is constituted by a personal computer, for example, and performs various controls on the signal analysis devices SA1,..., SAN. The control device 100 may be connected to an operation unit (not shown) through which an operator inputs various instructions and a display unit (not shown) that displays a signal analysis result.

  The control unit 18 is constituted by a microcomputer, for example, and controls the entire apparatus. In particular, the control unit 18 displays the display timing of the signal analysis result on the display unit 16 or the signal analysis based on the external trigger signal output from the trigger control unit 19 and the delay time information output from the control device 100. The start timing of the signal analysis process for the input RF signal in the unit 15 is controlled.

  The signal analysis unit 15 includes, for example, an original data storage unit 15a, an FFT processing unit 15b, a detection unit 15c, a log conversion unit 15d, and a storage unit 15e, and performs signal analysis processing on the input RF signal in the RF signal measurement mode. Is to do.

  In the configuration illustrated in FIG. 2, the signal analysis unit 15 performs the FFT process. However, this is merely an example, and the processing method of the signal analysis unit 15 is not limited to the FFT process. For example, the signal analysis unit 15 may perform modulation analysis, or may perform processing such as Power vs Time, Frequency vs Time, Phase vs Time, and the like. That is, these analysis processing methods can also be applied to the present invention. Note that these analysis processing methods are methods that can be understood by those skilled in the art of signal analyzers, and therefore their details are omitted.

  The original data storage unit 15a stores the digital data (amplitude value) output from the A / D conversion unit 14 in the memory area with the measurement frequency and the elapsed time of the clock as an address by using a write signal at almost the same timing as the clock. It is supposed to be. The stored digital data is so-called time domain data.

  The FFT processing unit 15b receives the observation frequency fv and the observation time tv received from the operation unit 17 and reads the corresponding measurement frequency and time domain data (digital data) of the clock elapsed time from the original data storage unit 15a. It is like that.

  Then, the FFT processing unit 15b performs FFT processing on the received time domain data at a predetermined time interval to convert it into frequency domain data, and a desired resolution bandwidth (F in the range of the observation bandwidth ΔF specified from the operation unit 17). Each frequency component and its size are calculated by (RBW).

  At this time, if the time interval of the timing of the FFT processing is Δt, the FFT processing unit 15b generates time domain data corresponding to the time window ΔT (ΔT ≧ Δt) at each processing timing from the time domain data of the observation frequency. The data is read from the storage unit 15a and subjected to FFT processing.

  The FFT processing unit 15b repeats the FFT processing until the observation time tv is reached while shifting the processing timing by one time interval Δt for each time window T. That is, the FFT processing unit 15b reads out time domain data between ± ΔT / 2 centered on the time position (address) m × Δt at a timing of m × Δt (for example, m is 1 to tv / Δt). The FFT calculation is repeated until m = tv / Δt.

  The time window ΔT is a time sufficient to convert time domain data into frequency domain data. In an extreme example, even if time domain data that is less than one cycle is converted into frequency domain data, the frequency may not be specified with high resolution. Note that the timing time interval Δt may be the same cycle as the clock of the A / D converter 14.

  The detection unit 15c converts the magnitude (power) of each frequency component into an effective value, an average value, or a peak value and outputs it (hereinafter referred to as “power”). The log conversion unit 15d compresses the output from the detection unit 15c logarithmically and sends it to the storage unit 15e.

  For example, the storage unit 15e stores the power of the corresponding frequency component in a memory area in which one address is the observation frequency fv and the other address is the lapse of the observation time tv.

  The control unit 18 can control the start timing of the signal analysis processing for the input RF signal in the signal analysis unit 15. Specifically, under the control of the control unit 18, for example, when the FFT processing unit 15b reads the time domain data corresponding to the observation time tv from the original data storage unit 15a, the trigger signal detection unit 19b detects the external trigger signal. It is preferable that the time domain data of the elapsed time of the clock corresponding to the time shifted by the delay time calculated by the delay time calculation unit 110 from the calculated time is read.

  The display unit 16 displays the power of each component of the observation frequency stored in the storage unit 15e, for example, as a color parameter at coordinates with the observation frequency as the vertical axis and the observation time as the horizontal axis.

  The control unit 18 can control the display start timing of the signal analysis result for the input RF signal in the display unit 16. Under the control of the control unit 18, for example, the signal related to the input RF signal based on the time shifted by the delay time calculated by the delay time calculation unit 110 from the time when the external trigger signal is detected by the trigger signal detection unit 19 b The analysis result should be displayed.

<RF signal measurement mode>
As shown in FIGS. 1 and 3, the time required for the trigger signal to propagate from the trigger signal input terminal 10 (point B) of the signal analyzer SA1 to the trigger signal input terminal 10 (point D) of the signal analyzer SA2 (Hereinafter, this will be referred to as “propagation time”.) T _d12 is given by _Equation 1.

Similarly, the propagation time t _d23 required for the trigger signal to propagate from the trigger signal input terminal 10 (point D) of the signal analyzer SA2 to the trigger signal input terminal 10 (point F) of the signal analyzer SA3 is expressed by the following equation (2). Given in.

Here, t _c1 , t _c2 ,..., T _{c (N−1)} are times required for the trigger signal to propagate through the cables c 1, c 2,. t ₁₁ , t ₂₁ ,..., t _N1 from when the trigger signal is input to the trigger signal input terminal 10 of the signal analyzers SA1, SA2,. , And is designed to have almost the same value in all the signal analyzers SA1, SA2,..., SAN.

In addition, t ₁₂ , t ₂₂ ,..., T _N2 are output from the switching unit 19c after the external trigger signal is detected by the trigger signal detection unit 19b of the signal analyzers SA1, SA2,. This is the time it takes to complete. t ₁₃ , t ₂₃ ,..., t _N3 are times required from when the trigger signal is output from the switching unit 19 c to when the trigger signal is output from the trigger signal output terminal 11.

<Delay correction value calculation mode>
Hereinafter, a signal analysis method in the signal analysis system 1 of the present embodiment will be described.
First, as shown in FIG. 4A, the operator disconnects the cable c0 from the trigger signal input terminal 10 of the signal analyzer SA1 in the state of FIG. 1 (RF signal measurement mode).

  Further, as shown in FIG. 4 (b), the operator places the trigger signal output terminal 11 of the signal analyzer SA1 and the trigger signal input terminal 10 of the signal analyzer SA2 in the state of FIG. 1 (RF signal measurement mode). Is connected to the trigger signal input terminal 10 and the trigger signal output terminal 11 of the signal analyzer SA1 so that the connector c is connected. Switched (cable connection stage).

  Next, the switching unit 19c selectively connects the trigger signal output terminal 11 to the output side of the trigger signal generating unit 19a (switching stage).

  Next, with the trigger signal output terminal 11 selectively connected to the output side of the trigger signal generation unit 19a, the trigger signal generation unit 19a passes through the switching unit 19c, the trigger signal output terminal 11, and the cable c1. The internal trigger signal is output toward the trigger signal detector 19b (internal trigger signal output stage). That is, a pulse signal of an internal trigger signal is output from the trigger control unit 19 of the signal analyzer SA1 instead of an external trigger signal.

  Next, the trigger signal detector 19b detects the internal trigger signal output from the trigger signal generator 19a (internal trigger signal detection stage).

Time Then, the delay correction value calculating unit 19d is where the time T ₀ of the internal trigger signal is outputted from the trigger signal generating unit 19a, the internal trigger signal is detected in the trigger signal detection unit 19b via the cable c1 calculating the difference _(T 1 -T ₀₎ delay correction value _{t d12} as' the T ₁ (delay correction value calculating step).

As will be described below, in the delay correction value calculation stage, the propagation time t _d12 ′ from point C ′ to point B ′ shown in FIG. 4B is calculated as the delay correction value. t _d12 ′ is given by _Equation 3.

Here, t _d12 of _Equation 1 can be expressed as _Equation 4 using t _d12 ′ of _Equation 3.

Here, (t ₁₂ -t _12p ) in _Equation 4 indicates the case where the external trigger signal from the trigger signal detector 19b is output from the trigger signal output terminal 11 and the trigger signal generator 19a with respect to the signal analyzer SA1. Is the time difference due to the path difference when the internal trigger signal from is output from the trigger signal output terminal 11. Since this path difference is due to a difference in internal logic, the time difference (t ₁₂ −t _12p ) can be designed to be sufficiently small.

For example, assuming that there is a difference of 1 mm as the above path difference and the wavelength shortening rate is 50%, (t ₁₂ −t _12p ) is a very small value of 6.67 ps and can be ignored. .

From the above, by _obtaining the delay correction value t _d12 ′, the trigger signal propagates from the trigger signal input terminal 10 (point B) of the signal analyzer SA1 to the trigger signal input terminal 10 (point D) of the signal analyzer SA2. An approximate value of the propagation time _td12 required for the above is obtained. Similarly, by _obtaining the delay correction values t _d23 ′, t _d34 ′,..., T _{d (N−1) N} ′, propagation regarding the signal analyzers SA2,. Approximate values of times _td23 , _td34 , ..., td _{(N-1) N} are obtained. Table 1 summarizes the correspondence between paths and delay correction values.

  Next, based on the delay correction value calculated by the delay correction value calculation unit 19d of the signal analyzers SA1, SA2,. ... Calculate the delay time to be set in the SAN (delay time calculation stage).

  Here, for example, the delay time of the (n + 1) th signal analyzer SA (n + 1) is the delay correction calculated by the delay correction value calculator 19d of the first to nth signal analyzers SA1,. Calculated as the sum of the values multiplied by (-1).

  As shown in FIG. 1, in order to reflect the delay correction value obtained in the delay correction value calculation stage in the entire signal analysis system 1, the control device 100 applies to the obtained signal analysis devices SA 1,. Information on the delay time is output to the control unit 18 of each signal analyzer SA1,..., SAN.

When the delay correction value is given as shown in Table 1, the delay time to be set for each signal analyzer SA1,..., SAN is given as shown in Table 2.

  Note that the calculation and setting of the delay time in the delay correction value calculation mode may be performed before shipment of the signal analyzer or the signal analysis system, or may be performed every time before processing in the RF signal measurement mode. Alternatively, it may be performed at an arbitrary timing by the operator.

  As described above, according to the present embodiment, when signal processing is performed in parallel using a plurality of signal processing devices connected in a daisy chain, an external measuring instrument is not used, and a connection cable and an internal device are used. The propagation delay time caused by the path can be measured, and synchronization between a plurality of signal processing devices can be achieved with high accuracy. For example, this is particularly effective when a plurality of input RF signals having different frequencies are measured in parallel using a plurality of signal processing devices.

  Furthermore, according to the present embodiment, the delay time caused by the connection cable and the path inside the apparatus can be corrected without using an external measuring instrument, so there is no need to prepare an external measuring instrument separately. Simplification is possible.

(Second Embodiment)
Next, a signal generation system 2 as a second embodiment of the present invention will be described with reference to the drawings. In addition, about the structure similar to 1st Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted suitably. Also, description of operations similar to those in the first embodiment will be omitted as appropriate.

  As shown in FIG. 5, the signal generation system 2 of the present embodiment includes N signal processing devices that can be daisy chained by a plurality of cables c0, c1, c2, c3,..., C (N−1). , SGN and a control device 200 for controlling the N signal generators SG1, SG2,..., SGN.

  As in the first embodiment, the cable c0 is for inputting an external trigger signal output from an external trigger signal generator to the trigger signal input terminal 10. The cable cn (n is a natural number) is connected between the trigger signal output terminal 11 of the nth signal generator SGn and the trigger signal input terminal 10 of the (n + 1) th signal generator SG (n + 1) in the RF signal output mode described later. Is for connecting the connector.

  The cable cn (n is a natural number) is a connector between the trigger signal output terminal 11 of the nth signal generator SGn and the trigger signal input terminal 10 of the nth signal generator SGn in the delay correction value calculation mode. It is also for connecting.

  Based on the delay correction value calculated by the delay correction value calculation unit 19d of each signal generator SG1,..., SG (N-1), the control device 200 controls each signal generator SG1,. A delay time calculation unit 210 that calculates a delay time to be set to

  Here, the absolute value of the delay time of the (n + 1) th signal generator SG (n + 1) calculated by the delay time calculator 210 is the first to N−1th signal generators SG1,. N-1) from the absolute value of the sum of the delay correction values calculated by the delay correction value calculation unit 19d, the delay correction value calculation unit 19d of the first to nth signal generators SG1,. This is equal to the value obtained by subtracting the absolute value of the sum of the calculated delay correction values.

  As shown in FIG. 6, the signal generator SG1 includes a waveform data storage unit 31, DACs 32 and 33, an orthogonal modulation unit 34, a local signal generation unit 35, an automatic level control circuit (ALC) 36, an operation unit 37, and a control unit 38. A step attenuator (step ATT) 39 is provided. The other signal generators SG2,..., SGN have the same configuration as the signal generator SG1.

  The housing 20 includes a trigger signal input terminal 10, a trigger signal output terminal 11, a control terminal 12, a reference frequency signal input terminal 21, and an RF signal output terminal 40.

  The waveform data storage unit 31 stores digital value baseband waveform data as a plurality of test signal data for testing the device under test. The operator can operate the operation unit 37 and select and output the test signal data stored in the waveform data storage unit 31 via the control unit 38.

  The test signal data includes baseband waveform data of an I-phase component (in-phase component) and a Q-phase component (orthogonal component). The waveform data is generated by, for example, a DSP (Digital Signal Processor) not shown. The waveform data storage unit 31 constitutes a baseband signal output unit.

  Each of the DACs 32 and 33 converts the digital baseband signal waveform data of the I-phase component and Q-phase component output from the waveform data storage unit 31 into an analog value and outputs the analog value to the quadrature modulation unit 34. .

  The local signal generation unit 35 is configured to generate a local oscillation signal having a local oscillation frequency based on a control signal from the control unit 38 and output the local oscillation signal to the quadrature modulation unit 34. The local signal generator 35 constitutes a local oscillation signal generator.

Note that the local signal generator 35 uses the reference frequency signal of the oscillation frequency (fc + f _IF ) output from the other signal generators SG2,..., SGN or an external local signal generator as the reference frequency. The reference frequency signal received via the signal input terminal 21 can be output to the quadrature modulation unit 34 instead of the local signal of the local frequency (fc + f _IF ) generated by itself. With such a configuration, the signal generator SG1 can perform frequency synchronization with the other signal generators SG2, ..., SGN.

  The quadrature modulation unit 34 multiplies the I-phase component from the DAC 32 and the Q-phase component from the DAC 33 by the local oscillation signal input from the local signal generation unit 35 to perform quadrature modulation and frequency conversion, thereby performing a radio frequency signal. (RF signal) is generated and output to the ALC 36. The quadrature modulation unit 34 constitutes a radio frequency signal generation unit.

  The ALC 36 adjusts the power level of the output signal of the quadrature modulation unit 34 to a predetermined power level and outputs it to the step ATT 39. The power level set by the ALC 36 is set by a control signal from the control unit 38. The ALC 36 can adjust the output signal level in units of 0.1 dB, for example. The ALC 36 constitutes signal level setting means.

  The operation unit 37 is operated by an operator to perform settings relating to test conditions and test procedures, and includes, for example, an input device such as a keyboard, a dial, or a mouse, and a control circuit that controls these devices. . Test conditions set by the operator include, for example, waveform data stored in the waveform data storage unit 31, the output level of the output RF signal output by the step ATT 39 via the RF signal output terminal 40, and the radio frequency.

  The control unit 38 is configured by a microcomputer, for example, and controls the entire apparatus. Further, the control unit 38 sends control signals for setting each test condition to the waveform data storage unit 31, the local signal generation unit 35, the ALC 36, and the step ATT39 based on each test condition set by the operator operating the operation unit 37. Each test condition is set.

  In particular, the control unit 38 controls the output timing of the test signal data from the waveform data storage unit 31 based on the external trigger signal output from the trigger control unit 19 and the delay time information output from the control device 200. It is supposed to be.

  For example, the control unit 38 obtains the test signal data from the waveform data storage unit 31 at a time deviated by the delay time calculated by the delay time calculation unit 210 from the time when the external trigger signal is detected by the trigger signal detection unit 19b. It is good to output.

  Specifically, with the delay time of the Nth signal generator SGN receiving the latest external trigger signal being the latest as zero, the waveform data storage unit of the other signal generators SG1,..., SG (N-1) The output timing of the test signal data from 31 may be delayed by the respective delay times.

  As the setting for the ALC 36, for example, when the operator sets the output level of the signal generator SG1 to −40.2 dBm, the control unit 38 sets the attenuation of the step ATT 39 to 30 dB, A control signal for setting the output signal level to -10.2 dBm is output.

  The step ATT 39 includes a plurality of attenuator sections each having a predetermined attenuation amount, and an ATT capable of attenuating the level of the input RF signal in a predetermined attenuation step by a combination of attenuation amounts of the respective attenuator sections. It is. This step ATT39 attenuates the input signal by the attenuation amount set by the control signal from the control unit 38, and outputs an output RF signal of the power level desired by the operator.

Hereinafter, a signal generation method in the signal generation system 2 of the present embodiment will be described.
First, as shown in FIG. 4A, the operator disconnects the cable c0 from the trigger signal input terminal 10 of the signal generator SG1 in the state of FIG. 5 (RF signal output mode).

  Further, as shown in FIG. 4 (b), the operator sets the trigger signal output terminal 11 of the signal generator SG1 and the trigger signal input terminal 10 of the signal generator SG2 in the state of FIG. 5 (RF signal output mode). The cable c1 having a connector connection therebetween is removed from the trigger signal input terminal 10 of the signal generator SG2, and the trigger signal input terminal 10 and the trigger signal output terminal 11 of the signal generator SG1 are connected by a connector. Can be reconnected (cable connection stage).

  Next, the switching unit 19c selectively connects the trigger signal output terminal 11 to the output side of the trigger signal generating unit 19a (switching stage).

  Next, with the trigger signal output terminal 11 selectively connected to the output side of the trigger signal generation unit 19a, the trigger signal generation unit 19a passes through the switching unit 19c, the trigger signal output terminal 11, and the cable c1. The internal trigger signal is output toward the trigger signal detector 19b (internal trigger signal output stage).

  Next, the trigger signal detector 19b detects the internal trigger signal output from the trigger signal generator 19a (internal trigger signal detection stage).

Time Then, the delay correction value calculating unit 19d is where the time T ₀ of the internal trigger signal is outputted from the trigger signal generating unit 19a, the internal trigger signal is detected in the trigger signal detection unit 19b via the cable c1 calculating the difference _(T 1 -T ₀₎ delay correction value _{t d12} as' the T ₁ (delay correction value calculating step).

  Next, the control device 200 determines the signal generators SG1, SG2,..., SG (N-1) based on the delay correction values calculated by the delay correction value calculation unit 19d. ... Calculate the delay time to be set in SGN (delay time calculation stage).

  Here, for example, the delay time of the (n + 1) th signal generator SG (n + 1) is the delay correction value calculator of the first to N−1th signal generators SG1,..., SG (N−1). Assuming that the sum of the delay correction values calculated by the delay correction value calculation unit 19d of the first to nth signal generators SG1,..., SGn is subtracted from the sum of the delay correction values calculated in 19d. Calculated.

  As shown in FIG. 5, in order to reflect the delay correction value obtained in the delay correction value calculation stage in the signal generation system 2, the control device 200 determines the delay for each of the obtained signal generation devices SG 1,. The time information is output to the control unit 38 of each signal generator SG1,.

The delay time to be set in each signal generator SG1,..., SGN is given as shown in Table 3 below, for example.

  Note that the calculation and setting of the delay time in the delay correction value calculation mode may be performed before shipment of the signal generator or the signal generation system, or may be performed every time before processing in the RF signal output mode. Alternatively, it may be performed at an arbitrary timing by the operator.

  As described above, according to the present embodiment, output RF signals can be output from a plurality of signal processing devices at substantially the same timing. For example, this is particularly effective when a plurality of output RF signals are transmitted simultaneously using the MIMO method.

  A signal processing apparatus, a signal analysis system, a signal generation system, a signal analysis method, and a signal generation method according to the present invention include, for example, a communication system that simultaneously transmits and receives a plurality of different signals using techniques such as carrier aggregation, MIMO, and an adaptive antenna. Can be applied to.

DESCRIPTION OF SYMBOLS 1 Signal analysis system 2 Signal generation system SA1, SA2, ..., SAN Signal analysis device SG1, SG2, ..., SGN Signal generation device c1, c2, ..., cN Cable 10 Trigger signal input terminal 11 Trigger signal Output terminal 13 RF unit 13a sweep unit 13b local signal generation unit 13c mixer unit 14 A / D conversion unit 15 signal analysis unit 15a original data storage unit 15b FFT processing unit 15c detection unit 15d log conversion unit 15e storage unit 16 display unit 18, 38 control unit 19 trigger control unit 19a trigger signal generation unit 19b trigger signal detection unit 19c switching unit 19d delay correction value calculation unit 31 waveform data storage unit (baseband signal output means)
34 Quadrature modulation unit (radio frequency signal generating means)
35 Local signal generator (local oscillation signal generator)
36 ALC (Signal level setting means)
39 Step attenuator (Step ATT)
100, 200 Control device 110, 210 Delay time calculation unit

Claims (11)

A daisy chain connectable signal processing device (SA1,..., SAN, SG1,..., SGN),
A trigger signal generator (19a) for generating an internal trigger signal;
A trigger signal detector (19b) for detecting the external trigger signal or the internal trigger signal input via the trigger signal input terminal (10) and outputting the external trigger signal;
By selectively connecting a trigger signal output terminal (11) to either output side of the trigger signal detector and the trigger signal generator, the external trigger signal output from the trigger signal detector, and A switching unit (19c) for selectively outputting any of the internal trigger signals output from the trigger signal generation unit to the outside via the trigger signal output terminal;
The switching unit connects the trigger signal output terminal to the output side of the trigger signal generation unit, and cables (c1,..., C (N) are connected between the trigger signal output terminal and the trigger signal input terminal. -1)), the internal trigger signal output from the trigger signal generation unit is detected by the trigger signal detection unit via the switching unit, the trigger signal output terminal, and the cable. A signal processing apparatus comprising: a delay correction value calculation unit (19d) that calculates a delay correction value as a time until the operation is performed.   The delay correction value calculation unit takes the difference between the time when the internal trigger signal is output from the trigger signal generation unit and the time when the internal trigger signal is detected by the trigger signal detection unit. The signal processing apparatus according to claim 1, wherein a correction value is calculated. A plurality (N units) of the signal processing device according to claim 1 or 2 and a control device (100) for controlling the N signal processing devices, wherein the trigger signal output terminal is provided by the switching unit. Is connected to the output side of the trigger signal detector, and a cable (c1, c1) is connected between the trigger signal output terminal of the nth signal processing device and the trigger signal input terminal of the (n + 1) th signal processing device. ..., a signal analysis system (1) for performing signal analysis on an input RF signal in a state where the connector is connected by c (N-1)),
The delay correction value calculation unit of the n-th signal processing device includes:
The cable is connected to a connector between the trigger signal input terminal of the nth signal processing device and the trigger signal output terminal of the nth signal processing device, and the trigger signal output terminal is connected by the switching unit. Calculate the delay correction value in a state connected to the output side of the trigger signal generator,
The control device calculates a delay time to be set for each signal processing device based on the delay correction value calculated by the delay correction value calculation unit of each signal processing device (110). A signal analysis system comprising: Each of the signal processing devices further includes a signal analysis unit (15) that performs signal analysis processing on the input RF signal, and a display unit (16) that displays a signal analysis result of the signal analysis unit,
The said display part displays the said signal analysis result on the basis of the time shifted | deviated by the said delay time from the time when the said external trigger signal was detected by the said trigger signal detection part. Signal analysis system. Each of the signal processing devices further includes a signal analysis unit (15) that performs signal analysis processing on the input RF signal,
4. The signal according to claim 3, wherein the signal analysis unit performs the signal analysis processing based on a time that is shifted by the delay time from a time when the external trigger signal is detected by the trigger signal detection unit. Analysis system.   The absolute value of the delay time of the (n + 1) th signal processing device calculated by the delay time calculation unit is the delay correction calculated by the delay correction value calculation unit of the first to nth signal processing devices. The signal analysis system according to claim 3, wherein the signal analysis system is equal to an absolute value of a sum of values. A plurality of (N) signal processing devices according to claim 1 or claim 2 and a control device (200) for controlling the N signal processing devices, wherein the trigger signal output terminal is provided by the switching unit. Is connected to the output side of the trigger signal detector, and a cable (c1, c1) is connected between the trigger signal output terminal of the nth signal processing device and the trigger signal input terminal of the (n + 1) th signal processing device. ..., a signal generation system (2) for generating an output RF signal in a state where the connector is connected by c (N-1)),
The delay correction value calculation unit of the n-th signal processing device includes:
The cable is connected to a connector between the trigger signal input terminal of the nth signal processing device and the trigger signal output terminal of the nth signal processing device, and the trigger signal output terminal is connected by the switching unit. Calculate the delay correction value in a state connected to the output side of the trigger signal generator,
The control device calculates a delay time to be set for each signal processing device based on the delay correction value calculated by the delay correction value calculation unit of each signal processing device (110). A signal generation system comprising: Each of the signal processing devices
Baseband signal output means (31) for outputting a baseband signal;
A local oscillation signal generating means (35) for generating a local oscillation signal having a predetermined local oscillation frequency;
Radio frequency signal generating means (34) for generating a radio frequency signal by multiplying the baseband signal and the local oscillation signal to perform quadrature modulation and frequency conversion;
Signal level setting means (36) for setting the signal level of the radio frequency signal to a predetermined signal level and outputting the signal level;
A step attenuator (39) for attenuating and outputting the radio frequency signal set to the predetermined signal level with a predetermined attenuation value;
The baseband signal output means outputs the baseband signal on the basis of a time shifted by the delay time from a time when the external trigger signal is detected by the trigger signal detection unit. The signal generation system described.   The absolute value of the delay time of the (n + 1) th signal processing device calculated by the delay time calculation unit is calculated by the delay correction value calculation unit of the first to N−1th signal processing devices. The absolute value of the sum of the delay correction values is equal to a value obtained by subtracting the absolute value of the sum of the delay correction values calculated by the delay correction value calculation unit of the first to nth signal processing devices. The signal generation system according to claim 7 or 8. A signal analysis method for performing signal analysis on an input RF signal using the signal analysis system according to claim 3,
A cable connection stage for connecting a cable (cn) between the trigger signal input terminal of the nth signal processing device and the trigger signal output terminal of the nth signal processing device;
A switching step of connecting the trigger signal output terminal to the output side of the trigger signal generating unit by the switching unit;
In the state where the trigger signal output terminal is connected to the output side of the trigger signal generating unit by the switching step, the trigger signal generating unit converts the internal trigger signal to the switching unit, the trigger signal output terminal, and the cable. An internal trigger signal output stage that outputs to the trigger signal detection unit via,
An internal trigger signal detection step of detecting the internal trigger signal output in the internal trigger signal output step by the trigger signal detector;
Delay correction value calculation that calculates a delay correction value based on the difference between the time when the internal trigger signal is detected by the internal trigger signal detection stage and the time when the internal trigger signal is output by the internal trigger signal output stage Stages,
A signal analysis method comprising: a delay time calculation step of calculating a delay time to be set in each signal processing device based on the delay correction value calculated in the delay correction value calculation step. A signal generation method for generating an output RF signal using the signal generation system according to claim 7, comprising:
A cable connection stage for connecting a cable (cn) between the trigger signal output terminal of the nth signal processing device and the trigger signal input terminal of the nth signal processing device;
A switching step of connecting the trigger signal output terminal to the output side of the trigger signal generating unit by the switching unit;
In the state where the trigger signal output terminal is connected to the output side of the trigger signal generating unit by the switching step, the trigger signal generating unit converts the internal trigger signal to the switching unit, the trigger signal output terminal, and the cable. An internal trigger signal output stage that outputs to the trigger signal detection unit via,
An internal trigger signal detection step of detecting the internal trigger signal output in the internal trigger signal output step by the trigger signal detector;
Delay correction value calculation that calculates a delay correction value based on the difference between the time when the internal trigger signal is detected by the internal trigger signal detection stage and the time when the internal trigger signal is output by the internal trigger signal output stage Stages,
A signal generation method comprising: a delay time calculation step of calculating a delay time to be set in each signal processing device based on the delay correction value calculated in the delay correction value calculation step.

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