JP2015061273A - Clock phase shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock phase shift circuit that shortens a total lock time without causing a harmonic lock.SOLUTION: The clock phase shift circuit includes: a PLL circuit phase-locked to a reference clock to generate a synchronous clock having a frequency N times that of the reference clock; a period setting circuit operating in synchronization with the reference clock to set a cycle detection period corresponding to one cycle of the reference clock; a period detection circuit operating in synchronization with the synchronous clock to output an active DLL start signal when detecting that a count value of the synchronous clock has become equal to the multiplication factor N within the cycle detection period; and a DLL circuit operatively started when the DLL start signal becomes active to shift the phase of the synchronous clock by a predetermined phase shift amount so as to output as a delayed clock.

Description

  The present invention shifts the phase of a synchronous clock generated by a PLL (Phase Locked Loop) circuit by a predetermined phase shift amount using a DLL (Delay Locked Loop) circuit, and outputs it as a delayed clock. It is about.

  The clock phase shift circuit shifts the phase of an input clock using a delay line, a DLL circuit, etc., and outputs it as an output clock. For example, DDR-SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory) In an interface circuit such as RSDS (Reduced Swing Differential Signaling), it is used to adjust the timing between an input clock and data input to a DDR-SDRAM or RSDS.

  For example, a clock phase shift circuit using a DLL circuit includes a PLL circuit and a DLL circuit, and is synchronized in phase with the reference clock by the PLL circuit and by multiplying the frequency of the reference clock by N (N is an integer of 1 or more). After generating the clock, the phase of the synchronous clock is shifted by a predetermined phase shift amount by the DLL circuit and output as a delayed clock.

  Hereinafter, a clock phase shift circuit using a DLL circuit will be described.

FIG. 7 is a block diagram showing an example of the configuration of a conventional clock phase shift circuit 40. As shown in FIG. The clock phase shift circuit 40 shown in the figure is constituted by a PLL circuit 12 and a DLL circuit 14.
The PLL circuit 12 includes a phase frequency comparator (PFD) and a charge pump (CP) 16, a loop filter (LF) 18, a voltage controlled oscillator (VCO) 20, and an N divider (1 / N) 22. And.

  In the clock phase shift circuit 40, the phase frequency comparator 16 of the PLL circuit 12 detects the phase difference between the reference clock REFCLK and the feedback clock FBCLK generated by the N frequency divider 22.

As a result, for example, when the phase of the feedback clock FBCLK is ahead of the phase of the reference clock REFCLK, the charge pump 16 discharges the capacitive element constituting the loop filter 18 and the control voltage decreases.
On the other hand, when the phase of the feedback clock FBCLK is delayed with respect to the phase of the reference clock REFCLK, the charge pump 16 charges up the aforementioned capacitive element, and the control voltage rises.

  Subsequently, the voltage-controlled oscillator 20 generates an oscillation clock, that is, a synchronous clock PLL_CLK, whose frequency decreases when the control voltage decreases and increases when the control voltage increases.

  Subsequently, the N frequency divider 22 divides the synchronous clock PLL_CLK by N to generate a feedback clock FBCLK having a frequency 1 / N of the frequency of the synchronous clock PLL_CLK.

  Thereafter, in the same manner, the phase difference between the reference clock REFCLK and the feedback clock FBCLK whose frequency has been changed is detected, and the control voltage changes accordingly and the frequency of the synchronous clock PLL_CLK is changed. Is repeatedly performed, the phase and frequency between the reference clock REFCLK and the synchronous clock PLL_CLK are locked.

  Then, the phase of the synchronous clock PLL_CLK is shifted by a predetermined phase shift amount (DLL delay) by the DLL circuit 14 and is output as the delayed clock DLL_CLK.

Next, FIG. 8 is a graph showing an example of the relationship between the synchronous clock of the PLL circuit 12 and the delay clock of the DLL circuit 14 shown in FIG.
In the clock phase shift circuit 40, first, the operation of the PLL circuit 12 is started. When the PLL circuit 12 starts operation, as shown in the graph of the figure, the period of the synchronous clock PLL_CLK gradually decreases, once overshoots and falls below the lock period T of the PLL circuit 12, and then gradually. The period is increased to exceed the period T, and thereafter the period is increased and decreased, and then locked to the period T.

  On the other hand, the DLL circuit 14 starts to operate after a predetermined time since the lock time until the period of the synchronous clock PLL_CLK is locked to the period T has elapsed. When the DLL circuit 14 starts operation, the phase shift amount of the delay clock DLL_CLK gradually increases and the lock phase shift amount of the DLL circuit 14 corresponding to the period T of the synchronous clock PLL_CLK, as shown in the graph of FIG. , The phase shift amount corresponding to the period T is locked.

In this case, since both the lock time until the period of the synchronous clock PLL_CLK is locked and the lock time until the phase shift amount of the delay clock DLL_CLK is locked, the total lock time becomes long. .
On the other hand, in order to shorten the total lock time, for example, it is conceivable to start the operations of both the PLL circuit 12 and the DLL circuit 14 simultaneously.

  The operation of the PLL circuit 12 in this case is the same as that shown in the graph of FIG. 8, as shown in the graph of FIG. 9, and the period of the synchronous clock PLL_CPL is increased and decreased repeatedly after overshooting once. Lock to.

  On the other hand, when the DLL circuit 14 starts operation, as shown in the graph of FIG. 6, the phase shift amount of the delay clock DLL_CLK gradually increases, and the synchronization clock when the period is still large while the period is gradually decreasing is obtained. In the case of the example shown in the figure, after reaching the phase shift amount corresponding to the period of PLL_CLK, and then repeating the increase / decrease following the change in the period of the synchronous clock PLL_CLK that gradually decreases further Is locked to the phase shift amount corresponding to the period 2T.

As described above, when the operations of both the PLL circuit 12 and the DLL circuit 14 are started simultaneously, the phase shift amount of the delay clock DLL_CLK is gradually increased with the phase shift amount corresponding to a period larger than the period T as a target. Become.
However, if the DLL circuit 14 cannot follow the change in the period of the synchronous clock PLL_CLK after that, the phase shift amount of the delay clock DLL_CLK is locked with a phase shift amount corresponding to a period of a plurality of periods T (harmonic) Lock).

  As described above, the shortening of the lock time of the entire clock phase shift circuit 40 and the risk of the occurrence of harmonic lock are in a trade-off relationship.

  Here, there are patent documents 1 to 5 as prior art documents relevant to the present invention. These documents describe a clock delay circuit that delays a clock signal generated by a clock generation circuit such as a PLL circuit for a predetermined time using a delay circuit such as a DLL circuit.

JP 2002-43934 A Special table 2007-536831 gazette JP 2008-71018 A JP 2008-210307 A JP 2009-104721 A

  An object of the present invention is to provide a clock phase shift circuit capable of solving the problems of the prior art and shortening the entire lock time without generating a harmonic lock.

In order to achieve the above object, according to the present invention, the frequency of the reference clock is set to N based on a multiplication number N (N is an integer of 1 or more) set in phase with a reference clock and set by a multiplication number setting signal. A PLL circuit that generates a synchronous clock having a multiplied frequency;
A period setting circuit that operates in synchronization with the reference clock and generates a period setting signal that sets a period detection period corresponding to one period of the reference clock;
Operates in synchronization with the synchronous clock, and counts the number of clocks of the synchronous clock during the period detection period, and starts detecting an active DLL when the count value is detected to be equal to the multiplication number N. A period detection circuit for outputting a signal;
A clock phase shift circuit comprising: a DLL circuit which starts an operation when the DLL start signal becomes active, shifts the phase of the synchronous clock by a predetermined phase shift amount, and outputs the delayed clock as a delay clock; It is to provide.

Here, the period detection circuit is
A counter that operates in synchronization with the synchronous clock, counts the number of synchronous clocks in the detection period, and outputs the count value;
A comparison circuit that compares the count value with the multiplication number N and outputs a comparison result in an active state when the count value becomes equal to the multiplication number N;
It is preferable to include a comparison result holding circuit that operates in synchronization with the synchronous clock and outputs the DLL start signal in the active state when the comparison result is in the active state.

  The period setting circuit may be a divide-by-2 circuit that operates in synchronization with the reference clock and generates a divided clock obtained by dividing the reference clock by two as the period setting signal.

  The DLL circuit is preferably two or more DLL circuits cascade-connected to the PLL circuit.

  In the present invention, after the PLL circuit starts operation, the synchronization clock count value multiplication number N becomes equal in the period detection period, that is, the synchronization clock period first reaches the synchronization clock lock period. When this is detected, the operation of the DLL circuit is started. Therefore, according to the present invention, the lock time of the entire clock phase shift circuit can be shortened without generating a harmonic lock.

1 is a block diagram of an embodiment showing a configuration of a clock phase shift circuit 10 of the present invention. FIG. 2 is a circuit diagram illustrating an example of a configuration of a period detection circuit 26 illustrated in FIG. 1. (A) And (B) is an example state transition diagram showing operation | movement of the period detection circuit 26 shown in FIG. 3 is an example timing chart illustrating an operation of a period detection circuit 26 illustrated in FIG. 2. 6 is a timing chart of another example showing the operation of the period detection circuit 26 shown in FIG. 3 is a graph illustrating an example of a relationship between a synchronous clock of a PLL circuit 12 illustrated in FIG. 1 and a delay clock of a DLL circuit 14; FIG. 6 is a block diagram illustrating an example of a configuration of a conventional clock phase shift circuit 40. 8 is a graph illustrating an example of a relationship between a synchronous clock of the PLL circuit 12 illustrated in FIG. 7 and a delay clock of the DLL circuit 14; 6 is a graph of another example showing the relationship between the synchronous clock of the PLL circuit 12 and the delay clock of the DLL circuit 14.

  Hereinafter, a clock phase shift circuit of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a block diagram of an embodiment showing a configuration of a clock phase shift circuit 10 of the present invention. The clock phase shift circuit 10 shown in the figure is further provided with a frequency divider (1/2) 24 and a period detection circuit 26 in the conventional clock phase shift circuit 40 shown in FIG.
That is, the clock phase shift circuit 10 includes the PLL circuit 12, the DLL circuit 14, the divide-by-2 (1/2) 24, and the cycle detection circuit 26.

A reference clock REFCLK and a multiplication number setting signal N_DIV are input to the PLL circuit 12.
The PLL circuit 12 is synchronized in phase with the reference clock REFCLK and having a frequency obtained by multiplying the frequency of the reference clock REFCLK by N based on the multiplication number N (N is an integer of 1 or more) set by the multiplication setting signal N_DIV. A clock PLL_CLK is generated, and a phase frequency comparator (PFD) and a charge pump (CP) 16, a loop filter (LF) 18, a voltage controlled oscillator (VCO) 20, and an N divider (1 / N ) 22.

  Since the PLL circuit 12 is the same as that included in the conventional clock phase shift circuit 40, the same components are denoted by the same reference numerals, and the repeated description thereof is omitted.

A reference clock REFCLK is input to the frequency divider 24.
The two-frequency divider 24 operates in synchronization with the rising edge of the reference clock REFCLK and generates a divided clock REFCLKD2 obtained by dividing the reference clock REFCLK by two. That is, each of the high level (H) and low level (L) periods of the divided clock REFCLKD2 corresponds to one cycle of the reference clock REFCLK.

  The two-frequency divider 24 is an example of a period setting circuit of the present invention that operates in synchronization with the reference clock REFCLK and generates a period setting signal that sets a period detection period corresponding to one period of the reference clock REFCLK. That is, the divided clock REFCLKD2 is an example of the period setting signal of the present invention. In the present embodiment, the H period of the divided clock REFCLKD2 is the period detection period.

The period detection circuit 26 receives the frequency-divided clock REFCLKD2, the multiplication number setting signal N_DIV, the synchronization clock PLL_CLK, and the initialization reset signal RSTN. The reset signal RSTN for initialization is a signal that becomes L only when initialization is performed.
The period detection circuit 26 operates in synchronization with the oscillation clock of the voltage-controlled oscillator 20 of the PLL circuit 12, that is, the rising edge of the synchronous clock PLL_CLK, and the number of clocks of the synchronous clock PLL_CLK during the period detection period set by the period setting signal. When the count value COUNT becomes equal to the multiplication number N, that is, when it is detected that the period of the synchronous clock PLL_CLK has reached the lock period T, the DLL start signal of H which is in the active state DLL_START is output.

The DLL circuit 14 is supplied with a synchronous clock PLL_CLK and a DLL start signal DLL_START.
The DLL circuit 14 starts operation when the DLL start signal DLL_START becomes H which is an active state, shifts the phase of the synchronous clock PLL_CLK by a predetermined phase shift amount (DLL delay), and outputs it as a delay clock DLL_CLK. is there.

  Although FIG. 1 shows one DLL circuit 14 connected to the PLL circuit 12, two or more DLL circuits 14 can be cascade-connected to the PLL circuit 12. In this case, the synchronous clock PLL_CLK and the DLL start signal DLL_START are input to the two or more DLL circuits 14, respectively.

  Next, the period detection circuit 26 will be described with a specific example.

  FIG. 2 is a circuit diagram showing an example of the configuration of the period detection circuit 26 shown in FIG. The period detection circuit 26 shown in the figure includes a counter 36 including a flip-flop (FF) 28 and an adder 30, a comparison circuit 32, an FF 34, and an AND circuit 38.

The output signal of the adder 30 is input to the data input terminal D of the FF 28, the synchronous clock PLL_CLK is input to the clock input terminal, and the logical product of the divided clock REFCLKD2 and the reset signal RSTN is input to the reset input terminal. The output signal of the AND circuit 38 taking
The count value COUNT output from the data output terminal Q of the FF 28 is input to one input terminal of the adder 30, and “1” is input to the other input terminal.
The counter 36 operates in synchronization with the rising edge of the synchronous clock PLL_CLK, counts the number of clocks of the synchronous clock PLL_CLK, and outputs the count value COUNT during the period detection period when the divided clock REFCLKD2 is H. It is.

Subsequently, the count value COUNT is input to the input terminal A of the comparison circuit 32, and the multiplication number setting signal N_DIV is input to the input terminal B.
The comparison circuit 32 compares the count value COUNT with the multiplication number N, and when the count value COUNT becomes equal to the multiplication number N, that is, when the period of the synchronous clock PLL_CLK reaches the period T, the output terminal A comparison result of H in an active state is output from Z.

The input terminal D of the FF 34 is connected to the power supply, the comparison result of the comparison circuit 32 is input to the enable input terminal EN, the synchronous clock PLL_CLK is input to the clock input terminal, and the reset signal RSTN is input to the reset input terminal. Is entered.
The FF 34 is an example of the comparison result holding circuit of the present invention, operates in synchronization with the rising edge of the synchronous clock PLL_CLK, and when the comparison result becomes H in the active state, the FF 34 is in the active state from the data output terminal Q. The DLL start signal DLL_START is output.

  Next, the operation of the period detection circuit 26 will be described.

As shown in the state transition diagram of FIG. 3A, the FF 28 is reset and the count value COUNT becomes “0” while the divided clock REFCLKD2 is L or the reset signal RSTN is L. At this time, the output signal of the adder 30 becomes “1”, and the comparison result of the comparison circuit 32 becomes L in the inactive state.
Further, as shown in the state transition diagram of FIG. 5B, while the reset signal RSTN is L, the FF 34 is reset and the DLL start signal DLL_START is initialized to L in the inactive state.

  On the other hand, as shown in the state transition diagram of FIG. 5A, during the period when the divided clock REFCLKD2 is H and the reset signal is H, the FF 28 operates in synchronization with the rising edge of the synchronous clock PLL_CLK. Is output as a count value COUNT. That is, the count value COUNT is counted up by one in synchronization with the rising edge of the synchronous clock PLL_CLK while the divided clock REFCLKD2 is H and the reset signal RSTN is H.

  Then, as shown in the state transition diagram of FIG. 5B, when the count value COUNT becomes equal to the multiplication number N, the comparison result of the comparison circuit 32 becomes H in the active state.

  Further, during the period when the reset signal RSTN is H, the FF 34 operates in synchronization with the rising edge of the synchronous clock PLL_CLK, and when the comparison result becomes H, outputs the active state H as the DLL start signal DLL_START.

Next, FIG. 4 is an example timing chart showing the operation of the period detection circuit 26 shown in FIG. This timing chart represents the operation of the period detection circuit 26 before the period of the synchronous clock PLL_CLK reaches the period T.
As shown in this timing chart, the reference clock REFCLK is a clock signal having a predetermined period, and the divided clock REFCLKD2 is a clock signal obtained by dividing the reference clock REFCLK by two in synchronization with the rising edge of the reference clock REFCLK. . Therefore, as described above, the H period and the L period of the divided clock REFCLKD2 each correspond to one cycle of the reference clock REFCLK.
Before the period of the synchronous clock PLL_CLK reaches the period T, the frequency of the synchronous clock PLL_CLK is relatively low, that is, the period of the synchronous clock PLL_CLK is relatively large. Therefore, in the period detection period in which the synchronous clock PLL_CLK is H, The count value COUNT does not reach the multiplication number N. Therefore, the DLL start signal DLL_START does not change from L in the inactive state.

FIG. 5 is a timing chart of another example showing the operation of the period detection circuit 26 shown in FIG. This timing chart represents the operation of the period detection circuit 26 when the period of the synchronous clock PLL_CLK reaches the period T.
As shown in this timing chart, when the period of the synchronous clock PLL_CLK reaches the period T, the frequency of the synchronous clock PLL_CLK becomes relatively high, that is, the period of the synchronous clock PLL_CLK becomes relatively small. The count value COUNT reaches the multiplication number N. When the count value COUNT reaches the multiplication number N, the DLL start signal DLL_START changes to H in the active state in synchronization with the next rise of the synchronous clock PLL_CLK.

  Next, the operation of the clock phase shift circuit 10 will be described.

  In the clock phase shift circuit 10, the PLL circuit 12 generates a synchronous clock PLL_CLK having a frequency obtained by multiplying the frequency of the reference clock REFCLK by N by synchronizing the phase with the reference clock REFCLK.

  On the other hand, the frequency divider 24 divides the reference clock REFCLK by two to generate a divided clock REFCLKD2.

  Subsequently, the period detection circuit 26 counts the number of clocks of the synchronous clock PLL_CLK while the divided clock REFCLKD2 is H, that is, the period detection period, and the count value COUNT becomes equal to the multiplication number N. When detected, that is, when it is detected that the period of the synchronous clock PLL_CLK has reached the period T, an active DLL start signal DLL_START is output.

  When the DLL start signal DLL_START becomes H which is an active state, the DLL circuit 14 starts to operate, and the DLL circuit 14 shifts the phase of the synchronous clock PLL_CLK by a predetermined phase shift amount and outputs it as a delay clock DLL_CLK.

Next, FIG. 6 is a graph showing an example of the relationship between the synchronous clock of the PLL circuit 12 and the delay clock of the DLL circuit 14 shown in FIG.
In the clock phase shift circuit 10, first, the operation of the PLL circuit 12 is started. When the PLL circuit 12 starts operation, as shown in the graph of the figure, the period of the synchronous clock PLL_CLK gradually decreases, once overshoots and falls below the lock period T of the PLL circuit 12, and then gradually. The period is increased to exceed the period T, and thereafter the period is increased and decreased, and then locked to the period T.

The DLL circuit 14 detects when the period detection circuit 26 first detects that the count value COUNT is equal to the multiplication number N, that is, the period of the synchronous clock PLL_CLK has reached the period T. Sometimes, the operation starts when the DLL start signal DLL_START becomes H in the active state.
When the DLL circuit 14 starts operation, the phase shift amount of the delay clock DLL_CLK gradually increases and the period of the synchronous clock PLL_CLK smaller than the period T in the middle of the period gradually decreasing, as shown in the graph of FIG. And then repeatedly increase and decrease following the change in the cycle of the synchronous clock PLL_CLK, and then reach the lock phase shift amount of the DLL circuit 14 corresponding to the cycle T of the synchronous clock PLL_CLK. The phase shift amount corresponding to the period T is locked.

The harmonic lock has a risk of occurring when the period of the synchronous clock PLL_CLK is larger than the period T. However, once the period of the synchronous clock PLL_CLK becomes smaller than the period T, the harmonic lock does not occur.
As described above, in the clock phase shift circuit 10, the operation of the DLL circuit 14 is started when it is detected that the period of the synchronous clock PLL_CLK first reaches the period T after the PLL circuit 12 starts operating. Let Therefore, the clock phase shift circuit 10 can shorten the lock time of the entire clock phase shift circuit 10 without generating a harmonic lock.

  The specific configurations of the PLL circuit 12, the DLL circuit 14, the period setting circuit, and the period detection circuit 26 are not limited at all, and various configurations that can realize the same function can be used. Also, the polarity of each signal is not limited at all, and the circuit configuration can be changed as appropriate according to the polarity of each signal.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

10, 40 Clock phase shift circuit 12 PLL circuit 14 DLL circuit 16 Phase frequency comparator (PFD) and charge pump (CP)
18 Loop filter (LF)
20 Voltage controlled oscillator (VCO)
22 N frequency divider 24 2 frequency divider 26 period detection circuit 28, 34 flip-flop (FF)
30 Adder 32 Comparison circuit 36 Counter 38 AND circuit

Claims (4)

A PLL circuit that is phase-synchronized with a reference clock and generates a synchronous clock having a frequency obtained by multiplying the frequency of the reference clock by N based on a multiplication number N (N is an integer of 1 or more) set by a multiplication number setting signal. When,
A period setting circuit that operates in synchronization with the reference clock and generates a period setting signal that sets a period detection period corresponding to one period of the reference clock;
Operates in synchronization with the synchronous clock, and counts the number of clocks of the synchronous clock during the period detection period, and starts detecting an active DLL when the count value is detected to be equal to the multiplication number N. A period detection circuit for outputting a signal;
A clock phase shift circuit comprising: a DLL circuit that starts an operation when the DLL start signal becomes active, shifts the phase of the synchronous clock by a predetermined phase shift amount, and outputs the delayed clock as a delay clock. The period detection circuit includes:
A counter that operates in synchronization with the synchronous clock, counts the number of synchronous clocks in the detection period, and outputs the count value;
A comparison circuit that compares the count value with the multiplication number N and outputs a comparison result in an active state when the count value becomes equal to the multiplication number N;
The clock phase shift circuit according to claim 1, further comprising: a comparison result holding circuit that operates in synchronization with the synchronous clock and outputs a DLL start signal in the active state when the comparison result is in an active state.   3. The frequency division circuit according to claim 1, wherein the period setting circuit is a two-frequency divider that operates in synchronization with the reference clock and generates a divided clock obtained by dividing the reference clock by two as the period setting signal. Clock phase shift circuit.   The clock phase shift circuit according to claim 1, wherein the DLL circuit is two or more DLL circuits cascade-connected to the PLL circuit.

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