JP2015060893A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the performance of a semiconductor device.SOLUTION: A semiconductor device has a transistor TR1 serving as an enhancement mode FET and a transistor TR2 serving as a depletion mode FET. In order from bottom, the transistor TR1 includes: a channel layer CH1 made of a nitride semiconductor layer; an electron supply layer ES1 which is formed on the channel layer CH1 and made of a nitride semiconductor layer and which has a larger band gap than the channel layer CH1; and a source electrode SE1, a drain electrode DE1, and a gate electrode GE1 which are formed on the electron supply layer ES1. In the transistor TR1, a p-type semiconductor region PS is formed, separately from a lower surface of the electron supply layer ES1, in the channel layer CH1 under the gate electrode GE1.

Description

  The present invention relates to a semiconductor device, and can be suitably used for, for example, a semiconductor device using a nitride semiconductor.

  Nitride semiconductors such as gallium nitride (GaN) have a larger band gap and higher electron mobility than silicon (Si) and gallium arsenide (GaAs), so that transistors for high withstand voltage, high output, or high frequency are used. Application to is expected. Therefore, development of a power control field effect transistor (FET) using a nitride semiconductor such as gallium nitride, that is, a power device has been promoted.

  As a field effect transistor using such a nitride semiconductor, a depletion mode FET in which a current flows between a source electrode and a drain electrode when no voltage is applied to the gate electrode, that is, a normally-on type field effect transistor There is. On the other hand, there is an enhancement mode FET in which no current flows between the source electrode and the drain electrode when no voltage is applied to the gate electrode, that is, a normally-off type field effect transistor. And, by integrating the depletion mode FET and the enhancement mode FET on the same substrate, a high-frequency power amplifier for small and high power, a high-frequency switch that can withstand high power input, and a logic circuit, An integrated semiconductor device can be realized.

  Japanese Unexamined Patent Application Publication No. 2012-28705 (Patent Document 1) and Japanese Unexamined Patent Application Publication No. 2000-277724 (Patent Document 2) describe a technique related to a semiconductor device in which a depletion mode FET and an enhancement mode FET are formed on the same substrate. Has been. Japanese Patent Application Laid-Open No. 2011-181922 (Patent Document 3) and Japanese Patent Application Laid-Open No. 2001-210657 (Patent Document 4) disclose a technique related to a semiconductor device in which a depletion mode FET and an enhancement mode FET are formed on the same substrate. Is described.

  Japanese Patent Laid-Open No. 2012-231002 (Patent Document 5) includes a back barrier layer formed above a substrate and made of p-type gallium nitride, and a channel layer made of gallium nitride formed on the back barrier layer. Techniques relating to the semiconductor device provided are described.

  Japanese Patent Laying-Open No. 2007-250727 (Patent Document 6) describes a technique related to a semiconductor device formed under a semiconductor layer made of n-type gallium nitride and having a semiconductor layer made of p-type gallium nitride. .

JP 2012-28705 A JP 2000-277724 A JP 2011-181922 A JP 2001-210657 A JP 2012-231002 A JP 2007-250727 A

  However, when the enhancement mode FET and the depletion mode FET are formed on the same substrate, the structure around the gate electrode in the enhancement mode FET may be different from the structure around the gate electrode in the depletion mode FET. In such a case, characteristics of the enhancement mode FET and the depletion mode FET may vary between both types of transistors or between one type of transistors, and the characteristics may become unstable. The performance of is reduced.

  Alternatively, even if the depletion mode FET is not formed on the substrate and only the enhancement mode FET is formed, if the structure around the gate electrode is complicated, the characteristics vary among the enhancement mode FETs, and the characteristics are different. There is a risk of instability, and the performance of the semiconductor device deteriorates.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the semiconductor device includes an enhancement mode FET and a depletion mode FET. The enhancement mode FET and the depletion mode FET are both in order from the bottom, a channel layer made of a nitride semiconductor layer, an electron supply formed on the channel layer, made of a nitride semiconductor layer, and having a larger band gap than the channel layer. And a source electrode, a drain electrode, and a gate electrode formed on the electron supply layer. In the enhancement mode FET, a p-type nitride semiconductor layer is formed in the channel layer under the gate electrode away from the lower surface of the electron supply layer.

  According to one embodiment, the performance of a semiconductor device can be improved.

2 is a main-portion cross-sectional view of the semiconductor device of First Embodiment; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. FIG. 10 is a cross-sectional view of a principal part of a semiconductor device of Comparative Example 1. FIG. 10 is a cross-sectional view of main parts of a semiconductor device of Comparative Example 2. FIG. 10 is a cross-sectional view of main parts of a semiconductor device of Comparative Example 3. FIG. 10 is a main-portion cross-sectional view of the semiconductor device of Embodiment 2; FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof. FIG. 10 is a main-portion cross-sectional view of the semiconductor device of Embodiment 3; FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Third Embodiment during a manufacturing step thereof. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Third Embodiment during a manufacturing step thereof. FIG. 10 is a main-portion cross-sectional view of the semiconductor device of Embodiment 4; FIG. 24 is an essential part cross-sectional view during a manufacturing step of the semiconductor device of the fourth embodiment. FIG. 24 is an essential part cross-sectional view during a manufacturing step of the semiconductor device of the fourth embodiment. FIG. 10 is a main-portion cross-sectional view of the semiconductor device of Embodiment 5; FIG. 25 is a main-portion cross-sectional view of the semiconductor device in Embodiment 5 during the manufacturing process; FIG. 25 is a main-portion cross-sectional view of the semiconductor device in Embodiment 5 during the manufacturing process;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, typical embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view for easy viewing of the drawings.

(Embodiment 1)
<Structure of semiconductor device>
The semiconductor device of the first embodiment is a semiconductor device having a field effect transistor, and a semiconductor device having a high electron mobility transistor (HEMT) as the field effect transistor.

  FIG. 1 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment.

  As shown in FIG. 1, the semiconductor device according to the first embodiment includes a substrate SUB, and a transistor TR1 and a transistor TR2 that are HEMTs as field effect transistors formed on the substrate SUB. The transistor TR1 is an enhancement mode FET in which a drain current does not flow when no voltage is applied to the gate electrode, that is, a normally-off type field effect transistor. On the other hand, the transistor TR2 is a depletion mode FET in which a drain current flows when no voltage is applied to the gate electrode, that is, a normally-on field effect transistor.

  The substrate SUB has a surface TS as a first main surface and a back surface BS as a second main surface opposite to the first main surface. The transistor TR1 is formed in a region AR1 on the surface TS side of the substrate SUB, and the transistor TR2 is formed in a region AR2 different from the region AR1 on the surface TS side of the substrate SUB.

  In the region AR1, the transistor TR1 is formed on the buffer layer BUF1 formed on the surface TS of the substrate SUB, the channel layer CH1 made of a nitride semiconductor layer formed on the buffer layer BUF1, and the channel layer CH1. An electron supply layer ES1 made of a nitride semiconductor layer. In addition, the transistor TR1 includes a source electrode SE1 and a drain electrode DE1 that are formed apart from each other on the electron supply layer ES1. The transistor TR1 has a gate electrode GE1 formed on the electron supply layer ES1 sandwiched between the source electrode SE1 and the drain electrode DE1 so as to be separated from both the source electrode SE1 and the drain electrode DE1.

  In addition, the transistor TR1 includes a p-type semiconductor region PS that is located on the back surface BS side of the gate electrode GE1 in the channel layer CH1 and that is formed in a portion away from the electron supply layer ES1. That is, the p-type semiconductor region PS is formed in the channel layer CH1 below the gate electrode GE1 and away from the lower surface of the electron supply layer ES1.

  In the region AR2, the transistor TR2 is formed on the buffer layer BUF2 formed on the surface TS of the substrate SUB, the channel layer CH2 made of the nitride semiconductor layer formed on the buffer layer BUF2, and the channel layer CH2. An electron supply layer ES2 made of a nitride semiconductor layer. The transistor TR2 has a source electrode SE2 and a drain electrode DE2 that are formed apart from each other on the electron supply layer ES2. The transistor TR2 has a gate electrode GE2 formed away from both the source electrode SE2 and the drain electrode DE2 on the electron supply layer ES2 sandwiched between the source electrode SE2 and the drain electrode DE2.

  On the other hand, the transistor TR2 does not have a semiconductor region corresponding to the p-type semiconductor region PS included in the transistor TR1. Therefore, no p-type semiconductor region is formed in a portion of the channel layer CH2 located on the back surface BS side of the gate electrode GE2 and away from the electron supply layer ES2. That is, no p-type semiconductor region is formed in the channel layer CH2 below the gate electrode GE2 in a portion away from the lower surface of the electron supply layer ES2.

  The substrate SUB is a semiconductor substrate made of, for example, silicon (Si), that is, a single crystal silicon substrate. The material of the substrate SUB is not particularly limited as long as the nitride semiconductor layer formed on the substrate SUB has crystallinity necessary for obtaining desired characteristics. Therefore, for example, a sapphire substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or the like can be used as the substrate SUB. When the substrate SUB is a single crystal silicon substrate, the plane orientation is preferably (111).

  In the area AR1, the buffer layer BUF1 is formed on the surface TS of the substrate SUB. In the area AR2, the buffer layer BUF2 is formed on the surface TS of the substrate SUB. The buffer layer BUF1 is formed to relieve the lattice constant difference between the substrate SUB and the channel layer CH1, and the buffer layer BUF2 is formed to relieve the lattice constant difference between the substrate SUB and the channel layer CH2. For example, the lattice constant difference between silicon (Si) constituting the substrate SUB and gallium nitride (GaN) constituting each of the channel layer CH1 and the channel layer CH2 can be reduced by the buffer layer BUF1 and the buffer layer BUF2, respectively. it can.

  When each of the channel layer CH1 and the channel layer CH2 made of gallium nitride (GaN) is directly formed on the substrate SUB made of silicon (Si), many cracks are formed in each of the channel layer CH1 and the channel layer CH2. May occur, a good epitaxial growth layer cannot be obtained, and it may be difficult to fabricate the HEMT. Therefore, each of the buffer layer BUF1 and the buffer layer BUF2 for the purpose of lattice relaxation is inserted between the substrate SUB and each of the channel layer CH1 and the channel layer CH2. By forming the buffer layer BUF1 and the buffer layer BUF2, a good epitaxial growth layer is obtained on each of the channel layer CH1 and the channel layer CH2 formed on each of the buffer layer BUF1 and the buffer layer BUF2, and the HEMT is manufactured. It becomes easy.

  As for each material of the buffer layer BUF1 and the buffer layer BUF2, each of the channel layer CH1 and the channel layer CH2 which are nitride semiconductor layers formed on each of the buffer layer BUF1 and the buffer layer BUF2, and the electron supply layer ES1 Each of the electron supply layers ES2 is not particularly limited as long as it has crystallinity necessary for obtaining desired characteristics. Accordingly, as each of the buffer layer BUF1 and the buffer layer BUF2, a nitride semiconductor layer made of gallium nitride (GaN), aluminum gallium nitride (AlGaN) or aluminum nitride (AlN), or a laminated film in which these are laminated is used. Can do. Further, when the substrate SUB is a gallium nitride substrate, the crystallinity of each of the channel layer CH1 and the channel layer CH2, the electron supply layer ES1, and the electron supply can be obtained without using each of the buffer layer BUF1 and the buffer layer BUF2. The respective crystallinity of the layer ES2 is maintained. Therefore, each of the buffer layer BUF1 and the buffer layer BUF2 may not be interposed between the substrate SUB and each of the channel layer CH1 and the channel layer CH2.

  The buffer layer BUF2 is preferably the same buffer layer as the buffer layer BUF1. Thereby, since the buffer layer BUF1 and the buffer layer BUF2 can be formed by the same process, the number of manufacturing processes of the semiconductor device can be reduced.

  A channel layer CH1 is formed on the buffer layer BUF1, and a channel layer CH2 is formed on the buffer layer BUF2. Each of channel layer CH1 and channel layer CH2 is made of a nitride semiconductor layer, and preferably made of gallium nitride (GaN). The thickness of each of the channel layer CH1 and the channel layer CH2 can be set to about 1 μm, for example.

  The gallium nitride constituting each of the channel layer CH1 and the channel layer CH2 is preferably undoped gallium nitride, that is, gallium nitride in an intrinsic state that does not exhibit either n-type conductivity or p-type conductivity ( i-GaN). That is, the conductivity type of gallium nitride constituting each of the channel layer CH1 and the channel layer CH2 is neither n-type nor p-type. Alternatively, gallium nitride constituting each of the channel layer CH1 and the channel layer CH2 is neither an n-type semiconductor nor a p-type semiconductor. In addition, undoped gallium nitride includes, for example, gallium nitride grown without intentional doping. Furthermore, a nitride semiconductor layer such as indium gallium nitride (InGaN) can be used as each of the channel layer CH1 and the channel layer CH2.

  Here, “semiconductor exhibits n-type conductivity”, “semiconductor conductivity type is n-type” and “n-type semiconductor” means that majority carriers in the semiconductor are electrons. To do. In addition, “a semiconductor exhibits p-type conductivity”, “a semiconductor has a p-type conductivity” and “a p-type semiconductor” means that majority carriers in the semiconductor are holes. To do.

When both electrons and holes are present as carriers in the semiconductor, the difference between the electron concentration and the hole concentration is an effective carrier concentration. In the present specification, “the majority carrier is an electron” means a state in which the electron concentration is higher than the hole concentration and the effective carrier concentration is higher than 1 × 10 ¹⁵ cm ^−3. And Further, “the majority carrier is a hole” means a state where the hole concentration is higher than the electron concentration and the effective carrier concentration is higher than 1 × 10 ¹⁵ cm ⁻³ .

On the other hand, the intrinsic state indicates a state where the electron concentration and the hole concentration are substantially equal, or a state where electrons or holes as carriers are not generated. In the present specification, the intrinsic state means a state where the effective carrier concentration is 1 × 10 ¹⁵ cm ⁻³ or less.

  The channel layer CH2 is preferably a nitride semiconductor layer that is the same layer as the channel layer CH1. Thereby, since the channel layer CH1 and the channel layer CH2 can be formed by the same process, the number of manufacturing steps of the semiconductor device can be reduced.

  An electron supply layer ES1 is formed on the channel layer CH1. The electron supply layer ES1 is made of a nitride semiconductor layer different from the nitride semiconductor layer constituting the channel layer CH1, for example, a nitride semiconductor layer having a band gap different from the band gap of the channel layer CH1. Preferably, the band gap of the electron supply layer ES1 is larger than the band gap of the channel layer CH1.

  An electron supply layer ES2 is formed on the channel layer CH2. The electron supply layer ES2 is made of a nitride semiconductor layer different from the nitride semiconductor layer constituting the channel layer CH2, for example, a nitride semiconductor layer having a band gap different from the band gap of the channel layer CH2. Preferably, the band gap of the electron supply layer ES2 is larger than the band gap of the channel layer CH2.

  Therefore, when a nitride semiconductor layer made of gallium nitride (GaN) is used as each of the channel layer CH1 and the channel layer CH2, aluminum gallium nitride (AlGaN) is preferably used as each of the electron supply layer ES1 and the electron supply layer ES2. A nitride semiconductor layer made of can be used. Further, when a nitride semiconductor layer made of indium gallium nitride (InGaN) is used as each of the channel layer CH1 and the channel layer CH2, preferably, the electron supply layer ES1 and the electron supply layer ES2 are gallium nitride or aluminum nitride, respectively. A nitride semiconductor layer made of gallium can be used.

Specifically, when a nitride semiconductor layer made of aluminum gallium nitride (AlGaN) is used as each of the electron supply layer ES1 and the electron supply layer ES2, the composition ratio of Al in each of the electron supply layer ES1 and the electron supply layer ES2 is determined. 15%, that is, the composition of AlGaN can be Al _0.15 Ga _0.85 N. In addition, the thickness of each of the electron supply layer ES1 and the electron supply layer ES2 can be 15 nm.

  The electron supply layer ES1 is formed in direct contact with the channel layer CH1, and a heterojunction whose conduction band changes discontinuously at the interface is formed between the channel layer CH1 and the electron supply layer ES1. . The electron supply layer ES2 is formed in direct contact with the channel layer CH2, and a heterojunction whose conduction band changes discontinuously at the interface is formed between the channel layer CH2 and the electron supply layer ES2. . Each of the electron supply layer ES1 and the electron supply layer ES2 can function as a carrier generation region. In addition, an n-type impurity such as silicon (Si) may be introduced into each of the electron supply layer ES1 and the electron supply layer ES2.

  Preferably, the electron supply layer ES2 is a nitride semiconductor layer that is the same layer as the electron supply layer ES1. Thereby, since the electron supply layer ES1 and the electron supply layer ES2 can be formed by the same process, the number of manufacturing steps of the semiconductor device can be reduced.

  A source electrode SE1 and a drain electrode DE1 are formed apart from each other on the electron supply layer ES1, and a source electrode SE2 and a drain electrode DE2 are formed apart from each other on the electron supply layer ES2. The source electrode SE1 and the drain electrode DE1 are both made of a conductor, and are made of a metal film such as a laminated film of a titanium (Ti) film and a gold (Au) film formed on the titanium film, for example. The source electrode SE2 and the drain electrode DE2 are both made of a conductor, and are made of a metal film such as a laminated film of a titanium film and a gold film formed on the titanium film, for example. Each of the source electrode SE1, the source electrode SE2, the drain electrode DE1, and the drain electrode DE2 extends in a direction substantially perpendicular to the paper surface of FIG. Each of the source electrode SE1 and the drain electrode DE1 is ohmically connected to the electron supply layer ES1, and each of the source electrode SE2 and the drain electrode DE2 is ohmically connected to the electron supply layer ES2.

  Preferably, each of the source electrode SE2 and the drain electrode DE2 is composed of a metal film MF2 in the same layer as the metal film MF1 constituting each of the source electrode SE1 and the drain electrode DE1 (see FIG. 8 described later). As a result, the source electrode SE1, the source electrode SE2, the drain electrode DE1, and the drain electrode DE2 can be formed in the same process, so that the number of manufacturing steps of the semiconductor device can be reduced.

  On the electron supply layer ES1 sandwiched between the source electrode SE1 and the drain electrode DE1, a gate electrode GE1 is formed apart from both the source electrode SE1 and the drain electrode DE1. Further, on the electron supply layer ES2 sandwiched between the source electrode SE2 and the drain electrode DE2, a gate electrode GE2 is formed apart from both the source electrode SE2 and the drain electrode DE2. Both the gate electrode GE1 and the gate electrode GE2 are made of a conductor, for example, a metal film such as a laminated film of a nickel (Ni) film and a gold (Au) film formed on the nickel film. Each of the gate electrode GE1 and the gate electrode GE2 extends in a direction substantially perpendicular to the paper surface of FIG.

  The gate electrode GE1 is preferably Schottky connected to the electron supply layer ES1, and the gate electrode GE2 is preferably Schottky connected to the electron supply layer ES2. This makes it difficult for current to flow between the gate electrode GE1 and the electron supply layer ES1 across the Schottky barrier, so that gate leakage current in the transistor TR1 can be reduced. In addition, since it becomes difficult for current to flow between the gate electrode GE2 and the electron supply layer ES2 across the Schottky barrier, gate leakage current in the transistor TR2 can be reduced.

  For example, in order to improve the breakdown voltage of each of the gate electrode GE1 and the gate electrode GE2, for example, gallium nitride is provided between the electron supply layer ES1 and the gate electrode GE1 and between the electron supply layer ES2 and the gate electrode GE2. A cap layer made of (GaN) may be formed. Further, in order to improve the ohmic contact property of each of the source electrode SE1 and the drain electrode DE1, as a semiconductor exhibiting n-type conductivity between each of the source electrode SE1 and the drain electrode DE1 and the electron supply layer ES1, For example, a cap layer made of n-type gallium nitride (GaN) may be formed. Further, in order to improve the ohmic contact property of each of the source electrode SE2 and the drain electrode DE2, as a semiconductor exhibiting n-type conductivity between each of the source electrode SE2 and the drain electrode DE2 and the electron supply layer ES2, For example, a cap layer made of n-type gallium nitride may be formed.

  In the first embodiment, in the region AR1, the p-type semiconductor region PS is formed in a portion of the channel layer CH1 located on the back surface BS side of the gate electrode GE1 and away from the electron supply layer ES1. Yes. That is, the p-type semiconductor region PS is formed in the channel layer CH1 below the gate electrode GE1 and away from the lower surface of the electron supply layer ES1. As a result, the structure of the gate electrode GE1 on the electron supply layer ES1 and the structure of the gate electrode GE2 on the electron supply layer ES2 can be made the same, thereby reducing variations in the characteristics of the transistors TR1 and TR2. can do.

As described above, when the channel layer CH1 is made of intrinsic gallium nitride (i-GaN), the p-type semiconductor region PS is doped with, for example, magnesium (Mg) as a p-type impurity. Is formed. In addition, the p-type impurity concentration in the p-type semiconductor region PS, that is, the impurity concentration of magnesium can be set to 1 × 10 ¹⁹ cm ⁻³ , for example.

  Here, the distance in the thickness direction of the substrate SUB between the upper surface of the p-type semiconductor region PS and the lower surface of the electron supply layer ES1 is defined as a distance DS1. At this time, the semiconductor device can be operated as a normally-off HEMT, that is, a field effect transistor by adjusting the distance DS1, the composition of the electron supply layer ES1, and the p-type impurity concentration in the p-type semiconductor region PS. it can. That is, in order to form a potential well near the interface with the electron supply layer ES1 in the channel layer CH1 to form a two-dimensional electron gas, the p-type semiconductor region PS is formed away from the electron supply layer ES1, and p The semiconductor region PS of the mold is not brought into contact with the electron supply layer ES1. On the other hand, in order to reduce the concentration of the two-dimensional electron gas in the channel layer CH1 to a level necessary for realizing a normally-off type HEMT, the p-type semiconductor region PS is brought close to the electron supply layer ES1.

A specific range of the specific distance DS1 is determined according to the composition of the electron supply layer ES1 and the p-type impurity concentration in the p-type semiconductor region PS. For example, when the composition of the electron supply layer ES1 made of aluminum gallium nitride is Al _0.15 Ga _0.85 N and the p-type impurity concentration is 1 × 10 ¹⁹ cm ⁻³ , the distance DS1 is preferably 50 The distance DS1 can be more preferably 100 nm.

  The p-type semiconductor region PS is formed in a region where the gate electrode GE1 is formed in plan view. That is, the length in the gate length direction of the portion where the p-type semiconductor region PS is formed is equal to or shorter than the gate length.

  In the specification of the present application, “in plan view” means a case of viewing from a direction perpendicular to the surface TS of the substrate SUB.

  In the present specification, the first semiconductor region being formed in the second region means that the first semiconductor region is located inside the second region in plan view. However, since a part of the first semiconductor region does not have to protrude outside the second region, in this specification, when the first semiconductor region is formed in the second region, One semiconductor region may be the same region as the second region. Therefore, for example, when the gate length of the gate electrode GE1 is set to 500 nm, the length in the gate length direction of the portion where the p-type semiconductor region PS is formed can be set to 500 nm.

  Thereby, when a voltage is not applied to the gate electrode GE1, a region where the two-dimensional electron gas is not formed in the channel layer CH1 does not extend so much from the gate electrode GE1 to the source electrode SE1 side and the drain electrode DE1 side. can do. Therefore, the resistance when the transistor TR1 is in an on state, that is, the on-resistance can be reduced while the transistor TR1 is operated as a normally-off HEMT.

  Preferably, the transistor TR1 has an opening OP1 that penetrates the substrate SUB from the back surface BS of the substrate SUB and reaches the channel layer CH1. The p-type semiconductor region PS is formed in a portion of the channel layer CH1 exposed at the bottom of the opening OP1. Thereby, when manufacturing the semiconductor device, the p-type impurity can be easily introduced into the channel layer CH1 exposed at the bottom of the opening OP1 from the back surface BS side of the substrate SUB. Therefore, the transistor TR1 can be easily manufactured while making the structure of the gate electrode GE1 of the transistor TR1 as the enhancement mode FET the same as the structure of the gate electrode GE2 of the transistor TR2 as the depletion mode FET.

  As a structure after the p-type semiconductor region PS is formed, the opening OP1 reaches the p-type semiconductor region PS from the back surface BS of the substrate SUB through the substrate SUB.

  More preferably, the opening OP1 penetrates the substrate SUB from the back surface BS of the substrate SUB and reaches the channel layer CH1 in the region of the channel layer CH1 where the gate electrode GE1 is formed in plan view. The p-type semiconductor region PS is formed in a region of the channel layer CH1 where the opening OP1 reaches the channel layer CH1 in plan view. Thereby, in the channel layer CH1, the p-type semiconductor region PS can be formed in the region where the gate electrode GE1 is formed in plan view. Therefore, the on-resistance of the transistor TR1 can be reduced while the transistor TR1 is operated as a normally-off HEMT.

  In the first embodiment, unlike the fourth embodiment described later, the width of the p-type semiconductor region PS is in the thickness direction of the p-type semiconductor region PS except for the upper portion of the p-type semiconductor region PS. It shall be uniform along.

  The transistor TR1 includes a conductive layer CL1 made of a conductive film buried in the opening OP1, and electrically connected to the p-type semiconductor region PS exposed at the bottom of the opening OP1. The conductive film is made of, for example, a nickel (Ni) film, a platinum (Pt) film, and a gold (Au) film sequentially formed on the bottom surface and side surfaces of the opening OP1. Thus, the heat generated in the transistor TR1 can be easily transferred to the back surface BS side, and thus the transistor TR1 can be stably operated.

  As shown in FIG. 1, a metal film BM may be formed on the back surface BS of the substrate SUB, and the conductor layer CL1 may be formed integrally with the metal film BM. At this time, the metal film BM includes, for example, a nickel (Ni) film, a platinum (Pt) film, and a gold (Au) film sequentially formed on the back surface BS of the substrate SUB. Thus, the heat generated in the transistor TR1 can be easily radiated from the metal film BM through the conductor layer CL1, so that the transistor TR1 can be operated more stably. In addition, the conductor layer CL1 and the metal film BM can be equipotential with the source electrode SE1, for example. As a result, when a high voltage is applied between the source electrode SE1 and the drain electrode DE1, holes generated in the p-type semiconductor region PS, that is, holes generated in the transistor TR1, are converted into p-type semiconductor regions. Since it can be easily removed without accumulating inside the PS, the breakdown voltage of the transistor TR1 can be improved.

<Operation of semiconductor device>
Next, the operation of the semiconductor device according to the first embodiment will be described. Here, the transistor TR2 not having the p-type semiconductor region PS operates as a depletion mode FET, that is, a normally-on type device, and the transistor TR1 having the p-type semiconductor region PS operates as an enhancement mode FET, that is, a normally-off type device. The point will be described.

  In the transistor TR2 as the HEMT shown in FIG. 1, a two-dimensional electron gas 2DEG is formed in the vicinity of the interface between the channel layer CH2 and the electron supply layer ES2. Specifically, the band gap of, for example, gallium nitride (GaN) that forms the channel layer CH2 is different from the band gap of, for example, aluminum gallium nitride (AlGaN) that forms the electron supply layer ES2. For this reason, a potential well whose bottom energy is lower than the Fermi level is formed in the vicinity of the interface between the channel layer CH2 and the electron supply layer ES2 due to the influence of the conduction band offset based on the difference in the band gap. As a result, when no voltage is applied to the gate electrode GE2, a two-dimensional electron gas 2DEG is formed in the vicinity of the interface between the channel layer CH2 and the electron supply layer ES2, and the transistor TR2 operates as a normally-on type device. In FIG. 1, the two-dimensional electron gas 2DEG is schematically shown by a broken line.

  Here, the transistor TR1 as the HEMT has a structure similar to that of the transistor TR2 except that the p-type semiconductor region PS is provided in the channel layer CH1 under the gate electrode GE1. Therefore, the two-dimensional electron gas 2DEG is formed near the interface between the channel layer CH1 and the electron supply layer ES1 in the channel layer CH1 other than the portion under the gate electrode GE1. However, in the transistor TR1, the p-type semiconductor region PS is formed in the channel layer CH1 below the gate electrode GE1 so as to be separated from the electron supply layer ES1, so that the conduction band of the channel layer CH1 is below the gate electrode GE1. Energy rises. As a result, the energy of the potential well formed in the vicinity of the interface with the electron supply layer ES1 in the channel layer CH1 becomes higher than the Fermi level, and when no voltage is applied to the gate electrode GE1, The two-dimensional electron gas 2DEG can be prevented from being formed in the channel layer CH1. Thereby, the transistor TR1 operates as a normally-off device.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. 2 to 9 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of First Embodiment.

  First, as shown in FIG. 2, for example, a metal organic chemical vapor deposition (MOCVD) method is performed on a substrate SUB which is a semiconductor substrate made of silicon with an exposed (111) plane. A plurality of semiconductor layers are stacked. The substrate SUB has a front surface TS and a back surface BS.

  First, the buffer layer BUF1 made of undoped gallium nitride (GaN) is formed on the surface TS of the substrate SUB in the region AR1 on the surface TS side of the substrate SUB, and the substrate SUB is formed in the region AR2 on the surface TS side of the substrate SUB. A buffer layer BUF2 that is the same layer as the buffer layer BUF1 is formed on the surface TS. Each film thickness of the buffer layer BUF1 and the buffer layer BUF2 can be set to about 1 μm, for example.

  Next, a channel layer CH1, which is a nitride semiconductor layer made of, for example, undoped gallium nitride (GaN), is formed on the buffer layer BUF1 by epitaxial growth, and the nitride in the same layer as the channel layer CH1 is formed on the buffer layer BUF2. A channel layer CH2 that is a semiconductor layer is formed by epitaxial growth. The film thickness of each of the channel layer CH1 and the channel layer CH2 can be set to about 1 μm, for example.

  Next, an electron supply layer ES1 which is a nitride semiconductor layer made of, for example, undoped aluminum gallium nitride (AlGaN) is formed on the channel layer CH1 by epitaxial growth, and the same layer as the electron supply layer ES1 is formed on the channel layer CH2. An electron supply layer ES2 that is a nitride semiconductor is formed by epitaxial growth. The film thickness of each of the electron supply layer ES1 and the electron supply layer ES2 can be, for example, about 15 nm.

  In this manner, as shown in FIG. 2, a semiconductor layer structure including the buffer layer BUF1, the channel layer CH1, and the electron supply layer ES1 is formed on the substrate SUB in the region AR1, and on the substrate SUB in the region AR2. A semiconductor layer structure including the buffer layer BUF2, the channel layer CH2, and the electron supply layer ES2 is formed. These semiconductor layer structures are formed by group III plane growth stacked in the [0001] crystal axis (C axis) direction. After these semiconductor layer structures are formed, a mark pattern for forming the transistor TR1 and the p-type semiconductor region PS is formed on the electron supply layer ES1 in the region AR1, and the electron supply is performed in the region AR2. A mark pattern for forming the transistor TR2 is formed on the layer ES2.

  Note that a two-dimensional electron gas 2DEG is formed near the interface between the channel layer CH1 and the electron supply layer ES1, and a two-dimensional electron gas 2DEG is formed near the interface between the channel layer CH2 and the electron supply layer ES2.

  Next, as shown in FIGS. 3 and 4, in the area AR1, an opening OP1 that penetrates the substrate SUB from the back surface BS of the substrate SUB and reaches the channel layer CH1 is formed.

First, in the area AR1 and the area AR2, the back surface BS side of the substrate SUB is ground, and the substrate SUB is thinned to about 150 μm, for example. Next, after applying photoresist on the back surface BS of the substrate SUB to form a resist film (not shown) in the areas AR1 and AR2, pattern exposure is performed and development is performed, whereby the resist film is formed in the area AR1. An opening reaching the back surface BS of the substrate SUB is formed. Then, for example, by dry etching using sulfur hexafluoride (SF ₆ ) gas as an etching gas, as shown in FIG. 3, the opening OP11 that penetrates the substrate SUB from the back surface BS of the substrate SUB and reaches the buffer layer BUF1 is formed. Then, the resist film is removed.

Next, a photoresist is applied again to the back surface BS of the substrate SUB, a resist film RR1 is formed in the region AR1, and a resist film RR2 is formed in the region AR2. Next, pattern exposure is performed with a double-side exposure machine using a mark pattern for forming the p-type semiconductor region PS, for example, in a region where the p-type semiconductor region PS (see FIG. 5 described later) is to be developed. Thus, an opening OP13 that penetrates the resist film RR1 and reaches the buffer layer BUF1 is formed. Then, for example, by dry etching using boron trichloride (BCl ₃ ) gas as an etching gas, as shown in FIG. 4, the buffer layer BUF1 exposed at the bottom of the opening OP13 formed in the resist film RR1 is penetrated. An opening OP12 reaching the channel layer CH1 is formed. Thereby, an opening OP1 including the opening OP11 formed in the back surface BS of the substrate SUB and the opening OP12 formed in the bottom of the opening OP11 is formed.

  Preferably, the opening OP13 and the opening OP12 are formed in a region where the gate electrode GE1 (see FIG. 1) is formed in plan view. Thereby, the p-type semiconductor region PS (see FIG. 5 described later) can be formed in a region where the gate electrode GE1 (see FIG. 1) is formed in a plan view.

  In the example shown in FIG. 4, the opening width WT1 of the opening OP11 is larger than the opening width WT2 of the opening OP12. However, the opening width WT1 of the opening OP11 may not be larger than the opening width WT2 of the opening OP12, and the opening width WT1 of the opening OP11 may be equal to the opening width WT2 of the opening OP12.

  Next, as shown in FIG. 5, a p-type semiconductor region PS is formed. For example, a p-type semiconductor region PS is formed by introducing a p-type impurity into a portion of the channel layer CH1 exposed at the bottom of the opening OP1 by ion implantation.

  Specifically, ion implantation is performed using the patterned resist film RR1 (see FIG. 4) as a mask, and a portion of the channel layer CH1 exposed at the bottom of the opening OP1 is exposed to, for example, magnesium from the back surface BS side of the substrate SUB. A p-type impurity such as (Mg) is implanted. By adjusting the energy of the implanted ions, for example, ions as p-type impurities can be implanted to a position separated from the electron supply layer ES1 by the distance DS1 in the thickness direction of the substrate SUB in the channel layer CH1. . Further, as described above, the distance DS1 can be set to 100 nm, for example. Thereafter, the resist film RR1 (see FIG. 4) and the resist film RR2 (see FIG. 4) are removed, and heat treatment is performed at a temperature of about 850 ° C. for about 20 minutes, for example, to remove the implanted p-type impurity. By activating, the p-type semiconductor region PS can be formed.

  This reduces the concentration of the two-dimensional electron gas 2DEG formed in the vicinity of the interface between the channel layer CH1 and the electron supply layer ES1 in the channel layer CH1 on the p-type semiconductor region PS, or 0.

  Alternatively, instead of the ion implantation method, for example, a metal oxide such as magnesium oxide (MgO) is formed on the surface of the channel layer CH1 exposed at the bottom of the opening OP1, and heat treatment is performed to form magnesium in the channel layer CH1. A diffusion method for diffusing can also be used.

  As a structure after the p-type semiconductor region PS is formed, the opening OP1 reaches the p-type semiconductor region PS from the back surface BS of the substrate SUB through the substrate SUB.

  Next, as shown in FIG. 6, the conductor layer CL1 embedded in the opening OP1 is formed in the region AR1, and the metal film BM is formed on the back surface BS of the substrate SUB in the regions AR1 and AR2. Specifically, a nickel (Ni) film, a platinum (Pt) film, and a gold (Au) film are sequentially formed inside the opening OP1, thereby forming the conductor layer CL1 embedded in the opening OP1. . In the region AR1 and the region AR2, a metal film BM is formed by sequentially forming a nickel film, a platinum film, and a gold film on the back surface BS of the substrate SUB.

  Next, as shown in FIGS. 7 to 9 and FIG. 1, the source electrode SE1, the drain electrode DE1, and the gate electrode GE1 are formed in the region AR1, and the source electrode SE2, the drain electrode DE2, and the gate electrode GE2 are formed in the region AR2. Form.

  First, as shown in FIG. 7, a resist film FR1 is formed on the electron supply layer ES1 in the region AR1, and a resist film FR2 that is the same layer as the resist film FR1 is formed on the electron supply layer ES2 in the region AR2. Then, the resist film FR1 and the resist film FR2 are patterned by performing exposure / development processing on the resist film FR1 and the resist film FR2. The patterning of the resist film FR1 is performed so that the region where the source electrode SE1 and the drain electrode DE1 are formed is exposed, and the patterning of the resist film FR2 is performed so that the region where the source electrode SE2 and the drain electrode DE2 are formed is exposed. To be done.

  Next, a metal film MF1 is formed on the patterned resist film FR1, and a metal film MF2 in the same layer as the metal film MF1 is formed on the patterned resist film FR2. Thereby, in the region AR1, the metal film MF1 is formed directly on the electron supply layer ES1 in the region where the source electrode SE1 and the drain electrode DE1 are formed. In other regions of the region AR1, the metal film MF1 is formed on the resist film FR1. A metal film MF1 is formed. In the region AR2, the metal film MF2 is formed directly on the electron supply layer ES2 in the region where the source electrode SE2 and the drain electrode DE2 are formed. In other regions of the region AR2, the metal film MF2 is formed on the resist film FR2. A metal film MF2 is formed.

  The metal film MF1 and the metal film MF2 are, for example, a titanium (Ti) film, an aluminum (Al) film formed on the titanium film, a nickel (Ni) film formed on the aluminum film, and a nickel film. It is composed of the formed gold (Au) film. The metal film having such a configuration is expressed as Ti / Al / Ni / Au. The metal film MF1 and the metal film MF2 can be formed by a vapor deposition method, for example.

  Next, as shown in FIG. 8, the resist film FR1 is lifted off in the area AR1, and the resist film FR2 is lifted off in the area AR2. Then, in the region AR1, the resist film FR1 and the metal film MF1 formed on the resist film FR1 are removed, and only the metal film MF1 formed so as to be in direct contact with the electron supply layer ES1 remains. In the region AR2, the resist film FR2 and the metal film MF2 formed over the resist film FR2 are removed, and only the metal film MF2 formed so as to be in direct contact with the electron supply layer ES2 remains.

  Thereby, in the region AR1, the source electrode SE1 and the drain electrode DE1 made of the metal film MF1 in direct contact with the electron supply layer ES1 can be formed, and in the region AR2, from the metal film MF2 in direct contact with the electron supply layer ES2. Thus, the source electrode SE2 and the drain electrode DE2 can be formed. In the region AR1, the source electrode SE1 and the drain electrode DE1 are arranged apart from each other, and in the region AR2, the source electrode SE2 and the drain electrode DE2 are arranged apart from each other. Thereafter, the substrate SUB is subjected to a heat treatment so that each of the source electrode SE1 and the drain electrode DE1 is in ohmic contact with the channel layer CH1, and each of the source electrode SE2 and the drain electrode DE2 is connected to the channel layer CH2. Make ohmic contact.

  Next, as shown in FIG. 9, a resist film FR3 is formed on the electron supply layer ES1 including the surfaces of the source electrode SE1 and the drain electrode DE1 in the region AR1, and the source electrode SE2 and the drain electrode in the region AR2. A resist film FR4 that is the same layer as the resist film FR3 is formed on the electron supply layer ES2 including the surface of DE2. Then, the resist film FR3 and the resist film FR4 are patterned by subjecting the resist film FR3 and the resist film FR4 to exposure / development processing. The patterning of the resist film FR3 is performed so that the region where the gate electrode GE1 is formed is exposed, and the patterning of the resist film FR4 is performed so that the region where the gate electrode GE2 is formed is exposed.

  Next, a metal film MF3 is formed on the patterned resist film FR3, and a metal film MF4 in the same layer as the metal film MF3 is formed on the patterned resist film FR4. Thereby, in the region AR1, the metal film MF3 is formed directly on the electron supply layer ES1 in the region where the gate electrode GE1 is formed, and in other regions of the region AR1, the metal film MF3 is formed on the resist film FR3. Is formed. In the region AR2, the metal film MF4 is formed directly on the electron supply layer ES2 in the region where the gate electrode GE2 is formed. In other regions of the region AR2, the metal film MF4 is formed on the resist film FR4. It is formed.

  The metal film MF3 and the metal film MF4 are composed of, for example, a nickel (Ni) film and a gold (Au) film formed on the nickel film. The metal film having such a configuration is represented as Ni / Au. The metal film MF3 and the metal film MF4 can be formed by, for example, a vapor deposition method.

  Thereafter, the resist film FR3 is lifted off in the region AR1, and the resist film FR4 is lifted off in the region AR2. Then, in the region AR1, the resist film FR3 and the metal film MF3 formed on the resist film FR3 are removed, and only the metal film MF3 formed so as to be in direct contact with the electron supply layer ES1 remains. In the region AR2, the resist film FR4 and the metal film MF4 formed on the resist film FR4 are removed, and only the metal film MF4 formed so as to be in direct contact with the electron supply layer ES2 remains.

  As a result, the gate electrode GE1 (see FIG. 1) made of the metal film MF3 that is in direct contact with the electron supply layer ES1 can be formed in the region AR1, and the metal film MF4 that is in direct contact with the electron supply layer ES2 in the region AR2. A gate electrode GE2 (see FIG. 1) can be formed. In the region AR1, the gate electrode GE1 is disposed on the electron supply layer ES1 sandwiched between the source electrode SE1 and the drain electrode DE1, apart from both the source electrode SE1 and the drain electrode DE1. In the region AR2, the gate electrode GE2 is disposed on the electron supply layer ES2 sandwiched between the source electrode SE2 and the drain electrode DE2, apart from both the source electrode SE2 and the drain electrode DE2. Preferably, the gate electrode GE1 is formed so that the p-type semiconductor region PS is disposed in the region where the gate electrode GE1 is formed.

  Thereafter, although illustration is omitted, an element isolation region is formed by ion implantation of nitrogen (N) or the like in order to achieve element isolation between devices. As described above, as shown in FIG. 1, the transistor TR1 can be manufactured in the region AR1, and the transistor TR2 can be manufactured in the region AR2.

<E / D configuration with a different structure around the gate electrode>
FIG. 10 is a cross-sectional view of main parts of the semiconductor device of Comparative Example 1.

  As shown in FIG. 10, the semiconductor device of Comparative Example 1 also includes a transistor TR101 and a transistor TR102, which are HEMTs as field effect transistors, like the semiconductor device of the first embodiment. The transistor TR101 is an enhancement mode FET, that is, a normally-off type field effect transistor, and the transistor TR102 is a depletion mode FET, that is, a normally-on type field effect transistor.

  Similarly to the transistor TR1 of the first embodiment, the transistor TR101 includes a buffer layer BUF1 formed over the substrate SUB and a channel layer CH1 made of a nitride semiconductor layer formed over the buffer layer BUF1 in the region AR1, And an electron supply layer ES1 made of a nitride semiconductor layer formed on the channel layer CH1.

  On the other hand, unlike the transistor TR1 of the first embodiment, the transistor TR101 does not have the p-type semiconductor region PS (see FIG. 1) and is a cap formed of a nitride semiconductor layer formed on the electron supply layer ES1. The layer CP101 is included. Therefore, the source electrode SE1, the drain electrode DE1, and the gate electrode GE1 are formed on the cap layer CP101.

  Similarly to the transistor TR2 in the first embodiment, the transistor TR102 includes a buffer layer BUF2 formed over the substrate SUB and a channel layer CH2 made of a nitride semiconductor layer formed over the buffer layer BUF2 in the region AR2. And an electron supply layer ES2 made of a nitride semiconductor layer formed on the channel layer CH2.

  On the other hand, unlike the transistor TR2 in the first embodiment, the transistor TR102 includes a cap layer CP102 made of a nitride semiconductor layer formed on the electron supply layer ES2, and a gate insulating film GI102 formed on the cap layer 102. Have. The source electrode SE2 and the drain electrode DE2 are formed on the cap layer CP102, and the gate electrode GE2 is formed on the cap layer CP102 via the gate insulating film GI102.

  In the transistor TR101, the cap layer CP101 is formed between the electron supply layer ES1 and the gate electrode GE1, and the concentration of the two-dimensional electron gas formed in the vicinity of the interface with the electron supply layer ES1 in the channel layer CH1 is reduced. As a result, the transistor TR101 is operated as an enhancement mode FET.

  In the transistor TR102, similarly to the transistor TR101, a cap layer CP102 is formed between the electron supply layer ES2 and the gate electrode GE2, and the two-dimensional structure is formed in the vicinity of the interface with the electron supply layer ES2 in the channel layer CH2. Reduce the concentration of electron gas. However, in the transistor TR102, unlike the transistor TR101, since the gate insulating film GI102 is formed between the cap layer CP102 and the gate electrode GE2, a gate voltage higher than that of the gate electrode GE1 is required to modulate the channel. I need it. As a result, the transistor TR102 is operated as a depletion mode FET.

  FIG. 11 is a cross-sectional view of a principal part of the semiconductor device of Comparative Example 2.

  As shown in FIG. 11, the semiconductor device of Comparative Example 2 also includes a transistor TR201 and a transistor TR202, which are HEMTs as field effect transistors, similarly to the semiconductor device of the first embodiment. The transistor TR201 is an enhancement mode FET, that is, a normally-off type field effect transistor, and the transistor TR202 is a depletion mode FET, that is, a normally-on type field effect transistor.

  Unlike the transistor TR1 of the first embodiment, the transistor TR201 does not have the p-type semiconductor region PS (see FIG. 1). In the region AR1, the transistor TR201 includes a buffer layer BUF1 formed over the substrate SUB, an intrinsic nitride semiconductor layer NI201 formed over the buffer layer BUF1, and a channel formed over the nitride semiconductor layer NI201. Layer CH201. The transistor TR201 includes a nitride semiconductor layer NN201 formed on the channel layer CH201 and having a high n-type impurity concentration.

  In the transistor TR201, the source electrode SE1 and the drain electrode DE1 are formed on the nitride semiconductor layer NN201. In the nitride semiconductor layer NN201 between the source electrode SE1 and the drain electrode DE1, an opening OP201 that penetrates the nitride semiconductor layer NN201 and reaches the channel layer CH201 is formed. The gate electrode GE1 is formed on the channel layer CH201 exposed at the bottom surface of the opening OP201.

  In the region AR2, the transistor TR202 includes a buffer layer BUF2 formed over the substrate SUB, an intrinsic nitride semiconductor layer NI202 formed over the buffer layer BUF2, and a channel formed over the nitride semiconductor layer NI202. Layer CH202. The transistor TR202 includes a nitride semiconductor layer NN202 that is formed on the channel layer CH202 and has a high n-type impurity concentration.

  In the transistor TR202, the source electrode SE2 and the drain electrode DE2 are formed on the nitride semiconductor layer NN202. In the nitride semiconductor layer NN202 between the source electrode SE2 and the drain electrode DE2, an opening OP202 that penetrates the nitride semiconductor layer NN202 and reaches the channel layer CH202 is formed. The gate electrode GE2 is formed on the channel layer CH202 exposed at the bottom surface of the opening OP202.

  In Comparative Example 2, the depth position of the bottom surface of the opening OP202 is set higher than the depth position of the bottom surface of the opening OP201, and the thickness of the channel layer CH202 below the gate electrode GE2 is equal to that of the gate electrode GE1. It is made larger than the thickness of the lower channel layer CH201. Thereby, the transistor TR201 is operated as an enhancement mode FET, and the transistor TR202 is operated as a depletion mode FET.

  FIG. 12 is a cross-sectional view of a principal part of the semiconductor device of Comparative Example 3.

  As shown in FIG. 12, the semiconductor device of Comparative Example 3 also includes a transistor TR301 and a transistor TR302, which are HEMTs as field effect transistors, like the semiconductor device of the first embodiment. The transistor TR301 is an enhancement mode FET, that is, a normally-off type field effect transistor, and the transistor TR302 is a depletion mode FET, that is, a normally-on type field effect transistor.

  Similarly to the transistor TR1 of the first embodiment, the transistor TR301 includes a buffer layer BUF1 formed over the substrate SUB and a channel layer CH1 made of a nitride semiconductor layer formed over the buffer layer BUF1 in the region AR1. Have.

  On the other hand, unlike the transistor TR1 of the first embodiment, the transistor TR301 does not have the p-type semiconductor region PS (see FIG. 1), is formed on the channel layer CH1, and is a barrier layer BR310 as an electron supply layer. Have The barrier layer BR310 includes a barrier layer BR311 formed on the channel layer CH1 and a barrier layer BR312 formed on the barrier layer BR311. In the barrier layer BR312, an opening OP311 that penetrates the barrier layer BR312 and reaches the barrier layer BR311 is formed, and a p-type nitride semiconductor layer NP301 is formed so as to fill the inside of the opening OP311. . Over the nitride semiconductor layer NP301 including the surface of the nitride semiconductor layer CP301, an insulating film IF301 is formed. An opening OP312 is formed in the insulating film IF301 so as to penetrate the insulating film IF301 and reach the p-type nitride semiconductor layer NP301. The gate electrode GE1 is made of a conductive film embedded in the opening OP312. Is in contact with the type nitride semiconductor layer NP301. In addition, an opening OP313 and an opening OP314 that pass through the insulating film IF301, the barrier layer BR312 and the barrier layer BR311 and reach the channel layer CH1 are formed, and each of the source electrode SE1 and the drain electrode DE1 includes the opening OP313 and The conductive film is embedded in each of the openings OP314 and is in contact with the channel layer CH1.

  Similarly to the transistor TR2 of the first embodiment, the transistor TR302 includes a buffer layer BUF2 formed over the substrate SUB and a channel layer CH2 made of a nitride semiconductor layer formed over the buffer layer BUF2 in the region AR2. Have.

  On the other hand, unlike the transistor TR2 of Embodiment 1, the transistor TR302 is formed on the channel layer CH2 and has a barrier layer BR320 as an electron supply layer. The barrier layer BR320 includes a barrier layer BR321 formed on the channel layer CH2 and a barrier layer BR322 formed on the barrier layer BR321. The barrier layer BR322 is formed with an opening OP321 that penetrates the barrier layer BR322 and reaches the barrier layer BR321. The opening OP321 includes a conductive film embedded in the opening OP321, and the barrier layer BR321. And a Schottky electrode GE302 that is Schottky-connected. An insulating film IF302 is formed on the barrier layer BR322 including the surface of the Schottky electrode GE302. An opening OP322 is formed in the insulating film IF302 so as to penetrate the insulating film IF302 and reach the Schottky electrode GE302. The gate electrode GE2 is made of a conductive film embedded in the opening OP322, and the Schottky electrode GE302 and In contact. In addition, an opening OP323 and an opening OP324 that penetrate the insulating film IF302, the barrier layer BR322, and the barrier layer BR321 and reach the channel layer CH2 are formed, and each of the source electrode SE2 and the drain electrode DE2 includes the opening OP323 and The conductive film is embedded in each of the openings OP324, and is in contact with the channel layer CH2.

  In Comparative Example 3, the transistor TR301 is operated as an enhancement mode FET by providing the p-type nitride semiconductor layer NP301 between the barrier layer BR311 and the gate electrode GE1. In addition, by not providing a nitride semiconductor layer corresponding to the p-type nitride semiconductor layer NP301 between the barrier layer BR321 and the gate electrode GE2, the transistor TR302 is operated as a depletion mode FET.

  However, in Comparative Examples 1 to 3, the structure around the gate electrode in the region AR1 is different from the structure around the gate electrode in the region AR2. Therefore, the characteristics vary between both kinds of transistors or between one kind of transistors among the enhancement mode FET formed in the area AR1 and the depletion mode FET formed in the area AR2. May become unstable. Note that the configuration of the semiconductor device including the enhancement mode FET and the depletion mode FET is referred to as an E / D configuration.

  In Comparative Example 1, the threshold voltage becomes positive by reducing the thickness of the electron supply layer ES1 in the transistor TR101. Also in the transistor TR102, the electron supply layer ES2 is the same layer as the electron supply layer ES1. The electron supply layer. Therefore, in the transistor TR101, the sheet resistance increases between the source electrode SE1 and the drain electrode DE1 and the on-resistance increases, and in the transistor TR102, the sheet resistance increases between the source electrode SE2 and the drain electrode DE2. Increases on-resistance. In the transistor TR102, a gate insulating film GI102 is formed between the thinned electron supply layer ES1 and the gate electrode GE1 in order to operate as a depletion mode FET. However, depending on the film quality of the gate insulating film GI102, hysteresis may occur in the threshold voltage, and the performance of the semiconductor device is degraded.

  In Comparative Example 2, the thickness of the channel layer CH202 under the gate electrode GE2 is changed from the thickness of the channel layer CH201 under the gate electrode GE1 by changing the etching amount when etching the channel layer CH201 and the channel layer CH202. Also try to get bigger. However, since the channel layer CH202 is made of the same nitride semiconductor layer as the channel layer CH201, it is necessary to adjust the etching time, for example, in order to change the etching amount of the channel layer between the region AR1 and the region AR2. It is. Therefore, the etching time cannot be adjusted appropriately, and there is a possibility that the threshold voltage varies between both types of transistors TR201 and TR202 or between one type of transistors. Yes, the performance of the semiconductor device is degraded.

  In Comparative Example 3, the p-type nitride semiconductor layer NP301 is formed below the gate electrode GE1 in the region AR1, and the Schottky electrode GE302 is formed below the gate electrode GE2 in the region AR2. May become complicated. In the transistor TR301, depending on the method of forming the p-type nitride semiconductor layer NP301, an interface state is formed at the interface between the barrier layer BR311 and the p-type nitride semiconductor layer NP301, and hysteresis occurs in the threshold voltage. There is a risk. Further, in the transistor TR302, the barrier layer BR322 is etched. However, there is a possibility that the etching amount may vary, or damage may be applied during the etching, whereby the characteristics of the transistor TR302 may vary. Equipment performance is degraded.

  Even if only the enhancement mode FET is formed on the substrate without forming the depletion mode FET, if the structure around the gate electrode is complicated, the characteristics vary among the enhancement mode FETs, and the characteristics are different. There is a risk of instability, and the performance of the semiconductor device deteriorates.

<Main features and effects of the present embodiment>
In the semiconductor device according to the first embodiment, as shown in FIG. 1, in the region AR1, the p-type semiconductor region PS is separated from the lower surface of the electron supply layer ES1 in the channel layer CH1 below the gate electrode GE1. Is formed. Thus, since it is not necessary to form a p-type semiconductor region between the electron supply layer ES1 and the gate electrode GE1 in order to make the transistor TR1 an enhancement mode FET, the structure of the gate electrode GE1 on the electron supply layer ES1 is eliminated. And the structure of the gate electrode GE2 on the electron supply layer ES2 can be made the same. Accordingly, it is possible to reduce variations in characteristics of the transistors TR1 and TR2 while operating the transistor TR1 as an enhancement mode FET and operating the transistor TR2 as a depletion mode FET. Thus, the performance of the semiconductor device can be improved.

  In the first embodiment, the transistor TR1 as the enhancement mode FET with reduced characteristic variation and the transistor TR2 as the depletion mode FET with reduced characteristic variation are integrated on the substrate SUB. Can do. As a result, it is possible to realize a semiconductor device in which a small-sized high-frequency power amplifier for high power, a high-frequency switch capable of withstanding high power input, and a logic circuit are integrated.

  Preferably, the transistor TR1 has an opening OP1 that penetrates the substrate SUB from the back surface BS of the substrate SUB and reaches the channel layer CH1. The p-type semiconductor region PS is formed in a portion of the channel layer CH1 exposed at the bottom of the opening OP1. Thereby, when manufacturing the semiconductor device, the p-type impurity can be easily introduced into the channel layer CH1 exposed at the bottom of the opening OP1 from the back surface BS side of the substrate SUB. Therefore, the transistor TR1 can be easily manufactured while making the structure of the gate electrode GE1 of the transistor TR1 as the enhancement mode FET the same as the structure of the gate electrode GE2 of the transistor TR2 as the depletion mode FET.

  More preferably, the transistor TR1 has an opening OP1 that penetrates the substrate SUB from the back surface BS of the substrate SUB and reaches the channel layer CH1 in the region of the region AR1 where the gate electrode GE1 is formed in plan view. Have. The p-type semiconductor region PS is formed in a portion of the channel layer CH1 exposed at the bottom of the opening OP1. Thereby, the p-type semiconductor region PS can be formed in the region where the gate electrode GE1 is formed in plan view. Therefore, the on-resistance of the transistor TR1 can be reduced while the transistor TR1 is operated as a normally-off HEMT.

  In the semiconductor device of the first embodiment, it is possible to form only the transistor TR1 without forming the transistor TR2. Thereby, since the structure around the gate electrode GE1 in the transistor TR1 is not complicated, it is possible to reduce variation in characteristics of the transistor TR1 while operating the transistor TR1 as an enhancement mode FET (Embodiment 2 to Embodiment 2). The same applies to 5).

(Embodiment 2)
In the semiconductor device of the first embodiment, a nitride semiconductor layer having a composition different from that of the channel layer body is not formed in the middle of the channel layer in the thickness direction. In contrast, in the semiconductor device of the second embodiment, a nitride semiconductor layer containing aluminum (Al) is formed in the middle of the channel layer in the thickness direction.

<Structure of Semiconductor Device and Operation of Semiconductor Device>
FIG. 13 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment.

  As shown in FIG. 13, in the semiconductor device according to the second embodiment, portions other than the channel layer CH1 and the channel layer CH2 are the same as those of the semiconductor device according to the first embodiment.

  On the other hand, the channel layer CH1 of the transistor TR1 in the second embodiment is different from the channel layer CH1 in the transistor TR1 in the first embodiment on the nitride semiconductor layer CH11 and the nitride semiconductor layer CH11 formed on the buffer layer BUF1. And the nitride semiconductor layer CH13 formed on the nitride semiconductor layer CH12. Therefore, the electron supply layer ES1 is formed on the nitride semiconductor layer CH13.

  Further, the channel layer CH2 of the transistor TR2 in the second embodiment is different from the channel layer CH2 of the transistor TR2 in the first embodiment on the nitride semiconductor layer CH21 and the nitride semiconductor layer CH21 formed on the buffer layer BUF2. And the nitride semiconductor layer CH23 formed on the nitride semiconductor layer CH22. The nitride semiconductor layer CH21 is a nitride semiconductor layer that is the same layer as the nitride semiconductor layer CH11, and the nitride semiconductor layer CH22 is a nitride semiconductor layer that is the same layer as the nitride semiconductor layer CH12, and the nitride semiconductor layer CH23 is the same nitride semiconductor layer as the nitride semiconductor layer CH13. The electron supply layer ES2 is formed on the nitride semiconductor layer CH23.

  The nitride semiconductor layer CH11 and the nitride semiconductor layer CH13 can be nitride semiconductor layers similar to the nitride semiconductor layer constituting the channel layer CH1 of the first embodiment. The nitride semiconductor layer CH21 and the nitride semiconductor layer CH23 can be nitride semiconductor layers similar to the nitride semiconductor layer constituting the channel layer CH2 of the first embodiment.

  Preferably, the nitride semiconductor layer CH12 includes aluminum, and is made of, for example, aluminum gallium nitride (AlGaN). That is, in the transistor TR1 as the enhancement mode FET, the nitride semiconductor layer CH12 containing aluminum is formed in the middle of the channel layer CH1 in the thickness direction. Thus, when the p-type impurity made of magnesium (Mg) is introduced into the nitride semiconductor layer CH11 to form the p-type semiconductor region PS, the p-type impurity introduced into the nitride semiconductor layer CH11 is converted into the nitride semiconductor. Diffusion to the layer CH13 can be prevented or suppressed. Accordingly, variation in threshold voltage of the transistor TR1 can be reduced, and stability of the threshold voltage of the transistor TR1 can be improved.

  The effect of preventing or suppressing the diffusion of the p-type impurity is, for example, that the lattice of aluminum gallium nitride constituting the nitride semiconductor layer CH12 is increased with an increase in the aluminum composition ratio in the nitride semiconductor layer CH12 made of aluminum gallium nitride. This is thought to be because the constant becomes smaller and magnesium, which is a p-type impurity, becomes difficult to diffuse.

  Note that the composition ratio of aluminum in the nitride semiconductor layer CH12 made of aluminum gallium nitride means the ratio of the number of aluminum atoms to the total number of atoms of gallium and aluminum.

  In the second embodiment, in the region AR1, the p-type semiconductor region PS is formed in the nitride semiconductor layer CH11 in the portion located on the back surface BS side, that is, the lower side of the gate electrode GE1. In other words, the p-type semiconductor region PS is formed in the nitride semiconductor layer CH11 under the gate electrode GE1. Further, since the nitride semiconductor layer CH11 is separated from the electron supply layer ES1, the p-type semiconductor region PS formed in the nitride semiconductor layer CH11 is formed away from the electron supply layer ES1. Become. As a result, the structure of the gate electrode GE1 on the electron supply layer ES1 and the structure of the gate electrode GE2 on the electron supply layer ES2 can be made the same, thereby reducing variations in characteristics of the transistors TR1 and TR2. Can do.

  The p-type impurity concentration in the p-type semiconductor region PS of the second embodiment, that is, the impurity concentration of magnesium can be made the same as the p-type impurity concentration in the p-type semiconductor region PS of the first embodiment. . Also in the second embodiment, as in the first embodiment, the distance DS1 in the thickness direction of the substrate SUB between the upper surface of the p-type semiconductor region PS and the lower surface of the electron supply layer ES1, and the composition of the electron supply layer ES1. By adjusting the p-type impurity concentration in the p-type semiconductor region PS, the semiconductor device can be operated as a normally-off type HEMT.

  On the other hand, in the second embodiment, when the p-type semiconductor region PS is formed by introducing a p-type impurity made of magnesium (Mg) into the nitride semiconductor layer CH11, the p introduced into the nitride semiconductor layer CH11. It is possible to prevent or suppress the diffusion of type impurities into the nitride semiconductor layer CH13. Therefore, preferably, as shown in FIG. 13, in the nitride semiconductor layer CH11, the portion where the p-type semiconductor region PS is formed is a portion in contact with the lower surface of the nitride semiconductor layer CH12. That is, the p-type semiconductor region PS is formed in the nitride semiconductor layer CH11 below the gate electrode GE1 so as to be in contact with the lower surface of the nitride semiconductor layer CH12. Thereby, compared with Embodiment 1, the variation in threshold voltage of the transistor TR1 can be further reduced, and the stability of the threshold voltage of the transistor TR1 can be further improved.

  In the second embodiment, in the transistor TR2 as a depletion mode FET, the nitride semiconductor layer CH22 containing aluminum is also formed in the middle of the channel layer CH2 in the thickness direction. Further, since the nitride semiconductor layer CH22 contains aluminum, the band gap of the nitride semiconductor layer CH22 is larger than the band gap of the nitride semiconductor layer CH23. Thereby, since the confinement property of the two-dimensional electron gas 2DEG is improved, a depletion mode FET excellent in pinch-off property can be realized as the transistor TR2.

  The nitride semiconductor layer CH21 may not be the same layer as the nitride semiconductor layer CH11, the nitride semiconductor layer CH22 may not be the same layer as the nitride semiconductor layer CH12, and the nitride semiconductor layer CH23 The nitride semiconductor layer CH13 may not be the same layer.

  As described above, it is assumed that the p-type semiconductor region PS is formed in the nitride semiconductor layer CH11 under the gate electrode GE1 in contact with the lower surface of the nitride semiconductor layer CH12. At this time, the distance DS1 in the thickness direction of the substrate SUB between the upper surface of the nitride semiconductor layer CH11 and the lower surface of the electron supply layer ES1 is the sum of the thickness of the nitride semiconductor layer CH12 and the thickness of the nitride semiconductor layer CH13. Become. By adjusting the distance DS1, the composition of the electron supply layer ES1, and the p-type impurity concentration in the p-type semiconductor region PS, the semiconductor device can be operated as a normally-off field effect transistor. That is, in order to form a potential well near the interface with the electron supply layer ES1 in the nitride semiconductor layer CH13 to form the two-dimensional electron gas 2DEG, the p-type semiconductor region PS is nitrided away from the electron supply layer ES1. It is formed in the physical semiconductor layer CH11 so that the upper surface of the p-type semiconductor region PS and the lower surface of the electron supply layer ES1 are not brought into contact with each other. On the other hand, in order to reduce the concentration of the two-dimensional electron gas 2DEG in the nitride semiconductor layer CH13 to a level necessary for realizing a normally-off field effect transistor, the nitride semiconductor layer CH12 and the nitride semiconductor layer CH13 are thinned. Thus, the upper surface of the p-type semiconductor region PS is brought closer to the lower surface of the electron supply layer ES1.

  The specific range of the specific distance DS1 is determined according to the composition of the electron supply layer ES1 and the p-type impurity concentration in the p-type semiconductor region PS, as in the first embodiment.

  Also in the second embodiment, as in the first embodiment, the p-type semiconductor region PS is formed in a region where the gate electrode GE1 is formed in plan view. Accordingly, as in Embodiment 1, the transistor TR1 can be operated as a normally-off HEMT, and the on-resistance of the transistor TR1 can be reduced.

  In the second embodiment, preferably, the transistor TR1 has an opening OP1 that penetrates the substrate SUB from the back surface BS of the substrate SUB and reaches the nitride semiconductor layer CH11. The p-type semiconductor region PS is formed in a portion of the nitride semiconductor layer CH11 exposed at the bottom of the opening OP1. Thereby, when manufacturing the semiconductor device, the p-type impurity can be easily introduced into the nitride semiconductor layer CH11 exposed from the back surface BS side of the substrate SUB to the bottom of the opening OP1. Therefore, the transistor TR1 can be easily manufactured while making the structure of the gate electrode GE1 of the transistor TR1 as the enhancement mode FET the same as the structure of the gate electrode GE2 of the transistor TR2 as the depletion mode FET. As a structure after the p-type semiconductor region PS is formed, the opening OP1 reaches the p-type semiconductor region PS from the back surface BS of the substrate SUB through the substrate SUB.

  More preferably, the opening OP1 penetrates the substrate SUB from the back surface BS of the substrate SUB in a region of the nitride semiconductor layer CH11 where the gate electrode GE1 is formed in plan view. To reach. The p-type semiconductor region PS is formed in a region of the nitride semiconductor layer CH11 where the opening OP1 reaches the nitride semiconductor layer CH11 in plan view. Thereby, in the nitride semiconductor layer CH11, the p-type semiconductor region PS can be formed in the region where the gate electrode GE1 is formed in a plan view. Therefore, the on-resistance of the transistor TR1 can be reduced while the transistor TR1 is operated as a normally-off HEMT.

  In the second embodiment, unlike the fourth embodiment described later, the width of the p-type semiconductor region PS is assumed to be uniform along the thickness direction of the p-type semiconductor region PS.

  Similarly to the transistor TR1 of the first embodiment, the transistor TR1 of the second embodiment is made of a conductive film embedded in the opening OP1, and includes a p-type semiconductor region PS exposed at the bottom of the opening OP1. An electrically connected conductor layer CL1 is provided. Thus, the heat generated in the transistor TR1 can be easily transferred to the back surface BS side, and thus the transistor TR1 can be stably operated.

  In the second embodiment as well, as in the first embodiment, the conductor layer CL1 may be formed integrally with the metal film BM. Thus, holes generated in the transistor TR1 can be easily removed, so that the breakdown voltage of the transistor TR1 can be improved.

  The operation of the semiconductor device of the second embodiment is the same as that of the semiconductor device of the first embodiment.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. 14 to 16 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the second embodiment.

  First, as shown in FIG. 14, a plurality of semiconductor layers are stacked by, for example, MOCVD on a substrate SUB that is a semiconductor substrate made of silicon with the (111) plane exposed. The substrate SUB has a front surface TS and a back surface BS.

  First, similarly to the method for manufacturing the semiconductor device of the first embodiment, a buffer layer BUF1 made of undoped gallium nitride (GaN) is formed on the surface TS of the substrate SUB in the region AR1 on the surface TS side of the substrate SUB. In the region AR2 on the surface TS side of the substrate SUB, the buffer layer BUF2 that is the same layer as the buffer layer BUF1 is formed on the surface TS of the substrate SUB.

  Next, a channel layer CH1, which is a nitride semiconductor layer, is formed by epitaxial growth on the buffer layer BUF1, and a channel layer CH2, which is the same nitride semiconductor layer as the channel layer CH1, is epitaxially grown on the buffer layer BUF2. To form. The film thickness of each of the channel layer CH1 and the channel layer CH2 can be set to about 1 μm, for example.

  In the second embodiment, unlike the first embodiment, a nitride semiconductor layer CH11 made of, for example, undoped gallium nitride (GaN) is formed on the buffer layer BUF1, and the nitride semiconductor layer CH11 is formed on the buffer layer BUF2. The nitride semiconductor layer CH21 that is the same nitride semiconductor layer as the first layer is formed. Next, a nitride semiconductor layer CH12 made of, for example, aluminum gallium nitride (AlGaN) is formed on the nitride semiconductor layer CH11, and the nitride semiconductor layer that is the same layer as the nitride semiconductor layer CH12 is formed on the nitride semiconductor layer CH21. Nitride semiconductor layer CH22 is formed. Next, a nitride semiconductor layer CH13 made of, for example, undoped gallium nitride (GaN) is formed on the nitride semiconductor layer CH12, and the nitride semiconductor in the same layer as the nitride semiconductor layer CH13 is formed on the nitride semiconductor layer CH22. A nitride semiconductor layer CH23, which is a layer, is formed. Thus, the channel layer CH1 including the nitride semiconductor layer CH11, the nitride semiconductor layer CH12, and the nitride semiconductor layer CH13 is formed, and the channel layer including the nitride semiconductor layer CH21, the nitride semiconductor layer CH22, and the nitride semiconductor layer CH23. CH2 is formed.

  Next, as in Embodiment 1, the electron supply layer ES1 is formed over the channel layer CH1, and the electron supply layer ES2 is formed over the channel layer CH2. Thus, as shown in FIG. 14, a semiconductor layer structure including the buffer layer BUF1, the channel layer CH1, and the electron supply layer ES1 is formed on the substrate SUB in the region AR1, and on the substrate SUB in the region AR2. A semiconductor layer structure including the buffer layer BUF2, the channel layer CH2, and the electron supply layer ES2 is formed.

  A two-dimensional electron gas 2DEG is formed near the interface between the nitride semiconductor layer CH13 and the electron supply layer ES1, and a two-dimensional electron gas 2DEG is formed near the interface between the nitride semiconductor layer CH23 and the electron supply layer ES2. Is done.

  Next, as shown in FIG. 15, in the area AR1, an opening OP1 that penetrates the substrate SUB from the back surface BS of the substrate SUB and reaches the channel layer CH1 is formed. The step of forming the opening OP1 can be the same as the step described with reference to FIGS. 3 and 4 in the first embodiment.

  Specifically, as in the first embodiment, the opening OP11, the resist film RR1 and the resist film RR2, and the opening OP13 are sequentially formed and, unlike the first embodiment, exposed to the bottom of the opening OP13. An opening OP12 that penetrates through the buffer layer BUF1 and reaches the nitride semiconductor layer CH11 is formed. Thereby, an opening OP1 including the opening OP11 formed in the back surface BS of the substrate SUB and the opening OP12 formed in the bottom of the opening OP11 is formed.

  Next, as shown in FIG. 16, a p-type semiconductor region PS is formed. The step of forming the p-type semiconductor region PS can be performed in the same manner as the step described with reference to FIG. 5 in the first embodiment.

  However, in the second embodiment, unlike the first embodiment, the p-type impurity is introduced into a portion of the nitride semiconductor layer CH11 exposed at the bottom of the opening OP1 by, for example, an ion implantation method, thereby forming a p-type impurity. The semiconductor region PS is formed. By adjusting the energy of the implanted ions, for example, ions as p-type impurities can be implanted up to a portion of the nitride semiconductor layer CH11 that is in contact with the lower surface of the nitride semiconductor layer CH12. Thereafter, for example, a heat treatment is performed at a temperature of about 850 ° C. for about 20 minutes to activate the implanted p-type impurity, whereby the p-type semiconductor region PS can be formed. Thereafter, the resist film RR1 and the resist film RR2 are removed.

  A distance between the lower surface of the electron supply layer ES1 and the upper surface of the nitride semiconductor layer CH11 is a distance DS1. At this time, the p-type semiconductor region PS is formed in the channel layer CH1 away from the lower surface of the electron supply layer ES1 by a distance DS1 in the thickness direction of the substrate SUB. The distance DS1, that is, the sum of the thickness of the nitride semiconductor layer CH12 and the thickness of the nitride semiconductor layer CH13 can be set to 100 nm, for example.

  Also, in the portion of the nitride semiconductor layer CH13 on the p-type semiconductor region PS, does the concentration of the two-dimensional electron gas 2DEG formed near the interface between the nitride semiconductor layer CH13 and the electron supply layer ES1 decrease? Or 0.

  As a structure after the p-type semiconductor region PS is formed, the opening OP1 reaches the p-type semiconductor region PS from the back surface BS of the substrate SUB through the substrate SUB.

  In the second embodiment, unlike the first embodiment, the nitride semiconductor layer CH12 contains aluminum. Therefore, when the p-type impurity made of magnesium is introduced into the nitride semiconductor layer CH11 to form the p-type semiconductor region PS, the p-type impurity introduced into the nitride semiconductor layer CH11 diffuses into the nitride semiconductor layer CH13. This can be prevented or suppressed. Therefore, since the upper surface of the nitride semiconductor layer CH11 can be the upper surface of the p-type semiconductor region PS, variation in the distance DS1 between the lower surface of the electron supply layer ES1 and the upper surface of the p-type semiconductor region PS is reduced. Thus, variation in the threshold voltage of the transistor TR1 can be reduced.

  Next, a process similar to that described with reference to FIG. 6 in Embodiment 1 is performed to form the conductor layer CL1 in the region AR1, and a metal is formed on the back surface BS of the substrate SUB in the regions AR1 and AR2. A film BM is formed. Next, the same steps as those described in Embodiment 1 with reference to FIGS. 7 to 9 and FIG. 1 are performed, so that the source electrode SE1, the drain electrode DE1, the source electrode SE2, the drain electrode DE2, the gate electrode GE1, and A gate electrode GE2 is formed. Preferably, the gate electrode GE1 is formed so that the p-type semiconductor region PS is disposed in the region where the gate electrode GE1 is formed.

  Thereafter, by forming an element isolation region (not shown), the transistor TR1 can be manufactured in the region AR1 and the transistor TR2 can be manufactured in the region AR2, as shown in FIG.

<Main features and effects of the present embodiment>
The semiconductor device according to the second embodiment has the same characteristics as those of the semiconductor device according to the first embodiment. Therefore, the semiconductor device of the second embodiment has the same effect as that of the semiconductor device of the first embodiment.

  In addition, as shown in FIG. 13, in the transistor TR1 as the enhancement mode FET, the semiconductor device according to the second embodiment includes a nitride semiconductor layer made of aluminum gallium nitride in the middle of the channel layer CH1 in the thickness direction. CH12 is formed. Thereby, when the p-type impurity made of magnesium is introduced into the nitride semiconductor layer CH11 to form the p-type semiconductor region PS, the p-type impurity introduced into the nitride semiconductor layer CH11 is introduced into the nitride semiconductor layer CH13. Diffusion can be prevented or suppressed. Therefore, since the upper surface of the nitride semiconductor layer CH11 can be the upper surface of the p-type semiconductor region PS, variation in the distance DS1 between the lower surface of the electron supply layer ES1 and the upper surface of the p-type semiconductor region PS is reduced. be able to. Therefore, variation in threshold voltage of the transistor TR1 can be reduced, and stability of the threshold voltage of the transistor TR1 can be improved.

(Embodiment 3)
In the semiconductor device of the first embodiment, the conductor layer is embedded in the opening. In contrast, in the semiconductor device of the third embodiment, an insulator layer is embedded in the opening.

<Structure of Semiconductor Device and Operation of Semiconductor Device>
FIG. 17 is a fragmentary cross-sectional view of the semiconductor device of Third Embodiment.

  As shown in FIG. 17, in the semiconductor device according to the third embodiment, portions other than the insulator layer IL1 are the same as those of the semiconductor device according to the first embodiment.

  Unlike Embodiment 1, the transistor TR1 of Embodiment 3 is made of an insulating film embedded in the opening OP1, and is thermally connected to the p-type semiconductor region PS exposed at the bottom of the opening OP1. It has an insulator layer IL1. The insulating film constituting the insulating layer IL1 preferably has a thermal conductivity larger than that of the substrate SUB, and is made of, for example, aluminum nitride (AlN). Accordingly, compared to the case where the opening OP1 and the insulator layer IL1 are not formed, the heat generated in the transistor TR1 can be easily transferred to the back surface BS side through the insulator layer IL1, so that the transistor TR1 It can be operated stably.

  Further, in the third embodiment, preferably, the transistor TR2 includes an opening OP2 that penetrates the substrate SUB from the back surface BS of the substrate SUB and reaches the surface TS of the substrate SUB under the gate electrode GE2, and the opening OP2. And an insulating layer IL2 that is thermally connected to the buffer layer BUF2. The insulating film constituting the insulating layer IL2 preferably has a thermal conductivity larger than that of the substrate SUB, and is made of, for example, aluminum nitride (AlN). As a result, compared to the case where the opening OP2 and the insulator layer IL2 are not formed, the heat generated in the transistor TR2 can be easily transferred to the back surface BS side via the insulator layer IL2. It can be operated stably.

  Preferably, the insulating layer IL2 is made of the same insulating film as the insulating film constituting the insulating layer IL1. As a result, the insulator layer IL1 and the insulator layer IL2 can be formed by the same process, so that the number of manufacturing steps of the semiconductor device can be reduced.

  As shown in FIG. 17, a metal film BM may be formed on the back surface BS of the substrate SUB, and the metal film BM may be in contact with the insulator layer IL1 and the insulator layer IL2. The metal film BM can be the same as that in the first embodiment. Thus, the heat generated in the transistor TR1 can be easily radiated from the metal film BM through the insulator layer IL1, so that the transistor TR1 can be operated more stably. Further, since the heat generated in the transistor TR2 can be easily radiated from the metal film BM through the insulator layer IL2, the transistor TR2 can be operated more stably.

  The operation of the semiconductor device of the third embodiment is the same as that of the semiconductor device of the first embodiment.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device according to the third embodiment will be described. 18 and 19 are fragmentary cross-sectional views of the semiconductor device of the third embodiment during the manufacturing process thereof.

  In the third embodiment, the same processes as those described in the first embodiment with reference to FIGS. 2 to 4 are performed, and as shown in FIG. 18, in the area AR1, the substrate SUB is formed from the back surface BS of the substrate SUB. An opening OP1 that reaches the channel layer CH1 is formed. However, in the third embodiment, unlike the first embodiment, when the opening OP1 is formed in the area AR1, the opening reaching the buffer layer BUF2 through the substrate SUB from the back surface BS of the substrate SUB in the area AR2. Part OP2 is formed.

  First, in the area AR1, when forming the opening OP11 that penetrates the substrate SUB from the back surface BS of the substrate SUB and reaches the buffer layer BUF1, the buffer layer penetrates the substrate SUB from the back surface BS of the substrate SUB in the area AR2. An opening OP21 that reaches BUF2 is formed. Next, a resist film RR1 is formed on the back surface BS of the substrate SUB in the area AR1, and a resist film RR2 is formed on the back surface BS of the substrate SUB in the area AR2.

  Thereafter, in the region AR1, when the opening OP13 is formed in the resist film RR1 and the opening OP12 reaching the channel layer CH1 through the buffer layer BUF1 exposed at the bottom of the opening OP13 is formed, in the region AR2, The back surface BS of the substrate SUB is covered with a resist film RR2. Therefore, when the opening OP1 including the opening OP11 formed in the back surface BS of the substrate SUB and the opening OP12 formed in the bottom of the opening OP11 is formed in the area AR1, the opening in the area AR2 is formed. An opening OP2 including the part OP21 is formed.

  Next, a process similar to the process described with reference to FIG. 5 in the first embodiment is performed to form the p-type semiconductor region PS. As a structure after the p-type semiconductor region PS is formed, the opening OP1 reaches the p-type semiconductor region PS from the back surface BS of the substrate SUB through the substrate SUB.

  Next, as shown in FIG. 19, the insulator layer IL1 embedded in the opening OP1 and the insulator layer IL1 embedded in the opening OP2 are formed. Specifically, an insulating film made of aluminum nitride (AlN) is formed on the back surface BS of the substrate SUB including the inside of the opening OP1 and the inside of the opening OP2, for example, by MOCVD, and the opening OP1 and the opening The insulating film outside OP2 is removed. Thereby, the insulator layer IL1 embedded in the opening OP1 is formed, and the insulator layer IL2 embedded in the opening OP2 is formed.

  Next, a process similar to the part of the process described in Embodiment 1 with reference to FIG. 6 is performed to form the metal film BM on the back surface BS of the substrate SUB in the areas AR1 and AR2. Next, the same steps as those described in Embodiment 1 with reference to FIGS. 7 to 9 and FIG. 1 are performed, so that the source electrode SE1, the drain electrode DE1, the source electrode SE2, the drain electrode DE2, the gate electrode GE1, and A gate electrode GE2 is formed. Thereafter, by forming an element isolation region (not shown), as shown in FIG. 17, the transistor TR1 can be manufactured in the region AR1, and the transistor TR2 can be manufactured in the region AR2.

<Main features and effects of the present embodiment>
As shown in FIG. 17, in the semiconductor device of the third embodiment, an insulator layer IL1 is formed instead of the conductor layer CL1, and an insulator layer IL2 is formed. Features similar to those of the semiconductor device of the first embodiment are provided. Therefore, the semiconductor device of the third embodiment has the same effects as those of the semiconductor device of the first embodiment except for the effects that the conductor layer CL1 has.

  On the other hand, in the third embodiment, unlike the first embodiment, the transistor TR1 is made of an insulating film embedded in the opening OP1, and includes an insulator layer IL1 thermally connected to the p-type semiconductor region PS. Have. In the third embodiment in which the insulating layer IL1 is embedded in the opening OP1, the heat generated in the transistor TR1 is transferred to the back surface as compared with the first embodiment in which the conductor layer CL1 is embedded in the opening OP1. The ability to transmit to the BS side is reduced. However, compared to the case where the opening OP1 and the insulator layer IL1 are not formed, the heat generated in the transistor TR1 can be easily transferred to the back surface BS side through the insulator layer IL1. Therefore, the transistor TR1 can be stably operated.

  Further, in the third embodiment, unlike the first embodiment, the transistor TR2 includes an opening OP2 that penetrates the substrate SUB from the back surface BS of the substrate SUB and reaches the buffer layer BUF2, that is, the surface TS of the substrate SUB, and an opening The insulating layer IL2 is made of an insulating film embedded in the part OP2 and is thermally connected to the buffer layer BUF2. In the third embodiment in which the insulating layer IL2 is embedded in the opening OP2, the heat generated in the transistor TR2 is transmitted through the insulating layer IL2 as compared to the case where the opening OP2 and the insulating layer IL2 are not formed. Can be easily transmitted to the back surface BS side. Therefore, the transistor TR2 can be stably operated.

(Embodiment 4)
In the semiconductor device of the second embodiment, the width of the p-type semiconductor region PS is uniform along the thickness direction of the p-type semiconductor region PS. On the other hand, in the semiconductor device of the fourth embodiment, the width of the p-type semiconductor region PS decreases from the lower surface of the p-type semiconductor region PS toward the upper surface of the p-type semiconductor region PS.

<Structure of Semiconductor Device and Operation of Semiconductor Device>
FIG. 20 is a fragmentary cross-sectional view of the semiconductor device of the fourth embodiment.

  As shown in FIG. 20, in the semiconductor device according to the fourth embodiment, portions other than the opening OP1 and the p-type semiconductor region PS are the same as those of the semiconductor device according to the second embodiment.

  In the transistor TR1 of the fourth embodiment, unlike the second embodiment, the width of the p-type semiconductor region PS in the gate length direction of the transistor TR1 is the end surface on the back surface BS side of the p-type semiconductor region PS, that is, the lower surface. It decreases from PSS1 toward the end surface opposite to the back surface BS side, that is, the upper surface PSS2.

  Accordingly, at least one of the end on the drain electrode DE1 side and the end on the source electrode SE1 side of the upper surface PSS2 of the p-type semiconductor region PS has an angle between the side surface and the upper surface of the p-type semiconductor region PS. , It becomes an obtuse angle exceeding 90 degrees. Therefore, the electric field between the drain electrode DE1 side end on the upper surface PSS2 of the p-type semiconductor region PS and the drain electrode DE1, or the end portion on the source electrode SE1 side and the source on the upper surface PSS2 of the p-type semiconductor region PS. Since the electric field between the electrode SE1 can be relaxed, the breakdown voltage of the semiconductor device can be improved.

  Preferably, the side surface SS1 on the drain electrode DE1 side of the opening OP12 is set back from the side surface SS2 on the drain electrode DE1 side of the gate electrode GE1 toward the drain electrode DE1, and the upper surface PSS2 of the p-type semiconductor region PS is In plan view, it is included in the region where the gate electrode GE1 is formed. The p-type semiconductor region PS is formed in a portion of the nitride semiconductor layer CH11 exposed at the bottom of the opening OP12. In plan view, the end BE1 on the drain electrode DE1 side of the lower surface PSS1 of the p-type semiconductor region PS is disposed closer to the drain electrode DE1 than the side surface SS2 of the gate electrode GE1 on the drain electrode DE1 side. ing.

  As a result, at the end TE1 on the drain electrode DE1 side of the upper surface PSS2 of the p-type semiconductor region PS, the angle between the side surface PSS3 of the p-type semiconductor region PS and the upper surface PSS2 becomes an obtuse angle exceeding 90 degrees. . A high voltage is applied between the p-type semiconductor region PS and the drain electrode DE1. Therefore, since the electric field between the drain electrode DE1 and the end TE1 on the drain electrode DE1 side in the upper surface PSS2 of the p-type semiconductor region PS can be reliably relaxed, the breakdown voltage of the semiconductor device can be further improved. it can.

  In the fourth embodiment, when the nitride semiconductor layer CH12 is formed in the middle of the thickness direction of the channel layer CH1, that is, in the configuration of the second embodiment, the width of the p-type semiconductor region PS is from the lower surface. An example of decreasing toward the upper surface will be described. However, when the nitride semiconductor layer CH12 is not formed in the middle of the thickness direction of the channel layer CH1, that is, even in the configuration of the first embodiment, the width of the p-type semiconductor region PS decreases from the lower surface toward the upper surface. Alternatively, the same effect as described above, that is, the effect of improving the breakdown voltage of the semiconductor device can be obtained.

  The operation of the semiconductor device of the fourth embodiment is the same as that of the semiconductor device of the first embodiment.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device according to the fourth embodiment will be described. 21 and 22 are fragmentary cross-sectional views of the semiconductor device of the fourth embodiment during the manufacturing process thereof.

  In the present fourth embodiment, an opening that reaches the channel layer CH1 from the back surface BS of the substrate SUB through the substrate SUB by performing the same steps as those described in the second embodiment with reference to FIGS. OP1 is formed.

  However, in Embodiment 4, after the opening OP11 and the resist film RR1 and the resist film RR2 are sequentially formed, the side surface of the opening OP13 on the drain electrode DE1 side is the drain electrode DE1 of the gate electrode GE1 to be formed. The opening OP13 is formed so as to recede to the drain electrode DE1 side from the side surface SS2 on the side. Thereafter, an opening OP12 that reaches the nitride semiconductor layer CH11 through the buffer layer BUF1 exposed at the bottom of the opening OP13 is formed. As a result, as shown in FIG. 21, the opening OP12 is such that the side surface SS1 of the opening OP12 on the drain electrode DE1 side recedes from the side surface SS2 of the gate electrode GE1 on the drain electrode DE1 side to the drain electrode DE1 side. ,It is formed. In addition, an opening OP1 including an opening OP11 formed in the back surface BS of the substrate SUB and an opening OP12 formed in the bottom of the opening OP11 is formed.

  Next, as shown in FIG. 22, a p-type semiconductor region PS is formed. The step of forming the p-type semiconductor region PS can be performed in the same manner as the step described with reference to FIG. 16 in the second embodiment.

  However, in the fourth embodiment, unlike the second embodiment, for example, ions are implanted obliquely with respect to the back surface BS of the substrate SUB, and then heat treatment is performed. Thereby, the p-type semiconductor region PS can be formed such that the width of the p-type semiconductor region PS in the gate length direction decreases from the lower surface PSS1 to the upper surface PSS2 of the p-type semiconductor region PS. Preferably, the p-type semiconductor region PS can be formed so that the upper surface PSS2 of the p-type semiconductor region PS is included in the region where the gate electrode GE1 is formed in plan view. Then, the p-type semiconductor region PS can be formed in a portion of the nitride semiconductor layer CH11 exposed at the bottom of the opening OP12. Furthermore, in plan view, the end BE1 on the drain electrode DE1 side of the lower surface PSS1 of the p-type semiconductor region PS is disposed closer to the drain electrode DE1 than the side surface SS2 on the drain electrode DE1 side of the gate electrode GE1 to be formed. Thus, the p-type semiconductor region PS can be formed.

  As a structure after the p-type semiconductor region PS is formed, the opening OP1 reaches the p-type semiconductor region PS from the back surface BS of the substrate SUB through the substrate SUB.

  Next, a process similar to that described with reference to FIG. 6 in Embodiment 1 is performed to form the conductor layer CL1 in the region AR1, and a metal is formed on the back surface BS of the substrate SUB in the regions AR1 and AR2. A film BM is formed. Next, the same steps as those described in Embodiment 1 with reference to FIGS. 7 to 9 and FIG. 1 are performed, so that the source electrode SE1, the drain electrode DE1, the source electrode SE2, the drain electrode DE2, the gate electrode GE1, and A gate electrode GE2 is formed. Thereafter, by forming an element isolation region (not shown), as shown in FIG. 20, the transistor TR1 can be manufactured in the region AR1, and the transistor TR2 can be manufactured in the region AR2.

<Main features and effects of the present embodiment>
The semiconductor device according to the fourth embodiment has the same characteristics as those of the semiconductor device according to the first embodiment. Therefore, the semiconductor device of the fourth embodiment has the same effect as that of the semiconductor device of the first embodiment.

  In addition, as shown in FIG. 20, in the semiconductor device of the fourth embodiment, the width of the p-type semiconductor region PS in the gate length direction of the transistor TR1 is p from the lower surface PSS1 of the p-type semiconductor region PS. It decreases toward the upper surface PSS2 of the semiconductor region PS of the mold. Thereby, the electric field between the drain electrode DE1 side end of the upper surface PSS2 of the p-type semiconductor region PS and the end of the upper surface PSS2 of the p-type semiconductor region PS on the source electrode SE1 side Since the electric field between the source electrode SE1 can be relaxed, the breakdown voltage of the semiconductor device can be improved.

(Embodiment 5)
In the semiconductor device of the first embodiment, the portion of the channel layer located on the side of the p-type semiconductor region remains the channel layer. On the other hand, in the semiconductor device of the fifth embodiment, the portion of the channel layer located on the side of the p-type semiconductor region is a compensation region formed by introducing an n-type impurity into the p-type semiconductor region. is there.

<Structure of Semiconductor Device and Operation of Semiconductor Device>
FIG. 23 is a fragmentary cross-sectional view of the semiconductor device of the fifth embodiment.

  As shown in FIG. 23, in the semiconductor device according to the fifth embodiment, portions other than the channel layer CH1, the channel layer CH2, and the substrate SUB are the same as those of the semiconductor device according to the first embodiment.

  On the other hand, the channel layer CH1 of the transistor TR1 of the fifth embodiment is different from the channel layer CH1 of the transistor TR1 of the first embodiment on the nitride semiconductor layer CH31 and the nitride semiconductor layer CH31 formed on the buffer layer BUF1. And the nitride semiconductor layer CH33 formed on the nitride semiconductor layer CH32. Therefore, the electron supply layer ES1 is formed on the nitride semiconductor layer CH33.

  Further, the channel layer CH2 of the transistor TR2 in the fifth embodiment is different from the channel layer CH2 of the transistor TR2 in the first embodiment on the nitride semiconductor layer CH41 and the nitride semiconductor layer CH41 formed on the buffer layer BUF2. And the nitride semiconductor layer CH43 formed on the nitride semiconductor layer CH42. The nitride semiconductor layer CH41 is a nitride semiconductor layer that is the same layer as the nitride semiconductor layer CH31, and the nitride semiconductor layer CH42 is a nitride semiconductor layer that is the same layer as the nitride semiconductor layer CH32, and the nitride semiconductor layer CH43 is the same nitride semiconductor layer as the nitride semiconductor layer CH33. The electron supply layer ES2 is formed on the nitride semiconductor layer CH43.

  Nitride semiconductor layer CH31, nitride semiconductor layer CH33, nitride semiconductor layer CH41, and nitride semiconductor layer CH43 are the same nitride semiconductor layers as the nitride semiconductor layers constituting channel layer CH1 of the first embodiment. can do.

  In the fifth embodiment, the p-type semiconductor region PS is formed in the nitride semiconductor layer CH32 below the gate electrode GE1 in the region AR1. The p-type semiconductor region PS is formed by introducing a p-type impurity made of magnesium (Mg) into the nitride semiconductor layer CH32. As a result, the structure of the gate electrode GE1 on the electron supply layer ES1 and the structure of the gate electrode GE2 on the electron supply layer ES2 can be made the same, thereby reducing variations in characteristics of the transistors TR1 and TR2. Can do.

  On the other hand, in the fifth embodiment, a portion of the nitride semiconductor layer CH32 where the p-type semiconductor region PS is not formed is an intrinsic state or an n-type semiconductor layer. The nitride semiconductor layer CH42 is an intrinsic state or an n-type semiconductor layer.

  As will be described later with reference to FIGS. 24 and 25, the channel CH34 of the channel layer CH1 separated from the lower surface of the electron supply layer ES1, and the layer CH44 of the channel layer CH2 separated from the lower surface of the electron supply layer ES2, A p-type impurity is introduced by ion implantation from the surface TS side of the substrate SUB. Thereafter, an n-type impurity is introduced into the layer CH34 and the layer CH44 from the surface TS side of the substrate SUB by ion implantation in a region other than the region where the p-type semiconductor region PS is formed. Thereby, the p-type semiconductor region PS is formed in the layer CH34. Further, the nitride semiconductor layer CH32 and the nitride semiconductor layer CH42 are respectively formed in the layer CH34 where the p-type semiconductor region PS is not formed and in each of the layers CH44.

  In the fifth embodiment, since it is not necessary to form the opening OP1 (see FIG. 1) in the back surface BS of the substrate SUB, the number of manufacturing steps of the semiconductor device can be reduced.

  Note that the layer CH34 may be a lower layer portion of the channel layer CH1, the layer CH44 may be a lower layer portion of the channel layer CH2, and p-type impurities and n-type impurities may be sequentially introduced into the layers CH34 and CH44. Thus, the nitride semiconductor layer CH31 is not formed in the region AR1, and the channel layer CH1 can be made of the nitride semiconductor layer CH32 and the nitride semiconductor layer CH33. Further, in the region AR2, the nitride semiconductor layer CH41 is not formed, and the channel layer CH2 may be composed of the nitride semiconductor layer CH42 and the nitride semiconductor layer CH43.

  The operation of the semiconductor device of the fifth embodiment is the same as the operation of the semiconductor device of the first embodiment.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device of the fifth embodiment will be described. 24 and 25 are fragmentary cross-sectional views of the semiconductor device of the fifth embodiment during the manufacturing steps thereof.

  First, a process similar to that described with reference to FIG. 2 in Embodiment 1 is performed to form a semiconductor layer structure.

  Next, as shown in FIGS. 24 and 25, a p-type semiconductor region PS, a nitride semiconductor layer CH31, and a nitride semiconductor layer CH32 are formed. For example, the nitride semiconductor layer CH31 and the nitride semiconductor layer CH32 are formed by ion implantation.

  First, as shown in FIG. 24, in the region AR1, a layer CH34 of the channel layer CH1 that is away from the lower surface of the electron supply layer ES1 is opposite to the back surface BS side of the substrate SUB, that is, from the upper side, such as magnesium (Mg). A p-type impurity is implanted. In the region AR2, a p-type impurity such as magnesium is implanted into the layer CH44 of the channel layer CH2 away from the lower surface of the electron supply layer ES2 from the side opposite to the back surface BS side of the substrate SUB, that is, from the upper side. By adjusting the energy of the implanted ions, ions as p-type impurities are implanted in the region AR1 so that the upper surface of the layer CH34 is separated from the lower surface of the electron supply layer ES1 by the distance DS1 in the thickness direction of the substrate SUB. can do. Further, by adjusting the energy of the implanted ions, in the region AR2, ions as p-type impurities are separated from the lower surface of the electron supply layer ES2 by a distance DS1 in the thickness direction of the substrate SUB in the region CH2. Can be injected. The distance DS1 can be the same as in the first embodiment.

  Next, in the region AR1 and the region AR2, after applying a photoresist on the electron supply layer ES1 and the electron supply layer ES2 to form a resist film (not shown), pattern exposure is performed and development is performed. A resist pattern (not shown) is formed so as to cover the region where the p-type semiconductor region PS is to be formed. Then, ion implantation is performed using the formed resist pattern as a mask, and in the region other than the region where the p-type semiconductor region PS is formed, the layer CH34 is formed on the side opposite to the back surface BS side of the substrate SUB, that is, from above. For example, an n-type impurity such as silicon (Si) is implanted. Further, an n-type impurity such as silicon (Si) is implanted into the layer CH44 from the side opposite to the back surface BS side of the substrate SUB, that is, from the upper side.

  Thereafter, the resist pattern (not shown) is removed and, for example, heat treatment is performed at a temperature of about 850 ° C. for about 20 minutes to activate the implanted p-type impurity. Thus, as shown in FIG. 25, in the region AR1, the p-type semiconductor region PS is formed in the layer CH34, and the intrinsic state or the portion of the layer CH34 where the p-type semiconductor region PS is not formed is formed. A nitride semiconductor layer CH32 that is an n-type semiconductor layer is formed. The channel layer CH1 includes a nitride semiconductor layer CH31, a nitride semiconductor layer CH32 formed in the layer CH34, and a nitride semiconductor layer CH33 in order from the bottom.

  Preferably, the p-type semiconductor region PS is formed in a region where the gate electrode GE1 (see FIG. 23) is formed in plan view. Thus, the on-resistance of the transistor TR1 can be reduced while operating the transistor TR1 as a normally-off HEMT.

  On the other hand, as shown in FIG. 25, in the region AR2, a nitride semiconductor layer CH42 which is an intrinsic state or an n-type semiconductor layer is formed in the layer CH44. The channel layer CH2 includes a nitride semiconductor layer CH41, a nitride semiconductor layer CH42 formed in the layer CH44, and a nitride semiconductor layer CH43 in order from the bottom.

  Next, the same steps as those described in Embodiment 1 with reference to FIGS. 7 to 9 and FIG. 1 are performed, so that the source electrode SE1, the drain electrode DE1, the source electrode SE2, the drain electrode DE2, the gate electrode GE1, and A gate electrode GE2 is formed. Preferably, the gate electrode GE1 is formed so that the p-type semiconductor region PS is disposed in the region where the gate electrode GE1 is formed.

  Thereafter, by forming an element isolation region (not shown), as shown in FIG. 23, the transistor TR1 can be manufactured in the region AR1, and the transistor TR2 can be manufactured in the region AR2.

<Main features and effects of the present embodiment>
The semiconductor device of the fifth embodiment has the same characteristics as those of the semiconductor device of the first embodiment except that the conductor layer CL1 (see FIG. 1) is not formed. Therefore, the semiconductor device of the fifth embodiment has the same effects as those of the semiconductor device of the first embodiment, except for the effects that the conductor layer CL1 (see FIG. 1) has.

  On the other hand, in the fifth embodiment, unlike the first embodiment, as shown in FIG. 23, the opening OP1 (see FIG. 1) is not formed in the back surface BS of the substrate SUB. In the fifth embodiment in which the opening OP1 is not formed, the transistor OP is generated in the transistor TR1 as compared with the first embodiment in which the opening OP1 is formed and the conductor layer CL1 is embedded in the formed opening OP1. The ability to transfer the heat to the back BS side is reduced.

  However, in the fifth embodiment, there is no need to perform the step of forming the opening OP1 in the back surface BS of the substrate SUB. Therefore, the number of manufacturing steps of the semiconductor device can be reduced, and the semiconductor device can be easily manufactured.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

2DEG two-dimensional electron gas AR1, AR2 region BE1 end BM metal film BS back surface BUF1, BUF2 buffer layer CH1, CH2 channel layers CH11-CH13, CH21-CH23 nitride semiconductor layers CH31-CH33, CH41-CH43 nitride semiconductor layer CH34 , CH44 layer CL1, conductor layer DE1, DE2 drain electrode DS1, distance ES1, ES2 electron supply layers FR1-FR4 resist film GE1, GE2 gate electrode IL1, IL2 insulator layers MF1-MF4 metal films OP1, OP11, OP12, OP13 openings OP2, OP21 Opening PS Semiconductor region PSS1 Lower surface PSS2 Upper surface PSS3 Side surface RR1, RR2 Resist film SE1, SE2 Source electrode SS1, SS2 Side surface SUB Substrate TE1 End portion TR1, TR2 Transistor TS Surface WT 1, WT2 opening width

Claims (17)

A substrate having a first main surface and a second main surface opposite to the first main surface;
A first nitride semiconductor layer formed on the first main surface of the substrate in a first region on the first main surface side of the substrate;
A second region on the first main surface side of the substrate, formed on the first main surface of the substrate, and a second nitride semiconductor layer in the same layer as the first nitride semiconductor layer;
A third nitride semiconductor layer formed on the first nitride semiconductor layer;
A fourth nitride semiconductor layer formed on the second nitride semiconductor layer and in the same layer as the third nitride semiconductor layer;
A first source electrode and a first drain electrode for the first field-effect transistor, formed on the third nitride semiconductor layer and spaced apart from each other;
A second source electrode and a second drain electrode for a second field-effect transistor, formed on the fourth nitride semiconductor layer and spaced apart from each other;
A first gate electrode formed on the third nitride semiconductor layer sandwiched between the first source electrode and the first drain electrode, apart from either the first source electrode or the first drain electrode. When,
A second gate electrode formed on the fourth nitride semiconductor layer sandwiched between the second source electrode and the second drain electrode, apart from either the second source electrode or the second drain electrode. When,
A fifth nitride semiconductor layer formed in the first nitride semiconductor layer under the first gate electrode away from the lower surface of the third nitride semiconductor layer;
Have
The band gap of the third nitride semiconductor layer is larger than the band gap of the first nitride semiconductor layer,
The band gap of the fourth nitride semiconductor layer is larger than the band gap of the second nitride semiconductor layer,
The semiconductor device, wherein the fifth nitride semiconductor layer is a p-type semiconductor layer. The semiconductor device according to claim 1,
The first nitride semiconductor layer includes:
A sixth nitride semiconductor layer formed on the first main surface of the substrate in the first region;
A seventh nitride semiconductor layer formed on the sixth nitride semiconductor layer;
An eighth nitride semiconductor layer formed on the seventh nitride semiconductor layer;
Including
The second nitride semiconductor layer includes
A ninth nitride semiconductor layer formed on the first main surface of the substrate in the second region and in the same layer as the sixth nitride semiconductor layer;
A tenth nitride semiconductor layer formed on the ninth nitride semiconductor layer and in the same layer as the seventh nitride semiconductor layer;
An eleventh nitride semiconductor layer formed on the tenth nitride semiconductor layer and in the same layer as the eighth nitride semiconductor layer;
Including
The third nitride semiconductor layer is formed on the eighth nitride semiconductor layer;
The fourth nitride semiconductor layer is formed on the eleventh nitride semiconductor layer,
The seventh nitride semiconductor layer and the tenth nitride semiconductor layer include aluminum,
The semiconductor device, wherein the fifth nitride semiconductor layer is formed in the sixth nitride semiconductor layer under the first gate electrode. The semiconductor device according to claim 2,
The fifth nitride semiconductor layer is a semiconductor device formed in the sixth nitride semiconductor layer under the first gate electrode in contact with the lower surface of the seventh nitride semiconductor layer. The semiconductor device according to claim 2,
A first opening that penetrates the substrate from the second main surface of the substrate and reaches the fifth nitride semiconductor layer;
A first conductive layer made of a first conductive film embedded in the first opening and connected to the fifth nitride semiconductor layer exposed in the first opening;
A semiconductor device. The semiconductor device according to claim 2,
The fifth nitride semiconductor layer is a semiconductor device formed in a region where the first gate electrode is formed in a plan view. The semiconductor device according to claim 1,
A second opening reaching the fifth nitride semiconductor layer from the second main surface of the substrate through the substrate;
A first insulating layer made of a first insulating film embedded in the second opening and connected to the fifth nitride semiconductor layer exposed in the second opening;
Have
The semiconductor device according to claim 1, wherein the first insulator layer has a second thermal conductivity larger than a first thermal conductivity of the substrate. The semiconductor device according to claim 6.
A third opening that penetrates the substrate from the second main surface of the substrate and reaches the first main surface of the substrate under the second gate electrode;
A second insulator layer embedded in the third opening;
Have
The semiconductor device, wherein the second insulator layer has a third thermal conductivity larger than the first thermal conductivity of the substrate. The semiconductor device according to claim 6.
The fifth nitride semiconductor layer is a semiconductor device formed in a region where the first gate electrode is formed in a plan view. The semiconductor device according to claim 3.
A width of the fifth nitride semiconductor layer in a gate length direction of the first field effect transistor decreases from a lower surface of the fifth nitride semiconductor layer toward an upper surface of the fifth nitride semiconductor layer; Semiconductor device. The semiconductor device according to claim 9.
A fourth opening reaching the fifth nitride semiconductor layer from the second main surface of the substrate through the substrate;
A second conductive layer made of a second conductive film embedded in the fourth opening and connected to the fifth nitride semiconductor layer exposed in the fourth opening;
Have
The upper surface of the fifth nitride semiconductor layer is included in a region where the first gate electrode is formed in a plan view;
The first end on the first drain electrode side of the lower surface of the fifth nitride semiconductor layer has the first drain more than the first side surface of the first gate electrode on the first drain electrode side in plan view. A semiconductor device disposed on the electrode side. The semiconductor device according to claim 1,
The first nitride semiconductor layer includes:
A twelfth nitride semiconductor layer formed on the first main surface of the substrate in the first region;
A thirteenth nitride semiconductor layer formed on the twelfth nitride semiconductor layer;
Including
The second nitride semiconductor layer includes
A fourteenth nitride semiconductor layer formed on the first main surface of the substrate in the second region and in the same layer as the twelfth nitride semiconductor layer;
A fifteenth nitride semiconductor layer formed on the fourteenth nitride semiconductor layer and in the same layer as the thirteenth nitride semiconductor layer;
Including
The third nitride semiconductor layer is formed on the thirteenth nitride semiconductor layer;
The fourth nitride semiconductor layer is formed on the fifteenth nitride semiconductor layer;
The fifth nitride semiconductor layer is formed in the twelfth nitride semiconductor layer under the first gate electrode;
The first portion of the twelfth nitride semiconductor layer where the fifth nitride semiconductor layer is not formed is an intrinsic state or an n-type semiconductor layer.
The fourteenth nitride semiconductor layer is a semiconductor device which is an intrinsic state or an n-type semiconductor layer. The semiconductor device according to claim 11.
A first p-type impurity is introduced into the fifth nitride semiconductor layer;
The first p-type impurity and the first n-type impurity are introduced into the first portion of the twelfth nitride semiconductor layer,
The semiconductor device, wherein the fourteenth nitride semiconductor layer is doped with the first p-type impurity and the first n-type impurity. The semiconductor device according to claim 11.
The fifth nitride semiconductor layer is a semiconductor device formed in a region where the first gate electrode is formed in a plan view. The semiconductor device according to claim 1,
A fifth opening reaching the fifth nitride semiconductor layer from the second main surface of the substrate through the substrate;
A third conductive layer made of a third conductive film embedded in the fifth opening and connected to the fifth nitride semiconductor layer exposed in the fifth opening;
A semiconductor device. The semiconductor device according to claim 1,
The fifth nitride semiconductor layer is a semiconductor device formed in a region where the first gate electrode is formed in a plan view. The semiconductor device according to claim 1,
The first nitride semiconductor layer is made of indium gallium nitride or gallium nitride,
The semiconductor device, wherein the third nitride semiconductor layer is made of aluminum gallium nitride. The semiconductor device according to claim 16.
A semiconductor device in which magnesium is introduced into the fifth nitride semiconductor layer.

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