JP2015056617A - Light-receiving element, method for manufacturing the same, and optical sensor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a planar light-receiving element or the like capable of controlling diffusion depth with high accuracy in selective diffusion for forming a pn-junction.SOLUTION: A light-receiving element includes: a light-receiving layer; a diffusion concentration distribution adjustment layer; a window layer; a selective diffusion mask pattern; and a pixel electrode. Part of the window layer is removed for every opening of the selective diffusion mask pattern and a window layer through-hole is provided therein. Impurities penetrate into a side wall surface of the window layer through-hole and part of the diffusion concentration distribution adjustment layer forming a bottom surface of the window layer through-hole and are distributed therein. The pixel electrode is positioned on and in contact with the part of the diffusion concentration distribution adjustment layer forming the bottom surface of the window layer through-hole.

Description

  The present invention relates to a light receiving element, a manufacturing method thereof, and an optical sensor device, and more particularly to a light receiving element in the near infrared to infrared region, a manufacturing method thereof, and an optical sensor device.

  Infrared light, including near infrared, corresponds to the absorption spectrum region related to living organisms such as animals and plants, and the environment. Has been done. In particular, the expansion of photosensitivity from the near infrared to the long wavelength side is being promoted. In these light receiving elements, in order to increase sensitivity from the near infrared to the long wavelength side, a type 2 quantum well structure (multi-quantum well structure) is used as a light receiving layer, and impurities are introduced from the window layer by selective diffusion. A planar type light receiving element for forming pixels is employed (Patent Document 1). The method of forming pixels by selective diffusion has an advantage that the dark current is lower than the method of forming pixels by mechanical grooves. In the above-described type 2 multiple quantum well, an electron transition occurs from the valence band of GaAsSb to the conduction band of InGaAs so as to cross the heterointerface at the time of light reception. Therefore, in order to ensure sensitivity, the number of pairs of quantum wells Must be increased. For example, in the case of an InGaAs / GaAsSb multiple quantum well, about 250 pairs of InGaAs / GaAsSb are stacked.

However, the type 2 InGaAs / GaAsSb multiple quantum well is vulnerable to impurities, and only a minimum amount of impurities is allowed in the multiple quantum well during selective diffusion of the planar light receiving element. Therefore, a diffusion concentration distribution adjusting layer is inserted between the window layer provided with the selective diffusion mask pattern and the multiple quantum well structure. In this diffusion concentration distribution adjustment layer, the impurity concentration changes sharply from a high impurity concentration (about 1 to 5E18 cm ⁻³ ) in the window layer to a low concentration (about 1 to 5E16 cm ⁻³ ) impurity reaching the light receiving layer. The area to be included is included. In this diffusion concentration distribution adjustment layer, a material that slows the diffusion rate of impurities is used. For example, in the case of a type 2 InGaAs / GaAsSb multiple quantum well, zinc (Zn), which is a p-type impurity, is selectively diffused, but InGaAs is used for the diffusion concentration distribution adjusting layer. Since InGaAs suppresses the diffusion rate of Zn, it is easy to keep the region where the above-mentioned abrupt change from the high concentration to the low concentration is in the InGaAs layer.

Japanese Patent No. 4662188

  As described above, the impurity introduction for forming the pn junction may be performed from the opening of the selective diffusion mask pattern formed in contact with the window layer to the upper part of the light receiving layer through the window layer and the InGaAs diffusion concentration distribution adjusting layer. Alternatively, it should be kept in front of the light receiving layer. However, the accuracy of the depth of impurities in this selective diffusion is low, and there is a large variation at present. When impurities of low uncontrolled concentration enter the type 2 InGaAs / GaAsSb multiple quantum well, the crystallinity deteriorates and dark current increases, and the sensitivity decreases when the selective diffusion depth is shallow.

  An object of the present invention is to provide a light receiving element, a manufacturing method thereof, and an optical sensor device capable of controlling the diffusion depth with high accuracy in selective diffusion for forming a pn junction for each pixel. To do.

  The light receiving element of the present invention is a planar light receiving element having pixels by selective diffusion of impurities on a semiconductor substrate, the light receiving layer located on the semiconductor substrate, and the diffusion concentration located in contact with the light receiving layer A distribution adjustment layer, a window layer located in contact with the diffusion concentration distribution adjustment layer, a selective diffusion mask pattern located in contact with the window layer and having an opening for each pixel, and a pixel electrode provided in the pixel; The window layer is removed for each opening of the selective diffusion mask pattern to provide a window layer through-hole, and the impurity forms the side wall surface of the window layer through-hole and the bottom surface of the window layer through-hole. The pixel electrode is located in contact with the diffusion concentration distribution adjusting layer forming the bottom surface of the window layer through hole.

  According to the light receiving element of the present invention, in the selective diffusion for forming a pn junction for each pixel, the diffusion depth can be controlled with high accuracy.

It is a figure which shows the light receiving element in embodiment of this invention. It is an enlarged view of the window layer surface vicinity of the window layer through-hole of the light receiving element of FIG. FIG. 2 is a diagram showing a state in which a SiN film is deposited on a semiconductor stacked body in manufacturing the light receiving element of FIG. 1. It is a figure which shows the state which formed the pattern by which the opening part was opened in the SiN film. It is a figure which shows the state after performing the selective diffusion of zinc after providing the window layer through-hole in the opening part. It is a figure which shows the state which formed the pixel electrode in contact with the InGaAs diffused concentration distribution adjustment layer exposed to the bottom part of a window layer through-hole. It is a figure which shows the light receiving element which does not provide the conventional window layer through-hole of the test body group B in an Example.

[Description of Embodiment of Present Invention]
First, the contents of the embodiments of the present invention will be listed and described.
1. Light receiving element:
(1) Structure:
A planar type light receiving element having pixels by selective diffusion of impurities on a semiconductor substrate, a light receiving layer positioned on the semiconductor substrate, a diffusion concentration distribution adjusting layer positioned on and in contact with the light receiving layer, and a diffusion concentration A selective diffusion mask pattern comprising: a window layer located in contact with the distribution adjustment layer; a selective diffusion mask pattern located in contact with the window layer and having an opening for each pixel; and a pixel electrode provided in the pixel. The window layer is removed for each opening portion to provide a window layer through hole, and impurities penetrate into the side wall surface of the window layer through hole and the diffusion concentration distribution adjusting layer forming the bottom surface of the window layer through hole. The pixel electrode is positioned in contact with the diffusion concentration distribution adjusting layer that forms the bottom surface of the window layer through hole. According to this structure, since the window layer in the opening is removed, the impurities directly diffuse into the diffusion concentration distribution adjusting layer exposed in the window layer through hole. For this reason, since the factor of variation in the thickness variation of the window layer is removed, the pn junction can be accurately formed at the intended position.

(2) Window layer through hole:
The diameter of the window layer through-hole is preferably larger than the diameter of the opening of the selective diffusion mask pattern at least on the window layer surface. The impurity introduced by selective diffusion is also introduced into the peripheral portion of the window layer through hole on the upper surface of the window layer, and a pn junction is formed immediately below the mask portion of the selective diffusion mask pattern on the upper surface of the window layer. The end of the pn junction on the upper surface of the window layer is formed substantially concentrically with the window layer through hole on the upper surface. By making the diameter of the window layer through-hole larger than the diameter of the opening of the selective diffusion mask pattern on the surface of the window layer, the end of the pn junction on the surface of the window layer is selected consistently from the beginning to the end of selective diffusion. The mask portion of the diffusion mask pattern is covered and is not exposed to the atmosphere. For this reason, impurities such as high-concentration oxygen do not adhere to the end of the pn junction from the atmosphere, and as a result, the dark current can be kept low.

(3) Selected diffusion mask pattern:
The selective diffusion mask pattern is left as it is after selective diffusion. The reason is that if the selective diffusion mask pattern is removed after selective diffusion, the end of the pn junction on the upper surface of the window layer may be temporarily exposed to the atmosphere or the like. As a result, impurities such as oxygen adhere to the end of the pn junction, resulting in an increase in dark current. For this reason, the selective diffusion mask pattern is left as it is in the product. Usually, another passivation film is laminated on the selective diffusion mask pattern.

(4) Materials for window layer and selective diffusion mask pattern:
The selective diffusion mask pattern is preferably made of silicon nitride (SiN), and the window layer is preferably made of InP or InAlAs. In the combination of materials of the SiN selective diffusion mask portion and the InP window layer or InAlAs window layer, the leakage current is smaller than in the combination of other materials. There is also a great deal of technical data on these materials.

(5) Impurity and diffusion concentration distribution adjusting layer material:
It is preferable that the impurity is zinc (Zn) and the diffusion concentration distribution adjusting layer is formed of InGaAs. Zn has a slow diffusion rate in InGaAs. For this reason, a region in which impurities are sharply decreased from a high concentration to a low concentration by using an InGaAs layer as a diffusion concentration distribution adjusting layer that is located on a multiple quantum well that is vulnerable to impurities and adjusts the impurity concentration. Can be easily formed in the diffusion concentration distribution adjusting layer.

(6) Materials for window layer and diffusion concentration distribution adjusting layer:
The window layer is preferably InP, and the diffusion concentration distribution adjusting layer is preferably InGaAs. In addition to the reasons for the above materials, the ease of forming the window layer through-holes becomes a problem. By using InP as the window layer and InGaAs as the diffusion concentration distribution adjusting layer, an etching solution having a high InP etching rate and a very low InGaAs etching rate is generally available. For example, an aqueous hydrochloric acid solution. By using these, the window layer through-hole can be provided with high accuracy.

(7) Pixel electrode material in the InGaAs diffusion concentration distribution adjusting layer:
The pixel electrode needs to be in ohmic contact with the impurity region for each selectively diffused pixel. The pixel electrode is arranged to apply a reverse bias voltage to the ground electrode with respect to the pn junction and collect carriers generated by light reception.
(I) When InP is used for the window layer and zinc (Zn) is used as an impurity, an AuZn-based alloy was used as the pixel electrode material for realizing ohmic contact. The light receiving element is always used as a set with the readout circuit, but the readout electrodes provided in the readout circuit for collecting information such as the intensity of light reception of the pixels are connected to the pixel electrodes on a one-to-one basis. In order to reliably connect one readout electrode for each pixel electrode, a bump such as indium is interposed between the pixel electrode and the readout electrode. That is, a connection form of one pixel electrode / one bump / one readout electrode is formed. Normally used indium bumps do not have sufficient wettability with AuZn alloys. For this reason, when an indium bump is disposed on an AuZn alloy, a bump base metal pad of TiNiAu alloy is formed. In other words, when the window layer through-hole is not provided, the structure is as follows: Zn region of InP window layer / pixel electrode of AuZn alloy / bump base metal of TiNiAu alloy / electrode of indium bump.
(Ii) When providing the window layer through hole, the pixel electrode is brought into ohmic contact with the Zn region of the InGaAs diffusion concentration distribution adjusting layer. In this case, a TiPtAu alloy can be used as the material of the pixel electrode. Since the TiPtAu alloy has good wettability with the indium bump, it is not necessary to form a bump base metal. For this reason, the man-hour for formation of a bump base metal, the material of a bump base metal, etc. can be omitted. As a result, the runtime can be greatly shortened and the deposition cost can be reduced.
(Iii) In the case of (ii), a step of providing a window layer through-hole is added, but since the step of forming the AnZn-based electrode is eliminated, the overall process can be shortened. Furthermore, consumption of Au can be suppressed, and it can also contribute to cost reduction of material costs.

(8) Light receiving layer:
The light receiving layer may be a single-phase material such as InGaAs or GaInNAs most widely. The disadvantage that the accuracy of the position of the pn junction cannot be obtained due to the variation in the thickness of the window layer is the same even in a single-phase light-receiving layer such as InGaAs. Therefore, by providing the diffusion concentration adjusting layer and the window layer through hole, the position of the pn junction in the InGaAs light receiving layer can be arranged with high accuracy. However, the above-described structure including the diffusion concentration adjusting layer, the window layer through-hole, and the like exerts its effectiveness greatly when the light receiving layer has a type 2 multiple quantum well structure. The multiple quantum well structure is fragile to impurities, and when a high concentration of impurities is introduced, the crystallinity deteriorates and dark current increases. For this reason, by providing the structure of the light receiving element according to the present embodiment of the present invention, the introduction of impurities into the multiple quantum well is minimized, and the pn junction is accurately placed at a predetermined position where the sensitivity is not lowered. It becomes possible to arrange. In the type 2 multiple quantum well structure, the energy band of one compound semiconductor forming a pair is set slightly higher than the other, and an electron transition occurs from the higher valence band to the lower conduction band. Let As a result, the energy change associated with the transition is reduced, and light on the longer wavelength side can be received. Therefore, it is useful for a light receiving element in the near infrared to infrared region. Since the electron transition at the time of light reception crosses the interface of the pair, in order to ensure sufficient sensitivity, the number of quantum well layers must be increased, and the number of pairs is usually several tens to several hundreds.

(9) Type 2 multiple quantum well structure:
Any of (InGaAs / GaAsSb, InGaAs / GaInAs, and InAs / GaSb) is preferably used as the type 2 multiple quantum well structure. As a result, it is possible to obtain a light-receiving element having a sensitivity in the near-infrared to infrared range, which can reduce the dark current only by cooling with a Peltier element, and can be reduced in size and weight.

(10) Optical sensor device:
By combining one of the light receiving elements and the readout circuit, a near-infrared to infrared photosensor device can be obtained. If the object to be imaged (analyzed) contains a plurality of substances, and the plurality of substances have different absorption spectrum bands, the target is obtained by banding the light before entering the sensor chip, etc. The distribution and concentration of each substance in the object can be detected. A spectral imaging imaging system incorporating the above-described optical sensor device makes it possible to obtain such an image for each band.

2. Manufacturing method of light receiving element:
(1) Implementation of selective diffusion from the window layer through hole:
According to the method for manufacturing a light receiving element of the present invention, a planar light receiving element including pixels by selective diffusion of impurities is manufactured on a semiconductor substrate. In this manufacturing method, a light-receiving layer, a diffusion concentration distribution adjusting layer, and a window layer positioned on a semiconductor substrate are sequentially epitaxially grown, and a selective diffusion mask having an opening for each pixel in contact with the window layer A step of forming a pattern, a step of providing a window layer through hole in the window layer for each opening of the selective diffusion mask pattern, and introducing an impurity gas into the window layer through hole from the opening of the selective diffusion mask pattern And a step of diffusing impurities on the side wall surface and the bottom surface of the window layer through-hole, and in the step of providing the window layer through-hole, at least the diameter of the window layer through-hole on the surface of the window layer is selected. The area of the selectively diffused impurity on the surface is covered with the mask portion of the selective diffusion mask pattern on the surface of the window layer through-hole before starting the selective diffusion. To. As a result, since there is no window layer in the depth direction toward the light receiving layer, the inaccuracy of the position of the pn junction due to the thickness variation of the window layer is eliminated, and the pn junction can be arranged with high accuracy. Become. Further, the end of the pn junction on the surface of the window layer becomes a product without being exposed to the atmosphere or the like from the start to the end of selective diffusion. For this reason, impurities such as high-concentration oxygen do not adhere to the end of the pn junction, and the dark current can be kept low.

(2) Formation of through hole in window layer by etching:
In the step of providing the window layer through-hole, it is preferable to use an etchant having a large etching rate of the window layer at a ratio of 10 to 1 or more between the window layer and the diffusion concentration distribution adjusting layer. Thereby, the window layer through-hole can be provided with high accuracy. For example, in the case of an InP window layer / InGaAs diffusion concentration distribution adjusting layer, by using a 35% hydrochloric acid aqueous solution as an etching solution, the InP window layer is etched and InGaAs is hardly etched. As a result, a window layer through-hole having a uniform shape can be accurately provided for each opening of the selective diffusion mask pattern, which also realizes accurate selective diffusion, and thus accurate placement of pn junction positions. can do.

[Details of the embodiment of the present invention]
Next, specific examples of the light receiving element and the like according to the embodiment of the present invention will be described with reference to the drawings. In addition, this invention is not limited to these illustrations, is shown by the claim, and intends that all the changes within the meaning and range equivalent to the claim are included.

FIG. 1 is a diagram showing a light receiving element 50 according to an embodiment of the present invention. The light receiving element 50 shown in FIG. 1 has the following III-V semiconductor epitaxial layer structure.
(Fe doped semi-insulating InP substrate 1 / n-type buffer layer 2 / type 2 InGaAs / GaAsSb multiple quantum well structure light-receiving layer 3 / InGaAs diffusion concentration distribution adjusting layer 4 / InP window layer 5)
A plurality of pixels P are arranged. A p-type region 6 containing Zn is formed in each pixel P, and a pn junction 15 is formed at the tip of the p-type region 6. The pixel P is separated from the adjacent pixel by a region where Zn, which is a p-type impurity, is not selectively diffused, so that independence can be obtained. An anti-reflection film (ARF) 35 is attached to the incident surface on the back surface of the InP substrate 1.

  The pixel P includes a region where Zn raw material introduced from the opening 36h of the selective diffusion mask pattern 36 and the window layer through hole 5h is diffused into the InGaAs diffusion concentration distribution adjusting layer 4 and the InP window layer 5 which are solid phases. It is out. FIG. 2 is a partially enlarged view of the window layer through hole 5h. The InGaAs diffusion concentration distribution adjusting layer 4 is located at the bottom of the window layer through hole 5h, and the InP window layer 5 is located at the side. Since the window layer through-hole 5h is provided, it is not necessary to consider the thickness of the InP window layer 5 to control the position of the pn junction 15 during selective diffusion. For this reason, the position of the pn junction 15 can be accurately arranged. A reverse bias voltage is applied to the pn junction 15 between the pixel electrode 11 that is the p-side electrode and the common ground electrode 12 that is the n-side electrode.

  The diameter of the window layer through hole 5 h on the surface (upper surface) of the InP window layer 5 is larger than the diameter of the opening 36 h of the selective diffusion mask pattern 36. In the selective diffusion of Zn, the Zn source gas is diffused and introduced into the solid phase from the opening 36h and the window layer through hole 5h. On the upper surface of the window layer 5, an end 15e of the diffused Zn region appears. However, if the diameter of the window layer through-hole 5h is larger than the diameter of the opening 36h of the selective diffusion mask pattern 36 on the upper surface of the window layer 5, it is not exposed to the atmosphere of the processing chamber. The end 15e of the pn junction is an important part for suppressing dark current, and when oxygen or the like adheres to the end 15e at a high concentration, the dark current increases. In the present embodiment, the position of the pn junction 15 is accurately arranged at the intended position, and the end 15e of the pn junction is never exposed to the atmosphere of the processing chamber from the start to the end of selective diffusion. Since the selective diffusion mask pattern 36 is left as it is in the product as a part of the protective film without being removed, the end 15e of the pn junction is not exposed to a gas containing a large amount of impurities such as oxygen in the atmosphere or the processing chamber atmosphere until the end. .

  In FIG. 1, the pixel electrode 11 or the p-side electrode is in ohmic contact with the InGaAs diffusion concentration distribution adjusting layer 4. The material of the pixel electrode 11 contains a TiPtAu alloy as a main component. As described above, since the TiPtAu-based alloy has good wettability with the indium bump 29, it is not necessary to provide a bump base metal. When the window layer through hole 5h is not provided, because of the ohmic contact with the InP window layer 5, an AuZn-based alloy is used as the material of the pixel electrode, and the AuZn-based alloy has insufficient wettability with the indium bump. A bump base pad of TiNiAu alloy was necessary (see FIG. 7). In this embodiment, the bump base pad can be omitted, and a great manufacturing cost reduction such as a shortening of the manufacturing process can be obtained.

  Next, a manufacturing method will be described. Any epitaxial growth method may be used. For example, MBE (Molecular Beam Epitaxy) method, MOVPE (Metal Organic Vapor Phase Epitaxy) method and the like can be used. First, an n-type buffer layer 2 is grown on an InP substrate 1 using Si or the like as a dopant, and then a type 2 InGaAs / GaAsSb multiple quantum well is grown. The thickness is preferably about 3 nm to 6 nm for each layer, and the number of pairs is preferably about 100 to 400 pairs. Next, the InGaAs diffusion concentration distribution adjusting layer 4 and then the InP window layer 5 are epitaxially grown. Etching with buffered hydrofluoric acid (BHF) and etching with sulfuric acid are performed on the InP window layer 5 as pretreatment.

  Next, in order to form a selective diffusion mask pattern 36 in contact with the InP window layer 5 after the pretreatment, a silicon nitride (SiN) film 36a is deposited as shown in FIG. The SiN film 36a is preferably formed to a thickness of about 100 nm by a plasma CVD (Chemical Vapor Deposition) method or the like. The film 36a may not be a SiN film, but leakage current can be suppressed by combining the InP window layer 5 and the SiN film. Next, a resist film (not shown) is applied on the SiN film 36a, and a resist pattern is formed by photolithography. Thereafter, the selective diffusion mask pattern 36 is formed by etching the SiN film 36a with buffered hydrofluoric acid. Here, an opening 36h for selective diffusion is provided as shown in FIG.

  Thereafter, the InP window layer 5 is etched using a highly selective etching solution such as the 35% hydrochloric acid aqueous solution described above to provide the window layer through hole 5h in the opening 36h. The 35% hydrochloric acid aqueous solution is a highly selective etching solution that etches InP but hardly etches InGaAs. At this time, as shown in FIG. 2 and the like, the diameter of the window layer through hole 5h is set to be larger than the diameter of the opening 36h on the surface (upper surface) of the InP window layer 5. The reason is as described above.

  Next, as shown in FIG. 5, Zn source gas is introduced into the opening 36 h and the window layer through hole 5 h, and Zn is diffused into the solid phase to form the pn junction 15. Since the diameter of the window layer through hole 5h is larger than the diameter of the opening 36h on the surface (upper surface) of the window layer 5, the end 15e of the pn junction is exposed to the atmosphere of the processing chamber from the beginning to the end of the selective diffusion. Never happen. For this reason, a light receiving element with a low dark current can be obtained.

  Thereafter, a resist pattern (not shown) of the p-side electrode or the pixel electrode 11 is formed by photolithography, and a Ti / Pt / Au alloy-based electrode is formed by vacuum deposition as shown in FIG. Remove. As described above, since the TiPtAu alloy has good wettability with the indium bump, it is not necessary to form a bump base metal. For this reason, the man-hour for formation of a bump base metal, the material of a bump base metal, etc. can be omitted. As a result, the runtime can be greatly shortened and the deposition cost can be reduced. This reduction in electrode manufacturing cost is a secondary effect in the present embodiment.

  In order to verify the effect of the present embodiment, a test specimen A shown in FIG. 1 was prototyped and compared with the conventional test specimen group B (five specimens). As shown in FIG. 7, in the conventional specimen group B, Zn is diffused and introduced directly into the surface of the InP window layer 105 from the opening 136h of the selective diffusion mask pattern 36, so that the p-type region 106 and the tip thereof are introduced. A pn junction 115 is formed. Other stacked structures are (Fe-doped semi-insulating InP substrate 101 / n-type buffer layer 102 / type 2 InGaAs / GaAsSb multiple quantum well structure light-receiving layer 103 / InGaAs diffusion concentration distribution adjusting layer 104 / InP window layer 105) It is the same as the specimen A in FIG. Similarly, the AR film 135 is attached to the back surface of the InP substrate 101. The difference is that the specimen A in FIG. 1 has no window layer through-holes in the specimen group B as compared with the window layer through-holes 5h. Further, in FIG. 7, compared to the case where the bump base metal pad 127 is formed between the pixel electrode 111 and the indium bump 129, the test body A of the present invention example of FIG. .

For these specimen group B and specimen A, the position of the pn junction was specified by measuring the Zn concentration. As an analysis method, a SIMS analysis method (Secondary Ion Mass Spectroscopy) was used. The results are shown in Table 1. Table 1 also shows the results of variations in the thickness of the InP window layer for the specimen group B.

  It was found that the variation in the position of the pn junction of the test specimen A can be within the range of ± 20 nm, which is almost in agreement with the prediction based on the diffusion temperature and the like. This specimen A corresponds to rank A capable of stable production. This is because a window layer through-hole is provided at the selective diffusion introduction portion of Zn to eliminate the influence of the thickness variation of the InP window layer. On the other hand, in the specimen group B, since the variation in the thickness of the InP window layer already reached an average of 70 nm, it greatly deviated from the prediction based on the diffusion temperature and the like. That is, the accuracy of the position of the pn junction of the specimen group B corresponds to the rank C at a level where stable production is not achieved.

  According to the light receiving element of the present invention, the position of the pn junction in selective diffusion can be accurately arranged. In addition, when InGaAs is used for the diffusion concentration adjusting layer, a TiPtAu alloy can be used for the pixel electrode. Therefore, it is not necessary to provide a bump base metal for the indium bump, and it becomes possible to realize a reduction in the number of deposition steps, a reduction in the process, and the like.

  1 InP substrate, 2 buffer layer, 3 type 2 (InGaAs / GaAsSb) multiple quantum well structure, 4 InGaAs diffusion concentration distribution adjusting layer, 5 InP window layer, 5h window layer through-hole, 6 p-type region, 11 p-side electrode ( Pixel electrode), 12 ground electrode (n-side electrode), 15 pn junction, end of 15e pn junction, 29 bump, 35 antireflection (AR) film, 36 selective diffusion mask pattern, 36a SiN film, 36h opening, 50 light reception Element, P pixel.

Claims (10)

A planar type light receiving element having pixels by selective diffusion of impurities on a semiconductor substrate,
A light receiving layer located on the semiconductor substrate;
A diffusion concentration distribution adjusting layer located on and in contact with the light receiving layer;
A window layer located on and in contact with the diffusion concentration distribution adjusting layer;
A selective diffusion mask pattern located on and in contact with the window layer and having an opening for each pixel;
A pixel electrode provided on the pixel,
The window layer is removed for each opening of the selective diffusion mask pattern to provide a window layer through-hole,
The impurities are permeated and distributed in the side wall surface of the window layer through-hole and the diffusion concentration distribution adjusting layer forming the bottom surface of the window layer through-hole,
The light receiving element, wherein the pixel electrode is positioned on and in contact with the diffusion concentration distribution adjusting layer forming a bottom surface of the window layer through hole.   2. The light receiving element according to claim 1, wherein a diameter of the window layer through-hole is larger than a diameter of an opening of the selective diffusion mask pattern at least on a window layer surface.   The light receiving element according to claim 1, wherein the selective diffusion mask pattern is formed of silicon nitride (SiN), and the window layer is formed of InP or InAlAs.   4. The light receiving element according to claim 1, wherein the impurity is zinc (Zn), and the diffusion concentration distribution adjusting layer is formed of InGaAs. 5.   The light receiving element according to claim 4, wherein the pixel electrode contains a TiPtAu alloy as a main component.   The light receiving element according to claim 1, wherein the light receiving layer has a type 2 multiple quantum well structure.   The light receiving element according to any one of claims 1 to 6, wherein the light receiving layer has a multiple quantum well structure of any one of (InGaAs / GaAsSb, InGaAs / GaInAs, and InAs / GaSb).   An optical sensor device comprising the light receiving element according to claim 1 and a readout circuit. A method of manufacturing a planar light receiving element comprising a pixel by selective diffusion of impurities on a semiconductor substrate,
A step of sequentially epitaxially growing a light receiving layer, a diffusion concentration distribution adjusting layer, and a window layer located on the semiconductor substrate;
Forming a selective diffusion mask pattern having an opening for each pixel in contact with the window layer;
Providing a window layer through hole in the window layer for each opening of the selective diffusion mask pattern;
Introducing the impurity gas into the window layer through-hole from the opening of the selective diffusion mask pattern, and diffusing the impurity into the side wall surface and the bottom surface of the window layer through-hole,
In the step of providing the window layer through hole, at least the diameter of the window layer through hole on the surface of the window layer is made larger than the diameter of the opening of the selective diffusion mask pattern, and the selectively diffused impurities on the surface are formed. A method for manufacturing a light receiving element, wherein the region is a region covered with a mask portion of the selective diffusion mask pattern before the selective diffusion is started.   10. The light receiving element according to claim 9, wherein in the step of providing the window layer through hole, an etching solution is used in which the etching rate of the window layer and the diffusion concentration distribution adjusting layer is 10: 1 and the etching rate of the window layer is high. Manufacturing method.

Images