JP2015053443A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing capacitance between wirings of an SRAM.SOLUTION: A semiconductor device 1 includes an SRAM 10 having a plurality of memory cells MC where wirings AL1 and AL2 constituting storage nodes N1 and N2 are provided in an M0 layer lower than an M1 layer on which other wirings are provided. Thereby, the semiconductor device 1 can reduce capacitance between wirings provided on the wiring layer higher than the M1 layer. As a result, the semiconductor device 1 can, for instance, reduce a circuit scale of the SRAM 10, and the like.

Description

  The present invention relates to a semiconductor device, for example, a semiconductor device suitable for reducing the capacitance between wirings.

  Patent Document 1 discloses a configuration of a memory cell provided in a CMOS type SRAM.

  This memory cell is composed of six MOS transistors. Specifically, this memory cell includes PMOS load transistors TP1 and TP2, NMOS drive transistors TN1 and TN2, and NMOS access transistors TN3 and TN4. The PMOS inverter transistor TN1 and the NMOS driving transistor TN1 constitute a first inverter. The PMOS inverter transistor TN2 and the NMOS driving transistor TN2 constitute a second inverter. The output of the first inverter is supplied to the input of the second inverter, and the output of the second inverter is supplied to the input of the first inverter. As a result, data can be stored. The NMOS access transistor TN3 is provided between the output of the first inverter and one BL of the pair of bit lines, and is controlled to be turned on / off according to the potential of the word line WL. The NMOS access transistor TN4 is provided between the output of the second inverter and the other / BL of the pair of but line pairs, and is controlled to be turned on / off according to the potential of the word line WL. Thereby, data stored in the memory cell is read or data is written to the memory cell.

  In addition, Patent Document 2 discloses a semiconductor device in which SRAM and DRAM are mixedly mounted.

JP 2003-115551 A JP 2008-117864 A

  The related art has a problem that the wiring interval is narrowed as the SRAM is miniaturized and highly integrated, and the capacitance between the wirings is increased. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, in the semiconductor device, the first wiring configuring the storage node is provided in the first wiring layer lower than the second wiring layer provided with the second wiring different from the first wiring. SRAM including a plurality of memory cells.

  According to the embodiment, it is possible to provide a semiconductor device capable of reducing the interwiring capacitance of the SRAM.

3 is a circuit diagram showing a configuration example of a memory cell provided in an SRAM mounted on a semiconductor device according to a first embodiment; FIG. 4 is a plan view showing a layout configuration example from a diffusion layer to an M1 layer of a memory cell provided in an SRAM mounted on the semiconductor device according to the first embodiment; FIG. 4 is a plan view showing a layout configuration example of an M1 layer and vias of a memory cell provided in an SRAM mounted on a semiconductor device according to a first embodiment; FIG. 4 is a plan view showing a layout configuration example of an M0 layer of memory cells provided in the SRAM mounted on the semiconductor device according to the first embodiment; FIG. 3 is a cross-sectional view schematically showing a layout configuration example from a diffusion layer to an M1 layer of a memory cell provided in an SRAM mounted on the semiconductor device according to the first embodiment; FIG. 3 is a plan view showing a layout configuration example from a diffusion layer to an M1 layer of a memory cell according to the concept before reaching the first embodiment. FIG. 4 is a plan view showing a layout configuration example of an M1 layer and a via of a memory cell according to a concept before reaching the first embodiment. FIG. 3 is a cross-sectional view schematically showing a layout configuration from a diffusion layer to an M1 layer of a memory cell according to a concept before reaching the first embodiment. FIG. FIG. 6 is a cross-sectional view schematically showing a layout configuration of a semiconductor device according to a second exemplary embodiment. It is a circuit diagram which shows the structural example of the memory cell provided in DRAM.

  Hereinafter, embodiments will be described with reference to the drawings. Since the drawings are simplified, the technical scope of the embodiments should not be narrowly interpreted based on the description of the drawings. Moreover, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including operation steps and the like) are not necessarily essential except when clearly indicated and clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

<Embodiment 1>
FIG. 1 is a circuit diagram showing a configuration example of the memory cell MC provided in the SRAM 10 mounted on the semiconductor device 1 according to the first embodiment. In the SRAM 10, a plurality of memory cells MC are arranged in a matrix, and data stored in the memory cell MC specified by the address is read or data is written to the memory cell MC specified by the address. Or

  The memory cell MC is composed of six MOS transistors. Specifically, the memory cell MC includes a PMOS load transistor (first PMOS transistor) MP1, a PMOS load transistor (second PMOS transistor) MP2, an NMOS drive transistor (first NMOS transistor) MN1, and an NMOS drive transistor (second NMOS transistor). ) MN2, an NMOS access transistor (third NMOS transistor) MN3, and an NMOS access transistor (fourth NMOS transistor) MN4.

  The PMOS inverter MP1 and the NMOS drive transistor MN1 constitute a first inverter. The PMOS inverter transistor MP2 and the NMOS driving transistor MN2 constitute a second inverter. The output of the first inverter is supplied to the input of the second inverter, and the output of the second inverter is supplied to the input of the first inverter. That is, the first and second inverters are connected in a loop. As a result, data can be stored.

  More specifically, in the PMOS load transistor MP1, the source is connected to a power supply line to which the power supply voltage VDD is supplied (hereinafter referred to as the power supply line VDD), the drain is connected to the storage node N1, and the gate is connected to the storage node N2. It is connected to the. In the NMOS drive transistor MN1, the source is connected to a ground line to which the ground voltage VSS is supplied (hereinafter referred to as the ground line VSS), the drain is connected to the storage node N1, and the gate is connected to the storage node N2. In the PMOS load transistor MP2, the source is connected to the power supply line VDD, the drain is connected to the storage node N2, and the gate is connected to the storage node N1. In the NMOS drive transistor MN2, the source is connected to the ground line VSS, the drain is connected to the storage node N2, and the gate is connected to the storage node N1.

  The NMOS access transistor MN3 is provided between the storage node N1 and one BL of the bit line pair BL, / BL, and on / off is controlled according to the potential of the word line WL. The NMOS access transistor MN4 is provided between the storage node N2 and the other of the bit line pairs BL and / BL, and is turned on / off according to the potential of the word line WL. Thereby, data stored in the memory cell MC is read or data is written in the memory cell MC.

  FIG. 2 is a plan view showing a layout configuration example from the diffusion layer to the M1 layer of the memory cell MC shown in FIG. Note that the memory cell MC is formed by a region surrounded by an alternate long and short dash line in the drawing. For example, the plurality of memory cells MC having such a shape are arranged in a matrix so as to have a mirror inversion relationship with the adjacent memory cells MC.

  As shown in FIG. 2, a polysilicon wiring PL1 is provided on the n-type diffusion layer DN1. As a result, an NMOS driving transistor MN1 is formed which uses the polysilicon wiring PL1 as a gate and two n-type diffusion regions sandwiching the polysilicon wiring PL1 in the n-type diffusion layer DN1 as a drain and a source (upper left of the drawing). .

  A polysilicon wiring PL3 is provided on the n-type diffusion layer DN1. As a result, an NMOS access transistor MN3 is formed using the polysilicon wiring PL3 as a gate and two n-type diffusion regions sandwiching the polysilicon wiring PL3 in the n-type diffusion layer DN1 as a drain and a source (lower left in the drawing). . The drains of the NMOS drive transistor MN1 and the NMOS access transistor MN3 are formed by a common n-type diffusion region (first diffusion region).

  A polysilicon wiring PL2 is provided on the n-type diffusion layer DN2. As a result, an NMOS driving transistor MN2 is formed having the polysilicon wiring PL2 as a gate and the two n-type diffusion regions sandwiching the polysilicon wiring PL2 in the n-type diffusion layer DN2 as drains and sources (lower right of the drawing). ).

  A polysilicon wiring PL4 is provided on the n-type diffusion layer DN2. As a result, an NMOS access transistor MN4 is formed using the polysilicon wiring PL4 as a gate and the two n-type diffusion regions sandwiching the polysilicon wiring PL4 in the n-type diffusion layer DN2 as drains and sources (upper right in the drawing). . The drains of the NMOS drive transistor MN2 and the NMOS access transistor MN4 are formed by a common n-type diffusion region (third diffusion region).

  In addition, a polysilicon wiring PL1 is provided to extend on the p-type diffusion layer DP1. As a result, a PMOS load transistor MP1 is formed having the polysilicon wiring PL1 as a gate and two p-type diffusion regions sandwiching the polysilicon wiring PL1 in the p-type diffusion layer DP1 as drains and sources (on the center of the drawing). ). Here, the gates of the PMOS load transistor MP1 and the NMOS drive transistor MN1 are connected via a polysilicon wiring PL1.

  In addition, a polysilicon wiring PL2 extends over the p-type diffusion layer DP2. As a result, a PMOS load transistor MP2 is formed in which the polysilicon wiring PL2 is a gate and two p-type diffusion regions sandwiching the polysilicon wiring PL2 in the p-type diffusion layer DP2 are drains and sources (lower center of the drawing). ). Here, the gates of the PMOS load transistor MP2 and the NMOS drive transistor MN2 are connected via a polysilicon wiring PL2.

  Further, a contact (first contact) C1 is provided on an n-type diffusion region (first diffusion region) in which the drains of the NMOS drive transistor MN1 and the NMOS access transistor MN3 are formed in common. A contact (second contact) C2 is provided on the p-type diffusion region (second diffusion region) that forms the drain of the PMOS load transistor MP1. The contacts C1 and C2 are connected via a wiring (first wiring) AL1 provided in the M0 layer (first wiring layer). That is, the drains of the PMOS load transistor MP1 and the NMOS drive transistor MN1 are connected via the wiring AL1 provided in the M0 layer. Note that the wiring AL1 corresponds to the storage node N1. The M0 layer is lower than the wiring layer (second wiring layer) of the M1 layer or higher provided with the word line WL, the bit lines BL, / BL, the power supply line VDD, the ground line VSS, etc. (second wiring). It is a wiring layer.

  The contact C2 is also connected to the polysilicon wiring PL2. That is, the drains of the PMOS load transistor MP1 and the NMOS drive transistor MN1 and the gates of the PMOS load transistor MP2 and the NMOS drive transistor MN2 are connected via the contact C2.

  A contact (third contact) C3 is provided on the n-type diffusion region (third diffusion region) that commonly forms the drains of the NMOS drive transistor MN2 and the NMOS access transistor MN4. A contact (fourth contact) C4 is provided on the p-type diffusion region (fourth diffusion region) that forms the drain of the PMOS load transistor MP2. The contacts C3 and C4 are connected via a wiring (first wiring) AL2 provided in the M0 layer (first wiring layer). That is, the drains of the PMOS load transistor MP2 and the NMOS drive transistor MN2 are connected via the wiring AL2 provided in the M0 layer. Note that the wiring AL2 corresponds to the storage node N2.

  The contact C4 is also connected to the polysilicon wiring PL1. That is, the respective drains of the PMOS load transistor MP2 and the NMOS drive transistor MN2 and the respective gates of the PMOS load transistor MP1 and the NMOS drive transistor MN1 are connected via the contact C4.

  In addition, the source of the NMOS drive transistor MN1 is connected to a ground line VSS (or its relay wiring) provided in the M1 layer (a wiring layer higher than the M0 layer) via a contact C5. Similarly, the source of the NMOS drive transistor MN2 is connected to the ground line VSS (or its relay wiring) provided in the M1 layer via the contact C6. The source of the NMOS access transistor MN3 is connected to a bit line BL (or its relay wiring) provided in the M1 layer via a contact C7. The gate of the NMOS access transistor MN3 is connected to the word line WL (or its relay wiring) provided in the M1 layer via the contact C8. Similarly, the source of the NMOS access transistor MN4 is connected to the bit line / BL (or its relay wiring) provided in the M1 layer via the contact C9. The gate of the NMOS access transistor MN4 is connected to the word line WL (or its relay wiring) provided in the M1 layer via the contact C10. The source of the PMOS load transistor MP1 is connected to a power supply line VDD (or its relay wiring) provided in the M1 layer via a contact C11. The source of the PMOS load transistor MP2 is connected to a power supply line VDD (or its relay wiring) provided in the M1 layer via a contact C12.

  FIG. 3A is a plan view showing a layout configuration example of the M1 layer and vias of the memory cell MC shown in FIG. FIG. 3B is a plan view showing a layout configuration example of the M0 layer of the memory cell MC shown in FIG.

  As shown in FIG. 3A, in the M1 layer, a word line WL, bit lines BL and / BL, a power supply line VDD, a ground line VSS, or a relay wiring thereof is provided. These wirings are connected to wirings provided in a higher wiring layer through any of the vias V5 to V12. In contrast, as shown in FIG. 3B, only the wirings AL1 and AL2 are provided in the M0 layer.

  As shown in FIGS. 3A and 3B, the wirings AL1 and AL2 are provided in the M0 layer lower than the M1 layer, not in the wiring layer higher than the M1 layer, so that the wiring provided in the wiring layer higher than the M1 layer is congested. The degree is relaxed. That is, the interval between the wirings provided in the wiring layers equal to or higher than the M1 layer is widened. As a result, the inter-wiring capacitance of the wiring layer of the M1 layer or higher is reduced. As a result, for example, malfunction of the SRAM 10 due to the influence of the capacitance between wirings can be prevented. In addition, since the wiring interval can be reduced within a range satisfying the design rule, the circuit scale of the memory cell MC can be reduced. That is, miniaturization and high integration of the SRAM 10 can be realized.

  FIG. 4 is a cross-sectional view schematically showing a layout configuration from the diffusion layer to the M1 layer of the memory cell MC shown in FIG. Here, FIG. 4 corresponds to the A-A ′ sectional view of FIG. 2.

  As shown in FIG. 4, an NMOS driving transistor MN1 is formed by two n-type diffusion regions and a polysilicon wiring. An NMOS access transistor MN3 is formed by the two n-type diffusion regions and the polysilicon wiring. The n-type diffusion region (first diffusion region) that commonly forms the drains of the NMOS drive transistor MN1 and the NMOS access transistor MN3 is connected to the M0 via the contact C1 extending from the n-type diffusion region to the M0 layer. It is connected to the wiring AL1 provided in the layer. On the other hand, the n-type diffusion region forming the source of the NMOS drive transistor MN1 is connected to a ground line VSS provided in the M1 layer via a contact C5 extending from the n-type diffusion region to the M1 layer. The n-type diffusion region forming the source of the NMOS access transistor MN3 is connected to the bit line BL provided in the M1 layer via a contact C7 extending from the n-type diffusion region to the M1 layer.

  As can be seen from FIG. 4, by providing the wirings AL1 and AL2 in the M0 layer, the degree of congestion of the wiring in the M1 layer is reduced (that is, the interval between the wirings provided in the M1 layer is widened). ing). Thereby, the capacitance between the wirings of the M1 layer is reduced.

  Further, the wiring AL1 provided in the M0 layer is not connected to the wiring provided in the wiring layer higher than the M1 layer. That is, no contact extending to the M1 layer is formed on the wiring AL1. As a result, the number of contacts extending from the diffusion layer to the M1 layer is reduced and the contact interval is increased, so that the capacitance between the contacts is reduced.

(Memory cell MCx according to the concept before reaching the first embodiment)
Next, for comparison with the memory cell MC, the memory cell MCx examined by the inventors before reaching the present embodiment will be described. FIG. 5 is a plan view showing a layout configuration example from the diffusion layer to the M1 layer of the memory cell MCx.

  Note that the power supply line VDDx, ground line VSSx, word line WLx, bit lines BLx, / BLx, transistors MN1x to MN4x, MP1x, MP2x, n-type diffusion layers DN1x, DN2x, p-type diffusion layers DP1x, DP2x, memory cell MCx The wirings AL1x and AL2x, the polysilicon wirings PL1x to PL4x, the vias V5x to V12x, and the contacts C1x to C12x are respectively the power supply line VDD, the ground line VSS, the word line WL, the bit lines BL and / BL, and the transistor MN1 in the memory cell MC. MN4, MP1, MP2, n-type diffusion layers DN1, DN2, p-type diffusion layers DP1, DP2, wirings AL1, AL2, polysilicon wirings PL1-PL4, vias V5-V12, and contacts C1-C12.

  Here, in the memory cell MCx, unlike the memory cell MC, wirings AL1x and AL2x corresponding to the wirings AL1 and AL2 are provided in the M1 layer instead of the M0 layer. Since the other configuration of the memory cell MCx is the same as that of the memory cell MC, description thereof is omitted.

  FIG. 6 is a plan view showing a layout configuration example of the M1 layer and vias of the memory cell MCx. As shown in FIG. 6, in the M1 layer, a word line WLx, bit lines BLx, / BLx, a power supply line VDDx, a ground line VSSx or a relay wiring thereof, and wirings AL1x, AL2x are provided. Wirings other than the wirings AL1x and AL2x are connected to wirings provided in a higher wiring layer via any of the vias V5x to V12x.

  As shown in FIG. 6, in the memory cell MCx, wirings AL1x and AL2x are provided in the M1 layer together with other wirings. Therefore, the wiring provided in the M1 layer is congested. That is, the interval between the wirings provided in the M1 layer is narrowed. As a result, the capacitance between the wirings of the M1 layer is increased. Further, since it is necessary to widen the wiring interval so as to satisfy the design rule, the circuit scale of the memory cell MCx increases.

  FIG. 7 is a cross-sectional view schematically showing a layout configuration from the diffusion layer to the M1 layer of the memory cell MCx. Here, FIG. 7 corresponds to the B-B ′ cross-sectional view of FIG. 5.

  As shown in FIG. 7, the n-type diffusion region in which the drains of the NMOS drive transistor MN1x and the NMOS access transistor MN3x are commonly formed has an M1 layer via a contact C1x extending from the n-type diffusion region to the M1 layer. Are connected to the wiring AL1x. The other layout configuration of the memory cell MCx shown in FIG. 7 is the same as that of the memory cell MC shown in FIG.

  As shown in FIG. 7, as a result of the wiring AL1x being provided in the M1 layer, the number of contacts extending from the diffusion layer to the M1 layer is increased and the contact interval is reduced, so that the capacitance between the contacts is increased.

  On the other hand, in the memory cell MC according to the present embodiment, the wirings AL1 and AL2 are provided in the M0 layer lower than the M1 layer. As a result, the degree of congestion of the wirings provided in the wiring layers above the M1 layer is alleviated, so that the inter-wiring capacitance of the wiring layers above the M1 layer is reduced. Further, since the number of contacts extending from the diffusion layer to the wiring layer of M1 layer or more is reduced, the inter-contact capacitance is also reduced.

  As described above, in the memory cell MC provided in the SRAM 10 mounted on the semiconductor device 1 according to the present embodiment, the wiring layers AL1 and AL2 constituting the storage nodes N1 and N2 are provided with other wirings. It is provided in a lower wiring layer (M0 layer) than the wiring layer (wiring layer of M1 layer or more). As a result, the wiring congestion of the wiring layers of the M1 layer and higher is alleviated, and the inter-wiring capacitance of the wiring layers of the M1 layer and higher is reduced. Further, since the number of contacts extending from the diffusion layer to the wiring layer of M1 layer or more is reduced, the inter-contact capacitance is also reduced. As a result, the semiconductor device 1 according to the present embodiment can suppress, for example, malfunction of the SRAM 10 or realize miniaturization and high integration of the SRAM 10.

  As shown in FIG. 2, the wirings AL1 and AL2 provided in the M0 layer and the other wirings provided in the M1 layer are alternately arranged in the vertical direction of the drawing. Therefore, if considered simply, the interval between the wirings provided in the M1 layer is twice that of the wirings AL1 (or AL2) as compared to the case where all the wirings including the wirings AL1 and AL2 are provided in the M1 layer. Wide by width. Accordingly, it can be said that the inter-wiring capacitance of the memory cell MC is very small.

  Further, the ease of current flow is not required for the wirings AL1 and AL2 constituting the storage nodes N1 and N2. Therefore, for example, the wirings AL1 and AL2 wired in the M0 layer have a higher specific resistance than other wirings provided in the wiring layers higher than the M1 layer. As a specific example, the wirings AL1 and AL2 wired in the M0 layer are formed of a metal containing tungsten, and the other wirings provided in the wiring layers higher than the M1 layer are formed of copper. Thereby, the wirings AL1 and AL2 can be miniaturized, for example, the wiring height of the wirings AL1 and AL2 can be reduced.

<Embodiment 2>
FIG. 8 is a cross-sectional view schematically showing a layout configuration example of the semiconductor device 2 according to the second embodiment. The semiconductor device 2 further includes a DRAM 20 in addition to the SRAM 10 as compared with the semiconductor device 1. That is, the semiconductor device 2 is equipped with an eDRAM (Embedded DRAM). In FIG. 8, the memory cell MC of the SRAM 10 and the memory cell DMC of the DRAM 20 are shown. In the example of FIG. 8, a stack type capacitive element is used as the capacitive element used in the DRAM 20, and a COB (Capacitor Over Bitline) structure is adopted.

  FIG. 9 is a circuit diagram showing a configuration example of the memory cell DMC provided in the DRAM 20. The memory cell DMC shown in FIG. 9 includes a MOS transistor Tr1 and a capacitive element Cp. The MOS transistor Tr1 is provided between the DRAM bit line DBL and one electrode of the capacitive element Cp, and on / off is controlled according to the potential of the DRAM word line DWL. The other electrode of the capacitive element Cp is connected to a reference voltage terminal (for example, the ground line VSS).

  Returning to FIG. 8, in the DRAM 20, as in the case of the SRAM 10, the MOS transistor Tr <b> 1 is formed by the two diffusion regions and the polysilicon wiring. Further, the capacitor element Cp and the DRAM bit line DBL have an intermediate layer (interlayer insulating layer) between the base on which the diffusion layer and the like are formed and the M1 layer provided with wiring such as the SRAM word line WL and the like. Is provided. More specifically, the DRAM bit line DBL is provided in the M0 layer. The capacitive element Cp is provided in the intermediate layer 30 between the M1 layer and the M0 layer. The capacitive element Cp is composed of a lower electrode 21, an upper electrode 23, and a dielectric film 22 provided therebetween.

  A diffusion region forming one of the source and drain (hereinafter referred to as drain) of the MOS transistor Tr1 is connected to a DRAM bit line DBL provided in the M0 layer via a contact C21. A diffusion region that forms the other of the source and drain (hereinafter referred to as source) of the MOS transistor Tr1 is connected to the lower electrode 21 of the capacitive element Cp provided in the intermediate layer 30 via a contact C22. The upper electrode 23 of the capacitive element Cp is connected to a wiring (for example, a ground line VSS) provided in the M1 layer via a contact C23. In this way, the memory cell DMC of the DRAM 20 is formed.

  Here, the DRAM bit line DBL and the wirings AL1 and AL2 of the SRAM 10 are both provided in the M0 layer. Specifically, the DRAM bit line DBL and the wirings AL1 and AL2 are formed in the M0 layer by using the same material (for example, a metal containing tungsten) in the same manufacturing process. By using the wiring layer of the DRAM bit line DBL as the wiring layer of the wirings AL1 and AL2, it is not necessary to separately prepare a wiring layer for the wirings AL1 and AL2, so that an increase in design man-hours is suppressed. Further, an increase in circuit scale is suppressed.

  As described above, the semiconductor device 2 according to the present embodiment can achieve the same effects as the semiconductor device 1 according to the first embodiment. In addition, the semiconductor device 2 according to the present embodiment uses the wiring layer of the DRAM bit line DBL as the wiring layer of the wirings AL1 and AL2, so that it is not necessary to separately form a wiring layer for the wirings AL1 and AL2. The increase in design man-hours can be suppressed, and the increase in circuit scale can be suppressed.

  In the semiconductor device 2 according to the present embodiment, the number of contacts formed through the intermediate layer 30 can be reduced, so that the capacitance between the contacts can be effectively reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor device 10 SRAM
20 DRAM
21 Lower electrode 22 Dielectric film 23 Upper electrode 30 Intermediate layer AL1, AL2 Wiring BL, / BL Bit line C1-C12 contact C21-C23 contact Cp Capacitance element DBL DRAM bit line DWL DRAM word line DN1, DN2 n-type diffusion Layer DP1, DP2 p-type diffusion layer MC memory cell MN1 NMOS drive transistor MN2 NMOS drive transistor MN3 NMOS access transistor MN4 NMOS access transistor MP1 PMOS load transistor MP2 PMOS load transistor PL1 to PL4 polysilicon wiring Tr1 MOS transistors V5 to V12 via WL word line

Claims (11)

  An SRAM having a plurality of memory cells in which a first wiring constituting a storage node is provided in a first wiring layer lower than a second wiring layer provided with a second wiring different from the first wiring; A semiconductor device provided. Each of the plurality of memory cells includes
A first inverter having a first PMOS transistor and a first NMOS transistor;
A second inverter having a second PMOS transistor and a second NMOS transistor, inverting the output of the first inverter and outputting it to the input of the first inverter;
A third NMOS transistor provided between one of the pair of bit lines and the output of the first inverter, the on / off of which is controlled according to the potential of the word line;
2. The semiconductor device according to claim 1, further comprising: a fourth NMOS transistor provided between the other of the bit line pair and the output of the second inverter and controlled to be turned on / off according to the potential of the word line. .   A wiring connecting the drains of the first PMOS transistor and the first NMOS transistor and a wiring connecting the drains of the second PMOS transistor and the second NMOS transistor serve as the first wiring. The semiconductor device according to claim 2, provided in the layer. A first contact provided on a first diffusion region that commonly forms a drain of each of the first and third NMOS transistors;
A second contact provided on a second diffusion region forming a drain of the first PMOS transistor;
A third contact provided on a third diffusion region commonly forming the drains of the second and fourth NMOS transistors;
A fourth contact provided on a fourth diffusion region forming the drain of the second PMOS transistor,
The wiring that connects the first and second contacts and the wiring that connects the third and fourth contacts are provided as the first wiring in the first wiring layer. A semiconductor device according to 1.   The semiconductor device according to claim 1, wherein the first wiring has a higher specific resistance than the second wiring.   The semiconductor device according to claim 1, wherein the second wiring includes at least one of a word line, a bit line, a ground line, and a power supply line.   The semiconductor device according to claim 1, further comprising a DRAM.   The semiconductor device according to claim 7, wherein the first wiring is provided in the first wiring layer together with the bit line for the DRAM.   The semiconductor device according to claim 7, wherein the first wiring is formed of a material that is the same material as that of the DRAM bit line.   The semiconductor device according to claim 7, wherein the first wiring is formed in the same manufacturing process as the bit line for the DRAM.   The semiconductor device according to claim 7, wherein the capacitor element for DRAM is formed in an interlayer insulating layer between the first wiring and the second wiring.

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