JP2015053424A - Solar cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solar cell capable of suppressing the occurrence of a hot spot phenomenon.SOLUTION: The solar cell includes: a semiconductor substrate 10 which has a first main surface 10b and a second main surface 10a and is of one conductivity type; a region R1 of the one conductivity type which has a semiconductor layer structure 12 of the one conductivity type provided on the first main surface 10b; and a region R2 of the other conductivity type which has a semiconductor layer structure 13 of the other conductivity type provided on the first main surface 10b. The semiconductor layer structure 12 of the one conductivity type is formed in a partial region in the region R2 of the other conductivity type. In the partial region, an overlapping region R4 where the semiconductor layer structure 13 of the other conductivity type is provided on the semiconductor layer structure 12 of the one conductivity type is formed.

Description

  The present invention relates to a back junction solar cell.

  As a solar cell with high power generation efficiency, a so-called back junction type solar cell in which a p-type region and an n-type region are formed on the back side of the solar cell has been proposed (for example, Patent Document 1). In this back junction solar cell, it is not necessary to provide an electrode on the light receiving surface side, so that the light receiving efficiency can be increased.

  The solar cell module is configured by connecting a plurality of solar cells. In such a solar cell module, if some of the solar cells cannot receive sunlight due to entering the shadow of an obstacle, the solar cells It is known that a total generated voltage of other solar cells is applied as a reverse voltage, and a phenomenon in which some of the solar cells generate heat (hot spot phenomenon) occurs (for example, Patent Document 2).

JP 2012-33666 A JP 2013-33832 A

  An object of the present invention is to provide a solar cell capable of suppressing the occurrence of a hot spot phenomenon.

  The solar cell of the present invention comprises a semiconductor substrate having a first main surface and a second main surface and having one conductivity type, and a one conductivity type semiconductor layer structure provided on the first main surface. A region of one conductivity type and a region of another conductivity type having a semiconductor layer structure of another conductivity type provided on the first main surface, and a part of the region of the other conductivity type has the region A semiconductor layer structure of one conductivity type is formed, and an overlapping region in which the semiconductor layer structure of another conductivity type is provided on the semiconductor layer structure of one conductivity type is formed in the partial region.

  According to the present invention, occurrence of a hot spot phenomenon can be suppressed.

It is a typical top view of the solar cell in a 1st embodiment. It is typical sectional drawing which expands and shows a part of cross section which follows the II-II line | wire shown in FIG. It is a schematic plan view which shows the overlap area | region in 1st Embodiment. It is typical sectional drawing for demonstrating the manufacturing process of the solar cell in 1st Embodiment. It is typical sectional drawing for demonstrating the manufacturing process of the solar cell in 1st Embodiment. It is typical sectional drawing for demonstrating the manufacturing process of the solar cell in 1st Embodiment. It is typical sectional drawing for demonstrating the manufacturing process of the solar cell in 1st Embodiment. It is typical sectional drawing for demonstrating the manufacturing process of the solar cell in 1st Embodiment. It is typical sectional drawing for demonstrating the manufacturing process of the solar cell in 1st Embodiment. It is typical sectional drawing for demonstrating the manufacturing process of the solar cell in 1st Embodiment. It is typical sectional drawing for demonstrating the manufacturing process of the solar cell in 1st Embodiment.

  Hereinafter, preferred embodiments will be described. However, the following embodiments are merely examples, and the present invention is not limited to the following embodiments. Moreover, in each drawing, the member which has the substantially the same function may be referred with the same code | symbol.

  FIG. 1 is a schematic plan view of the solar cell in the first embodiment. FIG. 2 is a schematic cross-sectional view showing a part of a cross section taken along line II-II shown in FIG. 1 in an enlarged manner.

  The solar cell 1 is a back junction solar cell. FIG. 1 shows the back surface of the solar cell 1. As shown in FIG. 2, the solar cell 1 includes a semiconductor substrate 10. The semiconductor substrate 10 has a light receiving surface 10a as a second main surface and a back surface 10b as a first main surface. The semiconductor substrate 10 generates carriers by receiving the light 11 on the light receiving surface 10a. Here, the carriers are holes and electrons that are generated when light is absorbed by the semiconductor substrate 10.

  The semiconductor substrate 10 is composed of a crystalline semiconductor substrate having n-type or p-type conductivity. Specific examples of the crystalline semiconductor substrate include a crystalline silicon substrate such as a single crystal silicon substrate and a polycrystalline silicon substrate. Note that the semiconductor substrate can be formed of a semiconductor substrate other than a crystalline semiconductor substrate. For example, a compound semiconductor substrate made of GaAs, InP, or the like can be used in place of the semiconductor substrate 10. Hereinafter, in the present embodiment, an example in which the semiconductor substrate 10 is formed of an n-type crystalline silicon substrate that is one conductivity type will be described.

  On the light receiving surface 10 a of the semiconductor substrate 10, an i-type amorphous semiconductor layer 17 i made of an intrinsic amorphous semiconductor (hereinafter, the intrinsic semiconductor is referred to as “i-type semiconductor”) is formed. In the present embodiment, the i-type amorphous semiconductor layer 17i is specifically formed of i-type amorphous silicon containing hydrogen. The thickness of the i-type amorphous semiconductor layer 17i is not particularly limited as long as the thickness does not substantially contribute to power generation. The thickness of the i-type amorphous semiconductor layer 17i can be, for example, about several nm to 25 nm.

  Note that in the present invention, the “amorphous semiconductor” includes a microcrystalline semiconductor. A microcrystalline semiconductor refers to a semiconductor in which a semiconductor crystal is precipitated in an amorphous semiconductor.

  An n-type amorphous semiconductor layer 17n having the same conductivity type as that of the semiconductor substrate 10 is formed on the i-type amorphous semiconductor layer 17i. The n-type amorphous semiconductor layer 17n is an amorphous semiconductor layer to which an n-type dopant is added and has an n-type conductivity type. Specifically, in the present embodiment, the n-type amorphous semiconductor layer 17n is made of n-type amorphous silicon containing hydrogen. The thickness of the n-type amorphous semiconductor layer 17n is not particularly limited. The thickness of the n-type amorphous semiconductor layer 17n can be, for example, about 2 nm to 50 nm.

  On the n-type amorphous semiconductor layer 17n, an insulating layer 16 having both a function as an antireflection film and a function as a protective film is formed. The insulating layer 16 can be formed of, for example, silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the insulating layer 16 can be appropriately set according to the antireflection characteristics of the antireflection film to be applied. The thickness of the insulating layer 16 can be about 80 nm to 1000 m, for example.

  The stacked structure of the i-type amorphous semiconductor layer 17i, the n-type amorphous semiconductor layer 17n, and the insulating layer 16 has a function as a passivation layer of the semiconductor substrate 10 and a function as an antireflection film.

  On the back surface 10 b of the semiconductor substrate 10, an n-type semiconductor multilayer structure 12 that is one conductivity type and a p-type semiconductor multilayer structure 13 that is another conductivity type are formed. The n-type region R1 which is a region of one conductivity type has an n-type semiconductor stacked structure 12, and the p-type region R2 which is a region of other conductivity type has a p-type semiconductor stacked structure 13. doing. As shown in FIG. 1, each of the n-type region R1 and the p-type region R2 is formed in a comb shape. The n-type region R1 and the p-type region R2 are formed so as to be interleaved with each other. Therefore, on the back surface 10b, the n-type regions R1 and the p-type regions R2 are alternately arranged along the direction x perpendicular to the intersecting width direction y. An insulating region R3 is formed between the n-type region R1 and the p-type region R2.

  The n-type semiconductor multilayer structure 12 is formed on the i-type amorphous semiconductor layer 12i as the first intrinsic semiconductor layer and the i-type amorphous semiconductor layer 12i formed on the back surface 10b. The n-type amorphous semiconductor layer 12n is a laminated body. Like the i-type amorphous semiconductor layer 17i, the i-type amorphous semiconductor layer 12i is made of amorphous silicon containing hydrogen. The thickness of the i-type amorphous semiconductor layer 12i is not particularly limited as long as the thickness does not substantially contribute to power generation. The thickness of the i-type amorphous semiconductor layer 12i can be, for example, about several nm to 25 nm.

  The n-type amorphous semiconductor layer 12n is doped with an n-type dopant, like the n-type amorphous semiconductor layer 17n, and has an n-type conductivity type, like the semiconductor substrate 10. Specifically, in this embodiment, the n-type amorphous semiconductor layer 12n is made of n-type amorphous silicon containing hydrogen. The thickness of the n-type amorphous semiconductor layer 12n is not particularly limited. The thickness of the n-type amorphous semiconductor layer 12n can be, for example, about 2 nm to 50 nm.

  Insulating layers 18 are formed on both ends of the n-type semiconductor multilayer structure 12 except for the central portion in the direction x. A central portion in the direction x of the n-type semiconductor multilayer structure 12 is exposed from the insulating layer 18. The material of the insulating layer 18 is not particularly limited. The insulating layer 18 can be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like. Especially, it is preferable that the insulating layer 18 is formed of silicon nitride. The insulating layer 18 preferably contains hydrogen.

  The p-type semiconductor multilayer structure 13 is formed on the part of the back surface 10 b exposed from the n-type semiconductor multilayer structure 12 and the end of the insulating layer 18. The p-type semiconductor multilayer structure 13 is formed on the i-type amorphous semiconductor layer 13i as the second intrinsic semiconductor layer and the i-type amorphous semiconductor layer 13i formed on the back surface 10b. And a p-type amorphous semiconductor layer 13p.

  The i-type amorphous semiconductor layer 13i is made of amorphous silicon containing hydrogen. The thickness of the i-type amorphous semiconductor layer 13i is not particularly limited as long as the thickness does not substantially contribute to power generation. The thickness of the i-type amorphous semiconductor layer 13i can be, for example, about several nm to 25 nm.

  The p-type amorphous semiconductor layer 13p is an amorphous semiconductor layer having a p-type conductivity type to which a p-type dopant is added. Specifically, in the present embodiment, the p-type amorphous semiconductor layer 13p is made of p-type amorphous silicon containing hydrogen. The thickness of the p-type amorphous semiconductor layer 13p is not particularly limited. The thickness of the p-type amorphous semiconductor layer 13p can be, for example, about 2 nm to 50 nm.

  In the present embodiment, an i-type amorphous semiconductor layer 13i having a thickness that does not substantially contribute to power generation is provided between the crystalline semiconductor substrate 10 and the p-type amorphous semiconductor layer 13p. As in this embodiment, by providing the i-type amorphous semiconductor layer 13i between the n-type semiconductor substrate 10 and the p-type amorphous semiconductor layer 13p, the semiconductor substrate 10 and the p-type semiconductor stacked structure 13 are provided. It is possible to suppress the recombination of the minority carriers at the bonding interface. As a result, the photoelectric conversion efficiency can be improved.

  Note that each of the amorphous semiconductor layers 17i, 17n, 12, and 13 preferably contains hydrogen in order to improve passivation properties.

  On the n-type amorphous semiconductor layer 12n, an n-side electrode 14 as an electrode on one conductivity type side for collecting electrons is formed. On the other hand, on the p-type amorphous semiconductor layer 13p, a p-side electrode 15 as an electrode on the other conductivity type side that collects holes is formed. The p-side electrode 15 and the n-side electrode 14 are electrically insulated by interposing the insulating region R3.

  As described above, in the present embodiment, each of the n-type region R1 and the p-type region R2 is formed in a comb shape. For this reason, as shown in FIG. 1, each of the n-side electrode 14 and the p-side electrode 15 includes bus bars 14A and 15A and a plurality of fingers 14B and 15B. However, each of the n-side electrode 14 and the p-side electrode 15 is composed of only a plurality of fingers, and may be a bus bar-less electrode having no bus bar.

  Each of the n-side electrode 14 and the p-side electrode 15 is not particularly limited as long as it can collect carriers. In the present embodiment, each of the n-side electrode 14 and the p-side electrode 15 is formed by a stacked body of first to fourth conductive layers 19a to 19d.

  The first conductive layer 19a can be formed by, for example, TCO (Transparent Conductive Oxide) such as ITO (Indium Tin Oxide). Specifically, in the present embodiment, the first conductive layer 19a is made of ITO. The thickness of the first conductive layer 19a can be, for example, about 50 to 100 nm. The first conductive layer 19a can be formed by a thin film forming method such as a sputtering method or a CVD (Chemical Vapor Deposition) method.

  The second to fourth conductive layers 19b to 19d can be formed of a metal such as Cu or an alloy, for example. Specifically, in the present embodiment, each of the second and third conductive layers 19b and 19c is formed of Cu. The fourth conductive layer 19d is made of Sn. The thicknesses of the second to fourth conductive layers 19b to 19d can be about 50 nm to 1000 m, about 10 μm to 20 μm, and about 1 μm to 5 μm, respectively.

  In the present embodiment, of the first to fourth conductive layers 19a to 19d, the second conductive layer 19b constitutes a seed layer. Here, the “seed layer” refers to a layer that is a starting point for plating growth. The seed layer is generally made of a metal or an alloy. The second conductive layer 19b as a seed layer can be formed by a thin film forming method such as a sputtering method, a vapor deposition method, a printing method, or an ink jet method other than the plating method.

  In the present embodiment, the third and fourth conductive layers 19c and 19d are constituted by plating films.

<Overlapping region R4>
As shown in FIG. 2, the n-type semiconductor multilayer structure 12 is also formed in a partial region in the p-type region R2. In the present embodiment, an n-type semiconductor multilayer structure 12 is formed at a substantially central portion in the x direction of the p-type region R2. For this reason, in the region where the n-type semiconductor multilayer structure 12 is formed in the p-type region R2, the overlapping region R4 in which the p-type semiconductor multilayer structure 13 is provided on the n-type semiconductor multilayer structure 12 is provided. Is formed. In the overlapping region R4, the n-type semiconductor multilayer structure 12 and the p-type semiconductor multilayer structure 13 are stacked in this order on the n-type semiconductor substrate 10. Therefore, a semiconductor stacked structure of p / i / n / i / n is formed.

  This semiconductor stacked structure of p / i / n / i / n has nonlinearity in IV characteristics, and when a reverse bias voltage of about several volts is applied, it breaks down and becomes a current leakage path. For this reason, when a reverse bias voltage that causes a hot spot phenomenon is applied to the solar cell 1, the semiconductor stacked structure of p / i / n / i / n serves as a current leakage path and suppresses the occurrence of the hot spot phenomenon. be able to.

  In the present embodiment, a semiconductor stacked structure of p / i / n / i / n is shown as the semiconductor stacked structure formed in the overlapping region R4. However, the semiconductor multilayer structure formed in the overlapping region R4 is not limited to this. For example, an n / i / p / i / p semiconductor multilayer structure formed by laminating a p-type semiconductor multilayer structure and an n-type semiconductor multilayer structure in this order on a p-type semiconductor substrate. It may be. The semiconductor stacked structure of n / i / p / i / p also has non-linearity in IV characteristics, and when a reverse bias voltage of about several volts is applied, it breaks down and becomes a current leak path. Therefore, when a reverse bias voltage that causes a hot spot phenomenon is applied to the solar cell, it becomes a current leakage path, and the occurrence of the hot spot phenomenon can be suppressed.

  In the present embodiment, as a one-conductivity-type semiconductor layer structure, a first intrinsic semiconductor layer (i-type amorphous semiconductor layer 12i) provided on the first major surface 10b and a first intrinsic semiconductor layer (i An example of a one-conductivity-type semiconductor multilayer structure (n-type semiconductor multilayer structure 12) having a one-conductivity-type semiconductor layer (n-type amorphous semiconductor layer 12n) provided on the p-type amorphous semiconductor layer 12i) As shown. In addition, as another semiconductor layer structure of conductivity type, a second intrinsic semiconductor layer (i-type amorphous semiconductor layer 13i) provided on the first main surface 10b and a second intrinsic semiconductor layer (i-type amorphous semiconductor). An example of an other conductivity type semiconductor multilayer structure (p type semiconductor multilayer structure 13) having another conductivity type semiconductor layer (p type amorphous semiconductor layer 13p) provided on the porous semiconductor layer 13i) is shown. Yes.

  However, the “one-conductivity-type semiconductor layer structure” and the “other-conductivity-type semiconductor layer structure” in the present invention are not limited to these. For example, the one-conductivity-type semiconductor layer structure may be composed of only one-conductivity-type semiconductor layer, and the other-conductivity-type semiconductor layer structure is composed of only another-conductivity-type semiconductor layer. It may be. Therefore, in the one-conductivity-type semiconductor layer structure and the other-conductivity-type semiconductor layer structure, the first intrinsic semiconductor layer and the second intrinsic semiconductor layer are not necessarily provided. Therefore, in this case, the overlapping region may have a p / n / n semiconductor laminated structure or an n / p / p semiconductor laminated structure.

  FIG. 3 is a schematic plan view showing an overlapping region in the first embodiment. As shown in FIG. 3, in this embodiment, the n-type region R1 that is a region of one conductivity type and the p-type region R2 that is a region of another conductivity type extend in the first direction (y direction). It is formed as follows. The insulating region R3 is also formed to extend in the first direction (y direction). As shown in FIG. 1, the p-side electrode 15 includes a bus bar 15A and a plurality of fingers 15B. A p-type region R2 shown in FIG. 3 is a portion corresponding to the finger 15B. In the portion of the p-type region R2 corresponding to the bus bar 15A shown in FIG. 1, the overlapping region R4 is formed to extend in a direction (x direction) intersecting the first direction (y direction).

  In the present embodiment, as shown in FIG. 3, the overlapping region R4 is formed at a substantially central portion in the x direction of the p-type region R2. However, the region for forming the overlapping region R4 is not limited to this, and any region can be used as long as the n-type semiconductor multilayer structure 12 can be in contact with the semiconductor substrate 10 in the p-type region R2. It may be an area.

  The length of the overlapping region R4 (for example, the y direction in FIG. 3) is preferably in the range of 50 mm to 120 mm, and the width in the direction perpendicular to the length direction of the overlapping region R4 (for example, the x direction in FIG. 3) is It is preferably in the range of 3 μm to 30 μm.

<Method for manufacturing solar cell>
Hereinafter, with reference to FIGS. 4-11, the manufacturing method of the solar cell 1 of this embodiment is demonstrated.

  First, the semiconductor substrate 10 is prepared. Next, as shown in FIG. 4, an i-type amorphous semiconductor layer 17i and an n-type amorphous semiconductor layer 17n are formed on the light receiving surface 10a of the semiconductor substrate 10, and an i-type is formed on the back surface 10b. An amorphous semiconductor layer 21 and an n-type amorphous semiconductor layer 22 are formed. The formation method of i-type amorphous semiconductor layers 17i and 21 and n-type amorphous semiconductor layers 17n and 22 is not particularly limited. Each of the i-type amorphous semiconductor layers 17i and 21 and the n-type amorphous semiconductor layers 17n and 22 can be formed by, for example, a CVD (Chemical Vapor Deposition) method such as a plasma CVD method.

  Next, as shown in FIG. 5, the insulating layer 16 is formed on the n-type amorphous semiconductor layer 17 n and the insulating layer 23 is formed on the n-type amorphous semiconductor layer 22. In addition, the formation method of the insulating layers 16 and 23 is not specifically limited. The insulating layers 16 and 23 can be formed by, for example, a thin film forming method such as a sputtering method or a CVD method.

  Next, as shown in FIG. 6, the insulating layer 23 is etched to remove a part of the insulating layer 23. Specifically, a portion of the insulating layer 23 located on a region where the p-type semiconductor layer is bonded to the semiconductor substrate 10 in a later step is removed. Therefore, in the region corresponding to the p-type region R2, the insulating layer 23 is etched so as to leave a portion of the region where the n-type semiconductor multilayer structure 12 is provided. The insulating layer 23 can be etched using an acidic etching solution such as an HF aqueous solution, for example, when the insulating layer 23 is made of silicon oxide, silicon nitride, or silicon oxynitride.

  Next, as shown in FIG. 7, using the patterned insulating layer 23 as a mask, the i-type amorphous semiconductor layer 21 and the n-type amorphous semiconductor layer 22 are etched using an alkaline etchant. As a result, portions of the i-type amorphous semiconductor layer 21 and the n-type amorphous semiconductor layer 22 other than the portions covered by the insulating layer 23 are removed. As a result, a portion of the back surface 10b where the insulating layer 23 is not located above is exposed, and the i-type amorphous semiconductor layer 12i and the n-type amorphous semiconductor layer 12n (see FIG. 2).

  Here, as described above, in this embodiment, the insulating layer 23 is made of silicon oxide, silicon nitride, or silicon oxynitride. For this reason, although the etching rate of the insulating layer 23 with an acidic etching solution is high, the etching rate of the insulating layer 23 with an alkaline etching solution is low. On the other hand, the semiconductor layers 21 and 22 are made of amorphous silicon. For this reason, the semiconductor layers 21 and 22 have a low etching rate with an acidic etching solution and a high etching rate with an alkaline etching solution. Therefore, although the insulating layer 23 is etched by the acidic etching solution used in the step shown in FIG. 6, the semiconductor layers 21 and 22 are not substantially etched. On the other hand, the semiconductor layers 21 and 22 are etched by the alkaline etching solution used in the step shown in FIG. 7, but the insulating layer 23 is not substantially etched. Therefore, in the step shown in FIG. 6 and the step shown in FIG. 7, the insulating layer 23 or the semiconductor layers 21 and 22 can be selectively etched.

  Next, as shown in FIG. 8, only the insulating layer 23 in the region corresponding to the p-type region R2 is removed by etching using the above acidic etchant, and the n-type semiconductor stack thereunder is removed. The structure 12 is exposed. As a method of etching only the insulating layer 23 in the region corresponding to the p-type region R2, a method of etching by forming a mask layer on the other insulating layer 23 may be mentioned.

  Next, as shown in FIG. 9, the i-type amorphous semiconductor layer 24 and the p-type amorphous semiconductor layer 25 are sequentially formed in this order so as to cover the back surface 10b. A method for forming the amorphous semiconductor layers 24 and 25 is not particularly limited. The amorphous semiconductor layers 24 and 25 can be formed by, for example, a CVD method.

  Next, as shown in FIG. 10, a part of the portion of the amorphous semiconductor layers 24 and 25 located on the insulating layer 23 is etched. Thereby, the i-type amorphous semiconductor layer 13i and the p-type amorphous semiconductor layer 13p are formed from the amorphous semiconductor layers 24 and 25. In this step, a first etchant having an etching rate for the amorphous semiconductor layers 24 and 25 higher than that for the insulating layer 23 is used. For this reason, the amorphous semiconductor layers 24 and 25 are selectively etched out of the insulating layer 23 and the amorphous semiconductor layers 24 and 25.

  The “etching agent” includes a paste-like etching paste and an etching ink having a viscosity adjusted.

  Next, as shown in FIG. 11, the insulating layer 23 is etched. Specifically, the exposed portion of the insulating layer 23 is etched and removed using the second semiconductor etchant using the amorphous semiconductor layers 13i and 13p as a mask. Thereby, the n-type amorphous semiconductor layer 12n is exposed and the insulating layer 18 is formed from the insulating layer 23.

  In this step, a second etchant having an etching rate with respect to the insulating layer 23 higher than that with respect to the amorphous semiconductor layers 24 and 25 is used. For this reason, the insulating layer 23 is selectively etched among the insulating layer 23 and the amorphous semiconductor layers 24 and 25.

  As described above, the n-type semiconductor multilayer structure 12 including the i-type amorphous semiconductor layer 12i and the n-type amorphous semiconductor layer 12n on the first main surface 10b of the semiconductor substrate 10, A p-type semiconductor stacked structure 13 including the i-type amorphous semiconductor layer 13i and the p-type amorphous semiconductor layer 13p can be formed.

  Next, an n-side electrode 14 and a p-side electrode 15 are formed on each of the n-type amorphous semiconductor layer 12n and the p-type amorphous semiconductor layer 13p in the same manner as described in Patent Document 1. The solar cell 1 shown in FIG. 2 can be completed by performing an electrode formation process.

  Specifically, a first conductive layer 19a made of TCO and a second conductive layer 19b made of a metal or alloy such as Cu are formed by a CVD (Chemical Vapor Deposition) method such as a plasma CVD method or a sputtering method. They are formed in this order by a thin film forming method. Thereafter, the part located on the insulating layer 18 is divided to form the first and second conductive layers 19a and 19b in the state shown in FIG. This division can be performed by, for example, a photolithography method.

  Next, a third conductive layer 19c made of Cu and a fourth conductive layer 19d made of Sn are sequentially formed on the first and second conductive layers 19a and 19b by electrolytic plating. The n-side electrode 14 and the p-side electrode 15 shown in FIG. 2 can be completed.

  As described above, the solar cell 1 of the first embodiment shown in FIG. 2 can be manufactured.

  In the above embodiment, the overlapping region R4 extending substantially linearly along the extending direction of the p-type region R2 has been described as an example, but the present invention is not limited to this. For example, the overlapping region R4 formed in a zigzag shape or a wavy shape in plan view may be used. By forming the overlapping region R4 in a zigzag shape or a wavy shape, the overlapping region R4 can be relatively increased. By increasing the overlapping region R4, it is possible to increase the current leakage path when a reverse bias voltage is applied to the solar cell, and to more reliably suppress the occurrence of hot spots.

  In each of the above-described embodiments, n-type is taken as an example of one conductivity type and p-type is taken as an example of other conductivity type, but the present invention is not limited to this. N-type may be used.

DESCRIPTION OF SYMBOLS 1 ... Solar cell 10 ... Semiconductor substrate 10a ... 2nd main surface (light-receiving surface)
10b ... 1st main surface (back surface)
DESCRIPTION OF SYMBOLS 11 ... Light 12 ... n-type semiconductor laminated structure 12i ... i-type amorphous semiconductor layer 12n ... n-type amorphous semiconductor layer 13 ... p-type semiconductor laminated structure 13i ... i-type amorphous semiconductor layer 13p ... p-type Amorphous semiconductor layer 14 ... n-side electrodes 14A, 15A ... bus bars 14B, 15B ... finger 15 ... p-side electrode 16 ... insulating layer 17 ... amorphous semiconductor layer 17i ... i-type amorphous semiconductor layer 17n ... n-type non-layer Crystalline semiconductor layer 18 ... insulating layer 19a ... first conductive layer 19b ... second conductive layer 19c ... third conductive layer 19d ... fourth conductive layer 21 ... i-type amorphous semiconductor layer 22 ... n-type non-layer Crystalline semiconductor layer 23 ... insulating layer 24 ... i-type amorphous semiconductor layer 25 ... p-type amorphous semiconductor layer R1 ... n-type region R2 ... p-type region R3 ... insulating region R4 ... overlapping region

Claims (5)

A semiconductor substrate having a first main surface and a second main surface and having one conductivity type;
A region of one conductivity type having a semiconductor layer structure of one conductivity type provided on the first main surface;
Another conductivity type region having a semiconductor layer structure of another conductivity type provided on the first main surface,
The one conductivity type semiconductor layer structure is formed in a part of the other conductivity type region, and the other conductivity type semiconductor is formed on the one conductivity type semiconductor layer structure in the part region. A solar cell in which an overlapping region provided with a layer structure is formed. The one conductivity type semiconductor layer structure includes a first intrinsic semiconductor layer provided on the first main surface and a one conductivity type semiconductor layer provided on the first intrinsic semiconductor layer. A conductive semiconductor laminated structure,
The other-conductivity-type semiconductor layer structure includes a second intrinsic semiconductor layer provided on the first main surface and an other-conductivity-type semiconductor layer provided on the second intrinsic semiconductor layer. The solar cell according to claim 1, wherein the solar cell has a conductive semiconductor laminated structure.   The region of one conductivity type and the region of another conductivity type are formed so as to extend in a first direction, and the overlapping region is also formed so as to extend in the first direction. Or the solar cell of 2.   4. The solar cell according to claim 3, wherein a part of the overlapping region is formed to extend in a second direction that is a direction intersecting the first direction.   The solar cell according to any one of claims 1 to 4, wherein the one conductivity type is n-type and the other conductivity type is p-type.

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