JP2015050230A - Optical element and optical element array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small optical element in which an area of an upper surface of a contact layer positioned at a top layer of the optical element is large even in a case where an etching rate of the contact layer is small.SOLUTION: An optical element includes a base board 2, a plurality of semiconductor layers 30 stacked on an upper surface of the base board 2, an electrode 31, and an insulating film 9. The plurality of semiconductor layers 30 include a plurality of one conductive type semiconductor layers and a plurality of inverse conductive type semiconductor layers. A top layer includes an inverse conductive type contact layer 30f containing a plurality of truncated pyramids 30fa, 30fb, and 30fc. An area that contacts to a lower bottom of other truncated pyramid positioned above one truncated pyramid, at an upper bottom of one truncated pyramid, among the plurality of truncated pyramids, is smaller than an area of a lower bottom of other truncated pyramid. The electrode 31 is connected on an upper surface of the inverse conductive type contact layer 30f, and through the insulating film 9, disposed on a side surface of the plurality of inverse conductive type semiconductor layers and the plurality of one conductive type semiconductor layers.

Description

  The present invention relates to an optical element and an optical element array including the optical element.

  Conventionally, LED chips have been employed as optical elements in optical element arrays used for light sources such as various exposure apparatuses. For example, in the optical element array described in Patent Document 1, after a plurality of semiconductor layers are stacked on the upper surface of a substrate, a plurality of optical elements are formed in a stripe shape by a photolithography method. The plurality of arranged optical elements have a contact layer for connecting an electrode to the uppermost layer of the plurality of semiconductor layers.

  However, when the etching rate of the contact layer located at the uppermost layer is small, there is a problem that the side surface of the contact layer is etched by side etching to form a frustum shape and the area of the upper surface is reduced.

  The reduction in the area of the upper surface of the contact layer means that the light emitting area of the optical element is reduced, and the light emitted from the optical element cannot be extracted efficiently.

  Increasing the area of the upper surface of the contact layer can be dealt with by increasing the size of the optical element itself by previously calculating the side etching amount of the contact layer. However, increasing the size of the optical element not only reduces the size of the optical element but also increases the cost of the optical element. Further, since the pitch of the arrangement of the optical elements is required to be narrowed, the optical elements cannot be simply enlarged.

JP 2005-136130 A

  The present invention has been made in view of the above problems, and provides a small optical element having a large area on the upper surface of the contact layer even when the etching rate of the contact layer located on the uppermost layer of the optical element is small. The purpose is to do.

  An optical element of the present invention includes a substrate, a plurality of semiconductor layers stacked on the upper surface of the substrate, an electrode, and an insulating film, wherein the plurality of semiconductor layers include a plurality of one-conductivity-type semiconductor layers and a plurality of inverted layers. The uppermost layer has a reverse conductivity type contact layer composed of a plurality of frustum portions, and the one of the plurality of frustum portions at the upper base of one frustum portion The area in contact with the lower base of the other frustum portion located above the frustum portion is smaller than the area of the lower base of the other frustum portion, and the electrode is formed of the reverse conductivity type contact layer. It is connected to the upper surface and is disposed on the side surfaces of the plurality of one-conductivity-type semiconductor layers and the plurality of opposite-conductivity-type semiconductor layers with an insulating film interposed therebetween.

  The optical element of the present invention is characterized in that, in the above configuration, the height of the plurality of frustum portions is low on the base side.

Furthermore, the optical element of the present invention is the above-mentioned configuration, wherein the lower base of the lower base that is in contact with the lower base of the other frustum part among the upper bases of the plurality of frustum parts is in contact with the lower base of the lower base. The distance to the end is 1/5 or less of the thickness of the electrode, and the height of the plurality of frustum portions that are in contact with the other frustum portions is 1/10 or less of the thickness of the electrode. It is characterized by that.

  An optical element array of the present invention is characterized in that a plurality of the optical elements of the present invention are arranged on a substrate.

  According to the optical element of the present invention, the optical element includes a substrate, a plurality of semiconductor layers stacked on the upper surface of the substrate, an electrode, and an insulating film. The plurality of semiconductor layers include a plurality of one-conductivity-type semiconductor layers and a plurality of semiconductor layers. The reverse conductivity type semiconductor layer, and the uppermost layer has a reverse conductivity type contact layer composed of a plurality of frustum portions, and among the plurality of frustum portions, in the upper base of one frustum portion, The area in contact with the lower base of another frustum portion located above one frustum portion is smaller than the area of the lower base of the other frustum portion, and the electrode is the reverse conductivity type contact. A contact that is connected to the upper surface of the layer and disposed on the side surfaces of the plurality of one-conductivity-type semiconductor layers and the plurality of opposite-conductivity-type semiconductor layers via an insulating film, so Even if the etching rate of the layer is small, Large compact optical element area is realized.

(A) is sectional drawing which shows an example of the form of the optical element of this invention. (B) is an enlarged view of the reverse conductivity type contact layer which comprises the optical element shown to (a). It is a figure for demonstrating the formation method of the reverse conductivity type contact layer which comprises the optical element shown to Fig.1 (a). It is an enlarged view of the reverse conductivity type contact layer which comprises the optical element for demonstrating the 1st modification of the optical element shown to Fig.1 (a). It is a figure for demonstrating the position of the upper base end of a frustum part, and a lower base end.

  Hereinafter, examples of embodiments of the optical element 1 of the present invention will be described with reference to the drawings. The following examples illustrate the embodiments of the present invention, and the present invention is not limited to these embodiments.

  An optical element 1 shown in FIGS. 1A and 1B functions as a light source in an exposure apparatus such as an optical element head incorporated in an electrophotographic apparatus such as a page printer and a light source in a light emitting / receiving element sensor.

  The optical element 1 includes a substrate 2, a plurality of semiconductor layers 30 stacked on the upper surface of the substrate 2, electrodes 31 (first electrode 31 a and second electrode 31 b), and an insulating film 8.

The substrate 2 is a single crystal semiconductor substrate such as silicon (Si) and gallium arsenide (GaAs) and a single crystal insulating substrate such as sapphire (Al ₂ O ₃ ). For example, in the case of a single crystal semiconductor substrate, a substrate having an offset angle of 2 to 7 ° in the <011> direction with respect to the (100) plane is preferably used. In the case of sapphire, a C-plane substrate is preferred. Here, the C plane is the (0001) plane. As the substrate 2 of this example, a high resistance silicon (Si) substrate not doped with impurities is used.

  The plurality of semiconductor layers 30 are composed of a plurality of one-conductivity-type semiconductor layers and reverse-conductivity-type semiconductor layers. In this example, one conductivity type is n-type, and the other conductivity type is p-type.

First, on the upper surface of the substrate 2, there is a buffer layer 30a for buffering the difference in lattice constant between the substrate 2 and a semiconductor layer stacked on the upper surface of the substrate 2 (in this example, an n-type contact layer 30b described later). Is formed. The buffer layer 30a buffers the difference in lattice constant between the substrate 2 and the semiconductor layer formed on the upper surface of the substrate 2, thereby causing lattice distortion generated between the substrate 2 and the semiconductor layer constituting the optical element 1 or the like. Has a function of reducing the lattice defects or crystal defects of the entire semiconductor layer constituting the optical element 1 formed on the upper surface of the substrate 2.

  The buffer layer 30a of this example is made of gallium arsenide (GaAs) and has a thickness of about 2 to 3 μm.

An n-type contact layer 30b is formed on the upper surface of the buffer layer 30a. In the n-type contact layer 30b, gallium arsenide (GaAs) is doped with n-type impurities such as silicon (Si) or selenium (Se), and the doping concentration is 1 × 10 ¹⁶ to 1 × 10 ²⁰ atoms / cm ^3. The thickness is about 0.8 to 1 μm.

In this example, silicon (Si) is doped as an n-type impurity at a doping concentration of 1 × 10 ¹⁸ to 2 × 10 ¹⁸ atoms / cm ³ . A part of the upper surface of the n-type contact layer 30b is exposed, and this exposed part is connected to an external power source (not shown) via the first electric electrode 31a. In this example, although not shown, the first electrode 31a and the external power source are connected by wire bonding using a gold (Au) wire. It is also possible to select a wire such as an aluminum (Al) wire or a copper (Cu) wire instead of the gold (Au) wire.

  In this example, the first electrode 31a and the external power source are connected by wire bonding. However, instead of wire bonding, the electrical wiring may be joined to the first electrode 31a by solder or the like. Gold stud bumps may be formed on the upper surface of 31a, and the electrical wiring may be joined to the gold (Au) stud bumps by solder or the like. The n-type contact layer 30b has a function of reducing contact resistance with the first electrode 31a connected to the n-type contact layer 30b.

  The first electrode 31a is formed with a thickness of about 0.5 to 5 μm using, for example, a gold (Au) antimony (Sb) alloy, a gold (Au) germanium (Ge) alloy, a Ni-based alloy, or the like. At the same time, the first electrode 31a is disposed on the insulating film 8 formed so as to cover the upper surface of the n-type contact layer 30b from the upper surface of the substrate 2, and therefore, the first electrode 31a other than the substrate 2 and the n-type contact layer 30b. The semiconductor layer is electrically insulated.

The insulating film 8 is formed of, for example, an inorganic insulating film such as silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ), an organic insulating film such as polyimide, and the thickness thereof is set to about 0.1 to 1 μm. Yes.

An n-type cladding layer 30c is formed on the upper surface of the n-type contact layer 30b, and this n-type cladding layer 30c has a function of confining holes in an active layer 30d described later. In the n-type cladding layer 30c, aluminum gallium arsenide (AlGaAs) is doped with n-type impurities such as silicon (Si) or selenium (Se), and the doping concentration is 1 × 10 ¹⁶ to 1 × 10 ²⁰ atoms / cm. The thickness is about ³ , and the thickness is about 0.2 to 0.5 μm. In this example, silicon (Si) is doped as an n-type impurity at a doping concentration of 1 × 10 ^{17 to} 5 × 10 ¹⁷ atoms / cm ³ .

An active layer 30d is formed on the upper surface of the n-type cladding layer 30c, and this active layer 30d functions as a light-emitting layer that emits light when carriers such as electrons and holes are concentrated and recombined. . The active layer 30d is made of aluminum gallium arsenide (AlGaAs) containing no impurities, and has a thickness of about 0.1 to 0.5 μm. The active layer 30d in this example is a layer that does not contain impurities, but may be a p-type active layer that contains p-type impurities or an n-type active layer that contains n-type impurities. The band gap should be smaller than the band gap of the n-type cladding layer 30c and the p-type cladding layer 30e described later.

A p-type cladding layer 30e is formed on the upper surface of the active layer 30d, and has a function of confining electrons in the active layer 30d. In the p-type cladding layer 30e, aluminum gallium arsenide (AlGaAs) is doped with p-type impurities such as zinc (Zn), magnesium (Mg), or carbon (C), and the doping concentration is 1 × 10 ¹⁶ to 1 ×. The thickness is about 10 ²⁰ atoms / cm ³ and the thickness is about 0.2 to 0.5 μm. In this example, zinc (Zn) is doped as a p-type impurity at a doping concentration of 1 × 10 ^{19 to} 5 × 10 ¹⁹ atoms / cm ³ .

A p-type contact layer 30f is formed on the upper surface of the p-type cladding layer 30e. In the p-type contact layer 30f, aluminum gallium arsenide (AlGaAs) is doped with p-type impurities such as zinc (Zn), magnesium (Mg), or carbon (C), and the doping concentration is 1 × 10 ¹⁶ to 1 ×. The thickness is about 10 ²⁰ atoms / cm ³ and the thickness is about 0.2 to 0.5 μm. The p-type contact layer 30f is located at the uppermost layer of the plurality of semiconductor layers, and is composed of a plurality of frustum portions (three in this example, 30fa, 30fb, and 30fc). Here, the frustum is a three-dimensional figure obtained by removing from a cone a cone that shares a vertex and is similarly reduced.

  Among the plurality of frustum portions, below the other frustum portions located above the one frustum portion on the upper bottom of the frustum portion (the bottom surface above the two parallel bottom surfaces of the frustum) The area in contact with the bottom (the bottom surface below the two parallel bottom surfaces of the frustum) is smaller than the area of the bottom bottom of the other frustum portions. In the case of this example, the areas of the upper bases of the frustum parts 30fb and 30fc are smaller than the areas of the lower bases of the frustum parts 30fa and 30fb, respectively. In addition, the height of the frustum parts 30fa, 30fb, and 30fc of this example is equal.

  Thus, by forming the p-type contact layer 30f with a plurality of frustum portions, the area of the upper surface 30ft (upper bottom 30ft) of the p-type contact layer 30f can be increased. Therefore, the light emitted from the optical element 1 can be extracted efficiently. In addition, the area of the lower base of the frustum portion 30fc can be reduced as compared with the case where the p-type contact layer 30f is formed by one frustum portion.

  Therefore, even when the etching rate of the p-type contact layer 30f located at the uppermost layer of the optical element 1 is small, the small optical element 1 having a large area of the upper surface 30ft of the p-type contact layer 30f can be realized. .

  The p-type contact layer 30f is connected to an external power supply via the second electrode 31b. The method of connecting the second electrode 31b and the external power source and the variation of the bonding form are the same as in the case of the first electrode 31a. The p-type contact layer 30f has a function of reducing contact resistance with the second electrode 31b connected to the p-type contact layer 30f.

The second electrode 31b is connected to the upper surface 30ft of the p-type contact layer 30f, and the p-type contact layer 30f, the p-type cladding layer 30e, the active layer 30d, the n-type cladding layer 30c, and the n-type contact are interposed via the insulating film 8. Arranged on the side surfaces of the layer 30b and the buffer layer 30a. That is, the second electrode 31b is disposed on the side surfaces of the plurality of n-type semiconductor layers and the plurality of p-type semiconductor layers with the insulating film 8 interposed therebetween.

  The p-type contact layer 30f may have a two-layer structure in which the type and concentration of the p-type impurity to be doped are different. For example, by increasing the concentration of the p-type impurity on the upper surface side, the contact resistance with the second electrode 31b can be further lowered to increase the reliability of the connection between the p-type contact layer 30f and the second electrode 31b. The thickness may be about 0.01 to 0.03 μm. The layer on the upper surface side of the p-type contact layer 30f may be formed of, for example, gallium arsenide (GaAs) containing no impurities, and may be a cap layer having a function of preventing oxidation of the p-type contact layer 30f.

  The second electrode 31b is made of, for example, AuNi, AuCr, AuTi, or AlCr alloy in which gold (Au) or aluminum (Al) and nickel (Ni), chromium (Cr), or titanium (Ti) as an adhesion layer are combined. The thickness is about 0.5 to 5 μm. Since the second electrode 31b is disposed on the insulating film 8 formed so as to cover the upper surface of the p-type contact layer 30f from the upper surface of the substrate 2, a semiconductor other than the substrate 2 and the p-type contact layer 30f is disposed. It is electrically insulated from the layer.

  In the optical element 1 configured as described above, when a bias is applied between the first electrode 31a and the second electrode 31b, the active layer 30d emits light and functions as a light source.

(Optical element manufacturing method)
Next, an example of a manufacturing method of the optical element 1 is shown.

  First, a substrate 2 made of high-resistance silicon that is not doped with impurities is prepared.

Then, the substrate 2 is formed by MOCVD (Metal-organic Chemical Vapor).
The natural oxide film formed on the surface of the substrate 2 is removed by heat treatment in a reaction furnace of the Deposition apparatus. This heat treatment is performed, for example, at a temperature of 1000 ° C. for about 10 minutes.

  Next, using the MOCVD method, each semiconductor layer (buffer layer 30a, n-type contact layer 30b, n-type cladding layer 30c, active layer 30d, p-type cladding layer 30e, p-type contact layer 30f constituting the optical element 1 is formed. ) Are sequentially stacked on the substrate 2. Then, a photoresist is applied on the laminated semiconductor layer L (not shown), a desired pattern is exposed and developed by a photolithography method, and then the optical element 1 is formed by a wet etching method. At this time, etching is performed a plurality of times so that the p-type contact layer 30f is composed of a plurality of frustum portions 30fa, 30fb and 30fc, and a part of the upper surface of the n-type contact layer 30b is exposed. Thereafter, the photoresist is removed.

  In order for the p-type contact layer 30f to be composed of a plurality of frustum portions 30fa, 30fb, and 30fc, a method as shown in FIGS. 2A to 2F may be employed.

  First, as shown in FIG. 2A, a photoresist R1 is formed on the upper surface of a semiconductor layer S made of aluminum gallium arsenide (AlGaAs) to be the p-type contact layer 30f. Then, as shown in FIG. 2B, the frustum portion 30fa is formed by etching. Next, as shown in FIG. 2C, after removing the photoresist R1, the photoresist R2 is formed so as to cover the upper surface 30ft and the side surface of the frustum 30fa. Then, as shown in FIG. 2D, the frustum portion 30fb is formed by etching. Further, as shown in FIG. 2E, after removing the photoresist R2, the photoresist R3 is formed so as to cover the upper surface and the side surface of the frustum portion 30fa and the side surface of the frustum portion 30fb. Then, as shown in FIG. 2F, the frustum portion 30fc is formed by etching.

  Next, the insulating film 8 is formed so as to cover the exposed surface of the optical element 1 and the upper surface of the substrate 2 by using a thermal oxidation method, a sputtering method, a plasma CVD method, or the like. Subsequently, after applying a photoresist on the insulating film 8 and exposing and developing a desired pattern by a photolithography method, a first electrode 31a and a second electrode 31b, which will be described later, are respectively n-typed by a wet etching method. Openings for connecting to contact layer 30b and p-type contact layer 30f are formed in insulating film 8. Thereafter, the photoresist is removed.

  Next, after applying a photoresist on the insulating film 8, exposing and developing a desired pattern by a photolithography method, an alloy film for forming the first electrode 31a using a resistance heating method, a sputtering method, or the like Form. Then, using the lift-off method, the photoresist is removed and the first electrode 31a is formed in a desired shape. Similarly, the second electrode 31b is formed by the same process.

  As mentioned above, although the example of specific embodiment of this invention was shown, this invention is not limited to this, A various change is possible within the range which does not deviate from the summary of this invention.

  For example, as in the first modification shown in FIG. 3, the height of the plurality of frustum portions may be lower on the base 2 side. In the case of the first modification, the height of the frustum portion 30fa is the highest, and the heights of the frustum portions 30fb and 30fc are lower than the height of the frustum portion 30fa. By adopting such a configuration, the distance from the upper base end of each of the upper bases of the plurality of frustum parts that touches the lower base of the other frustum part to the lower base end of the lower base that touches it is shortened. Since it can do, it can suppress that the 2nd electrode 31b is disconnected at the boundary of the adjacent frustum part. In the case of this example, the distance from the upper bottom end of the frustum portion 30fb to the lower bottom end of the frustum portion 30fa and the distance from the upper bottom end of the frustum portion 30fc to the lower bottom end of the frustum portion 30fb are shortened. can do. FIG. 4 shows the positions of the upper and lower base ends of the frustum portion.

  Although not shown, the distance from the upper bottom end of each of the plurality of frustum portions in contact with the lower bottom of the other frustum portion to the lower bottom end of the lower bottom in contact is the second. It is 1/5 or less of the thickness of the electrode 31b, and the height of what is in contact with the other frustum portions among the plurality of frustum portions may be 1/10 or less of the thickness of the second electrode 31b. In the case of this example, the distance from the upper bottom end of the frustum portion 30fb to the lower bottom end of the frustum portion 30fa is 1/5 or less of the thickness of the second electrode 31b, and the heights of the frustum portions 30fb and 30fc Is 1/10 or less of the thickness of the second electrode 31b. By setting it as such a structure, it can suppress that the 2nd electrode 31b is disconnected at the boundary of the adjacent frustum part, and can improve connection reliability.

Furthermore, although not shown, an optical element array in which a plurality of optical elements 1 are arranged on a substrate may be used. In this case, if the substrate is formed of a single crystal semiconductor substrate such as silicon (Si) and gallium arsenide (GaAs) or a single crystal insulating substrate such as sapphire (Al ₂ O ₃ ), as in the case of the substrate 2, the substrate can be separated. There is no need to provide it, and an optical element array in which a plurality of optical elements 1 are formed on the substrate 2 can be obtained.

  Using a high resistance silicon (Si) substrate as a substrate, an optical element array of 0.3 mm × 8.1 mm made of gallium arsenide (GaAs) was formed on the upper surface of the substrate. In the optical element array, 192 optical elements are formed. It was visually confirmed that the light emitting area of the optical element, that is, the area of the upper surface of the p-type contact layer was widely formed in any optical element array. Then, in order to evaluate the connection reliability of the electrodes formed on the optical elements, 17 mA was continuously energized for 500 hours to each of the optical elements formed on the 3001 optical element array, and the light amount decrease before and after the continuous energization was evaluated. Measure the light quantity of each optical element before and after energization with a photo sensor, and the fluctuation rate of light quantity before and after energization (= light quantity before energization ÷ light quantity after energization × 100 [%]) should be within 5% for all optical elements If the light intensity is less than 5% and less than 10%, it is judged that the light intensity is reduced. The evaluation results are shown in Table 1.

  The distance from the upper base end to the lower base end of the frustum portion is 1/5 or less of the electrode thickness of the optical element, and the height of the frustum portion in contact with the other frustum portions is 10 minutes When it was 1 or less, the light quantity fluctuation rate before and after energization was within 5% in all the optical elements.

1 optical element 2 substrate 8 insulating film 30 semiconductor layer 30a buffer layer 30b n-type contact layer 30c n-type cladding layer 30d active layer 30e p-type cladding layer 30f p-type contact layer 31 electrode 31a first electrode 31b second electrode

Claims (4)

A substrate, a plurality of semiconductor layers stacked on the upper surface of the substrate, an electrode, and an insulating film;
The plurality of semiconductor layers include a plurality of one-conductivity-type semiconductor layers and a plurality of reverse-conductivity-type semiconductor layers, and an uppermost layer includes a reverse-conductivity-type contact layer composed of a plurality of frustum portions,
Of the plurality of frustum parts, the area of the upper base of one frustum part that is in contact with the bottom of another frustum part located above the one frustum part is the same as that of the other frustum part. It is smaller than the area of the bottom,
The electrode is connected to the upper surface of the reverse conductivity type contact layer and disposed on the side surfaces of the plurality of one conductivity type semiconductor layers and the plurality of reverse conductivity type semiconductor layers via an insulating film. An optical element.   The optical element according to claim 1, wherein the height of the plurality of frustum portions is low on the base side. The distance from the upper bottom end of each of the plurality of frustum portions contacting the lower bottom of the other frustum portion to the lower bottom end of the lower bottom in contact is 1 / th of the thickness of the electrode. 5 or less,
3. The optical element according to claim 1, wherein a height of one of the plurality of frustum portions that contacts another frustum portion is 1/10 or less of a thickness of the electrode.   An optical element array comprising a plurality of the optical elements according to any one of claims 1 to 3 arranged on a substrate.

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