JP2015050223A - Semiconductor energy beam detection element - Google Patents

Semiconductor energy beam detection element Download PDF

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JP2015050223A
JP2015050223A JP2013179147A JP2013179147A JP2015050223A JP 2015050223 A JP2015050223 A JP 2015050223A JP 2013179147 A JP2013179147 A JP 2013179147A JP 2013179147 A JP2013179147 A JP 2013179147A JP 2015050223 A JP2015050223 A JP 2015050223A
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山村　和久
Kazuhisa Yamamura
和久 山村
真太郎 鎌田
Shintaro Kamata
真太郎 鎌田
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Hamamatsu Photonics KK
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor energy beam detection element capable of suppressing the generation of discharge.SOLUTION: A semiconductor energy beam detection element ED1 is provided with a semiconductor substrate 1 having a main surface 1a and a main surface 1b which face each other. The semiconductor substrate 1 has: a first semiconductor region 3 of a first conductivity type, which is positioned on the main surface 1a side; a second semiconductor region 5 of the first conductivity type, which is positioned on the main surface 1b side and has a higher concentration of impurity than the first semiconductor region 3; a third semiconductor region 7 of a second conductivity type, which is positioned on the main surface 1a side and constitutes an energy-beam-sensitive region together with the first semiconductor region 3; a fourth semiconductor region 9 of the second conductivity type, which is positioned so as to surround the region, in which the third semiconductor region 7 is positioned, on the main surface 1a side; and a fifth semiconductor region 11 of the second conductivity type, which is positioned so as to follow the outer periphery of the semiconductor substrate 1 on the main surface 1a side.

Description

本発明は、γ線又はＸ線などの高エネルギー放射線、紫外線、可視光、又は赤外線などを含むエネルギー線を検出する半導体エネルギー線検出素子に関する。   The present invention relates to a semiconductor energy ray detection element for detecting energy rays including high energy radiation such as γ rays or X rays, ultraviolet rays, visible light, or infrared rays.

半導体エネルギー線検出素子として、互いに対向する第一主面と第二主面とを有する半導体基板を備え、当該半導体基板が、第一主面側に位置する第一導電型の第一半導体領域と、第二主面側に位置し、第一半導体領域よりも高い不純物濃度を有する第一導電型の第二半導体領域と、第一主面側に位置し、第一半導体領域とでエネルギー線感応領域を構成する、第二導電型の第三半導体領域と、を有するものが知られている（たとえば、特許文献１など）。   As a semiconductor energy ray detection element, a semiconductor substrate having a first main surface and a second main surface facing each other is provided, and the semiconductor substrate is a first conductivity type first semiconductor region located on the first main surface side; The first-conductivity-type second semiconductor region located on the second main surface side and having a higher impurity concentration than the first semiconductor region and the first semiconductor region located on the first main surface side are sensitive to energy rays. What has a 2nd conductivity type 3rd semiconductor area | region which comprises an area | region is known (for example, patent document 1 etc.).

半導体エネルギー線検出素子では、空乏層が半導体基板の側面に到達すると半導体基板をダイシングしたときに発生する結晶欠陥などにより、リーク電流が増加する懼れがある。このため、半導体基板は、第一主面側において半導体基板の外縁に沿うように位置し、第一半導体領域よりも不純物濃度が高い第一導電型の外縁半導体領域を更に有しており、当該外縁半導体領域が、空乏層が上記側面に到達するのを抑制している。   In the semiconductor energy ray detection element, when the depletion layer reaches the side surface of the semiconductor substrate, the leakage current may increase due to crystal defects generated when the semiconductor substrate is diced. For this reason, the semiconductor substrate further includes an outer edge semiconductor region of the first conductivity type that is positioned along the outer edge of the semiconductor substrate on the first main surface side and has an impurity concentration higher than that of the first semiconductor region. The outer edge semiconductor region suppresses the depletion layer from reaching the side surface.

特開２００１−２９１８９２号公報JP 2001-218992 A

半導体エネルギー線検出素子を動作させるために、半導体エネルギー線検出素子に高いバイアス電圧（たとえば、数百〜一千Ｖ程度）が印加される。この場合、第一半導体領域は、第三半導体領域から拡がる空乏層が第一主面側から第二半導体領域との界面まで到達した完全空乏化状態とされる必要がある。しかしながら、半導体エネルギー線検出素子に高いバイアス電圧が印加される場合、以下のような問題点が生じる懼れがある。   In order to operate the semiconductor energy ray detection element, a high bias voltage (for example, about several hundred to one thousand volts) is applied to the semiconductor energy ray detection element. In this case, the first semiconductor region needs to be in a fully depleted state in which a depletion layer extending from the third semiconductor region reaches the interface with the second semiconductor region from the first main surface side. However, when a high bias voltage is applied to the semiconductor energy ray detection element, the following problems may occur.

半導体エネルギー線検出素子には、一般に、半導体エネルギー線検出素子からの信号を読み出すＲＯＩＣ（Read-out IC）チップが接続される。半導体エネルギー線検出素子とＲＯＩＣチップとは、対応する電極同士がバンプ接続されるため、互いに近接して配置される。半導体エネルギー線検出素子に高いバイアス電圧が印加されると、上記外縁半導体領域が、第一半導体領域と同じ導電型であるため、外縁半導体領域の電位が第一半導体領域と同程度の高電位となる。このため、ＲＯＩＣチップと外縁半導体領域との間の電位差が大きく、当該外縁半導体領域とＲＯＩＣチップとの間で放電が生じやすい。特に、外縁半導体領域は、半導体基板の外縁の形状（角形状）に起因して電界が集中し易く、放電が生じやすい。ＲＯＩＣチップとの間で放電が生じると、半導体エネルギー線検出素子が破壊されてしまう懼れがある。   Generally, a ROIC (Read-out IC) chip that reads a signal from the semiconductor energy ray detecting element is connected to the semiconductor energy ray detecting element. The semiconductor energy ray detection element and the ROIC chip are arranged close to each other because the corresponding electrodes are bump-connected. When a high bias voltage is applied to the semiconductor energy ray detection element, the outer edge semiconductor region has the same conductivity type as the first semiconductor region, so that the potential of the outer edge semiconductor region is as high as the first semiconductor region. Become. For this reason, the potential difference between the ROIC chip and the outer edge semiconductor region is large, and electric discharge tends to occur between the outer edge semiconductor region and the ROIC chip. In particular, in the outer edge semiconductor region, the electric field tends to concentrate due to the shape (angular shape) of the outer edge of the semiconductor substrate, and electric discharge tends to occur. If a discharge is generated between the ROIC chip and the semiconductor energy ray detecting element, the element may be destroyed.

本発明は、放電の発生を抑制することが可能な半導体エネルギー線検出素子を提供することを目的とする。   An object of this invention is to provide the semiconductor energy-beam detection element which can suppress generation | occurrence | production of discharge.

本発明は、互いに対向する第一主面と第二主面とを有する半導体基板を備えた半導体エネルギー線検出素子であって、半導体基板は、第一主面側に位置する第一導電型の第一半導体領域と、第二主面側に位置し、第一半導体領域よりも不純物濃度が高い第一導電型の第二半導体領域と、第一主面側に位置し、第一半導体領域とでエネルギー線感応領域を構成する、第二導電型の第三半導体領域と、第一主面側において第三半導体領域が位置する領域の周囲を囲むように位置する、第二導電型の第四半導体領域と、第一主面側において半導体基板の外縁に沿うように位置する、第二導電型の第五半導体領域と、を有する。   The present invention is a semiconductor energy ray detection element comprising a semiconductor substrate having a first main surface and a second main surface facing each other, wherein the semiconductor substrate is of a first conductivity type located on the first main surface side. A first semiconductor region, a second semiconductor region of a first conductivity type located on the second main surface side and having an impurity concentration higher than that of the first semiconductor region; a first semiconductor region located on the first main surface side; A second conductive type third semiconductor region that constitutes the energy beam sensitive region, and a second conductive type fourth semiconductor region that surrounds the periphery of the region where the third semiconductor region is located on the first main surface side. A semiconductor region, and a fifth semiconductor region of a second conductivity type located along the outer edge of the semiconductor substrate on the first main surface side.

本発明では、半導体基板は、第一主面側において半導体基板の外縁に沿うように位置する第五半導体領域を有する。第五半導体領域は、第一半導体領域の導電型と異なる、第二導電型であるため、第一半導体領域と第五半導体領域との間で、ＰＮ障壁が形成される。これにより、半導体エネルギー線検出素子に高いバイアス電圧が印加される場合、第一半導体領域と第五半導体領域との間で形成されるＰＮ障壁により、電圧降下が生じ、第五半導体領域の電位が第一半導体領域の電位よりも下がる。したがって、半導体基板（第五半導体領域）とＲＯＩＣチップとの電位差が小さくなり、半導体基板とＲＯＩＣチップとの間で放電が生じにくい。   In the present invention, the semiconductor substrate has a fifth semiconductor region located along the outer edge of the semiconductor substrate on the first main surface side. Since the fifth semiconductor region has a second conductivity type different from the conductivity type of the first semiconductor region, a PN barrier is formed between the first semiconductor region and the fifth semiconductor region. Thereby, when a high bias voltage is applied to the semiconductor energy ray detection element, a voltage drop occurs due to the PN barrier formed between the first semiconductor region and the fifth semiconductor region, and the potential of the fifth semiconductor region becomes The potential drops below the potential of the first semiconductor region. Therefore, the potential difference between the semiconductor substrate (fifth semiconductor region) and the ROIC chip becomes small, and electric discharge hardly occurs between the semiconductor substrate and the ROIC chip.

半導体基板の形状に起因して、放電は、半導体基板の外縁で生じやすく、半導体基板の側面に沿って放電経路（電流経路）が形成されやすい。本発明では、この電流経路上に、第一半導体領域と第五半導体領域との間で形成されるＰＮ障壁が位置することから、当該電流経路を電流が流れ難い。これによっても、半導体基板とＲＯＩＣチップとの間で放電が生じにくい。   Due to the shape of the semiconductor substrate, discharge is likely to occur at the outer edge of the semiconductor substrate, and a discharge path (current path) is likely to be formed along the side surface of the semiconductor substrate. In the present invention, since the PN barrier formed between the first semiconductor region and the fifth semiconductor region is located on the current path, it is difficult for current to flow through the current path. This also makes it difficult for discharge to occur between the semiconductor substrate and the ROIC chip.

半導体基板は、第一主面側において第四半導体領域の周囲を囲むように第四半導体領域と第五半導体領域との間に位置し、第一半導体領域よりも不純物濃度が高い第一導電型の半導体領域を更に有していてもよい。この場合、第一半導体領域が完全空乏化された状態で、空乏層が半導体基板の側面に到達するのが抑制される。   The semiconductor substrate is located between the fourth semiconductor region and the fifth semiconductor region so as to surround the periphery of the fourth semiconductor region on the first main surface side, and the first conductivity type having a higher impurity concentration than the first semiconductor region. The semiconductor region may be further included. In this case, the depletion layer is prevented from reaching the side surface of the semiconductor substrate in a state where the first semiconductor region is completely depleted.

半導体基板は、半導体基板の側面に第一半導体領域が露出しないように側面側に位置し、第一半導体領域よりも不純物濃度が高い第一導電型の半導体領域を更に有していてもよい。この場合、第一半導体領域が完全空乏化された状態で、空乏層が半導体基板の側面に到達するのが抑制される。   The semiconductor substrate may further include a first conductivity type semiconductor region located on the side surface so that the first semiconductor region is not exposed on the side surface of the semiconductor substrate and having a higher impurity concentration than the first semiconductor region. In this case, the depletion layer is prevented from reaching the side surface of the semiconductor substrate in a state where the first semiconductor region is completely depleted.

半導体基板の側面として露出する第一半導体領域の表面を覆うように配置され、覆われた第一半導体領域の表面側に所定の極性の固定電荷を存在させるためのパッシベーション材料からなる膜と、を更に備えていてもよい。この場合、上記パッシベーション材料からなる膜で覆われた第一半導体領域の表面側に、所定の極性の固定電荷が存在することとなり、所定の極性の固定電荷が存在している第一半導体領域の上記表面側の領域は、アキュムレーション層として機能する。上記パッシベーション材料からなる膜は、側面側において第一半導体領域が側面に露出しないように位置しているため、空乏層が半導体基板の側面に到達するのが確実に抑制される。   A film made of a passivation material, which is arranged so as to cover the surface of the first semiconductor region exposed as a side surface of the semiconductor substrate, and for causing a fixed charge of a predetermined polarity to exist on the surface side of the covered first semiconductor region; Furthermore, you may provide. In this case, a fixed charge with a predetermined polarity exists on the surface side of the first semiconductor region covered with the film made of the passivation material, and the first semiconductor region with the fixed charge with a predetermined polarity exists. The region on the surface side functions as an accumulation layer. Since the film made of the passivation material is positioned on the side surface so that the first semiconductor region is not exposed to the side surface, the depletion layer is reliably suppressed from reaching the side surface of the semiconductor substrate.

第一導電型がＰ型であると共に、第二導電型がＮ型であり、パッシベーション材料が、Ａｌ２Ｏ３であってもよい。この場合、上記パッシベーション材料からなる膜で覆われた第一半導体領域の表面側に、正の固定電荷が存在する。 The first conductivity type may be P-type, the second conductivity type may be N-type, and the passivation material may be Al 2 O 3 . In this case, positive fixed charges exist on the surface side of the first semiconductor region covered with the film made of the passivation material.

半導体基板の第一主面として第二半導体領域と第三半導体領域との間の領域において露出する第一半導体領域の表面を覆うように配置され、覆われた第一半導体領域の表面側に所定の極性の固定電荷を存在させるためのパッシベーション材料からなる膜と、を更に備えていてもよい。この場合、上記パッシベーション材料からなる膜で覆われた第一半導体領域の表面側に、所定の極性の固定電荷が存在することとなり、所定の極性の固定電荷が存在している第一半導体領域の上記表面側の領域は、アキュムレーション層として機能する。上記パッシベーション材料からなる膜は、第二半導体領域と第三半導体領域との間の領域において露出する第一半導体領域の表面を覆うように配置されているため、空乏層が半導体基板の側面に到達するのが抑制される。   The first main surface of the semiconductor substrate is disposed so as to cover the surface of the first semiconductor region exposed in the region between the second semiconductor region and the third semiconductor region, and is predetermined on the surface side of the covered first semiconductor region. And a film made of a passivation material for allowing a fixed charge of a certain polarity to exist. In this case, a fixed charge with a predetermined polarity exists on the surface side of the first semiconductor region covered with the film made of the passivation material, and the first semiconductor region with the fixed charge with a predetermined polarity exists. The region on the surface side functions as an accumulation layer. Since the film made of the passivation material is disposed so as to cover the surface of the first semiconductor region exposed in the region between the second semiconductor region and the third semiconductor region, the depletion layer reaches the side surface of the semiconductor substrate. To be suppressed.

第一導電型がＮ型であると共に、第二導電型がＰ型であり、パッシベーション材料が、ＳｉＯ２又はＳｉ３Ｎ４であってもよい。この場合、上記パッシベーション材料からなる膜で覆われた第一半導体領域の表面側に、負の固定電荷が存在する。 The first conductivity type may be N type, the second conductivity type may be P type, and the passivation material may be SiO 2 or Si 3 N 4 . In this case, a negative fixed charge exists on the surface side of the first semiconductor region covered with the film made of the passivation material.

本発明によれば、放電の発生を抑制することが可能な半導体エネルギー線検出素子を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor energy ray detection element which can suppress generation | occurrence | production of discharge can be provided.

本発明の実施形態に係る半導体エネルギー線検出素子の断面構成を説明するための図である。It is a figure for demonstrating the cross-sectional structure of the semiconductor energy-beam detection element which concerns on embodiment of this invention. 本実施形態に係る半導体エネルギー線検出素子の平面図である。It is a top view of the semiconductor energy beam detection element concerning this embodiment. 本実施形態の第一変形例に係る半導体エネルギー線検出素子の断面構成を説明するための図である。It is a figure for demonstrating the cross-sectional structure of the semiconductor energy-beam detection element which concerns on the 1st modification of this embodiment. 本実施形態の第二変形例に係る半導体エネルギー線検出素子の断面構成を説明するための図である。It is a figure for demonstrating the cross-sectional structure of the semiconductor energy-beam detection element which concerns on the 2nd modification of this embodiment. 本第二変形例に係る半導体エネルギー線検出素子の平面図である。It is a top view of the semiconductor energy-beam detection element which concerns on this 2nd modification. 本実施形態の第三変形例に係る半導体エネルギー線検出素子の断面構成を説明するための図である。It is a figure for demonstrating the cross-sectional structure of the semiconductor energy-beam detection element which concerns on the 3rd modification of this embodiment. 本実施形態の第四変形例に係る半導体エネルギー線検出素子の断面構成を説明するための図である。It is a figure for demonstrating the cross-sectional structure of the semiconductor energy-beam detection element which concerns on the 4th modification of this embodiment. 本実施形態の第五変形例に係る半導体エネルギー線検出素子の断面構成を説明するための図である。It is a figure for demonstrating the cross-sectional structure of the semiconductor energy-beam detection element which concerns on the 5th modification of this embodiment.

以下、添付図面を参照して、本発明の好適な実施形態について詳細に説明する。なお、説明において、同一要素又は同一機能を有する要素には、同一符号を用いることとし、重複する説明は省略する。   Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted.

図１及び図２を参照して、本実施形態に係る半導体エネルギー線検出素子ＥＤ１の構成を説明する。図１は、本実施形態に係る半導体エネルギー線検出素子の断面構成を説明するための図である。図２は、本実施形態に係る半導体エネルギー線検出素子の平面図である。図２では、後述する絶縁膜１３、電極１５，１７，１９、パッシベーション膜２１、及びバンプ電極２３の図示を省略している。   With reference to FIGS. 1 and 2, the configuration of the semiconductor energy ray detection element ED <b> 1 according to the present embodiment will be described. FIG. 1 is a diagram for explaining a cross-sectional configuration of the semiconductor energy beam detection element according to the present embodiment. FIG. 2 is a plan view of the semiconductor energy ray detection element according to the present embodiment. In FIG. 2, illustration of an insulating film 13, electrodes 15, 17, 19, a passivation film 21, and a bump electrode 23 described later is omitted.

半導体エネルギー線検出素子ＥＤ１は、図１に示されるように、半導体基板１を備える。半導体基板１は、互いに対向する一対の主面１ａ，１ｂと、側面１ｃと、を有する、第一導電型（たとえば、Ｐ型）のシリコン基板である。側面１ｃは、一対の主面１ａ，１ｂ間を連結するように一対の主面１ａ，１ｂの対向方向に延びている。本実施形態では、半導体基板１は、図２に示されるように、平面視で矩形形状を呈しており、４つの側面１ｃを有する。   The semiconductor energy ray detection element ED1 includes a semiconductor substrate 1 as shown in FIG. The semiconductor substrate 1 is a first conductivity type (for example, P type) silicon substrate having a pair of main surfaces 1a and 1b and a side surface 1c facing each other. The side surface 1c extends in the opposing direction of the pair of main surfaces 1a and 1b so as to connect the pair of main surfaces 1a and 1b. In the present embodiment, as shown in FIG. 2, the semiconductor substrate 1 has a rectangular shape in plan view and has four side surfaces 1c.

半導体基板１は、主面１ａ側に位置する第一導電型（たとえば、Ｐ型）の第一半導体領域３と、主面１ｂ側に位置する第一導電型（たとえば、Ｐ型）の第二半導体領域５と、を有している。第二半導体領域５は、第一導電型の不純物（硼素など）が添加された領域であり、第一半導体領域３よりも不純物濃度が高い。第二半導体領域５は、たとえば、イオン注入法又は拡散法により、第一導電型の不純物を主面１ｂ側から半導体基板１に添加することにより形成される。   The semiconductor substrate 1 includes a first semiconductor region 3 of a first conductivity type (for example, P type) located on the main surface 1a side and a second of a first conductivity type (for example, P type) located on the main surface 1b side. And a semiconductor region 5. The second semiconductor region 5 is a region to which a first conductivity type impurity (such as boron) is added, and has an impurity concentration higher than that of the first semiconductor region 3. The second semiconductor region 5 is formed by adding a first conductivity type impurity from the main surface 1b side to the semiconductor substrate 1 by, for example, ion implantation or diffusion.

半導体基板１は、半導体基板１（第一半導体領域３）の主面１ａ側に、複数の第二導電型（たとえば、Ｎ型）の第三半導体領域７を有している。各第三半導体領域７の間には、第一半導体領域３の一部領域が介在している。すなわち、第三半導体領域７同士は、離隔している。各第三半導体領域７は、第二導電型の不純物（アンチモン、砒素、又はリンなど）が添加された領域であり、第一半導体領域３よりも不純物濃度が高い。半導体エネルギー線検出素子ＥＤ１では、第一半導体領域３と各第三半導体領域７とでＰＮ接合が形成されている。すなわち、各第三半導体領域７は、第一半導体領域３とでエネルギー線感応領域を構成している。   The semiconductor substrate 1 has a plurality of second conductivity type (for example, N-type) third semiconductor regions 7 on the main surface 1a side of the semiconductor substrate 1 (first semiconductor region 3). A part of the first semiconductor region 3 is interposed between the third semiconductor regions 7. That is, the third semiconductor regions 7 are separated from each other. Each third semiconductor region 7 is a region to which a second conductivity type impurity (such as antimony, arsenic, or phosphorus) is added, and has a higher impurity concentration than the first semiconductor region 3. In the semiconductor energy ray detection element ED1, a PN junction is formed by the first semiconductor region 3 and each third semiconductor region 7. That is, each third semiconductor region 7 forms an energy ray sensitive region with the first semiconductor region 3.

半導体基板１は、半導体基板１（第一半導体領域３）の主面１ａ側に、第二導電型（たとえば、Ｎ型）の第四及び第五半導体領域９，１１を有している。第四及び第五半導体領域９，１１も、第二導電型の不純物（アンチモン、砒素、又はリンなど）が添加された領域であり、第一半導体領域３よりも不純物濃度が高い。   The semiconductor substrate 1 has fourth and fifth semiconductor regions 9 and 11 of the second conductivity type (for example, N type) on the main surface 1a side of the semiconductor substrate 1 (first semiconductor region 3). The fourth and fifth semiconductor regions 9 and 11 are regions to which a second conductivity type impurity (such as antimony, arsenic, or phosphorus) is added, and the impurity concentration is higher than that of the first semiconductor region 3.

第四半導体領域９は、図２に示されるように、主面１ａと主面１ｂとの対向方向から見て、複数の第三半導体領域７が位置する領域の周囲を囲むように位置している。第四半導体領域９は、ガードリングとして機能する。第三半導体領域７と第四半導体領域９との間には、第一半導体領域３の一部領域が介在している。すなわち、第三半導体領域７と第四半導体領域９とは、離隔している。   As shown in FIG. 2, the fourth semiconductor region 9 is positioned so as to surround the periphery of the region where the plurality of third semiconductor regions 7 are located when viewed from the opposing direction of the main surface 1a and the main surface 1b. Yes. The fourth semiconductor region 9 functions as a guard ring. A partial region of the first semiconductor region 3 is interposed between the third semiconductor region 7 and the fourth semiconductor region 9. That is, the third semiconductor region 7 and the fourth semiconductor region 9 are separated from each other.

第五半導体領域１１は、図２に示されるように、主面１ａ側において半導体基板１の外縁に沿うように位置している。第四半導体領域９は、複数の第三半導体領域７が位置する領域と、第五半導体領域１１と、の間に位置している。すなわち、第五半導体領域１１は、主面１ａと主面１ｂとの対向方向から見て、第四半導体領域９の周囲を囲むように位置している。第四半導体領域９と第五半導体領域１１との間には、第一半導体領域３の一部領域が介在している。すなわち、第四半導体領域９と第五半導体領域１１とは、離隔している。   As shown in FIG. 2, the fifth semiconductor region 11 is located along the outer edge of the semiconductor substrate 1 on the main surface 1 a side. The fourth semiconductor region 9 is located between the region where the plurality of third semiconductor regions 7 are located and the fifth semiconductor region 11. That is, the fifth semiconductor region 11 is positioned so as to surround the fourth semiconductor region 9 when viewed from the opposing direction of the main surface 1a and the main surface 1b. Part of the first semiconductor region 3 is interposed between the fourth semiconductor region 9 and the fifth semiconductor region 11. That is, the fourth semiconductor region 9 and the fifth semiconductor region 11 are separated from each other.

第三、第四、及び第五半導体領域７，９，１１は、たとえば、イオン注入法又は拡散法により、第二導電型の不純物を主面１ａ側から半導体基板１に添加することにより形成される。   The third, fourth, and fifth semiconductor regions 7, 9, and 11 are formed by adding a second conductivity type impurity from the main surface 1a side to the semiconductor substrate 1 by, for example, an ion implantation method or a diffusion method. The

半導体基板１には、図１に示されるように、絶縁膜１３及び電極１５，１７，１９が配置されている。絶縁膜１３は、半導体基板１の主面１ａ側に、半導体基板１の主面１ａを覆うように、配置されている。絶縁膜１３は、たとえばＳｉＯ２からなる。絶縁膜１３は、たとえば、熱酸化法、スパッタ法、又はＰＥＣＶＤ（Plasma-enhanced Chemical Vapor Deposition）法などにより形成される。電極１５，１７，１９は、半導体領域７，９，１１上に形成された絶縁膜１３の一部を除去した後、対応する半導体領域７，９，１１毎に形成される。これにより、電極１５は第三半導体領域７に接続され、電極１７は第四半導体領域９に接続され、電極１９は第五半導体領域１１に接続される。電極１５，１７，１９は、たとえば、アルミニウムなどの電極材料からなる。図示は省略するが、半導体基板１の主面１ｂ側にも、第二半導体領域５に接続される電極が形成される。 As shown in FIG. 1, an insulating film 13 and electrodes 15, 17, 19 are disposed on the semiconductor substrate 1. The insulating film 13 is disposed on the main surface 1 a side of the semiconductor substrate 1 so as to cover the main surface 1 a of the semiconductor substrate 1. The insulating film 13 is made of, for example, SiO 2 . The insulating film 13 is formed by, for example, a thermal oxidation method, a sputtering method, or a PECVD (Plasma-enhanced Chemical Vapor Deposition) method. The electrodes 15, 17, 19 are formed for the corresponding semiconductor regions 7, 9, 11 after removing a part of the insulating film 13 formed on the semiconductor regions 7, 9, 11. Accordingly, the electrode 15 is connected to the third semiconductor region 7, the electrode 17 is connected to the fourth semiconductor region 9, and the electrode 19 is connected to the fifth semiconductor region 11. The electrodes 15, 17, 19 are made of an electrode material such as aluminum. Although not shown, an electrode connected to the second semiconductor region 5 is also formed on the main surface 1 b side of the semiconductor substrate 1.

半導体基板１には、更に、パッシベーション膜２１及びバンプ電極２３が配置されている。パッシベーション膜２１は、半導体基板１の主面１ａ側に、絶縁膜１３及び電極１５，１７，１９覆うように、配置されている。パッシベーション膜２１は、たとえばＳｉＮからなる。パッシベーション膜２１は、たとえばＣＶＤ（Chemical Vapor Deposition）法により形成される。バンプ電極２３は、第三半導体領域７上に形成されたパッシベーション膜２１の一部を除去した後、対応する第三半導体領域７毎に形成される。バンプ電極２３は、対応する電極１５とそれぞれ電気的に接続されている。バンプ電極２３は、たとえばＳｎ−Ａｇからなる。バンプ電極２３の形成方法は、ハンダボールを搭載する手法又は印刷法を用いることができる。電極１７，１９は、パッシベーション膜２１に覆われている。   A passivation film 21 and a bump electrode 23 are further disposed on the semiconductor substrate 1. The passivation film 21 is disposed on the main surface 1 a side of the semiconductor substrate 1 so as to cover the insulating film 13 and the electrodes 15, 17, 19. The passivation film 21 is made of SiN, for example. The passivation film 21 is formed by, for example, a CVD (Chemical Vapor Deposition) method. The bump electrode 23 is formed for each corresponding third semiconductor region 7 after removing a part of the passivation film 21 formed on the third semiconductor region 7. The bump electrode 23 is electrically connected to the corresponding electrode 15. The bump electrode 23 is made of, for example, Sn—Ag. As a method for forming the bump electrode 23, a method of mounting a solder ball or a printing method can be used. The electrodes 17 and 19 are covered with a passivation film 21.

半導体エネルギー線検出素子ＥＤ１は、図１に示されるように、ＲＯＩＣチップＲＣに実装されている。具体的には、半導体エネルギー線検出素子ＥＤ１は、ＲＯＩＣチップＲＣにバンプ接続される。ＲＯＩＣチップＲＣは、複数のパッド電極２５を備えており、対応するパッド電極２５とバンプ電極２３とが接続される。半導体エネルギー線検出素子ＥＤ１とＲＯＩＣチップＲＣとは、互いに近接して配置される。半導体基板１の主面１ａが、ＲＯＩＣチップＲＣに対向している。   The semiconductor energy ray detection element ED1 is mounted on the ROIC chip RC as shown in FIG. Specifically, the semiconductor energy ray detection element ED1 is bump-connected to the ROIC chip RC. The ROIC chip RC includes a plurality of pad electrodes 25, and the corresponding pad electrodes 25 and bump electrodes 23 are connected. The semiconductor energy ray detection element ED1 and the ROIC chip RC are arranged close to each other. The main surface 1a of the semiconductor substrate 1 faces the ROIC chip RC.

半導体エネルギー線検出素子ＥＤ１では、第二半導体領域５と第三半導体領域７との間にバイアス電圧（逆バイアス電圧）が印加されることにより、第三半導体領域７から第一半導体領域３に空乏層が拡がる。空乏層が第二半導体領域５に到達した状態が、完全空乏化状態である。   In the semiconductor energy ray detection element ED1, a depletion is performed from the third semiconductor region 7 to the first semiconductor region 3 by applying a bias voltage (reverse bias voltage) between the second semiconductor region 5 and the third semiconductor region 7. The layer expands. A state where the depletion layer reaches the second semiconductor region 5 is a completely depleted state.

以上のように、本実施形態では、半導体基板１は、主面１ａ側において半導体基板１の外縁に沿うように位置する第五半導体領域１１を有する。第五半導体領域１１は、第一半導体領域３の導電型と異なる、第二導電型であるため、第一半導体領域３と第五半導体領域との間で、ＰＮ障壁が形成される。これにより、半導体エネルギー線検出素子ＥＤ１に高いバイアス電圧（たとえば、数百〜一千Ｖ程度）が印加される場合、第一半導体領域３と第五半導体領域１１との間で形成されるＰＮ障壁により、電圧降下が生じ、第五半導体領域１１の電位が第一半導体領域３の電位よりも下がる。したがって、半導体基板１（第五半導体領域１１）とＲＯＩＣチップＲＣとの電位差が小さくなり、半導体基板１とＲＯＩＣチップＲＣとの間で放電が生じにくい。   As described above, in the present embodiment, the semiconductor substrate 1 has the fifth semiconductor region 11 positioned along the outer edge of the semiconductor substrate 1 on the main surface 1a side. Since the fifth semiconductor region 11 has a second conductivity type different from the conductivity type of the first semiconductor region 3, a PN barrier is formed between the first semiconductor region 3 and the fifth semiconductor region. Thereby, when a high bias voltage (for example, about several hundred to 1,000 V) is applied to the semiconductor energy ray detection element ED1, a PN barrier formed between the first semiconductor region 3 and the fifth semiconductor region 11 is applied. As a result, a voltage drop occurs, and the potential of the fifth semiconductor region 11 falls below the potential of the first semiconductor region 3. Therefore, the potential difference between the semiconductor substrate 1 (fifth semiconductor region 11) and the ROIC chip RC becomes small, and electric discharge is unlikely to occur between the semiconductor substrate 1 and the ROIC chip RC.

半導体基板１の形状に起因して、放電は、半導体基板１の外縁で生じやすく、半導体基板１の側面１ｃに沿って放電経路（電流経路）が形成されやすい。半導体エネルギー線検出素子ＥＤ１では、この電流経路上に、第一半導体領域３と第五半導体領域１１との間で形成されるＰＮ障壁が位置することから、当該電流経路を電流が流れ難い。これによっても、半導体基板１とＲＯＩＣチップＲＣとの間で放電が生じにくい。   Due to the shape of the semiconductor substrate 1, discharge is likely to occur at the outer edge of the semiconductor substrate 1, and a discharge path (current path) is likely to be formed along the side surface 1 c of the semiconductor substrate 1. In the semiconductor energy ray detection element ED1, since a PN barrier formed between the first semiconductor region 3 and the fifth semiconductor region 11 is located on this current path, it is difficult for current to flow through the current path. This also makes it difficult for discharge to occur between the semiconductor substrate 1 and the ROIC chip RC.

これらの結果、半導体エネルギー線検出素子ＥＤ１では、放電の発生を抑制することができる。なお、第四半導体領域９と第五半導体領域１１の間隔を所定の値に設定することにより、空乏層が側面１ｃに到達することを抑制することは可能である。   As a result, in the semiconductor energy ray detection element ED1, the occurrence of discharge can be suppressed. In addition, it is possible to suppress the depletion layer from reaching the side surface 1c by setting the distance between the fourth semiconductor region 9 and the fifth semiconductor region 11 to a predetermined value.

半導体基板とＲＯＩＣチップとの間の放電を抑制する構成として、半導体基板とＲＯＩＣチップとの電位差が小さくする構成が考えられる。具体的には、半導体基板の端部において、一対の主面側の電位をＲＯＩＣチップの電位と同程度とする両面構造を半導体エネルギー線検出素子に採用することが考えられる。しかしながら、この場合、半導体エネルギー線検出素子を製造するために両面プロセス（Double sided process）を実施する必要があり、製造プロセスの煩雑化及び高コスト化を招く懼れがある。   As a configuration for suppressing the discharge between the semiconductor substrate and the ROIC chip, a configuration in which the potential difference between the semiconductor substrate and the ROIC chip is reduced can be considered. Specifically, a double-sided structure in which the potential on the pair of main surfaces is approximately the same as the potential of the ROIC chip at the end of the semiconductor substrate may be adopted for the semiconductor energy ray detection element. However, in this case, it is necessary to perform a double sided process in order to manufacture the semiconductor energy beam detection element, which may lead to a complicated manufacturing process and high cost.

片面プロセス（Single sided process）により半導体エネルギー線検出素子を製造する場合、上述した製造プロセスの煩雑化及び高コスト化を防ぐことができる。片面プロセスにより製造された半導体エネルギー線検出素子では、放電対策として、半導体基板の端部とＲＯＩＣチップとの間に絶縁樹脂を充填する構成が考えられる。しかしながら、この場合には、絶縁樹脂を充填する工程を、半導体エネルギー線検出をＲＯＩＣチップに実装する際に、又は、実装後に、追加する必要があり、結果的に、製造プロセスの煩雑化は避けられない。   When a semiconductor energy ray detection element is manufactured by a single sided process, the above-described complicated manufacturing process and high cost can be prevented. In the semiconductor energy ray detection element manufactured by the single-sided process, a configuration in which an insulating resin is filled between the end portion of the semiconductor substrate and the ROIC chip is considered as a countermeasure against discharge. However, in this case, it is necessary to add the step of filling the insulating resin when the semiconductor energy ray detection is mounted on the ROIC chip or after the mounting. As a result, the manufacturing process is not complicated. I can't.

これらに対して、本実施形態の半導体エネルギー線検出素子ＥＤ１では、半導体基板１が、上記第五半導体領域１１を有することにより、放電の発生が抑制されるため、製造プロセスの煩雑化及び高コスト化を招くことはない。   On the other hand, in the semiconductor energy ray detection element ED1 of the present embodiment, since the semiconductor substrate 1 has the fifth semiconductor region 11, the occurrence of discharge is suppressed, so that the manufacturing process is complicated and the cost is high. There is no inconvenience.

次に、図３を参照して、本実施形態の第一変形例に係る半導体エネルギー線検出素子ＥＤ２の構成を説明する。図３は、本実施形態の第一変形例に係る半導体エネルギー線検出素子の断面構成を説明するための図である。   Next, with reference to FIG. 3, the structure of the semiconductor energy ray detection element ED2 according to the first modification of the present embodiment will be described. FIG. 3 is a diagram for explaining a cross-sectional configuration of the semiconductor energy ray detection element according to the first modification of the present embodiment.

半導体エネルギー線検出素子ＥＤ２では、半導体基板１は、半導体基板１（第一半導体領域３）の主面１ａ側に、第一導電型（たとえば、Ｐ型）の半導体領域３１を有している。半導体領域３１は、主面１ａと主面１ｂとの対向方向から見て、第四半導体領域９の周囲を囲むように第四半導体領域９と第五半導体領域１１との間に位置している。半導体領域３１は、第一導電型の不純物（硼素など）が添加された領域であり、第一半導体領域３よりも不純物濃度が高い。   In the semiconductor energy ray detection element ED2, the semiconductor substrate 1 has a first conductivity type (for example, P type) semiconductor region 31 on the main surface 1a side of the semiconductor substrate 1 (first semiconductor region 3). The semiconductor region 31 is located between the fourth semiconductor region 9 and the fifth semiconductor region 11 so as to surround the fourth semiconductor region 9 when viewed from the opposing direction of the main surface 1a and the main surface 1b. . The semiconductor region 31 is a region to which an impurity of the first conductivity type (boron or the like) is added, and has an impurity concentration higher than that of the first semiconductor region 3.

半導体領域３１は、第四半導体領域９と第五半導体領域１１とに接触している。このため、半導体領域３１における不純物濃度は、第三、第四、及び第五半導体領域７，９，１１における不純物濃度より低いことが好ましい。半導体領域３１の厚みは、第三、第四、及び第五半導体領域７，９，１１の厚みよりも小さい。   The semiconductor region 31 is in contact with the fourth semiconductor region 9 and the fifth semiconductor region 11. For this reason, the impurity concentration in the semiconductor region 31 is preferably lower than the impurity concentration in the third, fourth, and fifth semiconductor regions 7, 9, 11. The thickness of the semiconductor region 31 is smaller than the thickness of the third, fourth, and fifth semiconductor regions 7, 9, 11.

半導体領域３１は、たとえばイオン注入法により形成される。半導体領域３１が、所定の開口が形成されたマスクを用いることなくイオン注入法により形成される場合、半導体基板１の主面１ａとして露出している第一半導体領域３の表面側に、第一導電型（たとえば、Ｐ型）の半導体領域３３も形成される。半導体領域３３は、第三半導体領域７同士の間、及び、第三半導体領域７と第四半導体領域９との間に、それぞれ形成される。半導体基板１の主面１ａとして露出している第三、第四、及び第五半導体領域７，９，１１の表面側にも、第一導電型（たとえば、Ｐ型）の不純物が存在する領域３５が形成される。この場合でも、半導体領域３１，３３における不純物濃度が、第三、第四、及び第五半導体領域７，９，１１における不純物濃度より低く設定されることにより、第三、第四、及び第五半導体領域７，９，１１の機能に支障が生じるのを抑制できる。   The semiconductor region 31 is formed by, for example, an ion implantation method. When the semiconductor region 31 is formed by an ion implantation method without using a mask in which a predetermined opening is formed, the first semiconductor region 3 exposed as the main surface 1a of the semiconductor substrate 1 is exposed on the surface side of the first semiconductor region 3. A conductive type (for example, P type) semiconductor region 33 is also formed. The semiconductor regions 33 are formed between the third semiconductor regions 7 and between the third semiconductor region 7 and the fourth semiconductor region 9, respectively. A region where impurities of the first conductivity type (for example, P-type) exist also on the surface side of the third, fourth, and fifth semiconductor regions 7, 9, 11 exposed as the main surface 1a of the semiconductor substrate 1 35 is formed. Even in this case, the impurity concentrations in the semiconductor regions 31 and 33 are set lower than the impurity concentrations in the third, fourth, and fifth semiconductor regions 7, 9, and 11, so that the third, fourth, and fifth. It is possible to suppress the occurrence of trouble in the functions of the semiconductor regions 7, 9, and 11.

本変形例では、半導体基板１が、主面１ａ側において第四半導体領域９の周囲を囲むように第四半導体領域９と第五半導体領域１１との間に位置し、第一半導体領域３よりも不純物濃度が高い第一導電型の半導体領域３１を有している。これにより、第一半導体領域３が完全空乏化された状態で、空乏層が半導体基板１の側面１ｃに到達するのが抑制される。   In the present modification, the semiconductor substrate 1 is located between the fourth semiconductor region 9 and the fifth semiconductor region 11 so as to surround the periphery of the fourth semiconductor region 9 on the main surface 1 a side, and from the first semiconductor region 3. The semiconductor region 31 of the first conductivity type having a high impurity concentration. This suppresses the depletion layer from reaching the side surface 1c of the semiconductor substrate 1 in a state where the first semiconductor region 3 is completely depleted.

次に、図４及び図５を参照して、本実施形態の第二変形例に係る半導体エネルギー線検出素子ＥＤ３の構成を説明する。図４は、本実施形態の第二変形例に係る半導体エネルギー線検出素子の断面構成を説明するための図である。図５は、本第二変形例に係る半導体エネルギー線検出素子の平面図である。図５では、図２と同様に、絶縁膜１３、電極１５，１７，１９、パッシベーション膜２１、及びバンプ電極２３の図示を省略している。   Next, the configuration of the semiconductor energy ray detection element ED3 according to the second modification of the present embodiment will be described with reference to FIGS. FIG. 4 is a diagram for explaining a cross-sectional configuration of a semiconductor energy ray detection element according to a second modification of the present embodiment. FIG. 5 is a plan view of a semiconductor energy ray detection element according to the second modification. In FIG. 5, as in FIG. 2, illustration of the insulating film 13, the electrodes 15, 17, 19, the passivation film 21, and the bump electrode 23 is omitted.

半導体エネルギー線検出素子ＥＤ３では、半導体基板１は、半導体基板１（第一半導体領域３）の主面１ａ側に、第一導電型（たとえば、Ｐ型）の半導体領域３７を有している。半導体領域３７は、主面１ａと主面１ｂとの対向方向から見て、第四半導体領域９の周囲を囲むように第四半導体領域９と第五半導体領域１１との間に位置している。半導体領域３７は、第一導電型の不純物（硼素など）が添加された領域であり、第一半導体領域３よりも不純物濃度が高い。半導体領域３７は、たとえば、イオン注入法又は拡散法により、第一導電型の不純物を主面１ａ側から半導体基板１に添加することにより形成される。   In the semiconductor energy ray detection element ED3, the semiconductor substrate 1 has a first conductivity type (for example, P-type) semiconductor region 37 on the main surface 1a side of the semiconductor substrate 1 (first semiconductor region 3). The semiconductor region 37 is located between the fourth semiconductor region 9 and the fifth semiconductor region 11 so as to surround the fourth semiconductor region 9 when viewed from the opposing direction of the main surface 1a and the main surface 1b. . The semiconductor region 37 is a region to which a first conductivity type impurity (such as boron) is added, and has an impurity concentration higher than that of the first semiconductor region 3. The semiconductor region 37 is formed by adding a first conductivity type impurity from the main surface 1a side to the semiconductor substrate 1 by, for example, an ion implantation method or a diffusion method.

第四半導体領域９と半導体領域３７との間には、第一半導体領域３の一部領域が介在しており、第五半導体領域１１と半導体領域３７との間にも、第一半導体領域３の一部領域が介在している。すなわち、第四半導体領域９と半導体領域３７とは離隔していると共に、第五半導体領域１１と半導体領域３７とは離隔している。したがって、半導体領域３７の不純物濃度は、上述した半導体領域３１の不純物濃度よりも高く設定することができる。半導体領域３７における不純物濃度は、第三、第四、及び第五半導体領域７，９，１１における不純物濃度と同程度であってもよい。半導体領域３７の厚みは、第三、第四、及び第五半導体領域７，９，１１の厚みよりも小さい。   A part of the first semiconductor region 3 is interposed between the fourth semiconductor region 9 and the semiconductor region 37, and the first semiconductor region 3 is also interposed between the fifth semiconductor region 11 and the semiconductor region 37. Is partly intervened. That is, the fourth semiconductor region 9 and the semiconductor region 37 are separated from each other, and the fifth semiconductor region 11 and the semiconductor region 37 are separated from each other. Therefore, the impurity concentration of the semiconductor region 37 can be set higher than the impurity concentration of the semiconductor region 31 described above. The impurity concentration in the semiconductor region 37 may be approximately the same as the impurity concentration in the third, fourth, and fifth semiconductor regions 7, 9, and 11. The thickness of the semiconductor region 37 is smaller than the thicknesses of the third, fourth, and fifth semiconductor regions 7, 9, 11.

本変形例では、半導体基板１が、主面１ａ側において第四半導体領域９の周囲を囲むように第四半導体領域９と第五半導体領域１１との間に位置し、第一半導体領域３よりも不純物濃度が高い第一導電型の半導体領域３７を有している。これにより、第一半導体領域３が完全空乏化された状態で、空乏層が半導体基板１の側面１ｃに到達するのが抑制される。   In the present modification, the semiconductor substrate 1 is located between the fourth semiconductor region 9 and the fifth semiconductor region 11 so as to surround the periphery of the fourth semiconductor region 9 on the main surface 1 a side, and from the first semiconductor region 3. Also has a first conductivity type semiconductor region 37 having a high impurity concentration. This suppresses the depletion layer from reaching the side surface 1c of the semiconductor substrate 1 in a state where the first semiconductor region 3 is completely depleted.

次に、図６を参照して、本実施形態の第三変形例に係る半導体エネルギー線検出素子ＥＤ４の構成を説明する。図６は、本実施形態の第三変形例に係る半導体エネルギー線検出素子の断面構成を説明するための図である。   Next, with reference to FIG. 6, the structure of the semiconductor energy ray detection element ED4 according to the third modification of the present embodiment will be described. FIG. 6 is a diagram for explaining a cross-sectional configuration of a semiconductor energy ray detection element according to a third modification of the present embodiment.

半導体エネルギー線検出素子ＥＤ４では、半導体基板１は、第一半導体領域３が側面１ｃに露出しないように側面１ｃ側に位置する半導体領域３９を有している。半導体領域３９は、第一半導体領域３が側面１ｃに露出しないように、一対の主面１ａ，１ｂの対向方向に延びている。半導体領域３９における主面１ａ側の縁は、第五半導体領域１１に接触している。半導体領域３９における主面１ｂ側の縁は、第二半導体領域５に接触している。半導体領域３９は、第一導電型の不純物（硼素など）が添加された領域であり、第一半導体領域３よりも不純物濃度が高い。半導体領域３９は、第五半導体領域１１と接触しているため、半導体領域３９における不純物濃度は、第五半導体領域１１における不純物濃度より低いことが好ましい。半導体領域３９は、たとえばイオン注入法により形成される。   In the semiconductor energy ray detection element ED4, the semiconductor substrate 1 has a semiconductor region 39 located on the side surface 1c side so that the first semiconductor region 3 is not exposed to the side surface 1c. The semiconductor region 39 extends in the opposing direction of the pair of main surfaces 1a and 1b so that the first semiconductor region 3 is not exposed to the side surface 1c. The edge on the main surface 1 a side in the semiconductor region 39 is in contact with the fifth semiconductor region 11. The edge on the main surface 1 b side in the semiconductor region 39 is in contact with the second semiconductor region 5. The semiconductor region 39 is a region to which a first conductivity type impurity (such as boron) is added, and has an impurity concentration higher than that of the first semiconductor region 3. Since the semiconductor region 39 is in contact with the fifth semiconductor region 11, the impurity concentration in the semiconductor region 39 is preferably lower than the impurity concentration in the fifth semiconductor region 11. The semiconductor region 39 is formed by, for example, an ion implantation method.

本変形例では、半導体基板１が、第一半導体領域３が側面１ｃに露出しないように側面１ｃ側に位置し、第一半導体領域３よりも不純物濃度が高い第一導電型の半導体領域３９を有している。これにより、第一半導体領域３が完全空乏化された状態で、空乏層が半導体基板１の側面１ｃに到達するのが抑制される。   In this modification, the semiconductor substrate 1 is located on the side surface 1c side so that the first semiconductor region 3 is not exposed to the side surface 1c, and the first conductivity type semiconductor region 39 having a higher impurity concentration than the first semiconductor region 3 is formed. Have. This suppresses the depletion layer from reaching the side surface 1c of the semiconductor substrate 1 in a state where the first semiconductor region 3 is completely depleted.

本変形例では、半導体基板１は、必ずしも半導体領域３７を有している必要はない。しかしながら、上述したように、半導体領域３９の不純物濃度が比較的低く設定されるので、空乏層が半導体基板１の側面１ｃに到達するのを確実に抑制するためには、半導体基板１は、半導体領域３７を有していることが好ましい。   In this modification, the semiconductor substrate 1 does not necessarily have the semiconductor region 37. However, as described above, since the impurity concentration of the semiconductor region 39 is set to be relatively low, in order to reliably suppress the depletion layer from reaching the side surface 1c of the semiconductor substrate 1, the semiconductor substrate 1 is made of a semiconductor. It is preferable to have the region 37.

次に、図７を参照して、本実施形態の第四変形例に係る半導体エネルギー線検出素子ＥＤ５の構成を説明する。図７は、本実施形態の第四変形例に係る半導体エネルギー線検出素子の断面構成を説明するための図である。   Next, with reference to FIG. 7, the structure of the semiconductor energy ray detection element ED5 according to the fourth modification of the present embodiment will be described. FIG. 7 is a diagram for explaining a cross-sectional configuration of a semiconductor energy ray detection element according to a fourth modification of the present embodiment.

半導体エネルギー線検出素子ＥＤ５は、Ａｌ２Ｏ３からなる膜４１を備えている。膜４１は、半導体基板１の側面１ｃとして露出する第一半導体領域３の表面を覆うように配置されている。Ａｌ２Ｏ３は、覆われた第一半導体領域３の表面側に正の固定電荷を存在させるためのパッシベーション材料である。膜４１は、半導体基板１の側面１ｃ上に形成され、側面１ｃが膜４１で覆われる。すなわち、第一半導体領域３だけでなく、半導体基板１の側面１ｃとして露出する第二半導体領域５及び第五半導体領域１１の表面も、膜４１で覆われている。膜４１は、たとえば、ＡＬＤ（Atomic Layer Deposition）法により成膜される。 The semiconductor energy ray detection element ED5 includes a film 41 made of Al 2 O 3 . The film 41 is disposed so as to cover the surface of the first semiconductor region 3 exposed as the side surface 1 c of the semiconductor substrate 1. Al 2 O 3 is a passivation material for allowing positive fixed charges to exist on the surface side of the covered first semiconductor region 3. The film 41 is formed on the side surface 1 c of the semiconductor substrate 1, and the side surface 1 c is covered with the film 41. That is, not only the first semiconductor region 3 but also the surfaces of the second semiconductor region 5 and the fifth semiconductor region 11 exposed as the side surface 1 c of the semiconductor substrate 1 are covered with the film 41. The film 41 is formed by, for example, an ALD (Atomic Layer Deposition) method.

半導体エネルギー線検出素子ＥＤ５では、Ａｌ２Ｏ３からなる膜４１で覆われた第一半導体領域３の表面側には、正の固定電荷が存在する。正の固定電荷が存在している第一半導体領域３の上記表面側の領域は、アキュムレーション層４３として機能する。膜４１は、第一半導体領域３の表面上において、第五半導体領域１１との界面と、第二半導体領域５との界面と、にわたって半導体基板１の厚み方向に延びている。これにより、第一半導体領域３が完全空乏化された状態で、空乏層が半導体基板１の側面１ｃに到達するのが抑制される。 In the semiconductor energy ray detection element ED5, positive fixed charges exist on the surface side of the first semiconductor region 3 covered with the film 41 made of Al 2 O 3 . The region on the surface side of the first semiconductor region 3 where positive fixed charges are present functions as an accumulation layer 43. The film 41 extends in the thickness direction of the semiconductor substrate 1 across the interface with the fifth semiconductor region 11 and the interface with the second semiconductor region 5 on the surface of the first semiconductor region 3. This suppresses the depletion layer from reaching the side surface 1c of the semiconductor substrate 1 in a state where the first semiconductor region 3 is completely depleted.

膜４１は、半導体基板１の側面１ｃにおいて、第一半導体領域３の表面だけでなく、第二半導体領域５及び第五半導体領域１１の表面も覆っている。これにより、第一半導体領域３の上記表面が、膜４１で確実に覆われるため、空乏層が第一半導体領域３の上記表面（半導体基板１の側面１ｃ）に到達するのをより一層確実に抑制することができる。   The film 41 covers not only the surface of the first semiconductor region 3 but also the surfaces of the second semiconductor region 5 and the fifth semiconductor region 11 on the side surface 1 c of the semiconductor substrate 1. Thereby, since the surface of the first semiconductor region 3 is reliably covered with the film 41, the depletion layer can more reliably reach the surface of the first semiconductor region 3 (side surface 1c of the semiconductor substrate 1). Can be suppressed.

本変形例においても、半導体基板１は、必ずしも半導体領域３７を有している必要はない。しかしながら、空乏層が半導体基板１の側面１ｃに到達するのを確実に抑制するためには、半導体基板１は、半導体領域３７を有していることが好ましい。   Also in this modification, the semiconductor substrate 1 does not necessarily have the semiconductor region 37. However, in order to reliably suppress the depletion layer from reaching the side surface 1 c of the semiconductor substrate 1, the semiconductor substrate 1 preferably has the semiconductor region 37.

以上、本発明の好適な実施形態について説明してきたが、本発明は必ずしも上述した実施形態に限定されるものではなく、その要旨を逸脱しない範囲で様々な変更が可能である。   The preferred embodiments of the present invention have been described above. However, the present invention is not necessarily limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

第一導電型がＮ型であると共に、第二導電型がＰ型であってもよい。この場合には、絶縁膜１３が、上述したＳｉＯ２、又はＳｉ３Ｎ４からなることが好ましい。ＳｉＯ２又はＳｉ３Ｎ４は、覆われたＮ型の第一半導体領域３の表面側に負の固定電荷を存在させるためのパッシベーション材料である。 The first conductivity type may be an N type and the second conductivity type may be a P type. In this case, the insulating film 13 is preferably made of the above-described SiO 2 or Si 3 N 4 . SiO 2 or Si 3 N 4 is a passivation material for causing negative fixed charges to exist on the surface side of the covered N-type first semiconductor region 3.

絶縁膜１３は、半導体基板１の主面１ａとして露出する第一半導体領域３の表面を覆うように配置されている。したがって、絶縁膜１３が、ＳｉＯ２又はＳｉ３Ｎ４からなる場合、絶縁膜１３で覆われた第一半導体領域３の表面側には、負の固定電荷が存在する。負の固定電荷が存在している第一半導体領域３の上記表面側の領域は、図８に示されるように、アキュムレーション層４５として機能する。アキュムレーション層４５のうち、第四半導体領域９と第五半導体領域１１との間に位置する領域は、第四半導体領域９と第五半導体領域１１とを電気的に分離する。これにより、第一半導体領域３が完全空乏化された状態で、空乏層が半導体基板１の側面１ｃに到達するのが抑制される。 The insulating film 13 is disposed so as to cover the surface of the first semiconductor region 3 exposed as the main surface 1 a of the semiconductor substrate 1. Therefore, when the insulating film 13 is made of SiO 2 or Si 3 N 4 , negative fixed charges exist on the surface side of the first semiconductor region 3 covered with the insulating film 13. The region on the surface side of the first semiconductor region 3 where the negative fixed charge exists functions as an accumulation layer 45 as shown in FIG. In the accumulation layer 45, a region located between the fourth semiconductor region 9 and the fifth semiconductor region 11 electrically isolates the fourth semiconductor region 9 and the fifth semiconductor region 11. This suppresses the depletion layer from reaching the side surface 1c of the semiconductor substrate 1 in a state where the first semiconductor region 3 is completely depleted.

半導体基板１の形状、第三半導体領域７の数及び形状、並びに、第四及び第五半導体領域９，１１の形状は、上述した実施形態及び変形例に限られない。   The shape of the semiconductor substrate 1, the number and shape of the third semiconductor regions 7, and the shapes of the fourth and fifth semiconductor regions 9 and 11 are not limited to the above-described embodiments and modifications.

１…半導体基板、１ａ，１ｂ…主面、１ｃ…側面、３…第一半導体領域、５…第二半導体領域、７…第三半導体領域、９…第四半導体領域、１１…第五半導体領域、１３…絶縁膜、３１，３７，３９…半導体領域、４１…膜、４３，４５…アキュムレーション層、ＥＤ１，ＥＤ２，ＥＤ３，ＥＤ４，ＥＤ５…半導体エネルギー線検出素子。   DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 1a, 1b ... Main surface, 1c ... Side surface, 3 ... First semiconductor region, 5 ... Second semiconductor region, 7 ... Third semiconductor region, 9 ... Fourth semiconductor region, 11 ... Fifth semiconductor region , 13 ... Insulating film, 31, 37, 39 ... Semiconductor region, 41 ... Film, 43, 45 ... Accumulation layer, ED1, ED2, ED3, ED4, ED5 ... Semiconductor energy beam detecting element.

Claims (7)

互いに対向する第一主面と第二主面とを有する半導体基板を備えた半導体エネルギー線検出素子であって、
前記半導体基板は、
前記第一主面側に位置する第一導電型の第一半導体領域と、
前記第二主面側に位置し、前記第一半導体領域よりも不純物濃度が高い第一導電型の第二半導体領域と、
前記第一主面側に位置し、前記第一半導体領域とでエネルギー線感応領域を構成する、第二導電型の第三半導体領域と、
前記第一主面側において前記第三半導体領域が位置する領域の周囲を囲むように位置する、第二導電型の第四半導体領域と、
前記第一主面側において前記半導体基板の外縁に沿うように位置する、第二導電型の第五半導体領域と、を有することを特徴とする半導体エネルギー線検出素子。 A semiconductor energy ray detection element comprising a semiconductor substrate having a first main surface and a second main surface facing each other,
The semiconductor substrate is
A first semiconductor region of a first conductivity type located on the first main surface side;
A second semiconductor region of a first conductivity type located on the second main surface side and having an impurity concentration higher than that of the first semiconductor region;
A second semiconductor region of a second conductivity type, which is located on the first main surface side and constitutes an energy ray sensitive region with the first semiconductor region;
A fourth semiconductor region of a second conductivity type, which is positioned so as to surround a region where the third semiconductor region is located on the first main surface side;
A second energy-conducting fifth semiconductor region located along the outer edge of the semiconductor substrate on the first main surface side; 前記半導体基板は、前記第一主面側において前記第四半導体領域の周囲を囲むように前記第四半導体領域と前記第五半導体領域との間に位置し、前記第一半導体領域よりも不純物濃度が高い第一導電型の半導体領域を更に有することを特徴とする請求項１に記載の半導体エネルギー線検出素子。   The semiconductor substrate is located between the fourth semiconductor region and the fifth semiconductor region so as to surround the periphery of the fourth semiconductor region on the first main surface side, and has an impurity concentration higher than that of the first semiconductor region. The semiconductor energy ray detecting element according to claim 1, further comprising a semiconductor region having a high first conductivity type. 前記半導体基板は、前記半導体基板の側面に前記第一半導体領域が露出しないように前記側面側に位置し、前記第一半導体領域よりも不純物濃度が高い第一導電型の半導体領域を更に有することを特徴とする請求項１又は２に記載の半導体エネルギー線検出素子。   The semiconductor substrate further includes a first conductivity type semiconductor region located on the side surface so that the first semiconductor region is not exposed on the side surface of the semiconductor substrate and having a higher impurity concentration than the first semiconductor region. The semiconductor energy ray detecting element according to claim 1 or 2. 前記半導体基板の側面として露出する前記第一半導体領域の表面を覆うように配置され、覆われた前記第一半導体領域の前記表面側に所定の極性の固定電荷を存在させるためのパッシベーション材料からなる膜と、を更に備えることを特徴とする請求項１又は２に記載の半導体エネルギー線検出素子。   It is arranged so as to cover the surface of the first semiconductor region exposed as a side surface of the semiconductor substrate, and is made of a passivation material for allowing fixed charges having a predetermined polarity to exist on the surface side of the covered first semiconductor region. The semiconductor energy ray detection element according to claim 1, further comprising a film. 第一導電型がＰ型であると共に、第二導電型がＮ型であり、
前記パッシベーション材料が、Ａｌ２Ｏ３であることを特徴とする請求項４に記載の半導体エネルギー線検出素子。 The first conductivity type is P type and the second conductivity type is N type,
The semiconductor energy ray detecting element according to claim 4, wherein the passivation material is Al 2 O 3 . 前記半導体基板の前記第一主面として前記第二半導体領域と前記第三半導体領域との間の領域において露出する前記第一半導体領域の表面を覆うように配置され、覆われた前記第一半導体領域の前記表面側に所定の極性の固定電荷を存在させるためのパッシベーション材料からなる膜と、を更に備えることを特徴とする請求項１に記載の半導体エネルギー線検出素子。   The first semiconductor which is arranged and covered so as to cover the surface of the first semiconductor region exposed in the region between the second semiconductor region and the third semiconductor region as the first main surface of the semiconductor substrate The semiconductor energy ray detection element according to claim 1, further comprising a film made of a passivation material for causing a fixed charge having a predetermined polarity to exist on the surface side of the region. 第一導電型がＮ型であると共に、第二導電型がＰ型であり、
前記パッシベーション材料が、ＳｉＯ２又はＳｉ３Ｎ４であることを特徴とする請求項６に記載の半導体エネルギー線検出素子。 The first conductivity type is N type and the second conductivity type is P type,
The semiconductor energy ray detecting element according to claim 6, wherein the passivation material is SiO 2 or Si 3 N 4 .
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