JP2015050203A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a semiconductor device having a structure capable of controlling operation characteristics of a transistor.SOLUTION: A semiconductor device comprises: a semiconductor board SB1; a gate insulation film GI11 provided on the semiconductor board SB1; a gate insulation film GI12 which is provided on the semiconductor board SB1 and adjacent to the gate insulation film GI11 and has a film thickness different from that of the gate insulation film GI11; a gate electrode GE11 provided on the gate insulation film GI11; a gate electrode GE12 provided on the gate insulation film GI12; a side wall SW1 which is provided on a lateral face of a structure ST1 composed of the gate electrode GE11 and the gate electrode GE12 and which is formed by an insulating material; and first conductivity type source region SR1 and drain region DR1, which are provided on the semiconductor board SB1 to contact the side wall SW1 in planar view.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, for example, a technique applicable to a semiconductor device including a transistor and a manufacturing method thereof.

  Various studies have been made on transistors in order to improve their performance. For example, Patent Documents 1 to 4 describe technologies relating to MOS (Metal-Oxide-Semiconductor) transistors.

Patent Document 1 describes a MOS transistor having a Gate-OverLapped-Drain structure. Specifically, it is described that a conductive side spacer and a conductive thin film that electrically connects the side spacer and the gate electrode are formed. The technique described in Patent Document 2 relates to a gate overlap LDD (Light-Doped-Drain) transistor. Specifically, it is described that the side wall provided on the side surface of the gate electrode is formed of polycrystalline silicon having the same conductivity type as that of the low concentration layer formed thereunder.
The technique described in Patent Document 3 relates to a LDMOS (Laterally Diffused Metal Oxide Semiconductor) in which a drain region is separated from a gate electrode and a drift region is formed therebetween. Patent Document 4 describes that a gate electrode is divided into a plurality of gate electrodes through an insulator.

JP 2002-222946 A JP-A-5-218066 JP 2012-142441 A JP-A-5-326861

A semiconductor device including a transistor is required to have a structure capable of controlling the operation characteristics of the transistor from the viewpoint of improving the quality.
Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the second gate electrode is provided between the side surface of the first gate electrode and the sidewall. The second gate insulating film provided under the second gate electrode has a film thickness different from that of the first gate insulating film provided under the first gate electrode.

  According to the embodiment, it is possible to realize a semiconductor device having a structure capable of controlling the operation characteristics of the transistor.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. It is sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment. FIG. 9 is a cross-sectional view showing a modification of the semiconductor device shown in FIG. 8. It is sectional drawing which shows the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which shows the semiconductor device which concerns on 4th Embodiment. It is sectional drawing which shows the semiconductor device which concerns on 5th Embodiment. It is sectional drawing which shows the semiconductor device which concerns on 6th Embodiment. It is sectional drawing which shows the semiconductor device which concerns on 7th Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device shown in FIG. It is sectional drawing which shows the manufacturing method of the semiconductor device shown in FIG. FIG. 15 is a cross-sectional view showing a modification of the semiconductor device shown in FIG. 14. It is sectional drawing which shows the semiconductor device which concerns on 7th Embodiment. FIG. 19 is a cross-sectional view showing a modification of the semiconductor device shown in FIG. 18.

  Hereinafter, embodiments will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a cross-sectional view showing the semiconductor device SD1 according to the first embodiment. 2 to 7 are cross-sectional views showing a method for manufacturing the semiconductor device SD1 shown in FIG.

The semiconductor device SD1 according to this embodiment includes a semiconductor substrate SB1, a gate insulating film GI11, a gate insulating film GI12, a gate electrode GE11, a gate electrode GE12, a sidewall SW1, a source region SR1 and a drain region DR1. It is equipped with.
The gate insulating film GI11 is provided on the semiconductor substrate SB1. The gate insulating film GI12 is provided on the semiconductor substrate SB1 so as to be adjacent to the gate insulating film GI11, and has a film thickness different from that of the gate insulating film GI11. The gate electrode GE11 is provided on the gate insulating film GI11. The gate electrode GE12 is provided on the gate insulating film GI12. The sidewall SW1 is provided on the side surface of the structure ST1 including the gate electrode GE11 and the gate electrode GE12, and is formed of an insulating material. The source region SR1 and the drain region DR1 are provided in the semiconductor substrate SB1 so as to be in contact with the sidewall SW1 in plan view, and have the first conductivity type.

  In the semiconductor device SD1 according to this embodiment, the gate electrode GE12 is provided between the side surface of the gate electrode GE11 and the sidewall SW1 made of an insulating material. Further, the gate insulating film GI12 provided under the gate electrode GE12 has a film thickness different from that of the gate insulating film GI11 provided under the gate electrode GE11. In this case, the threshold voltage, on-current, leak current characteristics, etc. are adjusted by adjusting the material, film thickness, impurity concentration, etc. constituting the gate electrode GE12, or the material, film thickness, etc. constituting the gate insulating film GI12, respectively. The operation characteristics of the transistor TR1 can be controlled. Therefore, a semiconductor device capable of controlling the operating characteristics of the transistor can be realized.

  Hereinafter, the configuration of the semiconductor device SD1 and the method for manufacturing the semiconductor device SD1 according to the present embodiment will be described in detail.

First, the configuration of the semiconductor device SD1 will be described.
The semiconductor device SD1 includes a semiconductor substrate SB1 and a transistor TR1 provided on the semiconductor substrate SB1. In the present embodiment, the transistor TR1 is, for example, a memory cell transistor or a Logic transistor. Further, the semiconductor device SD1 according to the present embodiment can include transistors other than the transistor TR1. As the semiconductor substrate SB1, for example, a silicon substrate or a compound semiconductor substrate can be used.
The transistor TR1 according to this embodiment includes a gate insulating film GI11, a gate insulating film GI12, a gate electrode GE11, a gate electrode GE12, a sidewall SW1, a source region SR1, and a drain region DR1. .

The gate insulating film GI11 is provided on the semiconductor substrate SB1. The gate insulating film GI11 is formed of, for example, a silicon oxide film, a silicon oxynitride film, an insulating film made of a high dielectric constant material such as Hf, HfSiO, or HfSiON, or a laminated film in which two or more of these layers are laminated. The physical film thickness of the gate insulating film GI11 is, for example, not less than 1.0 nm and not more than 21 nm. In addition, the equivalent SiO ₂ film thickness of the gate insulating film GI11 is, for example, not less than 0.5 nm and not more than 20 nm. Accordingly, it is possible to reduce the on-resistance and miniaturize the semiconductor device while suppressing an increase in leakage current.

  The gate insulating film GI12 is provided on the semiconductor substrate SB1 so as to be adjacent to the gate insulating film GI11. In the present embodiment, for example, the gate insulating film GI12 is provided at least on the drain region DR1 side as viewed from the gate insulating film GI11. FIG. 1 illustrates the case where the gate insulating film GI12 is provided on the drain region DR1 side as viewed from the gate insulating film GI11 and is not provided on the source region SR1 side.

The gate insulating film GI12 is formed of, for example, a silicon oxide film, a silicon oxynitride film, an insulating film made of a high dielectric constant material such as Hf, HfSiO, or HfSiON, or a laminated film in which two or more of these layers are laminated. The material constituting the gate insulating film GI12 may be the same as or different from the material constituting the gate insulating film GI11.
In the present embodiment, the gate insulating film GI12 can be made of a material having a dielectric constant different from that of the material forming the gate insulating film GI11, for example. In this case, it is possible to control the operation characteristics of the transistor TR1, such as the threshold voltage and the on-current, by adjusting the dielectric constant of the gate insulating film GI12. On the other hand, the gate insulating film GI11 and the gate insulating film GI12 may be made of materials having the same dielectric constant.

  The gate insulating film GI12 has a film thickness different from that of the gate insulating film GI11. In this case, the thickness of the gate insulating film GI12 can be set separately from the thickness of the gate insulating film GI11. Therefore, the film thickness of the gate insulating film GI12 can be adjusted to control the operation characteristics of the transistor TR1. Here, the operating characteristics of the transistor TR1 include, for example, an on-current, a threshold voltage, and a leakage current characteristic.

In the present embodiment, the case where the gate insulating film GI11 and the gate insulating film GI12 have different physical film thicknesses is exemplified. Here, the physical film thickness of the gate insulating film GI12 can be made larger than, for example, the physical film thickness of the gate insulating film GI11. Thereby, the electric field under the gate electrode GE12 can be relaxed. For this reason, when the transistor TR1 is in the on state, the electric field strength in the vicinity of the drain region DR1 of the transistor TR1 can be relaxed, and characteristic deterioration due to hot carriers can be suppressed. Further, when the transistor TR1 is in an off state, the electric field strength in the vicinity of the drain region DR1 of the transistor TR1 can be relaxed, and leakage current due to GIDL (Gate-Induced-Drain-Leakage) can be reduced.
On the other hand, the physical thickness of the gate insulating film GI12 may be smaller than the physical thickness of the gate insulating film GI11. In this case, the on-state current of the transistor TR1 can be improved.
Note that the physical film thicknesses of the gate insulating film GI11 and the gate insulating film GI12 can be observed from a cross-sectional photograph obtained by, for example, a transmission electron microscope.

The ratio d ₂ / d ₁ of the physical film thickness d ₂ of the gate insulating film GI 12 to the physical film thickness d ₁ of the gate insulating film GI 11 is not particularly limited, but can be, for example, 1.1 or more and 30 or less. In this case, miniaturization of the semiconductor device can be promoted while effectively suppressing characteristic deterioration due to leakage current such as GIDL and hot carriers. At this time, the physical film thickness of the gate insulating film GI12 is preferably set to, for example, not less than 1.1 nm and not more than 30 nm.
D ₂ / d ₁ may be 0.05 or more and 0.9 or less. In this case, the on-current of the transistor TR1 can be effectively improved while suppressing an increase in leakage current. At this time, the physical film thickness of the gate insulating film GI12 is preferably set to, for example, not less than 0.9 nm and not more than 20 nm.

In the present embodiment, the gate insulating film GI11 and the gate insulating film GI12 may have different SiO ₂ film equivalent film thicknesses. In this case, the equivalent SiO ₂ film thickness of the gate insulating film GI12 can be made thicker or thinner than the equivalent SiO ₂ film thickness of the gate insulating film GI11 depending on the required transistor characteristics.
The ratio EOT ₂ / EOT ₁ of the SiO ₂ film equivalent film thickness EOT ₂ of the gate insulating film GI 12 to the SiO ₂ film equivalent film thickness EOT ₁ of the gate insulating film GI 11 is not particularly limited, but is, for example, 1.2 to 62 be able to. In this case, miniaturization of the semiconductor device can be promoted while more effectively suppressing characteristic deterioration due to leakage current such as GIDL and hot carriers. At this time, the equivalent SiO ₂ film thickness of the gate insulating film GI12 is preferably, for example, not less than 0.6 nm and not more than 31 nm.
Further, EOT ₂ / EOT ₁ may be 0.05 or more and 0.8 or less. In this case, the on-current of the transistor TR1 can be more effectively improved while suppressing an increase in leakage current. At this time, the equivalent SiO ₂ film thickness of the gate insulating film GI12 is preferably not less than 0.4 nm and not more than 19 nm, for example.
The gate insulating film GI11 and the gate insulating film GI12 may have the same equivalent SiO ₂ film thickness. In this case, the gate insulating film GI11 and the gate insulating film GI12 may have the same equivalent SiO ₂ film thickness while having different physical film thicknesses, for example.

  The gate electrode GE11 is provided on the gate insulating film GI11. The gate electrode GE11 is constituted by, for example, a polycrystalline silicon film, an amorphous silicon film, a silicide film, a metal film, or a laminated film in which two or more of these layers are laminated. When the gate electrode GE11 is formed of a polycrystalline silicon film or an amorphous silicon film, impurity ions may be implanted into the gate electrode GE11.

The gate electrode GE12 is provided on the gate insulating film GI12. In the present embodiment, the gate electrode GE12 is provided at least on the drain region DR1 side as viewed from the gate electrode GE11. FIG. 1 illustrates the case where the gate electrode GE12 is provided on the drain region DR1 side as viewed from the gate electrode GE11 and is not provided on the source region SR1 side.
In the present embodiment, the gate insulating film GI11 and the gate insulating film GI12 have different film thicknesses. Therefore, the lower end of the gate electrode GE11 provided on the gate insulating film GI11 and the lower end of the gate electrode GE12 provided on the gate insulating film GI12 have different heights from the surface of the semiconductor substrate SB1.

  The gate electrode GE12 is constituted by, for example, a polycrystalline silicon film, an amorphous silicon film, a silicide film, a metal film, or a laminated film in which two or more of these layers are laminated. In the present embodiment, the gate electrode GE12 can be made of a material different from that of the gate electrode GE11, for example. In this case, the work function of the gate electrode GE12 can be adjusted separately from the gate electrode GE11. This makes it possible to control the operation characteristics of the transistor TR1, such as the threshold voltage and the on-current. Note that the gate electrode GE11 and the gate electrode GE12 may be made of the same material.

When the gate electrode GE12 is composed of a polycrystalline silicon film or an amorphous silicon film, impurity ions may be implanted into the gate electrode GE12. In the present embodiment, the impurity concentration in the gate electrode GE12 can be made different from, for example, the impurity concentration in the gate electrode GE11. Also in this case, the SiO ₂ equivalent film thickness of the gate electrode GE12 can be adjusted separately from the gate electrode GE11. Therefore, it is possible to control the operation characteristics of the transistor TR1, such as the threshold voltage and the on-current. The gate electrode GE11 and the gate electrode GE12 may have the same impurity concentration.
In the present embodiment, for example, after forming the gate electrode GE12 on the side surface of the gate electrode GE11 into which the impurity ions have been implanted, impurity ions are implanted into the gate electrode GE11 and the gate electrode GE12, whereby the gate electrode GE11 and the gate are formed. The impurity concentrations of the electrodes GE12 can be different from each other.

  The gate electrode GE12 has a film thickness different from that of the gate electrode GE11, for example. In this case, the thickness of the gate electrode GE12 can be adjusted separately from the thickness of the gate electrode GE11. Therefore, by adjusting the film thickness of the gate electrode GE12, it is possible to control the operation characteristics of the transistor TR1, such as the threshold voltage. Note that the gate electrode GE12 and the gate electrode GE11 may have the same film thickness. Here, the film thicknesses of the gate electrode GE11 and the gate electrode GE12 indicate physical film thicknesses in the normal direction relative to the plane of the semiconductor substrate SB1.

The ratio l ₂ / l ₁ of the length l ₂ of the gate electrode GE12 in the gate length direction to the length l ₁ of the gate electrode GE11 in the gate length direction can be, for example, 0.001 or more and 0.990 or less.

FIG. 1 illustrates a case where the transistor TR1 has an insulating film IF1 provided continuously between the gate electrode GE11 and the gate electrode GE12 and under the gate electrode GE12. At this time, the gate insulating film GI12 is a portion located under the gate electrode GE12 in the insulating film IF1. Such a structure is obtained by a method for manufacturing the semiconductor device SD1 described later. In this case, the gate insulating film GI12 can be formed by patterning the insulating film IF1 using the gate electrode GE12 as a mask without performing a lithography process. Therefore, the gate insulating film GI12 can be easily formed.
As a material constituting the insulating film IF1, for example, those exemplified above as the material constituting the gate insulating film GI12 can be used.

The sidewall SW1 is provided on the side surface of the structure ST1 including the gate electrode GE11 and the gate electrode GE12. In the example shown in FIG. 1, the gate insulating film GI11 and the insulating film IF1 also form part of the structure ST1 together with the gate electrode GE11 and the gate electrode GE12. In the example shown in FIG. 1, the gate electrode GE12 is not provided on the source region SR1 side as viewed from the gate electrode GE11. In this case, the sidewall SW1 is provided on the side surface of the gate electrode GE11 on the source region SR1 side as viewed from the structure ST1, and the sidewall SW1 is provided on the side surface of the gate electrode GE12 on the drain region DR1 side.
The sidewall SW1 is made of an insulating material. Examples of the insulating material constituting the sidewall SW1 include a silicon nitride film or a silicon oxide film.

FIG. 1 illustrates the case where an insulating film IF3 is formed between the sidewall SW1 and the structure ST1. The insulating film IF3 functions as a spacer film, for example. Therefore, by forming the insulating film IF3, it is possible to control the lengths of extension regions ER1 and LDD regions LR1, which will be described later, and the positions of the source region SR1 and the drain region DR1. In the example shown in FIG. 1, the insulating film IF3 is provided between the sidewall SW1 and the gate electrode GE11 on the source region SR1 side as viewed from the structure ST1, and the sidewall SW1 and the gate electrode GE12 on the drain region DR1 side as viewed from the structure ST1. Insulating film IF3 is provided between each of them.
The insulating film IF3 is made of, for example, a silicon oxide film or a silicon nitride film.

  The source region SR1 and the drain region DR1 are provided in the semiconductor substrate SB1 so as to be in contact with the sidewall SW1 in plan view. Here, contacting with the side wall SW1 includes a case where the side wall SW1 is adjacent to the side wall SW1 in a plan view and a case where the side wall SW1 overlaps the side wall SW1. Such a configuration can be obtained by forming the source region SR1 and the drain region DR1 by ion implantation using the sidewall SW1 as a mask.

The source region SR1 and the drain region DR1 have the first conductivity type.
The source region SR1 and the drain region DR1 are formed, for example, in a second conductivity type well WL1 provided in the semiconductor substrate SB1. That is, the source region SR1 and the drain region DR1 are formed in wells of the same conductivity type. The second conductivity type is a conductivity type opposite to the first conductivity type. That is, the first conductivity type is either p-type or n-type, and the second conductivity type is either p-type or n-type.

The semiconductor device SD1 includes, for example, an extension region ER1 or an LDD (Light-Doped-Drain) region LR1 provided between the source region SR1 and the drain region DR1 so as to be adjacent to the source region SR1 or the drain region DR1. FIG. 1 illustrates the case where the extension region ER1 or the LDD region LR1 is formed at each of a position adjacent to the source region SR1 and a position adjacent to the drain region DR1.
Extension region ER1 and LDD region LR1 have the first conductivity type, and have an impurity concentration lower than that of source region SR1 and drain region DR1. Therefore, it is possible to suppress the short channel effect in the transistor TR1. In the present embodiment, the extension region ER1 is an impurity diffusion layer having a higher impurity concentration than the LDD region LR1. Whether to form the extension region ER1 or the LDD region LR1 can be selected based on factors such as reduction of the on-resistance, suppression of the short channel effect, or electric field relaxation.

When at least a part of the gate electrode GE12 overlaps with the extension region ER1 or LDD region LR1, a portion of the extension region ER1 or LDD region LR1 that overlaps with the gate electrode GE12 and the other portion have different impurity concentrations, for example. Can have. In this case, the impurity concentration in the portion overlapping with the gate electrode GE12 can be adjusted to control the operation characteristics of the transistor TR1 such as the on-current. In the extension region ER1 or the LDD region LR1, a portion overlapping with the gate electrode GE12 and the other portion may have the same impurity concentration.
In the present embodiment, for example, the impurity concentration of the extension region ER1 or the LDD region LR1 in the extension region ER1 or the LDD region LR1 that overlaps with the gate electrode GE12 and the other portion can be made different from each other. First, the extension region ER1 or the LDD region LR1 is formed by impurity ion implantation using the gate electrode GE11 as a mask. Next, the gate electrode GE12 is formed on the side surface of the gate electrode GE11. Next, impurity ion implantation is performed using the gate electrode GE11 and the gate electrode GE12 as a mask to increase the impurity concentration in the exposed region of the extension region ER1 or the LDD region LR1.

  The semiconductor device SD1 includes a channel region CR1 provided between the source region SR1 and the drain region DR1. In the present embodiment, the channel region CR1 is a region located on the surface of the semiconductor substrate SB1 in the well WL1, and is a region sandwiched between the source region SR1 and the drain region DR1. In the example shown in FIG. 1, the channel region CR1 is formed by an extension region ER1 or LDD region LR1 provided adjacent to the source region SR1, and an extension region ER1 or LDD region LR1 provided adjacent to the drain region DR1. Matches the area that is sandwiched.

In the present embodiment, the gate electrode GE12 is provided, for example, so that at least a part of the gate electrode GE12 overlaps the channel region CR1 in plan view. In this case, by adjusting the work function of the gate electrode GE12, the thickness of the gate insulating film GI12, the dielectric constant, and the like, the channel resistance in the channel region CR1 can be reduced and the on-state current of the transistor TR1 can be improved. .
On the other hand, the gate electrode GE12 may not overlap with the channel region CR1 in plan view. In this case, the gate electrode GE12 can reduce the resistance in the extension region ER1 or the LDD region LR1, thereby improving the on-current.

When at least part of the gate electrode GE12 overlaps with the channel region CR1, the portion of the channel region CR1 that overlaps with the gate electrode GE11 and the portion of the channel region CR1 that overlaps with the gate electrode GE12 may have different impurity concentrations, for example. it can. In this case, the impurity concentration in the portion overlapping the gate electrode GE12 in the channel region CR1 can be adjusted separately from the other portions. This makes it possible to control the operating characteristics of the transistor TR1, such as the threshold voltage. The portion of the channel region CR1 that overlaps with the gate electrode GE11 and the portion of the channel region CR1 that overlaps with the gate electrode GE12 may have the same impurity concentration.
In the present embodiment, the channel impurity concentration in the channel region CR1 in the gate length direction and the depth direction is controlled by impurity ion implantation in each step between the formation of the gate electrode GE11 and before the formation of the sidewall SW1. Thereby, in the channel region CR1, the impurity concentration of the portion overlapping the gate electrode GE11 and the portion overlapping the gate electrode GE12 can be made different from each other. An example of a method for controlling the impurity concentration in the channel region CR1 is as follows. First, the gate electrode GE11 is formed on the semiconductor substrate SB1 in which the well WL1 is formed. Next, impurity ions are implanted into the well WL1 using the gate electrode GE11 as a mask to increase the impurity concentration in the exposed region of the well WL1. Next, the gate electrode GE12 is formed on the side surface of the gate electrode GE11.

The semiconductor device SD1 includes, for example, a silicide layer SL1 formed on the gate electrode GE11 and the gate electrode GE12. The silicide layer SL1 electrically connects the gate electrode GE11 and the gate electrode GE12. This makes it possible to apply a voltage to the gate electrode GE11 and to apply a voltage to the gate electrode GE12 via the silicide layer SL1. In this case, since it is not necessary to form a contact via on the gate electrode GE12, the length of the gate electrode GE12 in the gate length direction can be miniaturized. Examples of the metal material constituting the silicide layer SL1 include Ti, Co, Ni, and Pt.
Note that the gate electrode GE11 and the gate electrode GE12 may be electrically connected to each other by, for example, a contact plug provided on each of them and a wiring provided on the contact plug. In this case, the silicide layer SL1 may not be formed.

  The semiconductor device SD1 includes, for example, a silicide layer SL2 provided in each of the source region SR1 and the drain region DR1. Silicide layer SL2 is provided, for example, adjacent to sidewall SW1 in plan view. Thereby, the contact resistance in the source region SR1 and the drain region DR1 can be reduced. Examples of the metal material constituting the silicide layer SL2 include Ti, Co, Ni, and Pt.

  The transistor TR1 according to this embodiment can be considered to be configured by a first transistor including the gate insulating film GI11 and the gate electrode GE11 and a second transistor including the gate insulating film GI12 and the gate electrode GE11. The threshold voltage of the second transistor may be the channel region CR1 or the extension region ER1 such as the material, film thickness, impurity concentration, etc., the material constituting the gate insulating film GI12, the film thickness, etc. It is possible to control by adjusting the impurity concentration distribution and the like in the LDD region LR1. In this way, by controlling the threshold voltage of the second transistor, the threshold voltage per unit gate length of the first transistor and the second transistor can be made different, and the operating characteristics of the transistor TR1 can be controlled. .

Next, a method for manufacturing the semiconductor device SD1 will be described.
The manufacturing method of the semiconductor device SD1 according to this embodiment is performed as follows, for example.
First, a conductive film is formed over the semiconductor substrate SB1. Next, the conductive film is etched to form the gate electrode GE11. Next, a conductive film CF1 is formed so as to cover the gate electrode GE11. Next, etch back is performed on the conductive film CF1 so that a portion located on the side surface of the gate electrode GE11 remains to form the gate electrode GE12 on the side surface of the gate electrode GE11. Next, a sidewall SW1 made of an insulating material is formed on the side surface of the structure ST1 made of the gate electrode GE11 and the gate electrode GE12. Next, ion implantation is performed on the semiconductor substrate SB1 using the structure ST1 and the sidewall SW1 as a mask to form the source region SR1 and the drain region DR1 in the semiconductor substrate SB1. Next, a silicide layer is formed on the upper surface of the gate electrode GE11, the upper surface of the gate electrode GE12, the upper surface of the source region SR1, and the upper surface of the drain region DR1.
Hereinafter, a method for manufacturing the semiconductor device SD1 according to the present embodiment will be described in detail.

First, an insulating film and a conductive film are sequentially formed on the semiconductor substrate SB1. As the material constituting the insulating film, those exemplified above as the insulating material constituting the gate insulating film GI11 can be used. In addition, as the conductive film, those exemplified above as the conductive material constituting the gate electrode GE11 can be used. Next, the insulating film and the conductive film are patterned by dry etching. Thereby, the gate insulating film GI11 and the gate electrode GE11 are formed on the semiconductor substrate SB1.
Next, an insulating film IF1 is formed over the semiconductor substrate SB1 so as to cover the gate electrode GE11. As a result, the structure shown in FIG.

  Next, as shown in FIG. 2B, a conductive film CF1 is formed over the insulating film IF1. The conductive film CF1 is formed using, for example, a CVD (Chemical Vapor Deposition) method. As the material for forming the conductive film CF1, those exemplified above as the conductive material for forming the gate electrode GE12 can be used.

Next, as shown in FIG. 3A, the conductive film CF1 is etched back so that a portion located on the side surface of the gate electrode GE11 remains. As a result, the gate electrode GE12 is formed on the side surface of the gate electrode GE11 via the insulating film IF1.
In the above-described step of etching back the conductive film CF1, the insulating film IF1 can function as an etching stopper film. For this reason, even after the step, the gate electrode GE11 and the semiconductor substrate SB1 are covered with the insulating film IF1.

Next, a resist film RF1 that covers a part of the gate electrode GE12 is formed on the insulating film IF1. In the present embodiment, for example, the resist film RF1 is formed so as to cover a portion of the gate electrode GE12 adjacent to the region where the drain region DR1 is formed in plan view. At this time, a portion of the gate electrode GE12 adjacent to the region where the source region SR1 is formed in plan view is exposed without being covered with the resist film RF1.
Next, a portion of the gate electrode GE12 that is not covered with the resist film RF1 is selectively removed by etching. Here, for example, radical plasma etching is performed. In the present embodiment, for example, a portion of the gate electrode GE12 adjacent to the region where the source region SR1 is formed in plan view is selectively removed.
Thereby, the structure shown in FIG. 3B is obtained.

Next, as shown in FIG. 4A, the resist film RF1 is removed by ashing or the like.
Next, as shown in FIG. 4B, the insulating film IF1 is removed by etching using the gate electrode GE12 as a mask. Here, for example, wet etching is performed. As a result, portions of the insulating film IF1 located between the gate electrode GE11 and the gate electrode GE12 and below the gate electrode GE12 remain. Thus, in this embodiment, it is not necessary to add a lithography process for patterning the insulating film IF1.

Next, as shown in FIG. 5A, ion implantation is performed on the semiconductor substrate SB1 using the structure ST1 including the gate electrode GE11 and the gate electrode GE12 as a mask. Thereby, the extension region ER1 or the LDD region LR1 is formed on the surface of the semiconductor substrate SB1. Note that the step of forming the extension region ER1 or the LDD region LR1 may be performed after the step of forming the gate electrode GE11 and before the step of forming the gate electrode GE12.
Next, as illustrated in FIG. 5B, an insulating film IF3 is formed over the semiconductor substrate SB1 so as to cover the gate electrode GE11 and the gate electrode GE12. In order to control the overlap length of the extension region ER1 or LDD region LR1 below the gate in consideration of lateral impurity diffusion, the extension region ER1 or LDD region LR1 is formed here by ion implantation. Also good.

Next, as shown in FIG. 6A, the insulating film IF3 is etched back. As a result, a portion of the insulating film IF3 located on the side surface of the structure ST1 configured by the gate electrode GE11 and the gate electrode GE12 remains. Therefore, the upper surface of the gate electrode GE11, the upper surface of the gate electrode GE12, and the surface of the semiconductor substrate SB1 are not covered with the insulating film IF3 and are exposed. Note that the formation of the extension region ER1 or the LDD region LR1 by ion implantation may be performed here.
Next, as shown in FIG. 6B, a sidewall SW1 is formed on the side surface of the structure ST1 including the gate electrode GE11 and the gate electrode GE12. The sidewall SW1 is formed by etching back an insulating film provided on the semiconductor substrate SB1 so as to cover the gate electrode GE11 and the gate electrode GE12, for example.

  Next, as shown in FIG. 7A, ion implantation is performed on the semiconductor substrate SB1 using the structure ST1 including the gate electrode GE11 and the gate electrode GE12 and the sidewall SW1 as a mask, and the source is supplied to the semiconductor substrate SB1. Region SR1 and drain region DR1 are formed. Here, for example, ion implantation is performed under conditions in which the dose amount and the implantation energy are higher than those in the above-described step of forming the extension region ER1 or the LDD region LR1.

Next, as shown in FIG. 7B, the silicide layer SL1 is formed on the upper surface of the gate electrode GE11 and the upper surface of the gate electrode GE12, and the silicide layer SL2 is formed on the upper surface of the source region SR1 and the upper surface of the drain region DR1, respectively. . Thereby, the gate electrode GE11 and the gate electrode GE12 are electrically connected to each other by the silicide layer SL1.
The silicide layer SL1 and the silicide layer SL2 are formed as follows, for example. First, after removing an oxide film such as a natural oxide film on the semiconductor substrate SB1, the gate electrode GE11, and the gate electrode GE12, a metal film is formed on the semiconductor substrate SB1, the gate electrode GE11, and the gate electrode GE12. Form. Examples of the metal material constituting the metal film include Ti, Co, Ni, and Pt. Next, the metal film, the semiconductor substrate SB1, the gate electrode GE11, and the gate electrode GE12 are reacted by heat treatment to form a silicide layer SL1 and a silicide layer SL2. Thereafter, the unreacted metal film is removed.

Thereafter, a multilayer wiring layer is formed on the semiconductor substrate SB1 so as to cover the transistor TR1.
In the present embodiment, for example, the semiconductor device SD1 is formed in this way.

Next, the effect of this embodiment will be described.
According to the present embodiment, the gate electrode GE12 is provided between the side surface of the gate electrode GE11 and the sidewall SW1 made of an insulating material. Further, the gate insulating film GI12 provided under the gate electrode GE12 has a film thickness different from that of the gate insulating film GI11 provided under the gate electrode GE11. In this case, the threshold voltage, on-current, leak current characteristics, etc. are adjusted by adjusting the material, film thickness, impurity concentration, etc. constituting the gate electrode GE12, or the material, film thickness, etc. constituting the gate insulating film GI12. The operation characteristics of the transistor TR1 can be controlled. Therefore, a semiconductor device capable of controlling the operation characteristics of the transistor can be realized.

(Second Embodiment)
FIG. 8 is a cross-sectional view showing a semiconductor device SD2 according to the second embodiment, and corresponds to FIG. 1 in the first embodiment. The semiconductor device SD2 according to the present embodiment can have the same configuration as the semiconductor device SD1 according to the first embodiment except for the configuration of the insulating film IF1.

  The insulating film IF1 is continuously provided between the gate electrode GE11 and the gate electrode GE12, under the gate electrode GE12, and under the sidewall SW1. In this case, the insulating film IF1 is patterned together with the sidewall SW1 in the etch-back process for forming the sidewall SW1. That is, in the region where the extension region ER1 or the LDD region LR1 is formed on the surface of the semiconductor substrate SB1, damage due to the etching process of the insulating film IF1 or the insulating film IF3 occurs, or unnecessary impurities are generated during the etching process. It is possible to suppress the injection. For this reason, it is possible to further improve the on-current in the transistor TR1 and further reduce the leakage current.

  In the manufacturing method of the semiconductor device SD2 according to the present embodiment, impurity ion implantation is performed using the gate electrode GE11 and the gate electrode GE12 as a mask in a state where the surfaces of the gate electrode GE11 and the semiconductor substrate SB1 are covered with the insulating film IF1. The extension region ER1 or the LDD region LR1 is formed. In addition, the insulating film IF1 is patterned together with the sidewall SW1 in an etch back process for forming the sidewall SW1. Except for these points, the manufacturing method of the semiconductor device SD2 according to the present embodiment can be performed in the same manner as the manufacturing method of the semiconductor device SD1 according to the first embodiment.

  FIG. 9 is a cross-sectional view showing a modification of the semiconductor device SD2 shown in FIG. FIG. 9 illustrates a case where the insulating film IF3 is not formed. In this case, the step of forming the insulating film IF3 can be omitted, and the number of manufacturing steps can be reduced.

  Also in this embodiment, the same effect as that of the first embodiment can be obtained.

(Third embodiment)
FIG. 10 is a cross-sectional view showing a semiconductor device SD3 according to the third embodiment, and corresponds to FIG. 1 in the first embodiment. The semiconductor device SD3 according to this embodiment can have the same configuration as the semiconductor device SD1 according to the first embodiment except for the configuration of the insulating film IF3.

  The insulating film IF3 is provided continuously between the structure ST1 constituted by the gate electrode GE11 and the gate electrode GE12 and the sidewall SW1, and under the sidewall SW1. In this case, the insulating film IF3 is patterned together with the sidewall SW1 in the etch back process for forming the sidewall SW1. That is, in the region where the extension region ER1 or the LDD region LR1 is formed in the surface of the semiconductor substrate SB1, damage due to the etching process of the insulating film IF3 occurs, or unnecessary impurities are implanted during the etching process. This can be suppressed. For this reason, it is possible to further improve the on-current in the transistor TR1 and further reduce the leakage current.

  In the method for manufacturing the semiconductor device SD3 according to the present embodiment, the insulating film IF3 is patterned together with the sidewall SW1 in the etch-back process for forming the sidewall SW1. Except for this point, the manufacturing method of the semiconductor device SD3 according to the present embodiment can be performed in the same manner as the manufacturing method of the semiconductor device SD1 according to the first embodiment.

  Also in this embodiment, the same effect as that of the first embodiment can be obtained.

(Fourth embodiment)
FIG. 11 is a cross-sectional view showing a semiconductor device SD4 according to the fourth embodiment, and corresponds to FIG. 1 in the first embodiment. The semiconductor device SD4 according to this embodiment can have the same configuration as the semiconductor device SD1 according to the first embodiment except that the semiconductor device SD4 includes the insulating film IF2.

The semiconductor device SD4 includes an insulating film IF2 made of a high dielectric constant material provided at least under the gate electrode GE12 between the insulating film IF1 and the gate electrode GE12. In this case, the operating characteristics of the transistor TR1 can be controlled by adjusting the film thickness, material, and the like of the insulating film IF2 that is a high dielectric constant film. Examples of the high dielectric constant material constituting the insulating film IF2 include Hf, HfSiO, and HfSiON.
In the present embodiment, by forming the insulating film IF2, for example, the threshold voltage of the transistor TR1 can be set high. For this reason, the roll-off characteristic in the transistor TR1 can be improved. Further, since the channel dose under the gate electrode GE12 can be reduced, the channel mobility can also be improved. Therefore, the on-state current of the transistor TR1 can be improved.
FIG. 11 illustrates the case where the insulating film IF2 is formed over the entire area between the insulating film IF1 and the gate electrode GE12. In this case, the insulating film IF2 can be etched together with the insulating film IF1 using the gate electrode GE12 as a mask.

  In the method for manufacturing the semiconductor device SD4 according to the present embodiment, the insulating film IF2 is formed on the insulating film IF1 after the step of forming the insulating film IF1 on the semiconductor substrate SB1 so as to cover the gate electrode GE11. The insulating film IF2 is patterned by wet etching simultaneously with the insulating film IF1, for example, using the gate electrode GE12 as a mask. Except for this point, the manufacturing method of the semiconductor device SD4 according to the present embodiment can be performed in the same manner as the manufacturing method of the semiconductor device SD1 according to the first embodiment.

  Also in this embodiment, the same effect as that of the first embodiment can be obtained.

(Fifth embodiment)
FIG. 12 is a cross-sectional view showing a semiconductor device SD5 according to the fifth embodiment, and corresponds to FIG. 1 in the first embodiment. The semiconductor device SD5 according to the present embodiment can have the same configuration as that of the semiconductor device SD1 according to the first embodiment, except that the configuration of the insulating film IF1 and the insulating film IF3 are not provided.

  As shown in FIG. 12, the insulating film IF1 is provided continuously between the gate electrode GE11 and the gate electrode GE12 and under the gate electrode GE12, and is provided on the side surface of the gate electrode GE11 that is not covered by the gate electrode GE12. It has been. That is, the gate electrode GE11 has the side surface on the source region SR1 side and the side surface on the drain region DR1 side covered with the insulating film IF1.

  In the method for manufacturing the semiconductor device SD5 according to this embodiment, the insulating film IF1 is patterned by, for example, etch back. Further, the step of forming the insulating film IF3 is not performed. Except for these points, the manufacturing method of the semiconductor device SD5 according to the present embodiment can be performed in the same manner as the manufacturing method of the semiconductor device SD1 according to the first embodiment.

  Also in this embodiment, the same effect as that of the first embodiment can be obtained.

(Sixth embodiment)
FIG. 13 is a cross-sectional view showing a semiconductor device SD6 according to the sixth embodiment, and corresponds to FIG. 12 in the fifth embodiment. The semiconductor device SD6 according to this embodiment can have the same configuration as the semiconductor device SD5 according to the fifth embodiment except for the configurations of the gate insulating film GI11 and the gate electrode GE11.

In the present embodiment, the gate insulating film GI11 is made of a high dielectric constant material. Further, at least the lower end portion of the gate electrode GE11 is configured by the metal film MF1. As a result, the insulating film capacitance C _ox in the transistor TR1 can be improved, and the on-current can be improved. Examples of the high dielectric constant material constituting the gate insulating film GI11 include Hf, HfSiO, and HfSiON. Further, examples of the metal material constituting the metal film MF1 include Ti, TiN, La, and Al. FIG. 13 illustrates a case where the lower end portion of the gate electrode GE11 is configured by the metal film MF1, and the other portion is configured by a polycrystalline silicon film or an amorphous silicon film.

  Also in this embodiment, the same effect as that of the first embodiment can be obtained.

(Seventh embodiment)
FIG. 14 is a cross-sectional view showing a semiconductor device SD7 according to the seventh embodiment, and corresponds to FIG. 1 in the first embodiment. 15 and 16 are cross-sectional views showing a method for manufacturing the semiconductor device SD7 shown in FIG. The semiconductor device SD7 according to the present embodiment can have the same configuration as that of the semiconductor device SD1 according to the first embodiment except that the semiconductor device SD7 does not include the insulating film IF1 and the configuration of the gate insulating film GI12.

In the present embodiment, the gate insulating film GI11 and the gate insulating film GI12 are integral with each other. That is, in the insulating film IF4 located under the gate electrode GE11 and the gate electrode GE12, the portion located under the gate electrode GE11 becomes the gate insulating film GI11, and the portion located under the gate electrode GE12 becomes the gate insulating film GI12. Thereby, a process of forming the gate insulating film GI12 separately from the process of forming the gate insulating film GI11 becomes unnecessary, and the number of manufacturing steps can be reduced. In the present embodiment, the insulating film IF1 shown in the first embodiment is not formed.
The portion of the insulating film IF4 that overlaps with the gate electrode GE12 has a different film thickness from the portion that overlaps with the gate electrode GE11. Thereby, the gate insulating film GI11 and the gate insulating film GI12 can have different thicknesses. FIG. 14 illustrates a case where one end portion on the drain region DR1 side of the end portion in the gate length direction of the insulating film IF4 has a film thickness different from that of other portions.

  The gate electrode GE11 and the gate electrode GE12 are in contact with each other. Thereby, the electrical connection between the gate electrode GE11 and the gate electrode GE12 can be improved. Here, the case where the gate electrode GE11 and the gate electrode GE12 are in contact with each other includes, for example, the case where the gate electrode GE11 and the gate electrode GE12 are in contact via the surface of the gate electrode GE11 or the surface of the gate electrode GE12. FIG. 14 illustrates a case where the side surface on the drain region DR1 side of the gate electrode GE11 and the side surface on the source region SR1 side of the gate electrode GE12 are in contact with each other.

The manufacturing method of the semiconductor device SD7 according to this embodiment is performed as follows, for example.
First, the insulating film IF4 and the conductive film are sequentially formed on the semiconductor substrate SB1. As the conductive film, those exemplified above as the conductive material constituting the gate electrode GE11 can be used. Next, the conductive film is patterned by dry etching to form a gate electrode GE11 on the semiconductor substrate SB1. At this time, by performing over-etching on the insulating film IF4, the film thickness in the portion of the insulating film IF4 that does not overlap with the gate electrode GE11 can be made thinner than the film thickness in the portion that overlaps with the gate electrode GE11. As a result, the structure shown in FIG.

Next, as shown in FIG. 15B, a conductive film CF1 is formed on the insulating film IF4 so as to cover the gate electrode GE11. At this time, the conductive film CF1 is provided in contact with the upper surface and the side surface of the gate electrode GE11. The conductive film CF1 can be formed using, for example, the method and material exemplified in the first embodiment.
Next, as shown in FIG. 16A, the conductive film CF1 is etched back so that the portion located on the side surface of the gate electrode GE11 remains. As a result, the gate electrode GE12 is formed on the side surface of the gate electrode GE11 so as to be in contact with the side surface.
In the above-described step of etching back the conductive film CF1, the insulating film IF4 can function as an etching stopper film. For this reason, even after the step, the gate electrode GE11 and the semiconductor substrate SB1 are covered with the insulating film IF4.

Next, a resist film RF1 that covers a part of the gate electrode GE12 is formed on the insulating film IF1. In the present embodiment, for example, the resist film RF1 is formed so as to cover a portion of the gate electrode GE12 adjacent to the region where the drain region DR1 is formed in plan view. Next, a portion of the gate electrode GE12 that is not covered with the resist film RF1 is selectively removed by etching.
Thereby, the structure shown in FIG. 16B is obtained.

  Thereafter, a process similar to the method for manufacturing the semiconductor device SD1 according to the first embodiment illustrated in FIGS. 4 to 7 can be performed to form the semiconductor device SD7.

  FIG. 17 is a cross-sectional view showing a modification of the semiconductor device SD7 shown in FIG. As shown in FIG. 17, the semiconductor device SD7 may not include the insulating film IF3. In this case, a process for manufacturing the insulating film IF3 is not necessary, and the number of manufacturing steps can be reduced.

  Also in this embodiment, the same effect as that of the first embodiment can be obtained.

(Eighth embodiment)
FIG. 18 is a cross-sectional view showing a semiconductor device SD8 according to the eighth embodiment, and corresponds to FIG. 1 in the first embodiment. The semiconductor device SD8 according to the present embodiment can have the same configuration as the semiconductor device SD1 according to the first embodiment except for the configurations of the gate electrode GE11 and the gate electrode GE12.

In the present embodiment, the gate electrode GE12 is provided on each of two side surfaces of the gate electrode GE11 whose normal direction is the gate length direction. In the example shown in FIG. 18, the gate electrode GE12 is formed on the side surface on the drain region DR1 side and the side surface on the source region SR1 side in the gate electrode GE11. In this case, the operation characteristics of the transistor TR1 can be controlled more effectively by adjusting the material of the gate electrode GE12.
In the present embodiment, the silicide layer SL1 is formed on the upper surface of the gate electrode GE11 and the upper surface of the gate electrode GE12 provided on the drain region DR1 side and the source region SR1 side of the gate electrode GE11. The structure ST1 includes the gate electrode GE11 and the gate electrode GE12 provided on the drain region DR1 side and the source region SR1 side of the gate electrode GE11. In this case, the sidewall SW1 is provided on the side surface of the gate electrode GE12 on both the source region SR1 side and the drain region DR1 side as viewed from the structure ST1. In the example shown in FIG. 18, the insulating film IF3 is provided between the sidewall SW1 and the gate electrode GE12 on each of the source region SR1 side and the drain region DR1 side as viewed from the structure ST1.

The gate insulating film GI12 is provided on each of one end side and the other end side in the gate length direction of the gate insulating film GI11. That is, the gate insulating film GI12 is provided on both the drain region DR1 side and the source region SR1 side when viewed from the gate insulating film GI11. In this case, the operation characteristics of the transistor TR1 can be more effectively controlled by adjusting the film thickness, material, and the like of the gate insulating film GI12.
In FIG. 18, an insulating film IF1 provided continuously between the gate electrode GE11 and the gate electrode GE12 and under the gate electrode GE12 is formed on both the drain region DR1 side and the source region SR1 side as viewed from the gate insulating film GI11. The At this time, on both the drain region DR1 side and the source region SR1 side, the portion of the insulating film IF1 located below the gate electrode GE12 becomes the gate insulating film GI12.

  In the method for manufacturing the semiconductor device SD8 according to the present embodiment, the step of selectively removing a part of the gate electrode GE12 by etching using the resist film RF1 as a mask is not performed. For this reason, the number of manufacturing steps can be reduced. Except for this point, the manufacturing method of the semiconductor device SD8 according to the present embodiment can be performed in the same manner as the manufacturing method of the semiconductor device SD1 according to the first embodiment.

  FIG. 19 is a cross-sectional view showing a modification of the semiconductor device SD8 shown in FIG. As illustrated in FIG. 19, the semiconductor device SD8 may not include the insulating film IF3. In this case, a process for manufacturing the insulating film IF3 is not necessary, and the number of manufacturing steps can be reduced.

  Also in this embodiment, the same effect as that of the first embodiment can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

SD1, SD2, SD3, SD4, SD5, SD6, SD7, SD8 Semiconductor device SB1 Semiconductor substrate TR1 Transistor GE11, GE12 Gate electrode ST1 Structure GI11, GI12 Gate insulating film SW1 Side wall SL1, SL2 Silicide layer SR1 Source region DR1 Drain region ER1 Extension region LR1 LDD region CR1 Channel region WL1 Well IF1, IF2, IF3, IF4 Insulating film CF1 Conductive film RF1 Resist film MF1 Metal film

Claims (16)

A semiconductor substrate;
A first gate insulating film provided on the semiconductor substrate;
A second gate insulating film provided on the semiconductor substrate adjacent to the first gate insulating film and having a film thickness different from that of the first gate insulating film;
A first gate electrode provided on the first gate insulating film;
A second gate electrode provided on the second gate insulating film;
A sidewall provided on a side surface of a structure configured by the first gate electrode and the second gate electrode and configured by an insulating material;
A source region and a drain region of a first conductivity type provided in the semiconductor substrate so as to be in contact with the sidewall in a plan view;
A semiconductor device comprising: The semiconductor device according to claim 1,
A semiconductor device comprising a first silicide layer formed on the first gate electrode and the second gate electrode and electrically connecting the first gate electrode and the second gate electrode. The semiconductor device according to claim 1,
A channel region provided between the source region and the drain region;
A semiconductor device in which at least a part of the second gate electrode overlaps with the channel region in plan view. The semiconductor device according to claim 1,
A semiconductor device comprising: a second silicide layer provided in each of the source region and the drain region so as to be adjacent to the sidewall in a plan view. The semiconductor device according to claim 1,
The semiconductor device wherein the source region and the drain region are formed in a second conductivity type well provided in the semiconductor substrate. The semiconductor device according to claim 1,
An extension region or LDD region of the first conductivity type provided between the source region and the drain region so as to be adjacent to the source region or the drain region and having a lower impurity concentration than the source region and the drain region; A semiconductor device provided. The semiconductor device according to claim 1,
A first insulating film provided continuously between the first gate electrode and the second gate electrode and under the second gate electrode;
The second gate insulating film is a semiconductor device that is a portion of the first insulating film located under the second gate electrode. The semiconductor device according to claim 7,
The semiconductor device, wherein the first insulating film is continuously provided between the first gate electrode and the second gate electrode, below the second gate electrode, and below the sidewall. The semiconductor device according to claim 7,
A semiconductor device comprising a second insulating film formed of a high dielectric constant material provided at least under the second gate electrode between the first insulating film and the second gate electrode. The semiconductor device according to claim 1,
A semiconductor device comprising a third insulating film provided continuously between the structure and the sidewall and below the sidewall. The semiconductor device according to claim 1,
The first gate insulating film is made of a high dielectric constant material,
A semiconductor device in which at least a lower end portion of the first gate electrode is formed of a metal film. The semiconductor device according to claim 1,
The first gate electrode and the second gate electrode are in contact with each other. The semiconductor device according to claim 1,
The semiconductor device in which the first gate insulating film and the second gate insulating film are integral with each other. The semiconductor device according to claim 1,
The second gate insulating film is a semiconductor device provided on each of one end side and the other end side in the gate length direction of the first gate insulating film. The semiconductor device according to claim 1,
The second gate electrode is a semiconductor device provided on each of two side surfaces of the first gate electrode whose normal direction is the gate length direction. Forming a first conductive film on a semiconductor substrate;
Etching the first conductive film to form a first gate electrode;
Forming a second conductive film so as to cover the first gate electrode;
Etching back the second conductive film so that a portion located on the side surface of the first gate electrode remains, and forming a second gate electrode on the side surface of the first gate electrode;
Forming a sidewall made of an insulating material on a side surface of a structure made of the first gate electrode and the second gate electrode;
Performing ion implantation on the semiconductor substrate using the structure and the sidewall as a mask to form a source region and a drain region in the semiconductor substrate;
Forming a silicide layer on an upper surface of the first gate electrode, an upper surface of the second gate electrode, an upper surface of the source region, and an upper surface of the drain region;
A method for manufacturing a semiconductor device comprising:

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