JP2015049391A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device allowing improvement in display quality.SOLUTION: The liquid crystal display device comprises: a first substrate which includes a gate wire G1 and a gate wire G2, a source wire S1 and a source wire S2, a switching element SW1 electrically connected to the gate wire G1 and the source wire S1, a switching element SW2 electrically connected to the gate wire G2 and the source wire S1, a pixel electrode PE1 electrically connected to the switching element SW1 and having a slit SLA extending in a first extension direction, a pixel electrode PE2 electrically connected to the switching element SW2 and having a slit SLB extending in a second extension direction, and which includes a common electrode CE facing the pixel electrode PE1 and the pixel electrode PE2; a second substrate which includes a blue color filter facing the pixel electrode PE1 and the pixel electrode PE2 between the source wire S1 and the source wire S2; a columnar spacer SP forming a cell gap between the first substrate and the second substrate and facing the blue color filter; and a liquid crystal layer.

Description

  Embodiments described herein relate generally to a liquid crystal display device.

  Liquid crystal display devices are used in various fields as display devices. In recent years, there has been an increasing demand for wide viewing angles in liquid crystal display devices. As a technique for realizing a wide viewing angle, there is an FFS (Fringe-Field Switching) mode. In particular, in the pseudo dual domain type FFS mode, the extension direction of the slit of the pixel electrode is alternately changed for each gate line, so that two types of domains are obtained in a pseudo manner on a panel having the same rubbing direction with respect to the pixel electrode. It is done.

  By the way, if a rubbing process is performed on a substrate on which columnar spacers for forming a cell gap between the substrates are formed, a difference occurs in the rubbing state with respect to the alignment film between the upstream side and the downstream side in the rubbing direction of the columnar spacers. Sometimes. When such a difference occurs in the rubbing state, a difference occurs in the alignment state of the liquid crystal molecules between the upstream side and the downstream side in the rubbing direction of the columnar spacer. For example, alignment failure of the liquid crystal molecules is caused on the downstream side. For this reason, there is a problem in that light leakage occurs in the pixel located downstream of the columnar spacer in the rubbing direction, resulting in a decrease in contrast ratio. In particular, when light is lost in a pixel having a high luminance, the contrast ratio can be significantly reduced. Further, when the color of the pixel located downstream of the columnar spacer in the rubbing direction is alternately different for each gate line, there is a problem that the chromaticity is different between the odd-numbered row and the even-numbered row.

JP 2012-113305 A

  An object of the present embodiment is to provide a liquid crystal display device capable of improving display quality.

According to this embodiment,
A first gate line and a second gate line; a first source line and a second source line that intersect the first gate line and the second gate line; and the first gate line and the first source line A first switching element electrically connected, a second switching element electrically connected to the second gate line and the first source line, and a first extension electrically connected to the first switching element. A first pixel electrode having a first slit extending in a direction and a second slit having a second slit extending in a second extending direction that is electrically connected to the second switching element and different from the first extending direction. A first substrate having two pixel electrodes, a common electrode having a common potential facing the first pixel electrode and the second pixel electrode, and the first source line and the second source line between the first source line and the second source line. First picture A second substrate having a blue color filter facing the electrode and the second pixel electrode; a columnar spacer that forms a cell gap between the first substrate and the second substrate and faces the blue color filter; There is provided a liquid crystal display device comprising a liquid crystal layer containing liquid crystal molecules held in the cell gap.

FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a display panel PNL constituting the liquid crystal display device of the present embodiment. FIG. 2 is a schematic plan view of a first configuration example of the pixels in the array substrate AR shown in FIG. 1 as viewed from the counter substrate CT side. FIG. 3 is a plan view schematically showing an example of the layout of the color filters CF1 to CF3 in the counter substrate CT shown in FIG. FIG. 4 is a cross-sectional view schematically showing the configuration of the display panel PNL including the pixels PX1 to PX3 and the columnar spacer SP2 shown in FIG. FIG. 5 is a schematic plan view of a second configuration example of the pixels in the array substrate AR shown in FIG. 1 as viewed from the counter substrate CT side.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a diagram schematically showing a configuration and an equivalent circuit of a display panel PNL constituting the liquid crystal display device of the present embodiment.

  In other words, the display panel PNL is an active matrix type transmissive liquid crystal display panel, and is held between the array substrate AR, the counter substrate CT arranged to face the array substrate AR, and the array substrate AR and the counter substrate CT. Liquid crystal layer LQ. The array substrate AR and the counter substrate CT are bonded together with a sealant SE in a state where a predetermined cell gap is formed between them. In the illustrated example, the sealing material SE is formed to have a rectangular frame-like closed loop shape. The cell gap is formed by columnar spacers (not shown) formed on the array substrate AR or the counter substrate CT. The liquid crystal layer LQ is held on the inner side surrounded by the sealing material SE in the cell gap between the array substrate AR and the counter substrate CT. The display panel PNL includes an active area ACT that displays an image on the inner side surrounded by the seal material SE. The active area ACT has, for example, a substantially rectangular shape and includes a plurality of pixels PX arranged in a matrix.

  In the active area ACT, the array substrate AR has a gate line G extending along the first direction X, a source line S extending along the second direction Y intersecting the first direction X, and a gate at each pixel PX. A switching element SW electrically connected to the wiring G and the source wiring S, a pixel electrode PE connected to the switching element SW in each pixel PX, a common electrode CE having a common potential, and the like are provided.

  Although the detailed configuration of the display panel PNL will be described later, the display panel PNL of the present embodiment mainly uses a lateral electric field such as an IPS (In-Plane Switching) mode and an FFS (Fringe Field Switching) mode. The mode can be applied, and both the pixel electrode PE and the common electrode CE are provided in the array substrate AR.

  Signal supply sources necessary for driving the display panel PNL such as the driving IC chip 2 and the flexible printed circuit (FPC) substrate 3 are located in the peripheral area PRP outside the active area ACT. In the illustrated example, the drive IC chip 2 and the FPC board 3 are mounted on the mounting portion MT of the array substrate AR that extends outward from the substrate end portion CTE of the counter substrate CT. The peripheral area PRP is an area surrounding the active area ACT and includes an area where the sealing material SE is disposed, and is formed in a rectangular frame shape.

  FIG. 2 is a schematic plan view of a first configuration example of the pixels in the array substrate AR shown in FIG. 1 as viewed from the counter substrate CT side. Here, a pixel structure to which an FFS mode, which is a mode using a lateral electric field, is described as an example, but only the main part necessary for the description is shown in the drawing.

  The array substrate AR includes gate lines G1 to G3, source lines S1 to S4, switching elements SW1 to SW6, a common electrode CE, pixel electrodes PE1 to PE6, columnar spacers SP1 to SP3, a first alignment film AL1, and the like.

  The gate wirings G1 to G3 extend along the first direction X, respectively. The source lines S1 to S4 extend substantially along the second direction Y and intersect the gate lines G1 to G3. These gate lines and source lines define the pixels PX1 to PX6.

  The pixels PX1 to PX3 arranged in the first direction X are different color pixels, and the pixels PX4 to PX6 are also different color pixels. The pixels PX1 and PX4 arranged in the second direction Y are pixels of the same color, for example, green (G) pixels. The pixels PX2 and PX5 arranged in the second direction Y are the same color pixels, for example, blue (B) pixels. The pixels PX3 and PX6 arranged in the second direction Y are the same color pixels, for example, red (R) pixels.

  The pixel PX1 is defined by the gate wiring G1, the gate wiring G2, the source wiring S1, and the source wiring S2, the pixel PX2 is defined by the gate wiring G1, the gate wiring G2, the source wiring S2, and the source wiring S3, and the pixel PX3 is a gate. It is defined by the wiring G1, the gate wiring G2, the source wiring S3, and the source wiring S4. These pixels PX1 to PX3 extend in the first extending direction D1 that intersects the second direction Y clockwise at an acute angle. The source lines S1 to S4 located on both sides of each pixel PX1 to PX3 extend in the first extending direction D1.

  The pixel PX4 is defined by the gate line G2, the gate line G3, the source line S1, and the source line S2, the pixel PX5 is defined by the gate line G2, the gate line G3, the source line S2, and the source line S3, and the pixel PX6 is the gate. It is defined by the wiring G2, the gate wiring G3, the source wiring S3, and the source wiring S4. These pixels PX4 to PX6 extend in the second extending direction D2 that intersects the second direction Y counterclockwise at an acute angle. The source lines S1 to S4 located on both sides of each pixel PX4 to PX6 extend in the second extending direction D2. The angle θ1 formed by the second direction Y and the first extending direction D1 is substantially the same as the angle θ2 formed by the second direction Y and the second extending direction D2, and is, for example, about 5 ° to 15 °. is there.

  The common electrode CE extends over substantially the entire area of the array substrate and is formed in common for the pixels PX1 to PX6. That is, the common electrode CE extends in the second direction Y over the gate lines G1 to G3, and extends in the first direction X over the source lines S1 to S4, and the pixels PX1 to PX6. Are arranged in each. In addition, although not described in detail, an opening for electrically connecting the pixel electrode and the switching element is formed in the common electrode CE in each pixel.

  In the pixel PX1, the switching element SW1 and the pixel electrode PE1 are arranged. The switching element SW1 is electrically connected to the gate line G2 and the source line S1. The pixel electrode PE1 is located between the source line S1 and the source line S2, and is connected to the switching element SW1.

  In the pixel PX2, a switching element SW2 and a pixel electrode PE2 are arranged. The switching element SW2 is electrically connected to the gate line G2 and the source line S2. The pixel electrode PE2 is located between the source line S2 and the source line S3, and is connected to the switching element SW2.

  In the pixel PX3, a switching element SW3 and a pixel electrode PE3 are arranged. The switching element SW3 is electrically connected to the gate line G2 and the source line S3. The pixel electrode PE3 is located between the source line S3 and the source line S4, and is connected to the switching element SW3.

  Similarly, in the pixel PX4, a switching element SW4 electrically connected to the gate line G3 and the source line S1, and a pixel electrode PE4 connected to the switching element SW4 are arranged. In the pixel PX5, a switching element SW5 electrically connected to the gate line G3 and the source line S2 and a pixel electrode PE5 connected to the switching element SW5 are arranged. In the pixel PX6, a switching element SW6 electrically connected to the gate line G3 and the source line S3, and a pixel electrode PE6 connected to the switching element SW6 are arranged.

  The switching elements SW1 to SW6 are, for example, thin film transistors (TFTs).

  The pixel electrodes PE1 to PE6 are respectively located above the common electrode CE. The pixel electrodes PE1 to PE3 are each formed in an island shape corresponding to the pixel shape extending in the first extending direction D1. Further, the pixel electrodes PE1 to PE3 each have a plurality of slits SLA extending in the first extending direction D1. The pixel electrodes PE4 to PE6 are each formed in an island shape corresponding to the pixel shape extending in the second extending direction D2. Further, the pixel electrodes PE4 to PE6 each have a plurality of slits SLB extending in the second extending direction D2. Each of the slits SLA and SLB faces the common electrode CE. In the illustrated example, each of the pixel electrodes PE1 to PE3 has two slits SLA, and each of the pixel electrodes PE4 to PE6 has two slits SLB.

  In the present embodiment, the columnar spacer is formed on the array substrate AR. The illustrated columnar spacers SP1 to SP3 are all arranged in blue pixels. That is, the columnar spacer SP1 is located in the vicinity of the intersection between the gate line G1 and the source line S3. The columnar spacer SP2 is located in the vicinity of the intersection between the gate line G2 and the source line S3, and is disposed across the position overlapping the source line S3 and the pixel electrode PE2 in the XY plane. The columnar spacer SP3 is located in the vicinity of the intersection between the gate line G3 and the source line S3, and is disposed across the position overlapping the source line S3 and the pixel electrode PE5 in the XY plane.

  These columnar spacers SP1 to SP3 arranged along the second direction Y are arranged in a staggered manner. In other words, every other columnar spacers SP1 and SP3 are located on the same straight line parallel to the second direction Y, and the columnar spacer SP2 is displaced from the same straight line connecting the columnar spacer SP1 and the columnar spacer SP3. It is arranged at the position.

  In the illustrated example, the pixel electrode PE2 (or the pixel PX2) has a shape that descends from the gate wiring G1 side toward the gate wiring G2, and the pixel electrode PE5 (or the pixel PX5) extends from the gate wiring G3 side to the gate wiring G2. It is a shape that rises to the left. The intersection between the gate line G2 and the source line S3 is located on the left side in the drawing with respect to the intersection between the gate line G1 and the source line S3 and the intersection between the gate line G3 and the source line S3. The columnar spacer SP2 is located on the left side in the drawing with respect to the columnar spacers SP1 and SP3.

  The first alignment film AL1 is formed with respect to the long axis of the slit SLA (first extending direction D1 in the example shown in FIG. 2) and the long axis of the slit SLB (second extending direction D2 in the example shown in FIG. 2). Are rubbed along a direction that intersects an acute angle of 45 ° or less. The rubbing direction R1 of the first alignment film AL1 is a direction parallel to the second direction Y, and intersects the first extending direction D1 or the second extending direction D2 with an angle of 5 ° to 15 °. is there.

  A region A1 indicated by a broken line in the drawing corresponds to a region downstream of the columnar spacer SP1 in the rubbing direction R1. Similarly, the region A2 corresponds to a region downstream of the columnar spacer SP2 in the rubbing direction R1, and the region A3 corresponds to a region downstream of the columnar spacer SP3 in the rubbing direction R1. These regions A1 to A3 are all located on the source wiring and in the blue pixel.

  FIG. 3 is a plan view schematically showing an example of the layout of the color filters CF1 to CF3 in the counter substrate CT shown in FIG.

  The counter substrate CT includes a light shielding layer BM, color filters CF1 to CF3, a second alignment film AL2, and the like.

  The color filter CF1, the color filter CF2, and the color filter CF3 are arranged along the first direction X in this order. These color filters CF1 to CF3 all extend along the second direction Y and are formed in a strip shape. The color filter CF1 is a green (G) color filter and extends over the green pixels, that is, the pixels PX1 and PX4 shown in FIG. The color filter CF2 is a blue (B) color filter and extends over the blue pixels, that is, the pixels PX2 and PX5 shown in FIG. The color filter CF3 is a red (R) color filter and extends over the red pixels, that is, the pixels PX3 and PX6 shown in FIG. The columnar spacers SP1 to SP3 indicated by broken lines in the drawing face the blue color filter CF2.

  In the color filters CF1 to CF3, end portions adjacent to each other overlap the light shielding layer BM. Each light shielding layer BM extends substantially along the second direction Y. Such a light shielding layer BM is located above the source wiring and the gate wiring shown in FIG. In the illustrated example, the light shielding layer BM is formed in a stripe shape positioned only above the source wiring, but may be formed in a lattice shape positioned above both the gate wiring and the source wiring. . Each of the pixels PX1 to PX6 is an area inside the light shielding layer BM and substantially corresponds to an area through which backlight light can be transmitted.

  The second alignment film AL2 is subjected to an alignment process along a direction parallel to the rubbing direction R1 of the first alignment film AL1. For example, the rubbing direction R2 of the second alignment film AL2 is opposite to the rubbing direction R1 of the first alignment film AL1.

  FIG. 4 is a cross-sectional view schematically showing the configuration of the display panel PNL including the pixels PX1 to PX3 and the columnar spacer SP2 shown in FIG.

  The array substrate AR is formed using a transparent first insulating substrate 10 such as a glass substrate or a resin substrate. On the side of the first insulating substrate 10 facing the counter substrate CT, the array substrate AR is provided with a switching element (not shown), a common electrode CE, pixel electrodes PE1 to PE3, a first insulating film 11, a second insulating film 12, and a first alignment. A film AL1, a columnar spacer SP2, and the like are provided.

  The common electrode CE is formed on the first insulating film 11. The common electrode CE is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The common electrode CE is covered with the second insulating film 12. Note that gate wiring, source wiring, switching elements, and the like (not shown) are formed between the first insulating substrate 10 and the first insulating film 11.

  The pixel electrodes PE1 to PE3 are formed on the second insulating film 12 and face the common electrode CE. Slits SLA are formed in the pixel electrodes PE1 to PE3, respectively. The pixel electrodes PE1 to PE3 are formed of a transparent conductive material, for example, ITO or IZO. The pixel electrodes PE1 to PE3 are covered with the first alignment film AL1. The first alignment film AL1 also covers the second insulating film 12. The first alignment film AL1 is formed of a material exhibiting horizontal alignment and is disposed on the surface in contact with the liquid crystal layer LQ of the array substrate AR.

  The columnar spacer SP2 is formed on the second insulating film 12, and a part thereof overlaps with the pixel electrode PE2. The columnar spacer SP2 is covered with the first alignment film AL1.

  On the other hand, the counter substrate CT is formed using a transparent second insulating substrate 20 such as a glass substrate or a resin substrate. The counter substrate CT includes a light shielding layer BM, a color filter CF1, a color filter CF2, a color filter CF3, an overcoat layer OC, a second alignment film AL2, and the like on the side of the second insulating substrate 20 facing the array substrate AR. Yes.

  The light shielding layer BM is formed on the inner surface of the second insulating substrate 20. The light shielding layer BM is formed of a black resin material or a light shielding metal material. Each of the color filters CF1 to CF3 is formed on the inner surface of the second insulating substrate 20. The color filter CF1 is formed of a resin material colored in green. The color filter CF2 is formed of a resin material colored in blue. The color filter CF3 is formed of a resin material colored in red.

  The overcoat layer OC covers the color filters CF1 to CF3. The overcoat layer OC flattens the unevenness of the surface of the color filters CF1 to CF3. The overcoat layer OC is formed of a transparent resin material. The overcoat layer OC is covered with the second alignment film AL2. The second alignment film AL2 is formed of a material exhibiting horizontal alignment, and is disposed on the surface in contact with the liquid crystal layer LQ of the counter substrate CT.

  The array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film AL1 and the second alignment film AL2 face each other. At this time, a predetermined cell gap is formed between the array substrate AR and the counter substrate CT by the illustrated columnar spacer SP2. The array substrate AR and the counter substrate CT are bonded together with a sealing material in a state where a cell gap is formed. The liquid crystal layer LQ is composed of a liquid crystal composition including liquid crystal molecules LM sealed in a cell gap formed between the first alignment film AL1 of the array substrate AR and the second alignment film AL2 of the counter substrate CT. .

  A backlight BL is disposed on the back side of the display panel PNL having such a configuration. Although various forms can be applied as the backlight BL, description of the detailed structure is omitted.

  On the outer surface of the array substrate AR, that is, the outer surface of the first insulating substrate 10, the first optical element OD1 including the first polarizing plate PL1 is disposed. On the outer surface of the counter substrate CT, that is, the outer surface of the second insulating substrate 20, the second optical element OD2 including the second polarizing plate PL2 is disposed. One of the first absorption axis of the first polarizing plate PL1 and the second absorption axis of the second polarizing plate PL2 is parallel to the initial alignment direction of the liquid crystal molecules LM, and the other is orthogonal to the initial alignment direction.

  The operation of the liquid crystal display device having the above configuration will be described below.

  When the voltage that forms a potential difference is not applied between the pixel electrode PE and the common electrode CE, the voltage is not applied to the liquid crystal layer LQ when the voltage is not applied, and the pixel electrode PE and the common electrode CE No electric field is formed between the two. Therefore, the liquid crystal molecules LM included in the liquid crystal layer LQ are aligned in the second direction Y in the XY plane by the alignment regulating force of the first alignment film AL1 and the second alignment film AL2, as shown by the solid line in FIG. Is initially oriented. That is, the initial alignment direction of the liquid crystal molecules LM is parallel to the second direction Y.

  When OFF, a part of the backlight light from the backlight BL passes through the first polarizing plate PL1 and enters the display panel PNL. The light incident on the display panel PNL is, for example, linearly polarized light that is orthogonal to the first absorption axis of the first polarizing plate PL1. The polarization state of such linearly polarized light hardly changes when it passes through the display panel PNL when it is OFF. For this reason, most of the linearly polarized light transmitted through the display panel PNL is absorbed by the second polarizing plate PL2 (black display).

  On the other hand, when a voltage that forms a potential difference is applied between the pixel electrode PE and the common electrode CE, the voltage is applied to the liquid crystal layer LQ, and the pixel electrode PE and the common electrode CE A fringe electric field is formed in between. For this reason, the liquid crystal molecules LM are aligned in an azimuth different from the initial alignment direction in the XY plane, as indicated by a broken line in FIG. In the positive-type liquid crystal material, for example, the liquid crystal molecules LM of the pixel PX3 rotate clockwise so as to be aligned in a direction substantially parallel to the fringe electric field in the XY plane, and the liquid crystal molecules LM of the pixel PX6 are In the XY plane, it rotates counterclockwise so that it is oriented in a direction substantially parallel to the fringe electric field. At this time, the liquid crystal molecules LM are aligned in a direction corresponding to the magnitude of the electric field.

  When ON, linearly polarized light orthogonal to the first absorption axis of the first polarizing plate PL1 enters the display panel PNL, and the polarization state changes according to the alignment state of the liquid crystal molecules LM when passing through the liquid crystal layer LQ. To do. For this reason, at the time of ON, at least a part of the light that has passed through the liquid crystal layer LQ is transmitted through the second polarizing plate PL2 (white display).

  With such a configuration, a normally black mode is realized.

  According to this embodiment, when the rubbing process is performed on the first alignment film AL1 of the array substrate AR on which the columnar spacers are formed, the first alignment film AL1 is formed on the upstream side and the downstream side in the rubbing direction of the columnar spacers. Even if there is a difference in the rubbing state, the region on the downstream side of the rubbing direction of the columnar spacer is formed at a position overlapping the source wiring or in the blue pixel. In the example shown in FIG. 2, the region A1 on the downstream side of the columnar spacer SP1, the region A2 on the downstream side of the columnar spacer SP2, and the region A3 on the downstream side of the columnar spacer SP3 all overlap with the source wiring S3. It is formed in the blue pixel. For this reason, even if light leakage due to misalignment of the liquid crystal molecules LM occurs in these regions A1 to A3, the blue pixel has a relatively low luminance compared to the red pixel and the green pixel, so the contrast ratio Can be suppressed. In addition, the region on the downstream side in the rubbing direction with respect to any columnar spacer is formed in the blue pixel and is not formed in the other color pixel, so the difference in chromaticity between the odd-numbered row and the even-numbered row is reduced. It becomes possible to reduce. Therefore, display quality can be improved.

  In addition, in a pseudo dual domain type liquid crystal display device that forms domains different from odd and even rows, the difference in contrast ratio and chromaticity can be reduced between odd and even rows, thus widening the viewing angle. Is possible.

  FIG. 5 is a schematic plan view of a second configuration example of the pixels in the array substrate AR shown in FIG. 1 as viewed from the counter substrate CT side.

  The second configuration example shown here is different from the first configuration example shown in FIG. 2 in that the columnar spacers SP1 to SP3 are arranged on the same straight line parallel to the second direction Y. Yes. In addition, about another structure, it is the same as the example shown in FIG. 2, The same referential mark is attached | subjected and description is abbreviate | omitted.

  That is, the columnar spacers SP1 to SP3 are formed on the array substrate AR, and are all arranged in the blue pixels. The columnar spacer SP1 is located closer to the source line S2 than the intersection between the gate line G1 and the source line S3. The columnar spacer SP2 is located in the vicinity of the intersection between the gate line G2 and the source line S3, and is disposed across the position overlapping the source line S3 and the pixel electrode PE2 in the XY plane. The columnar spacer SP3 is located closer to the source line S2 than the intersection of the gate line G3 and the source line S3, and is disposed at a position overlapping the pixel electrode PE5 between the source line S2 and the source line S3 on the XY plane. Has been.

  These columnar spacers SP1 to SP3 arranged along the second direction Y are located on the same straight line parallel to the second direction Y, which is the initial alignment direction of the liquid crystal molecules.

  The rubbing direction R1 of the first alignment film AL1 is a direction parallel to the second direction Y. The region A1 downstream in the rubbing direction R1 relative to the columnar spacer SP1, the region A2 downstream in the rubbing direction R1 relative to the columnar spacer SP2, and the region A3 downstream in the rubbing direction R1 relative to the columnar spacer SP3 Is also located in the blue pixel.

  In such a second configuration example, since the columnar spacers SP1 to SP3 are arranged on the same straight line parallel to the rubbing direction R1, the regions A1 to A3 that are liable to cause alignment defects of liquid crystal molecules are formed only on the straight line. Similarly to the first configuration example described above, it is possible to suppress a decrease in contrast ratio and to reduce the difference in chromaticity between the odd and even rows.

  As described above, according to this embodiment, a liquid crystal display device capable of improving display quality can be provided.

  In addition, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, in the above embodiment, the slit of each pixel electrode is formed so as to have a long axis parallel to the first extending direction or the second extending direction, but in a shape bent into a “<” shape. It may be formed. When each pixel electrode has a “<”-shaped slit, the rubbing direction R1 of the first alignment film and the rubbing direction R2 of the second alignment film are, for example, parallel to the second direction, and the columnar spacer is downstream in the rubbing direction. The blue pixels are arranged at the positions.

PNL ... Display panel AR ... Array substrate CT ... Counter substrate LQ ... Liquid crystal layer SW ... Switching element CE ... Common electrode PE1 to PE6 ... Pixel electrode SLA ... Slit SLB ... Slit CF1 ... Color filter (green) CF2 ... Color filter (blue) CF3 Color filter (red)
SP1 to SP3 ... Columnar spacer

Claims (6)

A first gate line and a second gate line; a first source line and a second source line that intersect the first gate line and the second gate line; and the first gate line and the first source line A first switching element electrically connected, a second switching element electrically connected to the second gate line and the first source line, and a first extension electrically connected to the first switching element. A first pixel electrode having a first slit extending in a direction and a second slit having a second slit extending in a second extending direction that is electrically connected to the second switching element and different from the first extending direction. A first substrate comprising two pixel electrodes, and a common electrode having a common potential facing the first pixel electrode and the second pixel electrode;
A second substrate comprising a blue color filter facing the first pixel electrode and the second pixel electrode between the first source line and the second source line;
A columnar spacer that forms a cell gap between the first substrate and the second substrate and faces the blue color filter;
A liquid crystal layer comprising liquid crystal molecules held in the cell gap;
A liquid crystal display device comprising:   The columnar spacer includes a first spacer facing the blue color filter at a position overlapping the second source line and the first pixel electrode, and the blue color at a position overlapping the second source line and the second pixel electrode. The liquid crystal display device according to claim 1, further comprising a second spacer facing the color filter.   The liquid crystal display device according to claim 2, wherein the first columnar spacer and the second columnar spacer are arranged at positions shifted from the same straight line parallel to the initial alignment direction of the liquid crystal molecules.   The columnar spacer includes a first spacer facing the blue color filter at a position overlapping the second source line and the first pixel electrode, and the first spacer between the first source line and the second source line. The liquid crystal display device according to claim 1, further comprising a second spacer that overlaps with the two pixel electrodes and faces the blue color filter.   The liquid crystal display device according to claim 4, wherein the first columnar spacer and the second columnar spacer are arranged on the same straight line parallel to an initial alignment direction of the liquid crystal molecules. The first extending direction is a direction that intersects an acute angle clockwise with respect to the initial alignment direction of the liquid crystal molecules, and the second extending direction is an acute angle counterclockwise with respect to the initial alignment direction of the liquid crystal molecules. The direction of crossing
6. The angle according to claim 1, wherein an angle formed between the first extending direction and the initial alignment direction is the same as an angle formed between the second extending direction and the initial alignment direction. Liquid crystal display device.

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