JP2015038780A - Controller, information processing system and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a controller, an information processing system and a program capable of appropriately power saving.SOLUTION: The controller has a setting section. When any factor that a system including plural components, the power to which can be independently controlled, restores from a sleep state that the number of the components to which the power is supplied is limited to a predetermined number and stops operation, the setting section sets a mode representing an operation state of the system according to the system processing time representing the time required for the processing after restoring the sleep state.

Description

  Embodiments described herein relate generally to a control device, an information processing system, and a program.

  Conventionally, various techniques for reducing power consumption of a system in which a microprocessor or the like is mounted are known. For example, in the sleep state (power saving state) in which the system operation is temporarily stopped, the clock is set to a low speed, while in the case of executing the process after returning from the sleep state, the clock is set to a high speed. It has been known.

Japanese Patent No. 3758477 JP 2008-5336 A JP 2011-65705 A

  However, in the conventional technique, the system operating state after the return is set without taking into account the time required for the processing after returning from the sleep state, and thus the power saving of the system cannot be appropriately performed. There is a case. For example, when the time required for processing after returning from the sleep state is short, wasteful power consumption occurs due to the clock being set at high speed even though the amount of power required by the system is small. Thereby, power saving cannot be performed appropriately.

  The problem to be solved by the present invention is to provide a control device, an information processing system, and a program capable of appropriately performing power saving.

  The control device of the embodiment includes a setting unit. When the setting unit has a factor that causes the system including a plurality of elements capable of individually controlling power to return from the sleep state in which the number of elements to which power is supplied is limited to a predetermined number and stops operation, A mode indicating the operating state of the system is set according to the system processing time indicating the time required for processing after returning from the sleep state.

  The program according to the embodiment is a factor that causes a computer including a plurality of elements capable of individually controlling power to return from a sleep state in which the number of elements to which power is supplied is limited to a predetermined number and the operation is stopped. When this occurs, this is a program for executing a step of setting a mode indicating the operating state of the system in accordance with the system processing time indicating the time required for processing after returning from the sleep state.

  The information processing system according to the embodiment includes a plurality of elements capable of individually controlling power, and the information processing system stops operation when the number of elements to which power is supplied is limited to a predetermined number. When a factor for returning from the sleep state occurs, the device operates in a mode corresponding to the time required for processing after returning from the sleep state.

The block diagram which shows the structural example of the system of 1st Embodiment. The block diagram which shows the function structural example of the processor of 1st Embodiment. The figure which shows the example of the data memorize | stored in the 1st memory | storage part of 1st Embodiment. The figure which shows the example of the data memorize | stored in the 2nd memory | storage part of 1st Embodiment. The figure which shows the calculation example of the system interruption processing time of 1st Embodiment. The sequence diagram which shows an example of the operation | movement procedure of the processor of 1st Embodiment. The sequence diagram which shows an example of the operation | movement procedure of the processor of 1st Embodiment. The flowchart which shows an example of the processing operation by the calculation part of 1st Embodiment. The block diagram which shows the structural example of the system of 2nd Embodiment. The block diagram which shows the function structural example of the processor of 2nd Embodiment. The figure which shows an example of the data memorize | stored in the 4th memory | storage part of 2nd Embodiment. The figure which shows an example of the data memorize | stored in the 5th memory | storage part of 2nd Embodiment. The sequence diagram which shows an example of the operation | movement procedure of the processor of 2nd Embodiment. The block diagram which shows the function structural example of the processor of 3rd Embodiment. The figure which shows an example of the data memorize | stored in the 3rd memory | storage part of 3rd Embodiment. The figure which shows the calculation example of the system interruption processing time of 3rd Embodiment. The sequence diagram which shows an example of the operation | movement procedure of the processor of 3rd Embodiment. The flowchart which shows an example of the processing operation by the calculation part of 3rd Embodiment. The sequence diagram which shows an example of the operation | movement procedure of the processor of 3rd Embodiment. The block diagram which shows the function structural example of the processor of 4th Embodiment. The figure which shows an example of the data memorize | stored in the 4th memory | storage part of 4th Embodiment. The sequence diagram which shows an example of the operation | movement procedure of the processor of 4th Embodiment. The block diagram which shows the function structural example of the processor of 5th Embodiment. The sequence diagram which shows an example of the operation | movement procedure of the processor of 5th Embodiment. The block diagram which shows the function structural example of the processor of 6th Embodiment. The sequence diagram which shows an example of the operation | movement procedure of the processor of 6th Embodiment. The sequence diagram which shows an example of the operation | movement procedure of the processor of 6th Embodiment. The figure which shows an example of the setting information memorize | stored in the 3rd memory | storage part of a modification. The block diagram which shows the structural example of the system of a modification. The block diagram which shows the function structural example of the processor of a modification. The block diagram which shows the structural example of the system of a modification.

  Hereinafter, embodiments of a control device, an information processing system, and a program according to the present invention will be described in detail with reference to the accompanying drawings.

(First embodiment)
FIG. 1 is a block diagram illustrating a configuration example of a target system (hereinafter simply referred to as “system”) 10 according to the present embodiment. As shown in FIG. 1, the system 10 includes a processor 100 and a storage area 170, which are mutually connected by a bus 190. Here, the system 10 can also be regarded as including a plurality of elements that can individually control the supplied power. The above elements include components that can individually control power and compartments within the components. For example, one section in an SOC (system on chip) including the processor 100 and the storage area 170 may be the above element.

  The processor 100 is a processing device that can execute one or more processes. As illustrated in FIG. 1, the processor 100 includes a CPU 110 and a storage unit 120. More specifically, the storage unit 120 includes a register 130 that stores various data, a primary cache 140 and a secondary cache 150 that store frequently used data and the like. The primary cache 140 stores data that is used more frequently. The secondary cache 150 stores frequently used data leaked from the primary cache 140.

  The storage area 170 stores programs and data used by the processor 100.

  FIG. 2 is a block diagram illustrating a configuration of functions realized by the CPU 110 mounted on the processor 100 executing an operating system (OS) 200 that is basic software, and hardware included in the processor 100. Here, it can be understood that a single OS 200 operates on the processor 100 and one or more processes (999-1 to 999-n) operate on the OS 200. In FIG. 2, the processor 100 includes hardware included in the processor 100, an OS 200 that operates on the processor 100, and one or more processes that operate on the OS 200.

  As illustrated in FIG. 2, the hardware included in the processor 100 includes a CPU 110, a first storage unit 910, and a second storage unit 930. The first storage unit 910 indicates an interrupt type indicating an interrupt type, and a time (waiting time) until an interrupt process indicating an interrupt process is started after an interrupt wait indicating a state of waiting for an interrupt occurs. The interrupt waiting time and the interrupt processing time indicating the interrupt processing time are stored in association with each other.

  FIG. 3 is a diagram illustrating an example of data stored in the first storage unit 910. In the example of FIG. 3, the interrupt waiting time corresponding to device reading is set to T1_m, and the interrupt processing time is set to T1_s. The interrupt waiting time corresponding to keyboard input is set to T2_m, and the interrupt processing time is set to T2_s. The interrupt waiting time corresponding to the timer is set to T3_m, and the interrupt processing time is set to T3_s. The interrupt waiting time corresponding to mouse input is set to T4_m, and the interrupt processing time is set to T4_s.

  Returning to FIG. 2, the description will be continued. The second storage unit 930 stores the interrupt type and the interrupt wait occurrence time indicating the time when the interrupt wait occurred in association with each other.

  FIG. 4 is a diagram illustrating an example of data stored in the second storage unit 930. In the example of FIG. 4, the interrupt wait occurrence time corresponding to device reading is set to Ta. Also, the interruption waiting time corresponding to the keyboard input is set to Tb. Furthermore, the interruption waiting time corresponding to the timer is set to Tc.

  Returning to FIG. 2 again, the description will be continued. As illustrated in FIG. 2, the OS 200 includes an interrupt wait setting unit 210, an interrupt detection unit 220, a calculation unit 230, a first determination unit 240, a mode setting unit 250, and an interrupt wait release unit 260.

  When an interrupt wait of a certain interrupt type occurs, the interrupt wait setting unit 210 stores the interrupt type that has been waiting for the interrupt and the interrupt wait occurrence time of the interrupt type in the second storage unit 930. In addition, when the interrupt process is started, the interrupt wait release unit 260 deletes the interrupt type corresponding to the interrupt process and the interrupt wait occurrence time corresponding to the interrupt type from the second storage unit 930. Detailed contents will be described later.

  The interrupt detection unit 220 detects the occurrence of an interrupt. More specifically, the interrupt detection unit 220 receives an interrupt notification (a signal indicating that an interrupt occurs) from inside and outside the processor 100, and identifies an interrupt type from which interrupt processing is started based on the interrupt notification.

  The calculation unit 230 calculates a system interrupt processing time indicating a time required until the interrupt processing executed after the system 10 returns from the sleep state. Here, a state in which the number of elements to which power is supplied is limited to a predetermined number and the operation of the system 10 is stopped is referred to as a sleep state. In the present embodiment, the idle state in which the CPU 110 does not execute any process (in other words, the idle state can be regarded as a state in which the system 10 does not execute any process) continues for a certain period. In this case, the system 10 shifts to the sleep state, but the present invention is not limited to this, and the conditions for shifting to the sleep state are arbitrary. On the other hand, when an interrupt occurs in the sleep state, the system 10 returns from the sleep state and executes interrupt processing.

  In the present embodiment, the calculation unit 230 performs an interrupt process that is executed independently without overlapping (overlap) with other interrupt processes immediately after the system 10 returns from the sleep state, or at least a part of the overlap. The time required until the completion of a plurality of interrupt processes executed with the is calculated as the system interrupt process time.

  Assume that in the sleep state, the three interrupt types of device reading, keyboard input, and timer interrupt are waiting for an interrupt. As shown in FIG. 5, the time when the interrupt processing by the device reading is started is set to t1, and the interrupt processing time is set to T1_s. In addition, the time when the interrupt processing by keyboard input is started is set to t2 (> t1), and the interrupt processing time is set to T2_s. Further, the time when the interrupt processing by the timer interrupt is started is set to t3 (> t2), and the interrupt processing time is set to T3_s. In the example of FIG. 5, it is assumed that the timing at which the system 10 returns from the sleep state is the time when interrupt processing by device reading is started (time at which an interrupt by device reading occurs) t1. Further, a part of the period in which the interrupt process by the device reading is executed overlaps with a part of the period in which the interrupt process by the keyboard input is executed. On the other hand, the period in which the interrupt process by the timer interrupt is executed is set independently without overlapping with the period in which the other interrupt processes are executed. Therefore, in the example of FIG. 5, the system interrupt processing time indicating the time required until the interrupt processing executed after the system 10 returns from the sleep state is completed by the interrupt processing by device reading and the interrupt processing by keyboard input. It is time to be executed. That is, in the example of FIG. 5, the system interrupt processing time Ts is calculated as T2_s + (t2-t1).

  The first determination unit 240 in FIG. 2 determines a mode indicating the operation state of the system 10 after returning from the sleep state, according to the system interrupt processing time calculated by the calculation unit 230. The operating state of the system 10 represents how the system 10 operates, and here, the sleep state is not included. In this example, there are a plurality of modes with different power consumptions, and the first determination unit 240 sets one of the plurality of modes to the sleep state according to the system interrupt processing time calculated by the calculation unit 230. It is determined as the mode of the system 10 after returning from. Each mode can be arbitrarily changed. For example, there may be a mode that “the power supply to the primary cache 140 is performed while the power supply to the secondary cache 150 is stopped” or “the primary cache 140 is stopped. And the power supply to each of the secondary caches 150 is stopped ”. In addition, there may be a mode in which power supply to other elements (for example, the storage area 170) is stopped, or there may be a mode in which the voltage of the CPU 110 and the value of the clock frequency are set to predetermined values.

  The mode setting unit 250 in FIG. 2 sets the mode of the system 10 to the mode determined by the first determination unit 240. As a result, the system 10 returns from the sleep state and shifts to the mode set by the mode setting unit 250.

  FIG. 6 is a sequence diagram illustrating an example of an operation procedure of the processor 100 when an interrupt wait occurs. For example, when a device attached to the system 10 (for example, a mouse, a keyboard, etc.) is in an interrupt wait state, information indicating that an interrupt wait of the device has occurred is notified from the device driver or the like to the interrupt wait setting unit 210. . By receiving the notification, the interrupt wait setting unit 210 can detect the interrupt type in which the interrupt wait has occurred (step S600). When detecting the interrupt type in which the interrupt wait has occurred, the interrupt wait setting unit 210 acquires the interrupt wait occurrence time of the detected interrupt type (in this example, the time when the above notification was received) (step S601). The second storage unit 930 is notified of the interrupt type that has been waiting for an interrupt and the time at which the interrupt has occurred (step S602). The second storage unit 930 stores the interrupt type notified from the interrupt wait setting unit 210 and the interrupt wait occurrence time in association with each other (step S603).

  FIG. 7 is a sequence diagram illustrating an example of an operation procedure from when an interrupt is generated to the processor 100 to when interrupt processing is started. As shown in FIG. 7, the interrupt detection unit 220 first detects the occurrence of an interrupt by receiving an interrupt notification from inside and outside the processor 100 (step S700). Next, the interrupt detection unit 220 identifies the interrupt type (interrupt type for which interrupt processing is started) of the generated interrupt from the received interrupt notification (step S701). Next, the interrupt detection unit 220 detects whether or not the system is in a sleep state (step S702). When the system is in the sleep state (result of step S702: YES), the interrupt detection unit 220 notifies the calculation unit 230 of the specified interrupt type (step S704). On the other hand, when the state of the system 10 is not the sleep state (the result of step S702: NO), the interrupt detection unit 220 notifies the interrupt waiting release unit 260 of the specified interrupt type (step S703). After step S703, the process proceeds to step S711. The contents of the process in step S711 will be described later.

  When the calculation unit 230 receives a notification of an interrupt type (interrupt type for which interrupt processing is started) from which an interrupt has occurred from the interrupt detection unit 220, the calculation unit 230 stores data stored in each of the first storage unit 910 and the second storage unit 930. Is used to calculate the system interrupt processing time (step S705). In other words, the calculation unit 230 calculates the system interrupt processing time when an interrupt occurs in the sleep state. In short, the calculation unit 230 calculates the system interrupt processing time indicating the time required until the interrupt processing executed after the system 10 returns from the sleep state.

  FIG. 8 is a flowchart illustrating an example of calculating the system interrupt processing time by the calculation unit 230. As shown in FIG. 8, the calculation unit 230 first extracts the interrupt type stored in the second storage unit 930 and the interrupt wait occurrence time corresponding to the interrupt type (step S800). Next, the calculation unit 230 initializes the measurement value i of the counter to “0” (step S801). The calculation unit 230 performs the processing of steps S802 to S806 described below for all the interrupt types extracted in step S800, thereby generating an interrupt generation time (interrupt processing start time) and an interrupt processing time. Create a correspondence table. This will be specifically described below.

  After step S801, the calculation unit 230 determines whether or not the measured value i of the counter has reached a value indicating the total number of interrupt types extracted in step S800 (step S802). When the measured value i of the counter has not reached the value indicating the total number of extracted interrupt types (result of step S802: No), the calculation unit 230 is still selected from the interrupt types extracted in step S800. One interrupt type that has not been selected is selected (step S803). Next, the calculation unit 230 extracts the interrupt waiting time and the interrupt processing time corresponding to the interrupt type selected in Step S803 from the first storage unit 910 (Step S804). Next, the calculation unit 230 calculates an interrupt occurrence time (interrupt processing start time) from the interrupt wait occurrence time and interrupt wait time corresponding to the interrupt type selected in step S803 (step S805). Specifically, the time when the interrupt waiting time elapses from the interrupt wait occurrence time is calculated as the interrupt occurrence time. Next, the calculation unit 230 associates the interrupt occurrence time calculated in step S805 with the interrupt processing time corresponding to the interrupt type selected in step S803 (the interrupt processing time extracted in step S804) (“correspondence” (Referred to as “data”) (step S806). Next, the calculation unit 230 increments the counter measurement value i by 1 (step S807). Then, the process returns to step S802 described above.

  In the above-described step S802, when the measured value i of the counter reaches the value indicating the total number of interrupt types extracted in step S800 (the result of step S802: YES), the calculation unit 230 performs the above-described order of interrupt occurrence time The correspondence data is rearranged (step S808).

  Next, the calculation unit 230 is executed after returning from the sleep state at the time when the interrupt processing time corresponding to the notified interrupt type elapses from the current time (in this example, when the occurrence of the interrupt is detected). Is set as the time when the interrupt processing ends (referred to as “system interrupt end time”) (step S809).

  Next, the calculation unit 230 determines whether or not the system interrupt end time is earlier than the interrupt generation time of another interrupt type for which no interrupt has been detected (step S810). When it is determined that the system interrupt end time is earlier than the interrupt generation time of other interrupt types (result of step S810: YES), the calculation unit 230 calculates the time from the current time to the system interrupt end time as a system interrupt process. The time is calculated (step S812). On the other hand, when it is determined that the system interrupt end time is later than the interrupt generation time of other interrupt types (result of step S810: NO), the calculation unit 230 resets the system interrupt end time (step S811). ). More specifically, the calculation unit 230 selects an interrupt type with the earliest interrupt generation time from among interrupt types whose interrupt generation time is earlier than the current system interrupt end time, and the interrupt generation time of the selected interrupt type Then, the time when the interrupt processing time of the selected interrupt type elapses is reset as the system interrupt end time. Then, the process returns to step S810 described above.

  Returning to FIG. 7 again, the description will be continued. The calculation unit 230 notifies the first determination unit 240 of the system interrupt processing time calculated as described above and the interrupt type notified from the interrupt detection unit 220 (interrupt type in which an interrupt has occurred). A request is made to determine the mode of the system 10 after returning from the sleep state (step S706). The first determination unit 240 determines the mode of the system 10 after returning from the sleep state according to the system interrupt processing time notified from the calculation unit 230 (step S707). More specifically, the first determination unit 240 determines the mode of the system 10 such that the number of operating elements (the number of elements to which power is supplied) increases as the system interrupt processing time increases. Hereinafter, an example of a mode determination method will be described. For example, when the system interrupt processing time notified from the calculation unit 230 is equal to or less than the first reference value, the first mode in which the minimum elements of the system 10 are operated (power consumption is minimized) is set as the system 10 mode. It can also be determined. The first mode may be a mode indicating a state in which, for example, the voltage and frequency are set to a minimum value that can be set, and the supply of power to each of the primary cache 140 and the secondary cache 150 is stopped. On the other hand, for example, when the system interrupt processing time notified from the calculation unit 230 is equal to or longer than the second reference value larger than the first reference value, all elements of the system 10 are operated (the power consumption is maximized). The mode can also be determined as the mode of the system 10. The second mode may be a mode in which power is supplied to all elements, for example. However, the present invention is not limited to this, as long as the system interrupt processing time is longer, a mode in which the power consumption is larger is determined as the mode of the system 10. The first determination unit 240 notifies the mode setting unit 250 of the mode of the system 10 determined as described above and the interrupt type in which the interrupt has occurred (step S708).

  The mode setting unit 250 sets the mode of the system 10 to the mode notified from the first determination unit 240 (step S709). As a result, the system 10 returns from the sleep state and shifts to the mode set by the mode setting unit 250. Next, the mode setting unit 250 notifies the interrupt wait cancellation unit 260 of the interrupt type in which the interrupt has occurred (step S710). Next, the interrupt wait cancellation unit 260 sets the second interrupt type notified from the mode setting unit 250 among the interrupt types stored in the second storage unit 930 and the second interrupt wait generation time corresponding to the interrupt type. It deletes from the memory | storage part 930 (step S711). As described above, when an interrupt wait has occurred, the interrupt type that has become an interrupt wait and the interrupt wait occurrence time indicating the time at which the interrupt was waited are associated with each other and stored in the second storage unit 930. On the other hand, when the interrupt wait is released (when an interrupt occurs), the interrupt type for which the interrupt wait is released and the interrupt wait occurrence time corresponding to the interrupt type are deleted from the second storage unit 930. This makes it possible to appropriately manage the current interrupt wait status. Then, the interrupt wait cancellation unit 260 starts executing the interrupt process corresponding to the interrupt type notified from the mode setting unit 250 (step S712).

  Here, when the system 10 is operated in the first mode (minimum set) described above, the power consumption of the system 10 can be reduced, while overhead due to processing for temporarily stopping the system 10 is large, The power consumption generated due to the influence of the processing (an increase in processing time due to a low voltage and frequency, an increase in memory access due to a cache not operating, etc.) cannot be ignored. For this reason, depending on the value of the above-described system interrupt processing time (the time required until the interrupt processing executed after the system 10 returns from the sleep state), the system 10 may be operated in the first mode. The generated power consumption may be larger than the power consumption generated when operating in another mode (for example, the above-described second mode).

  In the present embodiment, the mode of the system 10 is set according to the above-described system interrupt processing time. More specifically, as the above-described system interrupt processing time is longer, the mode is set such that the power consumption is higher. Therefore, the power consumption of the system 10 can be efficiently reduced while maintaining an appropriate processing time. Therefore, according to the present embodiment, the power consumption of the system can be efficiently reduced.

  In this embodiment, when an interrupt occurs in the sleep state, the mode of the system 10 is set according to the subsequent processing time. Therefore, even when the processing time is determined after the occurrence of the interrupt, the efficiency is improved. Therefore, there is an advantage that power consumption can be reduced. For example, when an interrupt is controlled by a control device external to the processor 100, the processing time after the occurrence of an interrupt in the sleep state cannot be accurately estimated before entering the sleep state. It is necessary to determine the mode of the system 10. Even in such a case, the power consumption can be efficiently reduced by applying the configuration of the present embodiment.

(Second Embodiment)
This embodiment is different from the first embodiment in that it has a function capable of setting the mode according to the power state of the power supply without operating the calculation unit 230 and the first determination unit 240 described above. Specific contents will be described below. In addition, about the part which overlaps with 1st Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted suitably.

  FIG. 9 is a block diagram illustrating a configuration example of the system 30 according to the second embodiment. As shown in FIG. 9, the system 30 includes a processor 100, a storage area 170, a power state management unit 360, a power generation module 380, and a battery 385, which are mutually connected by a bus 390. The power generation module 380 and the battery 385 can be regarded as the power source of the system 30.

  The power generation module 380 generates electric power necessary for operating the system 30. As an example, a configuration that generates power from sunlight, such as a solar panel, can be used as the power generation module 380. The battery 385 stores electric power necessary for operating the system 30.

  The power state management unit 360 manages the power state of the power source. For example, at least the power generation amount of the power generation module 380, the power generation tendency indicating the increase or decrease tendency of the power generation amount calculated from the power generation amount, the charge capacity of the battery 385, the charging tendency indicating the tendency of increase or decrease of the charge amount calculated from the charge capacity, etc. One is included in the power state of the power supply. The power state management unit 360 stores the previous power generation amount, and can grasp the power generation tendency by comparing with the current power generation amount. Moreover, the power state management unit 360 stores the previous charge capacity, and can grasp the charge tendency by comparing with the current charge capacity.

  FIG. 10 is a block diagram illustrating a functional configuration realized when the CPU 110 mounted on the processor 100 executes an operating system (OS) 400 that is basic software, and hardware included in the processor 100. As illustrated in FIG. 10, hardware included in the processor 100 includes a CPU 110, a first storage unit 910, a second storage unit 930, a fourth storage unit 970, and a fifth storage unit 990. In FIG. 10, the processor 100 includes hardware included in the processor 100, an OS 400 that operates on the processor 100, and one or more processes that operate on the OS 400.

  FIG. 11 is a diagram illustrating an example of data stored in the fourth storage unit 970. In the example of FIG. 11, the fourth storage unit 970 stores a power generation tendency, a charge amount, and a determination unit used for determining the mode of the system 30 in association with each other. That is, the fourth storage unit 970 can be regarded as storing the power state of the power supply and the mode determination method in association with each other. In the case of this figure, the power generation tendency shows an increasing tendency, and when the charge amount is less than a first threshold (for example, 40%), it indicates that the calculation unit 230 and the first determination unit 240 are operated. Further, when the power generation tendency shows an increasing tendency and the charge amount is equal to or more than the first threshold, it indicates that the second determination unit 490 described later is operated.

  In addition, when the power generation tendency shows a flat tendency and the charge amount is equal to or more than the second threshold (for example, 50%) and less than the third threshold (for example, 60%) that is larger than the second threshold, the calculation unit 230 It also shows that the first determination unit 240 is operated. In addition, for example, the power generation tendency shows a flat tendency, and when the charge amount is equal to or larger than the third threshold, the second determination unit 490 is operated.

  Further, the power generation tendency shows a tendency to decrease, and when the charge amount is a fourth threshold value (for example, 70%) or more, it indicates that the calculation unit 230 and the first determination unit 240 are operated. In addition, the power generation tendency shows a tendency to decrease, and when the charge amount is less than the fourth threshold value, the second determination unit 490 is operated.

  However, the present invention is not limited to this, and the fourth storage unit 970 may be configured to store, for example, only the charge amount and the determination unit to be used in association with each other, or to determine to use only the change amount of the power generation amount. The configuration may be such that the units are stored in association with each other. For example, the calculation unit 230 and the first determination unit 240 are used when the charge amount is greater than or equal to the fifth threshold and less than the sixth threshold greater than the fifth threshold, and the second determination unit 490 is used otherwise. It can also be used. Also, for example, when the amount of increase in power generation is less than the seventh threshold, or the absolute value of the amount of decrease in power generation is less than the eighth threshold (may be different from the seventh threshold or the same value). It is also possible to use the calculation unit 230 and the first determination unit 240, and otherwise use the second determination unit 490.

  FIG. 12 is a diagram illustrating an example of data stored in the fifth storage unit 990. In the example of FIG. 12, the fifth storage unit 990 stores a power generation tendency, a charge amount, and a mode of the system 30 in association with each other. That is, it can be understood that the fifth storage unit 990 stores the power state of the power supply and the mode of the system 30 in association with each other. In the case of this figure, when the power generation tendency shows an increasing tendency, the second mode is selected if the charge amount is not less than the ninth threshold (for example, 30%), and the first mode is selected otherwise. . In addition, when the power generation tendency is flat, the second mode is selected if the charge amount is equal to or greater than a tenth threshold (for example, 50%), and the first mode is selected otherwise. Further, when the power generation tendency shows a tendency to decrease, the second mode is selected if the charge amount is the eleventh threshold (for example, 70%) or more, and the first mode is selected otherwise.

  However, the present invention is not limited to this, and the fifth storage unit 990 may be configured to store, for example, only the charge amount and the mode of the system 30 in association with each other. The configuration may be such that the mode is stored in association with each other. For example, the second mode can be selected if the amount of charge is equal to or greater than the twelfth threshold, and the first mode can be selected if the amount of charge is less than the twelfth threshold. Also, for example, the second mode can be selected if the amount of increase in power generation is equal to or greater than the thirteenth threshold, and the first mode can be selected if it is equal to or less than the thirteenth threshold.

  Returning to FIG. 10 again, the description will be continued. As illustrated in FIG. 10, the OS 400 includes an interrupt waiting setting unit 210, an interrupt detection unit 220, a power state acquisition unit 480, a determination unit 470, a second determination unit 490, a calculation unit 230, and a first determination. Unit 240, mode setting unit 250, and interrupt wait canceling unit 260.

  The power state acquisition unit 480 acquires the power state of the power source from the power state management unit 360 and notifies the determination unit 470 of the power state. The determination unit 470 selects a determination unit that determines the mode of the system 30 based on the data stored in the fourth storage unit 970. The second determination unit 490 determines the mode of the system 30 according to the power state of the power source. Detailed contents will be described later.

  FIG. 13 is a sequence diagram illustrating an example of an operation procedure of the processor 100 from when an interrupt is generated until interrupt processing is started. First, the interrupt detection unit 220 detects the occurrence of an interrupt by receiving an interrupt notification from inside and outside the processor 100 (step S1200). Next, the interrupt detection unit 220 identifies the interrupt type of the generated interrupt from the received interrupt notification (step S1201). Next, the interrupt detection unit 220 detects whether or not the state of the system 30 is a sleep state (step S1202). When the state of the system 30 is the sleep state (the result of step S1202: YES), the interrupt detection unit 220 notifies the specified interrupt type to the power state acquisition unit 480 (step S1204). On the other hand, when the state of the system 30 is not the sleep state (the result of step S1202: NO), the interrupt detection unit 220 notifies the interrupt waiting release unit 260 of the specified interrupt type (step S1203). After step S1203, the process proceeds to step S1219. Since the content of the processing after step S1219 is the same as the content of the processing after step S711 of FIG. 7, detailed description is omitted.

  The power status acquisition unit 480 acquires the power status from the power status management unit 360 when receiving the notification of the interrupt type in which the interrupt has occurred from the interrupt detection unit 220 (step S1205). Next, the power state acquisition unit 480 notifies the determination unit 470 of the acquired power state (step S1206).

  When notified of the power state from the power state acquisition unit 480, the determination unit 470 determines the mode determination method of the system 30 from the power state and the value stored in the fourth storage unit 970 (step S1207). In the example of FIG. 11, the determination unit 470 operates the calculation unit 230 and the first determination unit 240 based on the power state acquired from the power state acquisition unit 480 and the data stored in the fourth storage unit 970. 30 modes are determined, or whether the system 30 mode is determined by operating the second determination unit 490. Hereinafter, an example of determining the mode determination method of the system 30 will be described with reference to the example of FIG. For example, when the power generation tendency obtained from the power state acquisition unit 480 is increasing and the charge amount is 30%, the calculation unit 230 and the first determination unit 240 are operated to set the mode of the system 30. To decide. That is, in this case, the determination unit 470 selects the calculation unit 230 and the first determination unit 240 as the determination unit that determines the mode of the system 30. Alternatively, when the power generation tendency obtained from the power state acquisition unit 480 is flat and the charge amount is 80%, it is determined to operate the second determination unit 490 to determine the mode of the system 30. That is, in this case, the determination unit 470 selects the second determination unit 490 as a determination unit that determines the mode of the system 30.

  When determination unit 470 determines to determine the mode of system 30 without operating calculation unit 230 and first determination unit 240 (result of step S1208: NO), that is, determination unit 470 determines the second determination. When it is determined to operate the unit 490 to determine the mode of the system 30, the determination unit 470 notifies the second determination unit 490 of the power state and requests the mode determination of the system 30 (step S1210). The second determination unit 490 uses the current power state of the power source sent from the determination unit 470 (the power state acquired by the power state acquisition unit 480) and the value stored in the fifth storage unit 990 to The mode is determined (step 1211). Hereinafter, a method for determining the mode of the system 30 when the fifth storage unit has the configuration of FIG. 12 will be described. Among the power states sent from the determination unit 470, the power generation tendency shows an increasing tendency, and if the charge amount is 50%, the second mode in which all elements of the system 30 are operated is set as the system 30 mode. Can be determined. Further, for example, when the power generation tendency is flat and the charge amount is 80%, the second mode can be determined as the mode of the system 30. On the other hand, the second determination unit 490 can determine the first mode in which the minimum elements of the system 30 are operated as the mode of the system 30. For example, when the power generation tendency is decreasing and the charge amount is 50%, the second determination unit 490 can determine the first mode as the mode of the system 30.

  Then, the second determination unit 490 notifies the mode setting unit 250 of the determined mode and the interrupt type in which the interrupt has occurred (step S1212). The mode setting unit 250 sets the mode of the system 30 to the mode notified from the first determination unit 240 or the second determination unit 490 (step S1217). As a result, the system 30 returns from the sleep state and shifts to the mode set by the mode setting unit 250.

  On the other hand, when it is determined to operate the calculation unit 230 and the first determination unit 240 to determine the mode of the system 30 (result of step S1208: YES), the determination unit 470 interrupts the calculation unit 230. The type of interrupt that has occurred is notified, and calculation of the system interrupt processing time is requested (step S1209). The subsequent contents after step S1213 are the same as the contents after step S705 in FIG.

  As described above, in this embodiment, the system 30 is operated in an optimal state according to the power state of the power supply when an interrupt occurs in the sleep state, so that the power consumption of the system 30 is efficiently reduced. However, the process can be executed. As described above, the method of reducing the power consumption by setting the mode of the system 30 according to the system interrupt processing time can reduce the power consumption of the processor 100, while the process for changing the mode of the system 30. The power consumption caused by overhead due to the above cannot be ignored. In the first state where the power generation amount and the charge amount are sufficient, it is more efficient to ignore the power consumption because the processing time can be shortened, but the power generation amount and the charge amount are not sufficient. In the case of two states, it is considered appropriate to operate with the minimum set from the viewpoint that the system 30 operates. In addition, when the power generation amount and the charge amount are in the third state, which is between the first state and the second state, it is appropriate to operate the system 30 in a mode corresponding to the above-described system interrupt processing time. It is believed that there is. That is, in the present embodiment, the mode setting of the system 30 is performed in consideration of the power state of the power source including the power generation amount, the charge amount, the power generation tendency, the charging tendency, and the like. There is an advantage that power consumption can be efficiently reduced while maintaining.

(Third embodiment)
In the first embodiment, when the interrupt occurs in the sleep state, the above-described system interrupt processing time is calculated. In the present embodiment, the system interrupt process is performed before the system shifts to the sleep state. This is different from the first embodiment in that time is calculated. Specific contents will be described below. In addition, about the part which is common in 1st Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted suitably. The basic configuration of the system of this embodiment is the same as that of the first embodiment. In the following description, the system of this embodiment is represented as 50.

  FIG. 14 is a block diagram illustrating a functional configuration realized when the CPU 110 mounted on the processor 100 executes an operating system (OS) 600 that is basic software, and hardware included in the processor 100. Here, it can be understood that a single OS 600 operates on the processor 100 and one or more processes (999-1 to 999-n) operate on the OS 600. In FIG. 14, the processor 100 includes hardware included in the processor 100, an OS 600 that operates on the processor 100, and one or more processes that operate on the OS 600.

  As illustrated in FIG. 14, the hardware included in the processor 100 includes a CPU 110, a first storage unit 910, a second storage unit 930, and a third storage unit 950. The third storage unit 950 stores setting information of the system 50 (information for setting the mode of the system 50) that is registered before the system 30 shifts to the sleep state and is read when returning from the sleep state. FIG. 15 is a diagram illustrating an example of setting information stored in the third storage unit 950. In the example of FIG. 15, as the setting information to be registered, the value of the voltage of the processor 100, the value of the frequency (number of clocks), the presence / absence of power supply to the primary cache 140, and the presence / absence of power supply to the secondary cache 150 are stored. ing. In the example of FIG. 15, the voltage value of the processor 100 is Vx, the frequency value is Fx, power supply to the primary cache 140 is performed (ON), and power supply to the secondary cache 150 is stopped (OFF). It is the setting. For example, when returning from the sleep state with this setting, power is supplied to the primary cache 140, while supply of power to the secondary cache 150 is stopped. The next cache 150 cannot be used.

  Returning to FIG. 14, the description will be continued. The OS 600 includes an interrupt waiting setting unit 210, an idle state detection unit 680, a calculation unit 630, a first determination unit 640, a sleep processing unit 690, an interrupt detection unit 620, a mode setting unit 650, and setting information. An acquisition unit 655 and an interrupt waiting cancellation unit 260 are included. The idle state detection unit 680 detects an idle state. The idle state indicates a state where the CPU 110 is not executing any processing.

  When the idle state is detected by the idle state detection unit 680, the calculation unit 630 uses the data stored in each of the first storage unit 910 and the second storage unit 930 to return the system 50 from the sleep state. The system interrupt processing time indicating the time until the processing to be executed is completed is calculated. As in the first embodiment, the system interrupt processing time calculated in the present embodiment is executed immediately after the system 50 returns from the sleep state without overlapping (overlapping) with other interrupt processing. Or a plurality of interrupt processes that are executed with at least some overlap. Here, the interrupt wait setting unit 210 of the present embodiment knows in advance the interrupt wait occurrence time of each interrupt type, and writes the interrupt type and the interrupt wait occurrence time in association with each other in the second storage unit 930. This is different from the first embodiment. That is, in the present embodiment, the correspondence relationship between the interrupt type and the interrupt wait occurrence time is written in the second storage unit 930 in advance.

  FIG. 16 illustrates an example of a method in which the calculation unit 630 calculates the system interrupt processing time using the first storage unit 910 and the second storage unit 930. In the example of FIG. 14, there are three interrupt types waiting for an interrupt: device reading, keyboard input, and timer interrupt. As shown in FIG. 16, the time when the interrupt processing by the device reading is started is set to t1, and the interrupt processing time is set to T1_s. In addition, the time when the interrupt processing by keyboard input is started is set to t2 (> t1), and the interrupt processing time is set to T2_s. Furthermore, the time when the interrupt processing by the timer interrupt is started is set to t3 (> t2), and the interrupt processing time is set to T3_s. In the example of FIG. 16, it can be seen that the interrupt generated immediately after the system 50 returns from the sleep state is an interrupt due to device reading, and an interrupt due to keyboard input occurs during the interrupt processing. Therefore, it can be understood that the system interrupt processing time in this case is the time for performing interrupt processing by device reading and interrupt processing by keyboard input. That is, in the example of FIG. 16, it can be said that the system interrupt processing time Ts is T2_s + (t2-t1).

  Returning to FIG. 14 again, the description will be continued. The first determination unit 640 determines the mode of the system 50 after the return from the system interrupt processing time calculated by the calculation unit 630, and writes setting information for setting the determined mode in the third storage unit 950. .

  The sleep processing unit 690 saves the data stored in the register 130, the primary cache 140, and the secondary cache 150 included in the processor 100 to the storage area 170, temporarily stops the operation of the processor 100, and saves power ( Set to sleep mode.

  The interrupt detection unit 620 detects an interrupt notification from inside and outside of the processor 100 and notifies the setting information acquisition unit 655 of the interrupt type specified by the interrupt notification.

  When the interrupt type is notified from the interrupt detection unit 620, the setting information acquisition unit 655 reads the setting information recorded in the third storage unit 950 and notifies the mode setting unit 650 of the setting information and the interrupt type. When notified from the setting information acquisition unit 655, the mode setting unit 650 sets the mode of the system 50 based on the notified setting information.

  FIG. 17 is a sequence diagram illustrating an example of an operation procedure from the detection of the idle state of the processor 100 to the transition to the sleep state. As shown in FIG. 17, first, the idle state detection unit 680 detects the idle state of the processor 100 (step S1600), and requests the calculation unit 630 to calculate the system interrupt processing time (step S1601). Receiving the request, the calculation unit 630 calculates the system interrupt processing time using the data stored in each of the first storage unit 910 and the second storage unit 930 (step S1602).

  FIG. 18 is a flowchart illustrating an example of calculating the system interrupt processing time by the calculation unit 630. The contents of steps S1700 to S1708 are the same as the contents of steps S800 to S808 of FIG. In step S1709 after step S1708, the calculation unit 630 generates an interrupt generation time ("the latest interrupt generation time" as the latest interrupt generation time) among interrupt types that generate an interrupt after returning from the sleep state. The time when the interrupt processing time of the interrupt type elapses is set as the system interrupt end time.

  Next, the calculation unit 630 determines whether or not the current system interrupt end time is earlier than the interrupt generation time of other interrupt types (step S1710). When it is determined that the system interrupt end time is earlier than the interrupt generation time of other interrupt types (result of step S1710: YES), the calculation unit 630 is scheduled to return from the sleep state (that is, the latest interrupt) The time from the occurrence time) to the system interrupt end time is calculated as the system interrupt processing time (step S1712). On the other hand, when it is determined that the system interrupt end time is later than the interrupt generation time of other interrupt types (result of step S1710: NO), the calculation unit 630 resets the system interrupt end time (step S1711). ). More specifically, the calculation unit 630 selects an interrupt type with the earliest interrupt generation time from among interrupt types whose interrupt generation time is earlier than the current system interrupt end time, and the interrupt generation time of the selected interrupt type Then, the time when the interrupt processing time of the selected interrupt type elapses is reset as the system interrupt end time. Then, the process returns to step S1710 described above.

  Returning to FIG. 17 again, the description will be continued. The calculation unit 630 notifies the first determination unit 640 of the system interrupt processing time calculated as described above, thereby requesting determination of the mode of the system 50 after returning from the sleep state (step S1603). ). The first determination unit 640 determines the mode of the system 50 after returning from the sleep state according to the system interrupt processing time notified from the calculation unit 630 (step S1604). The contents of step S1604 are the same as the contents of step S707 in FIG. Next, the first determination unit 640 writes the setting information of the determined mode in the third storage unit 950 (step S1605). Next, the first determination unit 640 requests the sleep processing unit 690 to execute sleep processing that causes the system 50 to transition to the sleep state (step S1606).

  The sleep processing unit 690 requested to execute the sleep process executes the sleep process according to the current mode of the system 50 (step S1607). For example, if power is supplied to the primary cache 140, the sleep processing unit 690 saves the data stored in the primary cache 140 in the storage area 170. For example, if the power is supplied to the secondary cache 150, the sleep processing unit 690 saves the data stored in the secondary cache 150 to the storage area 170. Then, the sleep processing unit 690 saves the data stored in the register 130 to the storage area 170, and temporarily stops the operation of the processor 100. Thereby, the system 50 shifts to a power saving state (sleep state).

  FIG. 19 is a sequence diagram illustrating an example of an operation procedure from when an interrupt is generated to the processor 100 to when interrupt processing is started. As shown in FIG. 17, first, the interrupt detection unit 220 detects the occurrence of an interrupt by receiving an interrupt notification from inside and outside the processor 100 (step S1800). Next, the interrupt detection unit 220 identifies the interrupt type (interrupt type for which interrupt processing is started) of the generated interrupt from the received interrupt notification (step S1801). Next, the interrupt detection unit 220 detects whether or not the state of the system 50 is a sleep state (step S1802). When the system 50 is in the sleep state (result of step S1802: YES), the interrupt detection unit 220 notifies the setting information acquisition unit 655 of the specified interrupt type (step S1804). On the other hand, when the state of the system 50 is not the sleep state (result of step S702: NO), the interrupt detection unit 220 notifies the interrupt wait cancellation unit 260 of the specified interrupt type (step S1803). After step S1803, the process proceeds to step S1809. The contents after step S1809 are the same as the contents after step S711 in FIG.

  The setting information acquisition unit 655 reads the setting information written in the third storage unit 950 when receiving the notification of the interrupt type in which the interrupt has occurred from the interrupt detection unit 620 (step S1805). Next, the setting information acquisition unit 655 notifies the mode setting unit 650 of the read setting information and interrupt type (step S1806). The mode setting unit 650 sets the mode of the system 50 according to the setting information notified from the setting information acquisition unit 655 (step S1807). As illustrated in FIG. 15, when “first cache: ON, second cache: OFF” is written in the third storage unit 950, the mode setting unit 650 supplies power to the primary cache 140. Is started and initialization is performed, but power is not supplied to the secondary cache 150. Then, the mode setting unit 650 notifies the interrupt waiting cancellation unit 260 of the interrupt type in which the interrupt has occurred (step S1808). Since the contents after step S1808 are the same as the contents after step S710 in FIG. 7, detailed description thereof is omitted.

  As in the first embodiment described above, the method of calculating the system interrupt processing time when an interrupt occurs in the sleep state and determining the mode after the return is initialized when the system returns from the sleep state. Since these calculations must be performed in a state where they are not performed, there is a problem that the time required for the calculation and the power consumption of the processor 100 are large. For example, immediately after the system returns from the sleep state, the voltage and frequency remain at the values in the sleep state, and power supply to the primary cache 140 and the secondary cache 150 has not started. A situation where a memory access occurs can be considered. On the other hand, in the present embodiment, the system interrupt processing time can be calculated in an optimal situation by calculating the above-described system interrupt processing time before the system enters the sleep state (before the system stops). it can. Before the system transitions to the sleep state, the voltage, frequency, primary cache 140, and secondary cache 150 are in substantially the same state as in the mode in which the system is operating normally. The system interrupt processing time can be calculated in a situation suitable for calculating the interrupt processing time. That is, according to the present embodiment, it is possible to execute the system interrupt processing time calculation process while efficiently reducing the power consumption of the system.

(Fourth embodiment)
Similar to the second embodiment, the present embodiment is different from the third embodiment in that it has a function capable of setting a mode according to the power state of the power source. Specific contents will be described below. In addition, about the part which is common in 2nd Embodiment and 3rd Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted suitably. The basic configuration of the system of this embodiment is the same as that of the second embodiment. In the following description, the system of this embodiment is represented as 70.

  FIG. 20 is a block diagram illustrating a configuration of functions realized when the CPU 110 mounted on the processor 100 executes an operating system (OS) 800 that is basic software, and hardware included in the processor 100. As illustrated in FIG. 20, the hardware included in the processor 100 includes a CPU 110, a first storage unit 910, a second storage unit 930, a third storage unit 950, a fourth storage unit 975, and a fifth storage. Part 990. In FIG. 20, the hardware included in the processor 100, the OS 800 that operates on the processor 100, and one or more processes that operate on the OS 800 are represented by the processor 100.

  FIG. 21 is a diagram illustrating an example of data stored in the fourth storage unit 975. In the example of FIG. 21, the fourth storage unit 975 stores a power generation tendency, a charge amount, and a module used for mode determination in association with each other. Similarly to the second embodiment, the fourth storage unit 975 can be regarded as storing the power state of the power supply and the mode determination method in association with each other. In the case of this figure, the power generation tendency shows an increasing tendency, and when the charge amount is less than the first threshold (for example, 40%), the setting information acquisition unit 655 is used to determine the mode of the system 70. ing. That is, the mode is determined using the setting information acquired from the setting information acquisition unit 655. Further, when the power generation tendency shows an increasing tendency and the charge amount is equal to or more than the first threshold, it indicates that the mode determined by the second determination unit 490 is used.

  Further, when the power generation tendency shows a flat tendency and the charge amount is equal to or higher than the second threshold value (for example, 50%) and less than the third threshold value (for example, 60%) larger than the second threshold value, the setting information is acquired. The mode is determined using the setting information acquired from the section 855. In addition, for example, the power generation tendency shows a flat tendency, and when the charge amount is equal to or greater than the third threshold, the mode determined by the second determination unit 490 is used.

  Furthermore, the power generation tendency shows a tendency to decrease, and when the charge amount is a fourth threshold value (for example, 70%) or more, it indicates that the mode is determined using the setting information acquired from the setting information acquisition unit 855. ing. In addition, the power generation tendency shows a tendency to decrease, and when the charge amount is less than the fourth threshold, the mode determined by the second determination unit 490 is used. Not limited to this, the fourth storage unit 975 may have a configuration in which, for example, only the charge amount and the module to be used are stored in association with each other, as in the fourth storage unit 970, or a change in the power generation amount The configuration may be such that only the amount and the module to be used are stored in association with each other.

  Returning to FIG. 20 again, the description will be continued. As illustrated in FIG. 20, the OS 800 includes an interrupt waiting setting unit 210, an idle state detection unit 680, a calculation unit 630, a first determination unit 640, a sleep processing unit 690, an interrupt detection unit 820, and a power state. The acquisition unit 480, the determination unit 870, the second determination unit 490, the setting information acquisition unit 655, the mode setting unit 850, and the interrupt wait release unit 260 are included.

  The interrupt detection unit 820 detects an interrupt notification from inside or outside the processor 100 and notifies the power status acquisition unit 480 of the interrupt type specified by the interrupt notification.

  The determination unit 870 determines a mode determination method for the system 70 based on the data stored in the fourth storage unit 975. In the present embodiment, when an interrupt occurs in the sleep state, the power state acquisition unit 480 acquires the power state from the power state management unit 360 and notifies the determination unit 870 of the acquired power state. The determination unit 870 selects a module to be used for mode determination of the system 70 based on the power state acquired from the power state acquisition unit 480 and the data stored in the fourth storage unit 975. For example, when the setting information acquisition unit 655 is selected as a module used for mode determination, the determination unit 870 requests the setting information acquisition unit 655 to extract setting information from the third storage unit 950. Then, the setting information acquisition unit 855 acquires the setting information stored in the third storage unit 950 and notifies the mode setting unit 850 of the setting information. On the other hand, when the second determination unit 490 is selected as the module used for mode determination, the determination unit 870 requests the second determination unit 490 to determine the state. This determination method is the same as in the second embodiment.

  The mode setting unit 850 sets the mode of the system 70 using the setting information notified from the setting information acquisition unit 655 or the second determination unit 490.

  FIG. 22 is a sequence diagram illustrating an example of an operation procedure of the processor 100 from when an interrupt occurs until interrupt processing is started. First, the interrupt detection unit 820 detects the occurrence of an interrupt by receiving an interrupt notification from inside and outside the processor 100 (step S2000). Next, the interrupt detection unit 820 identifies an interrupt type (interrupt type for which interrupt processing is started) corresponding to the generated interrupt from the received interrupt notification (step S2001). Next, the interrupt detection unit 820 detects whether or not the state of the system 70 is a sleep state (step S2002). If the system 70 is in the sleep state (result of step S2002: YES), the interrupt detection unit 820 notifies the identified interrupt type to the power state acquisition unit 480 (step S2004). On the other hand, when the state of the system 70 is not the sleep state (the result of step S2002: NO), the interrupt detection unit 820 notifies the interrupt waiting release unit 260 of the specified interrupt type (step S2003). After step S2003, the process proceeds to step S2017. Since the content of the processing after step S2017 is the same as the content of the processing after step S711 of FIG. 7, detailed description is omitted.

  When receiving the notification of the interrupt type of the generated interrupt from the interrupt detection unit 820, the power state acquisition unit 480 acquires the power state from the power state management unit 360 (step S2005). Then, the power state acquisition unit 460 notifies the determination unit 870 of the interrupt type and the power state (step S2006).

  The determination unit 870 determines a mode determination method of the system 70 from the power state acquired from the power state acquisition unit 480 and the data stored in the fourth storage unit 975 (step S2007). In the example of FIG. 21, the determination unit 870 operates the setting information acquisition unit 655 to change the mode of the system 70 from the power state acquired from the power state acquisition unit 480 and the data stored in the fourth storage unit 975. Whether to determine (in other words, to determine the mode of the system 70 using the setting information stored in the third storage unit 950), or to operate the second determination unit 490 to determine the mode of the system 70 To decide. Hereinafter, an example of determining the mode determination method of the system 70 will be described with reference to FIG. For example, when the power generation tendency obtained from the power state acquisition unit 480 is increasing and the charge amount is 30%, the determination unit 870 selects the setting information acquisition unit 655 as a module used for mode determination. That is, in this case, the determination unit 870 determines to determine the mode of the system 70 using the setting information stored in the third storage unit 950. On the other hand, for example, when the power generation tendency obtained from the power state acquisition unit 480 is flat and the charge amount is 80%, the determination unit 870 selects the second determination unit 490 as a module used for mode determination. . That is, in this case, the determination unit 870 determines to operate the second determination unit 490 to determine the mode of the system 70.

  When the determination unit 470 determines to determine the mode of the system 70 without using the setting information acquisition unit 655 (the result of step S2008: NO), that is, the second determination unit 490 is operated to operate the mode of the system 70. If it is determined to determine, the determination unit 870 notifies the second determination unit 490 of the interrupt type and power state of the generated interrupt (step S2012). The second determination unit 490 determines the mode of the system 70 from the power state sent from the determination unit 870 and the data stored in the fifth storage unit 990 (step 2013). This determination method is the same as in the second embodiment. Then, the determination unit 870 notifies the mode setting unit 850 of the determined mode setting information and the interrupt type in which the interrupt has occurred (step S2014). The mode setting unit 850 sets the mode of the system 70 according to the setting information notified from the determination unit 870 (step S2015). As a result, the system 70 returns from the sleep state and shifts to the mode set by the mode setting unit 850.

  On the other hand, when it is determined to determine the mode of the system 70 using the setting information acquisition unit 655 (the result of step S2008: YES), that is, the system 70 using the setting information stored in the third storage unit 950. If it is determined to determine the mode, the determination unit 870 notifies the setting information acquisition unit 655 of the interrupt type (step S2009). The setting information acquisition unit 655 reads the setting information stored in the third storage unit 950 (step S2010), and notifies the mode setting unit 850 of the read setting information and the interrupt type in which the interrupt has occurred (step S2010). Step S2011). The mode setting unit 850 sets the mode of the system 70 according to the setting information notified from the determination unit 870 (step S2015). As a result, the system 70 returns from the sleep state and shifts to the mode set by the mode setting unit 850.

  As described above, the method of reducing the power consumption by shifting the processor 100 to the sleep state can reduce the power consumption of the processor 100, but has a large overhead due to the processing for temporarily stopping the system 70. The power consumption generated due to the processing (for example, processing such as saving and restoring registers and flushing the cache memory) and the influences thereof (such as an increase in memory access due to the flushing of the cache memory) cannot be ignored. In the first state where the power generation amount and the charge amount are sufficient, it is more efficient to ignore the power consumption because the processing time can be shortened, but the power generation amount and the charge amount are not sufficient. In the case of two states, it is considered appropriate to operate with the minimum set from the viewpoint that the system 70 operates. In the case of the third state in which the power generation amount and the charge amount are between the first state and the second state, the mode corresponding to the above-described system interrupt processing time (stored in the third storage unit 950) It is considered appropriate to operate the system 70 in the mode set by the setting information. That is, in this embodiment, since the mode setting of the system 70 is performed in consideration of the power state of the power supply, there is an advantage that the power consumption can be efficiently reduced while maintaining the processing time according to the power status of the system 70. is there.

(Fifth embodiment)
This embodiment is different from the fourth embodiment in that it is determined whether or not to calculate the system interrupt processing time according to the power state of the power supply in the stage before the system enters the sleep state. Specific contents will be described below. In addition, about the part which is common in 4th Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted suitably. The basic configuration of the system of this embodiment is the same as that of the fourth embodiment. In the following description, the system of this embodiment is represented as 90.

  FIG. 23 is a block diagram illustrating a configuration of functions realized when the CPU 110 mounted on the processor 100 executes an OS (operating system) 1000 that is basic software, and hardware included in the processor 100. As illustrated in FIG. 20, the hardware included in the processor 100 includes a CPU 110, a first storage unit 910, a second storage unit 930, a third storage unit 950, a fourth storage unit 970, and a fifth storage. Part 990. In FIG. 23, the processor 100 includes hardware included in the processor 100, an OS 1000 that operates on the processor 100, and one or more processes that operate on the OS 1000.

  As shown in FIG. 23, the OS 1000 includes an interrupt waiting setting unit 210, an idle state detection unit 680, a power state acquisition unit 480, a second determination unit 1090, a determination unit 1085, a calculation unit 630, 1 determination unit 640, sleep processing unit 690, interrupt detection unit 820, setting information acquisition unit 655, mode setting unit 650, and interrupt wait release unit 260.

  The determination unit 1085 determines a mode determination method of the system 100 according to the power state notified from the power state acquisition unit 480. The second determination unit 1090 determines the mode of the system 100 according to the power state of the power source, and registers the determined mode in the third storage unit 950.

  FIG. 24 is a sequence diagram illustrating an example of an operation procedure from the detection of the idle state of the processor 100 to the transition to the sleep state. As shown in FIG. 24, the idle state detection unit 680 first detects the idle state of the processor 100 (step S2200), and requests the power state acquisition unit 480 to read the power state (step S2201). Receiving the request, the power status acquisition unit 480 acquires the power status from the power status management unit 360 (step S2202). Next, the power state acquisition unit 480 notifies the determination unit 1085 of the acquired power state (step S2203). Then, the determination unit 1085 determines a mode determination method of the system 90 from the power state acquired from the power state acquisition unit 480 (step S2204). In the example of FIG. 11, the determination unit 1085 calculates the system interrupt processing time by the calculation unit 630 from the power state of the power source acquired from the power state acquisition unit 480 and the data stored in the fourth storage unit 970. It is determined whether to determine 90 modes or to determine the mode of the system 90 using the second determination unit 1090.

  For example, in the case of FIG. 11, a method for determining the mode of the system 90 is determined based on the power generation tendency and the charge amount. For example, if the power generation tendency shows an increasing tendency and the charge amount is 30%, the mode of the system 90 is determined by calculating the system interrupt time by the calculation unit 630. For example, if the power generation tendency shows an increasing tendency and the charge amount is 50%, the mode of the system 90 is determined using the second determination unit 1090. Further, for example, when the power generation tendency is flat and the charge amount is 55%, the mode of the system 90 is determined by calculating the system interruption time by the calculation unit 630. For example, if the power generation tendency is flat and the charge amount is 20%, the mode of the system 90 is determined using the second determination unit 1090. Further, for example, when the power generation tendency is reduced and the charge amount is 80%, the mode of the system 90 is determined by calculating the system interruption time by the calculation unit 630. For example, if the power generation tendency shows a decreasing tendency and the charge amount is 60%, the mode of the system 90 is determined using the second determination unit 1090. However, the present invention is not limited to this, and the mode determination method may be determined based on, for example, only the charge amount or only the amount of change in power generation amount.

  When it is determined not to calculate the system interrupt processing time by the calculation unit 630 (result of step S22005: NO), that is, when it is determined to determine the mode of the system 90 using the second determination unit 1090 The determination unit 1085 notifies the second determination unit 1090 of the power state and requests determination of the mode of the system 90 (step S2207). The second determination unit 1090 determines the mode of the system 90 after returning from the sleep state according to the power state notified from the determination unit 1085 and the data stored in the fifth storage unit (step S2208). For example, when the power generation tendency shows an increasing tendency and the charge amount is 50%, the second determination unit 1090 determines the second mode in which the system 90 operates all the elements of the system as the mode of the system 90. be able to. Further, for example, when the power generation tendency shows a flat tendency and the charge amount is 70%, the second determination unit 1090 can determine the second mode as the mode of the system 90. Further, for example, when the power generation tendency shows a flat tendency and the charge amount is 40%, the second determination unit 1090 sets the first mode in which the minimum element that minimizes the power consumption is operated as the mode of the system 90. Can be determined as In addition, for example, when the power generation tendency tends to decrease and the charge amount is 60%, the second determination unit 1090 can determine the first mode as the mode of the system 90.

  Then, the second determination unit 1090 writes the setting information of the determined mode in the third storage unit 950 (step S2209). Next, the second determination unit 1090 requests the sleep processing unit 690 to execute sleep processing that causes the system 90 to enter the sleep state (step S2210).

  On the other hand, when it is determined that the calculation unit 630 calculates the system interrupt processing time (result of step S2205: YES), the determination unit 1085 requests the calculation unit 630 to calculate the system interrupt processing time ( Step S2206). The subsequent contents after step S2211 are the same as the contents after step S1602 in FIG.

  As described above, in the present embodiment, before the system 90 shifts to the sleep state (before the system stops), the mode of the system 90 (the system after returning from the sleep state) according to the power state of the power source. 90 mode), the processing can be executed while efficiently reducing the power consumption of the system 90 in accordance with the power state of the system 90. The method for determining the optimum system 90 mode can reduce the power consumption of the system 90, while processing for determining the mode of the system 90 (calculation processing of the system interrupt processing time by the calculation unit 630, etc.). This increases the processing time and power consumption. In the present embodiment, the mode of the system 90 is limited to the case where the mode of the system 90 must be dynamically determined according to the power state of the system 90 (when the power state satisfies the predetermined condition described above). By performing the process for determining the power consumption, there is an advantage that the power consumption can be efficiently reduced.

(Sixth embodiment)
In the first embodiment described above, the value of the interrupt processing time stored in the first storage unit 910 is a fixed value. However, in this embodiment, the value of the interrupt processing time stored in the first storage unit 910 is Set to variable. Specific contents will be described below. In addition, about the part which is common in 1st Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted suitably. The basic configuration of the system of this embodiment is the same as that of the first embodiment. In the following description, the system of the present embodiment is expressed as 95.

  FIG. 25 is a block diagram illustrating a functional configuration realized when the CPU 110 mounted on the processor 100 executes an operating system (OS) 1200 that is basic software, and hardware included in the processor 100. Here, it can be understood that a single OS 1200 operates on the processor 100 and one or more processes (999-1 to 999-n) operate on the OS 1200. In FIG. 25, the processor 100 includes hardware included in the processor 100, an OS 1200 that operates on the processor 100, and one or more processes that operate on the OS 1200.

  As shown in FIG. 25, the hardware included in the processor 100 includes a CPU 110, a first storage unit 910, and a second storage unit 930. The OS 1200 includes an interrupt wait setting unit 210, an interrupt detection unit 220, a calculation unit 230, a first determination unit 240, a mode setting unit 250, an interrupt wait release unit 1260, and an update unit 1290.

  The interrupt wait release unit 1260 is different from the first embodiment in that it has a function of notifying the update unit 1290 of the interrupt type corresponding to the interrupt process when starting the interrupt process.

  The update unit 1290 starts measuring the interrupt processing time corresponding to the interrupt type for which the interrupt processing is started when the interrupt processing is started, and stops measuring the interrupt processing time when the interrupt processing is completed. Of the interrupt processing times stored in the first storage unit 910, the value of the interrupt processing time corresponding to the interrupt type is replaced (updated) with the measurement result.

  FIG. 26 is a sequence diagram illustrating an example of an operation procedure from when an interrupt occurs to the processor 100 to when interrupt processing is started. Since the contents of steps S2400 to S2410 are the same as the contents of steps S700 to S710 in FIG. 7, detailed description thereof is omitted. In step S2410, the interrupt wait cancellation unit 1260 that has received the notification of the interrupt type in which the interrupt has occurred from the mode setting unit 250 notifies the update unit 1290 of the interrupt type in which the interrupt has occurred (step S2411). Receiving the notification of the interrupt type that caused the interrupt, the updating unit 1290 starts measuring the interrupt processing time corresponding to the notified interrupt type (step S2414). For example, the update unit 1290 may manage the interrupt type and the current time in association with each other. The contents of steps S2412 and S2413 in FIG. 26 are the same as the contents of steps S711 and S712 in FIG.

  FIG. 27 is a sequence diagram illustrating an example of an operation procedure of the processor 100 when an interrupt wait occurs. Since the contents of steps S2500 and S2501 are the same as the contents of steps S600 and S601 of FIG. 6, detailed description thereof is omitted. After step S2501, the interrupt wait setting unit 210 notifies each of the second storage unit 930 and the update unit 1290 of the interrupt type that has been interrupted and the interrupt wait occurrence time (step S2502). Since the content of step S2503 is the same as the content of step S603 of FIG. 6, detailed description thereof is omitted.

  The update unit 1290 that has received the notification of the interrupt type that has been waiting for an interrupt and the time of occurrence of the interrupt wait stops the measurement of the interrupt processing time corresponding to the notified interrupt type, and the measurement result corresponds to the interrupt type. Is acquired as the interrupt processing time (step S2504). Next, the update unit 1290 updates the first storage unit 910 (step S2505). More specifically, the update unit 1290 includes the interrupt processing time acquired in step S2504 as the interrupt processing time value corresponding to the notified interrupt type among the interrupt processing times stored in the first storage unit 910. Replace with the value of.

  As described above, in the present embodiment, in order to measure the time from the start to the end of interrupt processing and to set the value of the interrupt processing time stored in the first storage unit 910 variably, The value of the processing time stored in the first storage unit 910 can be approximated to an optimal value in the current system.

(Modification)
As mentioned above, although embodiment of this invention was described, each above-mentioned embodiment was shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, in the first embodiment described above, the return factor indicating the factor for returning from the sleep state is the occurrence of an interrupt. After the system recovers from the sleep state, until interrupt processing that is executed independently without overlapping with other interrupt processing, or multiple interrupt processing that is executed with at least some overlap is completed Is calculated as the system interrupt processing time, and the system mode is set according to the calculated system interrupt processing time. However, the present invention is not limited to this. That is, the return factor is not limited to the occurrence of an interrupt, and can be set arbitrarily. When the return factor occurs, the system processing time (system interrupt processing time) indicating the time required for processing after returning from the sleep state May be configured to set the mode according to this example.

  In the example of FIG. 15, as an example of the setting information stored in the third storage unit 950, the voltage of the processor 100, the frequency, the presence / absence of power supply to the primary cache 140, and the presence / absence of power supply to the secondary cache 150 are given. Although described, the present invention is not limited to this, and the contents of the setting information can be arbitrarily set. For example, a configuration using only the clock (frequency) as the setting information may be used. In addition, a configuration may be used in which information specifying a memory transfer method and a memory transfer rate is used as setting information. In addition, when the instruction set used at the time of interrupt processing is limited to a part, information that specifies that power supply to other parts related to the instruction set is stopped (power off) is used as setting information It may be. For example, in the case of the ARM processor, an instruction set called NEON is prepared separately from the ARM standard instruction. However, when this is configured separately as a system, the power supply to the NEON part can be stopped. . FIG. 28 is a diagram illustrating an example in which information specifying each of a memory transfer method, a transfer rate, and an available instruction set is used as setting information.

  In each of the above-described embodiments, the processor 100 includes the register 130, the primary cache 140, and the secondary cache 150. However, the present invention is not limited to this, and for example, the processor 100 includes the primary cache 140 and the secondary cache 150. The structure which does not have 150 may be sufficient. With this configuration, the primary cache 140 and the secondary cache 150 are not included as system mode setting targets (system configuration targets), and processing related thereto can be omitted. Further, instead of the primary cache 140 and the secondary cache 150, an internal memory called an instruction memory or a data memory may be included, or a configuration including both may be used. With this configuration, an internal memory may be included as a system mode setting target, and processing related thereto may be performed.

  Furthermore, a configuration in which at least a part of the functions of the OS (200, 400, 600, 800, 1000, 1200) described above is realized by hardware other than the processor 100 may be employed. For example, as illustrated in FIG. 29, the function of the processor 100 according to the first embodiment may be realized by an interrupt management unit 1460 that is hardware different from the processor 100. In this case, the management of the first storage unit 910 is performed by the interrupt management unit 1460, and when the data stored in the first storage unit 910 is read by the OS 200, the data is read via the interrupt management unit 1460. The system in the example of FIG.

  For example, as illustrated in FIG. 30, the power state management unit 360 implemented as hardware in the second embodiment described above is configured as a power management unit 1690 that is one function in the OS 1600. Also good. The power management unit 1690 obtains a power generation amount from the power generation module 380 and a charge amount from the battery 385, and periodically acquires those values to estimate a power generation tendency and a charge tendency. The determination unit 1670 can realize the same function by acquiring the power state of the target system from the power management unit 1690.

  Moreover, the structure which measures the interruption processing time currently performed in the update part 1290 mentioned above in each process (999-1 to 999-n) may be sufficient. Further, in the above description, the interrupt processing time is measured from the interrupt occurrence time to the interrupt wait occurrence time, but other methods are also conceivable. In the case where a plurality of interrupt processes are performed, a method of accurately grasping the time during which each interrupt process is performed and using the time during which the interrupt process is performed as an interrupt processing time may be used.

  FIG. 31 is a block diagram illustrating a configuration example of the system 15 according to a modification of the first embodiment. As shown in FIG. 31, the system 15 includes a processor 100, a storage area 170, and a control device 197, which are mutually connected by a bus 195. The processor 100 is a processing device that can execute one or more processes. The control device 197 receives an interrupt request indicating an interrupt request by the device from each of a plurality of devices (device 1 (199-1) to device n (199-n)), and receives the received interrupt request. Whether to transmit to the processor 100 is determined. Based on the condition, the control device 197 stores the received interrupt request or transmits it to the processor 100. Even if the time at which an interrupt occurs by the control device 197 as in the system 15 is changed, the state (mode) of the system 15 is set in accordance with it, so that there is an advantage that power consumption can be efficiently reduced.

  Further, the program executed by the CPU 110 may be provided by being stored on a computer connected to a network such as the Internet and downloaded via the network. Further, the program executed by the CPU 110 may be provided or distributed via a network such as the Internet. The program executed by the CPU 110 may be provided by being incorporated in advance in a ROM or the like.

10 system 30 system 50 system 70 system 90 system 100 processor 110 CPU
120 Storage unit 130 Register 140 Primary cache 150 Secondary cache 170 Storage area 190 Bus 210 Interrupt wait setting unit 220 Interrupt detection unit 230 Calculation unit 240 First determination unit 250 Mode setting unit 260 Interrupt wait release unit 360 Power state management unit 380 Power generation module 385 Battery 390 Bus 470 Determination unit 490 Second determination unit 620 Interrupt detection unit 630 Calculation unit 640 First determination unit 650 Mode setting unit 655 Setting state acquisition unit 680 Idle state detection unit 690 Sleep processing unit 850 Mode setting unit 870 Determination Unit 910 first storage unit 930 second storage unit 950 third storage unit 1085 determination unit 1090 second determination unit 1260 interrupt wait release unit 1290 update unit 1460 interrupt management unit 1670 determination unit 1690 power management unit

Claims (14)

When a system including a plurality of elements capable of individually controlling power is limited to a predetermined number of elements to which power is supplied and a factor of returning from the sleep state in which the operation is stopped occurs, the sleep state A setting unit for setting a mode indicating an operation state of the system according to a system processing time indicating a time required for processing after returning from the system,
Control device. When a system including a plurality of elements capable of individually controlling power is limited to a predetermined number of elements to which power is supplied and a factor of returning from the sleep state in which the operation is stopped occurs, the sleep state Setting a mode indicating the operating state of the system according to the system processing time indicating the time required for processing after returning from
Control device. When a factor for returning from the sleep state has occurred, a mode indicating a system operation state is set according to a system processing time indicating a time required for processing after returning from the sleep state.
Control device. When a system including a plurality of elements capable of individually controlling power is limited to a predetermined number of elements to which power is supplied and a factor of returning from the sleep state in which the operation is stopped occurs, the sleep state Operating the system in a mode corresponding to the system processing time indicating the time required for processing after returning from
Control device. When a factor for returning from the sleep state occurs, the system is operated in a mode corresponding to the system processing time indicating the time required for processing after returning from the sleep state.
Control device. An information processing system including a plurality of elements capable of individually controlling power,
When the information processing system has a factor for returning from the sleep state in which the number of the elements to which power is supplied is limited to a predetermined number and stopping the operation, it is necessary for processing after returning from the sleep state. Operates in a time-dependent mode,
Information processing system. When a factor to return from the sleep state occurs, it operates in a mode according to the time required for processing after returning from the sleep state.
Information processing system. On the computer,
When a system including a plurality of elements capable of individually controlling power is limited to a predetermined number of elements to which power is supplied and a factor of returning from the sleep state in which the operation is stopped occurs, the sleep state A program for executing a step of setting a mode indicating an operating state of the system according to a system processing time indicating a time required for processing after returning from the system. On the computer,
When a system including a plurality of elements capable of individually controlling power is limited to a predetermined number of elements to which power is supplied and a factor of returning from the sleep state in which the operation is stopped occurs, the sleep state A program for executing a step of setting a mode indicating an operating state of the system according to a system processing time indicating a time required for processing after returning from the system. On the computer,
A program for executing a step of setting a mode indicating a system operating state according to a system processing time indicating a time required for processing after returning from the sleep state when a factor for returning from the sleep state occurs . On the computer,
When a system including a plurality of elements capable of individually controlling power is limited to a predetermined number of elements to which power is supplied and a factor of returning from the sleep state in which the operation is stopped occurs, the sleep state A program for executing a step of operating the system in a mode corresponding to a system processing time indicating a time required for processing after returning from the system. On the computer,
A program for executing a step of operating the system in a mode corresponding to a system processing time indicating a time required for processing after returning from the sleep state when a factor for returning from the sleep state occurs. In a computer installed in an information processing system that includes multiple elements that can individually control power,
When the information processing system has a factor for returning from the sleep state in which the number of the elements to which power is supplied is limited to a predetermined number and stopping the operation, it is necessary for processing after returning from the sleep state. A program for executing a step in which the information processing system operates in a mode according to time. In the computer installed in the information processing system,
A program for causing the information processing system to execute a step in a mode according to a time required for processing after returning from the sleep state when a factor for returning from the sleep state occurs.

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