JP2015037343A - Step-down device, step-up device and transformation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transformation device that performs an appropriate voltage transformation compactly and inexpensively in a simple configuration.SOLUTION: Complementary on/off actions of FETs 11, 12 and complementary on/off actions of FETs 13, 14 are repeated to transform a voltage applied between a drain of the FET 11 and a source of the FET 12 and output the transformed voltage from between a drain of the FET 13 and a source of the FET 14. An output circuit 16 outputs one PWM signal and another used to turn on/off the FETs 11, 14, respectively. If the one (or the other) PWM signal outputted has a duty of 100% (or 0%), the output circuit 16 outputs a PWM signal involving repeated turn-on/off actions of the FET 11 (or the FET 14) and having a total of an on period of the FET 11 (or the FET 14) and an off period adjacent to the on period longer than a period of the one (or the other) PWM signal.

Description

  The present invention relates to a step-down device that steps down an applied voltage, a step-up device that steps up an applied voltage, and a transformer device that steps up and steps down the applied voltage and transforms the voltage.

  Currently, a vehicle is equipped with a transformer device (for example, see Patent Document 1) that steps up and down a voltage applied by a battery to transform the voltage and applies the transformed voltage to a load.

  A conventional transformer as described in Patent Document 1 includes first, second, third, and fourth switches that are, for example, N-channel FETs (Field Effect Transistors). In this case, in the conventional transformer, the source of the first switch and the drain of the second switch are connected to one end of the coil, and the source of the third switch and the fourth switch are connected to the other end of the coil. The drain is connected. The source of the second switch is connected to the source of the fourth switch. In the conventional transformer, the negative electrode of the battery is connected to the source of the second switch, the positive electrode of the battery is connected to the drain of the first switch, and the sources of the second and fourth switches are grounded.

  Each of the first, second, third, and fourth switches is turned on when a voltage equal to or higher than a predetermined voltage is applied to the gate with reference to the source potential, and a voltage lower than the predetermined voltage at the gate with reference to the source potential. Turns off when is applied. In the conventional transformer, by adjusting the gate voltages of the first, second, third and fourth switches, complementary on / off of the first and second switches and third and fourth switches The voltage applied by the battery is transformed.

  Specifically, the voltage applied by the battery is boosted by repeating complementary ON / OFF of each of the third and fourth switches while maintaining the first and second switches on and off, respectively. . Then, the voltage applied by the battery is stepped down by repeating complementary ON / OFF of each of the first and second switches while maintaining the third and fourth switches on and off, respectively. The voltage transformed by step-up or step-down is output from the drain of the third switch and the source of the fourth switch, and feeds the load connected between the drain of the third switch and the source of the fourth switch. To do.

JP 2005-192212 A

  In the conventional transformer, in order to turn on the first and third switches whose sources are not grounded, a capacitor is usually connected between the source and the gate for each of the first and third switches.

  A capacitor connected between the source and gate of the first switch stores the power supplied by the battery when the first and second switches are off and on respectively, and discharges when the first switch is turned on. Then, a voltage higher than a certain voltage is applied between the source and drain of the first switch to turn on the first switch. Similarly, a capacitor connected between the source and gate of the third switch stores the power supplied by the battery when the third and fourth switches are off and on respectively, and turns on the third switch. In this case, the third switch is turned on by applying a voltage higher than a certain voltage between the source and drain of the third switch.

  In a conventional transformer, for example, when either one of step-down and step-up is performed for a long time, there is a possibility that the first switch or the third switch is kept on for a long time. In this case, for each of the first and third switches, the charge accumulated in the capacitor connected between the source and the gate is reduced by maintaining the switch on for a long period of time, and the voltage between the source and the gate becomes a certain voltage or more May not be maintained. For this reason, the conventional transformer device has a problem that the voltage applied to the gates of the first and third switches becomes unstable, and the transformation cannot be performed appropriately.

  A similar problem exists in the conventional step-down device and step-up device in which two switches each having one end connected to one end of the coil and the other end of one switch are grounded.

  In the conventional step-down device, the two switches are repeatedly turned on and off repeatedly to step down the voltage applied between the other ends of the two switches, and the stepped down voltage is applied to the other end of the coil and one of the two ends. Applied to a load connected between the other end of the switch.

  In the conventional booster, the voltage applied between the other end of the coil and the other end of one switch is boosted by repeating two complementary on / off operations, and the boosted voltage is switched to two switches. It is applied to a load connected between the other ends.

  In each of such conventional step-down devices and step-up devices, when the voltage applied by the battery is applied to the load as it is without performing step-down or step-up, the other switch may be kept on for a long period of time. . Therefore, when the other switch is a semiconductor switch such as an N-channel FET, for example, the voltage applied to the gate of the other switch becomes unstable. There is a problem that boosting cannot be performed appropriately.

  As a configuration that solves the problems of the conventional transformer, step-down device, and step-up device, the capacitor that turns on the semiconductor switch can be charged regardless of the on / off state of the switch included in each device. A configuration in which a possible charge pump circuit is provided can be considered.

  However, when each of the conventional transformer, step-down device, and step-up device is provided with a charge pump, there is a problem that the device becomes large, the configuration becomes complicated, and the manufacturing cost increases.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a transformer device that can appropriately perform transformation, has a simple configuration, is small, and is inexpensive.
Another object of the present invention is to provide a step-down device that can appropriately perform step-down, has a simple structure, is small, and is inexpensive.
Another object of the present invention is to provide a booster that can perform boosting appropriately, has a simple configuration, is small, and is inexpensive.

  The step-down device according to the present invention repeats complementary ON / OFF of two switches each having one end connected to one end of a coil, thereby applying a voltage applied between the other ends of the two switches. In a step-down device that steps down and outputs a stepped-down voltage from between the other end of one of the two switches and the other end of the coil, on / off of the other switch of the two switches An output circuit for outputting a PWM signal used for switching, and when the duty of the output PWM signal is 100%, the output circuit repeatedly switches on / off the other switch, and the other switch The PWM signal is output so that the sum of the ON period and the OFF period adjacent to the ON period is longer than the period of the output PWM signal. And wherein the are.

  In the present invention, one end of each of the two switches is connected to one end of the coil. The two switches are repeatedly turned on / off in a complementary manner, for example, a voltage applied between the other ends of the two switches by a battery is stepped down. The stepped-down voltage is output from between the other end of one of the two switches and the other end of the coil, for example, a load connected between the other end of one switch and the other end of the coil. Supply power.

  The output circuit outputs a PWM (Pulse Width Modulation) signal used for on / off switching in the other of the two switches. The PWM signal is composed of, for example, a high level voltage indicating that the other switch is on and a low level voltage indicating that the other switch is off. The duty is a period in which the PWM signal is a high level voltage in one cycle. Is the ratio.

  When the duty of the output PWM signal is 100%, the output circuit outputs a PWM signal that repeatedly switches on / off in the other switch. Regarding the switching performed by the output of the PWM signal, the sum of the ON period in the other switch and the OFF period adjacent to the ON period is longer than the cycle of the output PWM signal.

  Accordingly, since the on / off state of the other switch is always switched during a certain period, the other switch is not turned on for a long period of time. Further, since the two switches are complementarily turned on / off, one of the switches is not turned off for a long time. For this reason, one and the other switches are turned on and off, and a period for charging the capacitor for turning on the other switch is always provided during a certain period. Thus, since a charge pump circuit for charging the capacitor is unnecessary, the apparatus is small and inexpensive, and the configuration is simple.

  Further, when the duty of the PWM signal output from the output circuit is 100%, the sum of the ON period in the other switch and the OFF period adjacent to the ON period is longer than the period of the output PWM signal. For each of the two switches, the number of on / off switching operations repeated in a certain period is small. For this reason, each of the two switches has a low loss caused by ON / OFF switching repeatedly during a certain period.

  In the step-down device according to the present invention, the output circuit generates a first PWM signal used for on / off switching in the other switch, and a duty of the first PWM signal generated by the generation unit is 100%. The first PWM signal is repeatedly turned on / off in the other switch, and the changing unit changes the sum of the on period and the off period to a second PWM signal longer than the period of the first PWM signal. The output circuit outputs the first PWM signal when the duty of the first PWM signal generated by the generation unit is less than 100%, and the duty of the first PWM signal generated by the generation unit is 100 The second PWM signal is output when the value is%.

  In the present invention, the output circuit includes a generation unit and a change unit. The generation unit generates a first PWM signal used for on / off switching in the other switch. When the duty of the first PWM signal generated by the generation unit is 100%, the changing unit repeatedly switches on / off the first PWM signal in the other switch, the on period in the other switch, and the on period Is changed to a second PWM signal that is longer than the period of the first PWM signal.

  The output circuit outputs the first PWM signal when the duty of the first PWM signal generated by the generation unit is less than 100%, and outputs the second PWM signal when the duty of the first PWM signal generated by the generation unit is 100%. Output. Thereby, when the duty of the output first PWM signal is 100%, the output circuit repeats on / off switching in the other switch, the on period in the other switch, and the off period adjacent to the on period. The second PWM signal whose total is longer than the period of the first PWM signal is output.

  The step-down device according to the present invention is characterized in that the sum of the on period and the off period is constant.

  In the present invention, for the other switch that is turned on / off when the duty of the PWM signal output from the output circuit is 100%, the sum of the on period and the off period adjacent to the on period is constant. It is. Furthermore, since each of the two switches is complementarily turned on / off, the sum of the off period and the on period adjacent to the off period is constant for one of the switches. Therefore, a period is periodically provided in which one and the other switches are turned on and off, the capacitor for turning on the other switch is stably charged, and the other switch is connected between the other ends of the two switches. The applied voltage is stepped down more appropriately.

  The boosting device according to the present invention repeats complementary ON / OFF of two switches each having one end connected to one end of the coil, so that the other end of the coil and one of the two switches In a booster that boosts a voltage applied to the other end of a switch and outputs the boosted voltage from the other end of each of the two switches, PWM used for on / off switching of the one switch An output circuit for outputting a signal, and when the duty of the output PWM signal is zero%, the output circuit repeatedly performs on / off switching in the one switch, The PWM signal is configured such that the sum of the off period adjacent to the on period is longer than the period of the output PWM signal. That.

  In the present invention, one end of each of the two switches is connected to one end of the coil. The two switches are repeatedly turned on / off in a complementary manner, and the voltage applied between the other end of the coil and the other end of one of the two switches is boosted by, for example, a battery. The boosted voltage is output from the other end of each of the two switches, and for example, a load connected between the other ends of each of the two switches is fed.

  The output circuit outputs a PWM signal used for switching on / off in one of the two switches. The PWM signal is composed of, for example, a high level voltage indicating that one switch is on and a low level voltage indicating that one switch is off, and the duty is a period in which the PWM signal is a high level voltage in one cycle. Is the ratio.

  When the duty of the output PWM signal is zero%, the output circuit outputs a PWM signal that repeatedly switches on / off in one of the switches. Regarding the switching performed by the output of the PWM signal, the sum of the ON period in one switch and the OFF period adjacent to the ON period is longer than the cycle of the output PWM signal.

  Accordingly, on / off in one switch is always switched during a certain period, and the two switches are complementarily turned on / off, so that the other switch is not turned on for a long time. For this reason, one and the other switches are turned on and off, and a period for charging the capacitor for turning on the other switch is always provided during a certain period. Accordingly, since a charge pump circuit for charging the capacitor is unnecessary, the apparatus is small and inexpensive, and the configuration is simple.

  When the duty of the PWM signal output from the output circuit is 0%, the sum of the ON period in one switch and the OFF period adjacent to the ON period is longer than the period of the output PWM signal. For each of the two switches, the number of on / off switching repeated in a certain period is small. For this reason, each of the two switches has a low loss caused by ON / OFF switching repeatedly during a certain period.

  In the booster according to the present invention, the output circuit generates a first PWM signal used for on / off switching of the one switch, and a duty of the first PWM signal generated by the generation unit is 0%. The first PWM signal is repeatedly turned on / off in the one switch, and the changing unit changes the sum of the on period and the off period to a second PWM signal that is longer than the cycle of the first PWM signal. The output circuit outputs the first PWM signal when the duty of the first PWM signal generated by the generation unit exceeds zero%, and the duty of the first PWM signal generated by the generation unit is The second PWM signal is configured to be output when it is zero%.

  In the present invention, the output circuit includes a generation unit and a change unit. The generation unit generates a first PWM signal used for on / off switching in the other switch. When the duty of the first PWM signal generated by the generation unit is zero%, the changing unit repeats the on / off switching of the first PWM signal in one switch, the on period in one switch, and the on period in this on period. The sum of the adjacent off periods is changed to a second PWM signal that is longer than the period of the first PWM signal.

  The output circuit outputs the first PWM signal when the duty of the first PWM signal generated by the generation unit exceeds zero%, and outputs the second PWM signal when the duty of the first PWM signal generated by the generation unit is zero%. Is output. As a result, when the duty of the output first PWM signal is zero%, the output circuit repeatedly switches on / off in one switch, and the on period in one switch and the off period adjacent to the on period And outputs a second PWM signal that is longer than the period of the first PWM signal.

  The booster according to the present invention is characterized in that the sum of the on period and the off period is constant.

  In the present invention, the sum of the on period and the off period adjacent to the on period is constant for one switch that is turned on / off when the duty of the PWM signal output from the output circuit is zero%. It is. Furthermore, since each of the two switches is complementarily turned on / off, the sum of the off period and the on period adjacent to the off period is constant for the other switch. Therefore, a period is periodically provided in which one and the other switches are turned on and off, the capacitor for turning on the other switch is stably charged, and the other switch is connected between the other ends of the two switches. The applied voltage is boosted more appropriately.

  The transformer device according to the present invention includes a first switch and a second switch each having one end connected to one end of the coil, a third switch having one end connected to the other end of the coil, the coil and the second switch. A fourth switch connected between the other ends of the switches, and complementary ON / OFF of the first and second switches and complementary ON / OFF of the third and fourth switches. By repeating, the voltage applied between the other ends of the first and second switches is transformed, and the transformed voltage is transformed between the other end of the third switch and one end of the fourth switch on the second switch side. Output circuit for outputting a first PWM signal used for on / off switching in the first switch and a second PWM signal used for on / off switching in the fourth switch When the duty of the first PWM signal to be output is 100%, the output circuit repeatedly performs on / off switching in the first switch, and the on-period in the first switch and the off-state adjacent to the on-period When a PWM signal having a total period longer than the period of the first PWM signal is output and the duty of the second PWM signal to be output is zero%, the fourth switch is repeatedly turned on / off, and the second switch A total of an ON period in the four switches and an OFF period adjacent to the ON period is configured to output a PWM signal longer than the cycle of the second PWM signal.

  In the present invention, one end of each of the first and second switches is connected to one end of the coil, a third switch is connected to the other end of the coil, and between the other ends of the coil and the second switch. The 4th switch is connected to. Complementary ON / OFF of the first and second switches and complementary ON / OFF of the third and fourth switches are repeated, for example, applied between the other ends of the first and second switches by a battery, for example. Transform the voltage. The transformed voltage is output between the other end of the third switch and one end on the second switch side of the fourth switch, for example, between the other end of the third switch and one end on the second switch side of the fourth switch. Power is supplied to the load connected to.

  The output circuit outputs a first PWM signal used for on / off switching in the first switch and a second PWM signal used for on / off switching in the fourth switch. The first PWM signal (or the second PWM signal) is, for example, a high level voltage indicating that the first switch (or the fourth switch) is on, and a low level voltage indicating that the first switch (or the fourth switch) is off. The duty is a ratio of a period in which the first PWM signal (or the second PWM signal) is a high level voltage in one cycle.

  When the duty of the first PWM signal to be output is 100%, the output circuit outputs a PWM signal that repeatedly switches on / off in the first switch. Regarding the switching performed by outputting the PWM signal, the sum of the ON period in the first switch and the OFF period adjacent to the ON period is longer than the cycle of the first PWM signal to be output. Further, the output circuit outputs a PWM signal that repeatedly switches on / off in the fourth switch when the duty of the second PWM signal to be output is zero%. Regarding the switching performed by the output of the PWM signal, the sum of the ON period in the fourth switch and the OFF period adjacent to the ON period is longer than the cycle of the output second PWM signal.

  Therefore, ON / OFF in each of the first and fourth switches is always switched during a certain period. Since the first and second switches are complementarily turned on / off, and the third and fourth switches are complementarily turned on / off, the second and third switches are always turned on / off during a certain period. Switched. Therefore, the first and second switches are not turned on and off for a long time, and the third and fourth switches are not turned on and off for a long time. Therefore, since a period for charging the capacitor for turning on each of the first and third switches is always provided during a certain period, a charge pump circuit for charging the capacitor is unnecessary. Therefore, the apparatus is small and inexpensive, and the configuration is simple.

  When the duty of the first PWM signal output from the output circuit is 100%, the sum of the ON period in the first switch and the OFF period adjacent to the ON period is longer than the period of the first PWM signal. Similarly, when the duty of the second PWM signal output from the output circuit is zero%, the sum of the ON period in the fourth switch and the OFF period adjacent to the ON period is also longer than the period of the second PWM signal. Therefore, the first, second, third, and fourth switches have low loss caused by ON / OFF switching that is repeated for a certain period.

  In the transformer device according to the present invention, the output circuit includes a first generation unit that generates a third PWM signal used for on / off switching in the first switch, and a third PWM signal generated by the first generation unit. When the duty is 100%, the third PWM signal is repeatedly switched on / off in the first switch, and the sum of the on period and the off period in the first switch is longer than the cycle of the third PWM signal. First changing means for changing to a fourth PWM signal, and the output circuit outputs the third PWM signal when the duty of the third PWM signal generated by the first generating means is less than 100%, The fourth PWM signal is output when the duty of the third PWM signal generated by the first generation means is 100%. And features.

  In the present invention, the output circuit includes first generation means and first change means. The first generation means generates a third PWM signal used for on / off switching in the first switch. When the duty of the third PWM signal generated by the first generation unit is 100%, the first changing unit repeatedly performs on / off switching of the third PWM signal in the first switch, and the ON period in the first switch The sum of the on period and the off period adjacent to the on period is changed to a fourth PWM signal that is longer than the period of the third PWM signal.

  The output circuit outputs the third PWM signal when the duty of the third PWM signal generated by the first generator is less than 100%, and when the duty of the third PWM signal generated by the first generator is 100% The fourth PWM signal is output. Thereby, when the duty of the output third PWM signal is 100%, the output circuit repeatedly switches on / off in the first switch, and the on-period in the first switch and the off-period adjacent to the on-period The fourth PWM signal whose total is longer than the period of the third PWM is output.

  The transformer device according to the present invention is characterized in that the sum of the ON period and the OFF period in the first switch is constant.

  In the present invention, for the first switch that is turned on / off when the duty of the first PWM signal output from the output circuit is 100%, the sum of the on period and the off period adjacent to the on period is It is constant. Furthermore, since the first and second switches are complementarily turned on / off, the sum of the off period and the on period adjacent to the off period is also constant for the second switch. For this reason, a period in which each of the first and second switches is turned off and on is provided periodically, and a capacitor for turning on the first switch is stably charged, and each of the first and second switches is charged. The voltage applied between the other ends is more appropriately transformed.

  In the transformer device according to the present invention, the output circuit includes a second generation unit that generates a fifth PWM signal used for on / off switching in the fourth switch, and a fifth PWM signal generated by the second generation unit. When the duty is zero%, the fifth PWM signal is repeatedly turned on / off in the fourth switch, and the sum of the on period and the off period in the fourth switch is longer than the cycle of the fifth PWM signal. Second output means for changing to a sixth PWM signal, and the output circuit outputs the fifth PWM signal when the duty of the fifth PWM signal generated by the second generation means exceeds zero%, The sixth PWM signal is output when the duty of the fifth PWM signal generated by the second generation means is zero%. To.

  In the present invention, the output circuit includes second generation means and second change means. The second generation means generates a fifth PWM signal used for on / off switching in the fourth switch. When the duty of the fifth PWM signal generated by the second generation unit is zero%, the second changing unit repeatedly switches the fifth PWM signal on / off in the fourth switch, and sets the ON period in the fourth switch. The sum of the on period and the off period adjacent to the on period is changed to a sixth PWM signal that is longer than the cycle of the fifth PWM signal.

  The output circuit outputs the fifth PWM signal when the duty of the fifth PWM signal generated by the second generation means exceeds zero%, and the duty of the fifth PWM signal generated by the second generation means is zero% To output the sixth PWM signal. Thus, when the duty of the output fifth PWM signal is zero%, the output circuit repeatedly performs on / off switching in the fourth switch, and the on period in the fourth switch and the off period adjacent to the on period And outputs a sixth PWM signal that is longer than the cycle of the fifth PWM signal.

  The transformer device according to the present invention is characterized in that the sum of the ON period and the OFF period in the fourth switch is constant.

  In the present invention, for the fourth switch that is turned on / off when the duty of the second PWM signal output from the output circuit is zero%, the sum of the on period and the off period adjacent to the on period is It is constant. Furthermore, since the third and fourth switches are complementarily turned on / off, the sum of the off period and the on period adjacent to the off period is also constant for the third switch. For this reason, a period in which each of the third and fourth switches is periodically turned off and on is provided, and a capacitor for turning on the third switch is stably charged, and each of the first and second switches is The voltage applied between the other ends is more appropriately transformed.

  According to the voltage transforming apparatus according to the present invention, the voltage can be appropriately transformed, and the loss caused by the on / off switching performed during a predetermined period in each of the first, second, third, and fourth switches is small. Is small, inexpensive, and simple in construction.

  According to the step-down device according to the present invention, the step-down operation can be performed appropriately, loss caused by ON / OFF switching performed during a certain period in each of the two switches is small, and the device is small and inexpensive. The configuration is simple.

  According to the boosting device of the present invention, boosting can be performed appropriately, loss caused by on / off switching performed during a certain period in each of the two switches is small, and the device is small and inexpensive. The configuration is simple.

3 is a block diagram showing a configuration of a transformer device in Embodiment 1. FIG. It is a timing chart for explaining voltage boosting operation of a transformer. 6 is a timing chart showing an on / off operation of an FET when a boosting operation is performed. It is a timing chart for explaining voltage reduction operation of a transformer. 6 is a timing chart showing the on / off operation of the FET when the step-down operation is performed. 6 is a block diagram showing a configuration of a step-down device according to Embodiment 2. FIG. FIG. 10 is a block diagram showing a configuration of a booster device in a third embodiment.

Hereinafter, the present invention will be described in detail with reference to the drawings illustrating embodiments thereof.
(Embodiment 1)
FIG. 1 is a block diagram showing the configuration of the transformer device in the first embodiment. The transformer device 1 is connected to both ends of each of the battery 3 and the load 4. The voltage applied by the battery 3 is boosted and stepped down to transform the voltage, and the transformed voltage is applied to the load 4. Apply.

  The transformer 1 includes N-channel FETs 11, 12, 13, 14, a differential amplifier 15, an output circuit 16, drive circuits 17, 19, 21, 22, inverters 18, 20, capacitors C1, C2,. , C5, diodes D1, D2, a coil L1, and a resistor R1. The output circuit 16 includes a generation unit 51, a change unit 52, an AND circuit 53, and an OR circuit 54. The drive circuit 17 has an inverter 61 and switches S1 and S2, and the drive circuit 21 has a switch S3 and a resistor R2. The drive circuit 19 has a switch S4 and a resistor R3, and the drive circuit 22 has an inverter 71 and switches S5 and S6.

  The drain of the FET 11 is connected to the positive terminal of the battery 3, and the source of the FET 12 is connected to the negative terminal of the battery 3. The source of the FET 11 and the drain of the FET 12 are connected to one end of the coil L1. The other end of the coil L1 is connected to the source of the FET 13 and the drain of the FET 14. The source of the FET 14 is connected to the source of the FET 12. Thus, the FET 14 is connected between the other end of the coil L1 and the source of the FET 12. The sources of the FETs 12 and 14 are grounded.

  The drain of the FET 13 is connected to one end of each of the capacitor C1 and the resistor R1, and the other end of the resistor R1 is connected to one end of the load 4. The source of the FET 14 is connected to the other end of the capacitor C1 and the load 4. A positive terminal and a negative terminal of the differential amplifier 15 are connected to one end and the other end of the resistor R 1, respectively, and an output terminal of the differential amplifier 15 is connected to the output circuit 16. The output circuit 16 is further connected to the drains of the FETs 11 and 13, the drive circuits 17 and 19, and the input terminals of the inverters 18 and 20.

  In the output circuit 16, the output terminal of the differential amplifier 15 and the drains of the FETs 11 and 13 are connected to the generation unit 51. Each of the AND circuit 53 and the OR circuit 54 has two input terminals and one output terminal, and the generation unit 51 is further connected to one input terminal of each of the AND circuit 53 and the OR circuit 54. Yes. The other input terminal of each of the AND circuit 53 and the OR circuit 54 is connected to the changing unit 52. Similar to the generation unit 51, the change unit 52 is connected to the drains of the FETs 11 and 13. The generation unit 51 and the change unit 52 are grounded. The output terminal of the AND circuit 53 is connected to the drive circuit 17 and the input terminal of the inverter 18, and the output terminal of the OR circuit 54 is connected to the drive circuit 19 and the input terminal of the inverter 20.

  The drive circuit 17 is further connected to the gate of the FET 11, the cathode of the diode D1, and one end of each of the capacitors C2 and C3. The anode of the diode D1 is connected to the drain of the FET 11, and the other ends of the capacitors C2 and C3 are connected to the source of the FET 11. The drive circuit 17 is grounded.

  In the drive circuit 17, the input terminal of the inverter 61 is connected to the output terminal of the AND circuit 53. One end of the switch S1 is connected to the cathode of the diode D1 and one end of the capacitor C2. The other end of the switch S1 is connected to the gate of the FET 11 and one end of each of the capacitor C3 and the switch S2. The other end of the switch S2 is grounded.

The output terminal of the inverter 18 is connected to the drive circuit 21. The drive circuit 21 is further connected to the gate of the FET 12 and is also grounded. The drive circuit 21 is applied with a constant voltage Vcc.
In the drive circuit 21, the voltage Vcc is applied to one end of the switch S3, and the other end of the switch S3 is connected to the gate of the FET 12 and one end of the resistor R2. The other end of the resistor R2 is grounded.

The drive circuit 19 is further connected to the gate of the FET 14 and is also grounded. A constant voltage Vcc is also applied to the drive circuit 19.
In the drive circuit 19, the voltage Vcc is applied to one end of the switch S4, and the other end of the switch S4 is connected to the gate of the FET 14 and one end of the resistor R3. The other end of the resistor R3 is grounded.

  The output terminal of the inverter 20 is connected to the drive circuit 22. The drive circuit 22 is further connected to the gate of the FET 13, the cathode of the diode D2, and one end of each of the capacitors C4 and C5. The anode of the diode D2 is connected to the drain of the FET 11, and the other ends of the capacitors C4 and C5 are connected to the source of the FET 13.

  In the drive circuit 22, the input terminal of the inverter 71 is connected to the output terminal of the inverter 20. One end of the switch S5 is connected to the cathode of the diode D2 and one end of the capacitor C4. The other end of the switch S5 is connected to the gate of the FET 13 and one end of each of the capacitor C5 and the switch S6. The other end of the switch S6 is grounded.

The FETs 11, 12, 13, and 14 function as switches. Each of the FETs 11, 12, 13, and 14 is turned on because a current flows from the drain to the source when a voltage higher than a certain voltage is applied to the gate with reference to the source potential, and is applied to the gate with reference to the source potential. When the voltage is less than a certain voltage, no current flows from the drain to the source, so that the voltage is turned off. In the transformer 1, the FETs 11, 12, 13, and 14 are turned on / off by adjusting the voltage applied to the gate.
The FETs 11, 12, 13, and 14 function as first, second, third, and fourth switches, respectively.

  In the transformer 1, the voltage applied by the battery 3 between the drain of the FET 11 and the source of the FET 12 by repeating complementary ON / OFF of the FETs 11 and 12 and complementary ON / OFF of the FETs 13 and 14. , And the transformed voltage is output from between the drain of the FET 13 and the source of the FET 14. Thereby, the transformed voltage is applied to the load 4 through the resistor R1, and the load 4 is fed.

  Complementary on / off of the FETs 11 and 12 is performed by turning on the FET 11 and turning off the FET 12, turning on the FET 11 and turning on the FET 12. Similarly, the FETs 13 and 14 are complementarily turned on / off by turning on the FET 14 and turning off the FET 13, turning off the FET 14 and turning on the FET 13.

  The voltage applied by the battery 3 between the drain of the FET 11 and the source of the FET 12 by repeating the complementary ON / OFF of the FETs 11 and 12 in a state where the complementary ON / OFF of the FETs 13 and 14 is repeated. Step down. When the FETs 11 and 12 are on and off, a current flows from the positive terminal of the battery 3 to the coil L1 via the FET 11, and energy is accumulated in the coil L1. Here, when the FETs 13 and 14 are off and on, the current flows from the coil L <b> 1 through the FET 14 and returns to the negative terminal of the battery 3. When the FETs 13 and 14 are on and off, the current flows from the coil L1 through the FET 13, the resistor R1, and the load 4, and returns to the negative terminal of the battery 3. At this time, a voltage is applied between the drain of the FET 13 and the source of the FET 14.

  When the FETs 11 and 12 are switched on and off from the state where the FETs 11 and 12 are switched off and on, the current flowing to the coil L1 is cut off, and the coil L1 is to maintain the amount of current flowing to itself. , Energy is released, and a current is generated from the coil L1. Here, when the FETs 13 and 14 are off and on, current flows in the order of the FETs 14 and 12 from the other end of the coil L1 and returns to one end of the coil L1. Further, when the FETs 13 and 14 are on and off, current flows from the other end of the coil L1 to the FET 13, the resistor R1, the load 4, and the FET 12 and returns to one end of the coil L1. At this time, a voltage is applied between the drain of the FET 13 and the source of the FET 14, and the voltage applied between the drain of the FET 13 and the source of the FET 14 is stepped down as the energy of the coil L1 is released.

  When the complementary ON / OFF of the FETs 11 and 12 is repeated while the complementary ON / OFF of the FETs 13 and 14 is repeated, the voltage applied between the drain of the FET 13 and the source of the FET 14 is a capacitor. After being smoothed by C1, it is applied to the load 4 via the resistor R1. At this time, the average voltage applied between the drain of the FET 13 and the source of the FET 14, that is, the voltage smoothed by the capacitor C 1 is a voltage obtained by stepping down the voltage applied by the battery 3. The step-down width is increased or decreased according to the period during which the FETs 11 and 12 are off and on.

  The voltage applied by the battery 3 between the drain of the FET 11 and the source of the FET 12 by repeating the complementary ON / OFF of the FETs 13 and 14 in a state where the complementary ON / OFF of the FETs 11 and 12 is repeated. Boost. When the FETs 13 and 14 are off and on, when the FETs 11 and 12 are on and off, current flows from the positive terminal of the battery 3 in the order of the FET 11, the coil L1, and the FET 14, and returns to the negative terminal of the battery 3. At this time, a large amount of current flows through the coil L1, and energy is accumulated in the coil L1.

  When the FETs 13 and 14 are switched from the off and on states to the on and off states, when the FETs 11 and 12 are on and off, current is supplied from the positive terminal of the battery 3 to the FET 11, the coil L 1, and the FET 13. The resistance R1 and the load 4 flow in this order and return to the negative terminal of the battery 3. At this time, since the current flows through the resistor R1 and the load 4, the amount of current flowing through the coil L1 decreases. Therefore, the coil L1 boosts the voltage at the other end of the coil L1 on the FET 13 side with reference to the voltage applied to the one end of the coil L1 on the FET 11 side in order to maintain the amount of current flowing therethrough. Thereby, the voltage applied between the drain of the FET 13 and the source of the FET 14 is higher than the voltage applied by the battery 3 between the drain of the FET 11 and the source of the FET 12.

When the complementary ON / OFF of the FETs 13 and 14 is repeated while the complementary ON / OFF of the FETs 11 and 12 is repeated, the voltage applied between the drain of the FET 13 and the source of the FET 14 is a capacitor. After being smoothed by C1, it is applied to the load 4 via the resistor R1. At this time, the average voltage applied between the drain of the FET 13 and the source of the FET 14, that is, the voltage smoothed by the capacitor C <b> 1 is a voltage obtained by boosting the voltage applied by the battery 3. The step-up width becomes larger or smaller depending on the period during which the FETs 13 and 14 are off and on.
When the FETs 11 and 12 are turned off and on, current does not flow from the positive terminal of the battery 3 to the coil L1 via the FET 11 regardless of the on / off state of the FETs 13 and 14, respectively.

  The differential amplifier 15 amplifies the voltage across the resistor R1, that is, the voltage proportional to the amount of output current flowing through the load 4, and outputs the amplified voltage from the output terminal to the output circuit 16. The output circuit 16 outputs two PWM signals based on the voltage between the drain of the FET 11 and the source of the FET 12, the voltage between the drain of the FET 13 and the source of the FET 14, and the voltage input from the differential amplifier 15. Specifically, the output circuit 16 outputs one PWM signal used for on / off switching of the FETs 11 and 12 to the drive circuit 17 and the input terminal of the inverter 18, and turns on / off the FETs 13 and 14. The other PWM signal used for switching off is output to the input terminal of the inverter 20 and the drive circuit 19.

  In the output circuit 16, the generation unit 51 includes a voltage applied between the drain of the FET 11 and the source of the FET 12, a voltage applied between the drain of the FET 13 and the source of the FET 14, and a voltage input from the differential amplifier 15. PWM signal 1 and PWM signal 2 are generated based on the above.

The PWM signal 1 is composed of a high level voltage and a low level voltage lower than the high level voltage, and is used for on / off switching in the FET 11. The duty of the PWM signal 1, that is, the ratio of the period in which the PWM signal 1 is at a high level voltage in one cycle is 0% or more and 100% or less.
The PWM signal 2 is also composed of high-level and low-level voltages, and is used for on / off switching in the FET 14. The duty of the PWM signal 2, that is, the ratio of the period in which the PWM signal 2 is at a high level voltage in one cycle is 0% or more and 100% or less.

The generation unit 51 outputs the generated PWM signal 1 to one input terminal of the AND circuit 53, and outputs the generated PWM signal 2 to one input terminal of the OR circuit 54. The generation unit 51 corresponds to first and second generation means.
The changing unit 52 changes the change signal 1 for changing the PWM signal 1 and the PWM signal 2 based on the voltage between the drain of the FET 11 and the source of the FET 12 and the voltage between the drain of the FET 13 and the source of the FET 14. A change signal 2 is generated for this purpose.

Like the PWM signal 1 and the PWM signal 2, the change signal 1 and the change signal 2 are configured by high-level and low-level voltages, respectively.
The change unit 52 outputs the change signal 1 to the other input terminal of the AND circuit 53 and inputs the change signal 2 to the other input terminal of the OR circuit 54.

The AND circuit 53 outputs a high level voltage when both the PWM signal 1 and the change signal 1 input to the two input terminals indicate a high level voltage, and at least the PWM signal 1 and the change signal 1 are output. When one of them indicates a low level voltage, a low level voltage is output.
The AND circuit 53 outputs the PWM signal 1 and the PWM signal corresponding to the change signal 1 input to the two input terminals to the input terminal of the inverter 18 and the input terminal of the inverter 61 of the drive circuit 17. .

The OR circuit 54 outputs a high level voltage when at least one of the PWM signal 2 and the change signal 2 input to the two input terminals indicates a high level voltage, and the PWM signal 2 and the change signal 2 are output. When both indicate a low level voltage, a low level voltage is output.
The OR circuit 54 outputs a PWM signal corresponding to the PWM signal 2 and the change signal 2 input to the two input terminals to the input terminal of the inverter 20 and the drive circuit 19.

  Each of the inverters 18, 20, 61 and 71 outputs a low level voltage from the output terminal when the PWM signal input to the input terminal is a high level voltage, and the PWM signal input to the input terminal is low. When it is a level voltage, a high level voltage is output from the output terminal. Each of the inverters 18, 20, 61, 71 inverts the high level and low level voltages of the PWM signal input to the input terminal, and outputs a PWM signal obtained by inverting the high level and low level voltages from the output terminal. .

  The inverters 18 and 61 invert the high-level and low-level voltages of the PWM signal output from the output terminal of the AND circuit 53. The inverter 20 inverts the high level and low level voltages of the PWM signal output from the output terminal of the OR circuit 54 and outputs the PWM signal obtained by inverting the high level and low level voltages to the input terminal of the inverter 71. To do. The inverter 71 inverts the high level and low level voltages of the PWM signal output from the output terminal of the inverter 20.

  The switch S1 is turned on and off according to the high level and low level voltages of the PWM signal output from the output terminal by the AND circuit 53, and the switch S2 is the high level of the PWM signal output from the output terminal by the inverter 61. It is turned on and off according to the low level voltage. The switch S3 is turned on and off in accordance with the high level and low level voltages of the PWM signal output from the output terminal by the inverter 18.

  The switch S4 is turned on and off according to the high-level and low-level voltages of the PWM signal output from the output terminal by the OR circuit 54. The switch S5 is turned on and off according to the high level and low level voltages of the PWM signal output from the output terminal by the inverter 20, and the switch S6 is switched to the high level of the PWM signal output from the output terminal of the inverter 71. It is turned on and off according to the low level voltage.

  When the PWM signal output from the output terminal of the AND circuit 53 is a low level voltage, the switches S1, S2, and S3 are turned off, on, and on, respectively. At this time, since the switch S3 is on, a voltage Vcc higher than a certain voltage is applied to the gate of the FET 12, and the FET 12 is turned on.

Further, current flows in the order of the diode D1, the capacitor C2, and the FET 12 from the positive terminal of the battery 3 and returns to the negative terminal of the battery 3. As a result, the capacitor C2 is charged.
Furthermore, current flows in the order of the switch S2 and the FET 12 from one end of the capacitor C3 on the FET 11 side, returns to the other end of the capacitor C3, and the capacitor C3 is discharged. Thereby, the voltage applied to the gate of the FET 11 becomes less than a certain voltage, and the FET 11 is turned off.
As described above, when the AND circuit 53 outputs a low level voltage from the output terminal, the FETs 11 and 12 are turned off and on.

  When the PWM signal output from the output terminal of the AND circuit 53 is a high level voltage, the switches S1, S2, and S3 are turned on, off, and off, respectively. At this time, the capacitor C2 is discharged, and the current flows from one end of the capacitor C2 on the diode D1 side in the order of the switch S1 and the capacitor C3, and returns to the other end of the capacitor C2. As a result, the capacitor C3 is charged, a voltage higher than a certain voltage is applied between the source and the gate of the FET 11, and the FET 11 is turned on.

Further, since the switch S3 is off, the voltage applied to the gate of the FET 12 becomes zero volts, and the FET 12 is turned off.
As described above, when the AND circuit 53 outputs a high level voltage from the output terminal, the FETs 11 and 12 are turned on and off.

  Therefore, when the PWM signal output from the output terminal of the AND circuit 53 is a low level voltage, the FETs 11 and 12 are turned off and on, and the PWM signal output from the output terminal of the AND circuit 53 is a high level voltage. In this case, the FETs 11 and 12 are turned on and off, respectively. Thus, the FETs 11 and 12 are turned on / off in a complementary manner.

  Note that the capacitance of the capacitor C3 is the input capacitance of the FET 11. The drive circuit 17 functions as a circuit for turning on / off the FET 11 according to the PWM signal output from the output terminal by the AND circuit 53, and the drive circuit 21 according to the PWM signal output from the output terminal by the inverter 18. Functions as a circuit for turning on / off the FET 12.

  When the PWM signal output from the output terminal of the OR circuit 54 is a high level voltage, the switches S4, S5, and S6 are turned on, off, and on, respectively. At this time, since the switch S4 is on, a voltage Vcc higher than a certain voltage is applied to the gate of the FET 14, and the FET 14 is turned on.

Further, current flows in the order of the diode D2, the capacitor C4, and the FET 14 from the positive terminal of the battery 3 and returns to the negative terminal of the battery 3. As a result, the capacitor C4 is charged.
Furthermore, current flows in the order of the switch S6 and the FET 14 from one end of the capacitor C5 on the FET 13 side, returns to the other end of the capacitor C5, and the capacitor C5 is discharged. Thereby, the voltage applied to the gate of the FET 13 becomes less than a certain voltage, and the FET 13 is turned off.
As described above, when the OR circuit 54 outputs a high level voltage from the output terminal, the FETs 13 and 14 are turned off and on.

  When the PWM signal output from the output terminal of the OR circuit 54 is a low level voltage, the switches S4, S5 and S6 are turned off, on and off, respectively. At this time, the capacitor C4 is discharged, and current flows from one end of the capacitor C4 on the diode D2 side in the order of the switch S5 and the capacitor C5, and returns to the other end of the capacitor C4. As a result, the capacitor C5 is charged, a voltage higher than a certain voltage is applied between the source and gate of the FET 13, and the FET 13 is turned on.

Further, since the switch S4 is off, the voltage applied to the gate of the FET 14 is zero volts, and the FET 14 is turned off.
As described above, when the OR circuit 54 outputs a high level voltage from the output terminal, the FETs 13 and 14 are turned on and off.

  Therefore, when the PWM signal output from the output terminal of the OR circuit 54 is a high level voltage, the FETs 13 and 14 are turned off and on, respectively, and the PWM signal output from the output terminal of the OR circuit 54 is a low level voltage. In this case, the FETs 13 and 14 are turned on and off, respectively. Thus, the FETs 13 and 14 are turned on / off in a complementary manner.

  Note that the capacitance of the capacitor C5 is the input capacitance of the FET 13. The drive circuit 19 functions as a circuit for turning on / off the FET 14 according to the PWM signal output from the output terminal by the OR circuit 54, and the drive circuit 22 corresponds to the PWM signal output from the output terminal by the inverter 20. Functions as a circuit for turning on / off the FET 13.

  FIG. 2 is a timing chart for explaining the step-up operation of the transformer 1. In FIG. 2, the PWM signal 1 and the PWM signal 2 output from the generation unit 51, the change signal 1 and the change signal 2 output from the change unit 52, and the output signals of the AND circuit 53 and the OR circuit 54 are shown. Yes.

  When the voltage step-up operation is performed in the transformer 1, the voltage between the drain of the FET 13 and the source of the FET 14 is higher than the voltage between the drain of the FET 11 and the source of the FET 12, that is, the output voltage of the battery 3. When the voltage between the drain of the FET 13 and the source of the FET 14 is higher than the voltage between the drain of the FET 11 and the source of the FET 12, the generator 51 outputs the PWM signal 1 having a duty of 100%, and the differential amplifier 15 outputs The PWM signal 2 whose duty becomes small according to the voltage level is output. At this time, the duty of the PWM signal 2 output from the generation unit 51 exceeds zero%.

  When the voltage step-down operation is performed in the transformer 1, the voltage between the drain of the FET 13 and the source of the FET 14 is lower than the voltage between the drain of the FET 11 and the source of the FET 12, that is, the output voltage of the battery 3. When the voltage between the drain of the FET 13 and the source of the FET 14 is lower than the voltage between the drain of the FET 11 and the source of the FET 12, the generation unit 51 outputs the PWM signal 2 having a duty of zero%, and the differential amplifier 15 outputs The PWM signal 1 whose duty becomes small according to the voltage level is output. At this time, the duty of the PWM signal 1 output from the generation unit 51 is less than 100%.

FIG. 2 shows a PWM signal 1 having a duty of 100% and a PWM signal 2 having a duty that is increased or decreased according to the level of the voltage output from the differential amplifier 15. In the example illustrated in FIG. 2, the generation unit 51 gradually decreases the duty of the PWM signal 2 in order to reduce the voltage output from the differential amplifier 15, i.e., to reduce the output current flowing to the load 4 via the resistor R <b> 1. doing.
In FIG. 2, the broken line represents the period of the PWM signal 1, and the interval between adjacent broken lines corresponds to one period of the PWM signal 1.

  In the changing unit 52, when the voltage between the gate of the FET 13 and the source of the FET 14 is higher than the voltage between the gate of the FET 13 and the source of the FET 14, the duty of the PWM signal 1 generated by the generating unit 51 is 100%. It is determined that the duty of the PWM signal 2 generated by the generation unit 51 exceeds zero%. Further, when the voltage between the gate of the FET 13 and the source of the FET 14 is lower than the voltage between the gate of the FET 13 and the source of the FET 14, the duty of the PWM signal 1 generated by the generation unit 51 is less than 100%, and the generation unit It is determined that the duty of the PWM signal 2 generated by 51 is zero%.

  When the changing unit 52 determines that the duty of the PWM signal 1 generated by the generating unit 51 is 100%, in other words, the duty of the PWM signal 2 generated by the generating unit 51 is determined to exceed zero%. In this case, a pulse signal as shown in FIG. The pulse signal output as the change signal 1 is composed of high level and low level voltages. Here, the sum of the high level period in which the change signal 1 indicates a high level voltage and the low level period in which the change signal 1 indicates a low level voltage and is adjacent to the above-described high level period is: As shown in FIG. 2, it is longer than one cycle of the PWM signal 1, specifically, five times as long as one cycle of the PWM signal 1. Furthermore, the low level period is shorter than one period of the PWM signal 1 and is, for example, one tenth of one period in the PWM signal 1. The sum of one high level period and the low level period adjacent to the high level period is constant, and the low level period is also constant.

  In the AND circuit 53 in which the PWM signal 1 and the change signal 1 shown in FIG. 2 are input to the two input terminals, the duty of the input PWM signal 1 is 100%. The PWM signal is output from the output terminal.

  As described above, when the PWM signal output from the output terminal of the AND circuit 53 is a high level voltage, the FETs 11 and 12 are turned on and off, respectively, and the PWM signal output from the output terminal of the AND circuit 53 is low level. When the voltage is applied, the FETs 11 and 12 are turned off and on, respectively. Therefore, in the PWM signal output from the AND circuit 53, the high level period corresponds to an on period in which the FET 11 is on, and the low level period corresponds to an off period in which the FET 11 is off. Since the FETs 11 and 12 are complementarily turned on / off as described above, in the PWM signal output from the AND circuit 53, the high level period corresponds to the off period of the FET 12, and the low level period corresponds to the on period of the FET 12. Equivalent to.

  Therefore, when the duty of the PWM signal 1 generated by the generation unit 51 is 100%, the change unit 52 outputs the change signal 1 so that the PWM signal 1 is repeatedly turned on / off in the FET 11. Change to signal. In the ON / OFF switching of the FET 11 performed by the PWM signal, the sum of the ON period in the FET 11 and the OFF period adjacent to the ON period is longer than the cycle of the PWM signal 1. Specifically, the PWM signal 1 Is five times the period. The output circuit 16 outputs the PWM signal changed by the changing unit 52 when the duty of the PWM signal 1 generated by the generating unit 51 is 100%. The changing unit 52 functions as a first changing unit.

Further, when the duty of the PWM signal 1 generated by the generation unit 51 is 100%, the change signal 1, that is, the high level period and the low level period of the PWM signal output from the AND circuit 53 are constant. The sum of the on period and the off period is constant. In this case, since the low level period of the PWM signal output from the AND circuit 53 is shorter than one cycle of the PWM signal 1, the off period in the FET 11 is also shorter than one cycle of the PWM signal 1.
Since the FETs 11 and 12 are complementarily turned on / off, the sum of the on period and the off period in the FET 12 is constant, and the on period in the FET 12 is shorter than one period of the PWM signal 1.

When the changing unit 52 determines that the duty of the PWM signal 1 generated by the generating unit 51 is 100%, in other words, when the duty of the PWM signal 2 generated by the generating unit 51 exceeds zero%. If it is determined, a change signal 2 that is constant at a low level voltage is output. As a result, the OR circuit 54 outputs the PWM signal 2 generated by the generation unit 51 as it is from the output terminal of the OR circuit 54.
Therefore, the output circuit 16 outputs the PWM signal 2 generated by the generation unit 51 when the duty of the PWM signal 2 generated by the generation unit 51 exceeds zero%.

  FIG. 3 is a timing chart showing the on / off operation of the FETs 11, 12, 13, and 14 when the boosting operation is performed. As shown in FIG. 3, each of the FETs 13 and 14 is complementarily turned on / off with a duty corresponding to the voltage output from the output terminal of the differential amplifier 15, so that a predetermined amount of current flows through the load 4. Has been adjusted. In addition, since a period during which the FETs 11 and 12 are off and on and the capacitor C2 is charged is always provided during a certain period, a charge pump circuit that charges the capacitor C2 regardless of the on / off state of the FETs 11 and 12 is unnecessary. It is. For this reason, the transformer 1 is small and inexpensive, and the configuration of the transformer 1 is simple.

  Further, when the duty of the PWM signal output from the AND circuit 53 by the output circuit 16 is 100%, the sum of the ON period and the OFF period adjacent to the ON period for each of the FETs 11 and 12 is the generation unit 51. Is longer than the cycle of the generated PWM signal 1, specifically, five times the cycle. For this reason, the number of on / off switchings of the FETs 11 and 12 repeated during a certain period is small, and the loss caused by the on / off switching repeated during the certain period is low for each of the FETs 11 and 12.

  The sum of the on period and the off period adjacent to the on period is the sum of the FETs 11 and 12 that are turned on / off when the duty of the PWM signal output from the AND circuit 53 by the output circuit 16 is 100%. Since it is constant, a period in which the FETs 11 and 12 are turned off and on is provided periodically. Thereby, the capacitor C2 for turning on the FET 11 is stably charged, and the voltage applied between the drain of the FET 11 and the source of the FET 12 is more appropriately transformed.

  FIG. 4 is a timing chart for explaining the step-down operation of the transformer 1. 4, similarly to FIG. 2, the PWM signal 1 and the PWM signal 2 output from the generation unit 51, the change signal 1 and the change signal 2 output from the change unit 52, and the outputs of the AND circuit 53 and the OR circuit 54, respectively. Signal.

When the step-down operation is performed, the generation unit 51, as described above, the PWM signal 1 whose duty is increased or decreased according to the level of the voltage output from the differential amplifier 15, and the PWM whose duty is zero%. Signal 2 is generated. In the example shown in FIG. 4, the generation unit 51 gradually increases the duty of the PWM signal 1 in order to increase the voltage output from the differential amplifier 15, that is, to increase the output current flowing through the load 4 via the resistor R <b> 1. doing.
In FIG. 4, the broken line represents the period of the PWM signal 2, and the interval between the broken lines adjacent to each other corresponds to one period of the PWM signal 2.

  When the changing unit 52 determines that the duty of the PWM signal 2 generated by the generating unit 51 is zero%, in other words, when the duty of the PWM signal 1 generated by the generating unit 51 is less than 100% Then, a pulse signal as shown in FIG. The pulse signal output as the change signal 2 is composed of high level and low level voltages. Here, the sum of the high level period in which the change signal 2 indicates a high level voltage and the low level period in which the change signal 2 indicates a low level voltage and is adjacent to the above-described high level period is: As shown in FIG. 4, it is longer than one cycle of the PWM signal 2, specifically, five times as long as one cycle of the PWM signal 2. Furthermore, the high level period is shorter than one period of the PWM signal 2 and is, for example, one tenth of one period in the PWM signal 2. The sum of one high level period and the low level period adjacent to the high level period is constant, and the high level period is also constant.

  In the OR circuit 54 in which the PWM signal 2 and the change signal 2 shown in FIG. 4 are input to the input terminals, the duty of the input PWM signal 2 is zero%. Output as a signal from the output terminal.

  As described above, when the PWM signal output from the output terminal of the OR circuit 54 is a high level voltage, the FETs 13 and 14 are turned off and on, and the PWM signal output from the output terminal of the OR circuit 54 is a low level voltage. The FETs 13 and 14 are turned on and off. Therefore, in the PWM signal output from the OR circuit 54, the high level period corresponds to an on period in which the FET 14 is on, and the low level period corresponds to an off period in which the FET 14 is off. Since the FETs 13 and 14 are complementarily turned on / off as described above, in the PWM signal output from the OR circuit 54, the high level period corresponds to the off period of the FET 13, and the low level period corresponds to the on period of the FET 13. Equivalent to.

  Therefore, the changing unit 52 outputs the changing signal 2 when the duty of the PWM signal 2 generated by the generating unit 51 is zero%, and thus the PWM signal 2 is repeatedly switched on / off in the FET 14. Change to signal. In the ON / OFF switching of the FET 14 performed by the PWM signal, the sum of the ON period in the FET 14 and the OFF period adjacent to the ON period is longer than the cycle of the PWM signal 2. Specifically, the PWM signal 2 Is five times the period. The output circuit 16 outputs the PWM signal changed by the changing unit 52 when the duty of the PWM signal 2 generated by the generating unit 51 is zero%. The changing unit 52 functions as a second changing unit.

Furthermore, when the duty of the PWM signal 2 generated by the generation unit 51 is 0%, the change signal 2, that is, the high level period and the low level period of the PWM signal output from the OR circuit 54 are constant. The sum of the on period and the off period is constant. In this case, since the high level period of the PWM signal output from the OR circuit 54 is shorter than one period of the PWM signal 2, the ON period in the FET 14 is also shorter than one period of the PWM signal 2.
Since the FETs 13 and 14 are complementarily turned on / off, the sum of the on period and the off period in the FET 13 is constant, and the off period in the FET 13 is shorter than one period of the PWM signal 2.

Further, when the changing unit 52 determines that the duty of the PWM signal 2 generated by the generating unit 51 is zero%, in other words, the changing unit 52 determines that the duty of the PWM signal 1 generated by the generating unit 51 is less than 100%. In this case, a change signal 1 that is constant at a high level voltage is output. Thereby, the AND circuit 53 outputs the PWM signal 1 generated by the generation unit 51 as it is from the output terminal of the AND circuit 53.
Therefore, the output circuit 16 outputs the PWM signal 1 generated by the generation unit 51 when the duty of the PWM signal 1 generated by the generation unit 51 is less than 100%.

  FIG. 5 is a timing chart showing the on / off operation of the FETs 11, 12, 13, and 14 when the step-down operation is performed. As shown in FIG. 5, each of the FETs 11 and 12 is turned on / off in a complementary manner with a duty corresponding to the voltage output from the output terminal of the differential amplifier 15, so that a predetermined amount of current flows through the load 4. Has been adjusted. In addition, since a period during which the FETs 13 and 14 are off and on and the capacitor C2 is charged is always provided during a certain period, a charge pump circuit for charging the capacitor C4 regardless of the on / off state of the FETs 13 and 14 is unnecessary. It is. For this reason, the transformer 1 is small and inexpensive, and the configuration of the transformer 1 is simple.

  Further, when the duty of the PWM signal output from the OR circuit 54 by the output circuit 16 is 0%, the sum of the ON period and the OFF period adjacent to the ON period for each of the FETs 13 and 14 is the generation unit 51. Is longer than the period of the generated PWM signal 2, specifically, five times the period. For this reason, the number of on / off switchings of the FETs 13 and 14 repeated during a certain period is small, and the loss caused by the on / off switching repeated during the certain period is low for each of the FETs 13 and 14.

  Further, for each of the FETs 13 and 14 that are turned on / off when the duty of the PWM signal output from the OR circuit 54 by the output circuit 16 is 0%, the sum of the on period and the off period adjacent to the on period is Since it is constant, a period in which the FETs 13 and 14 are turned off and on is provided periodically. As a result, the capacitor C2 for turning on the FET 13 is stably charged, and the voltage applied between the drain of the FET 11 and the source of the FET 12 is more appropriately transformed.

  In the transformer 1 configured as described above, the output circuit 16 outputs the PWM signal 1 generated by the generation unit 51 from the output terminal of the AND circuit 53 while the step-down operation is performed. The output circuit 16 switches from the step-down operation to the step-up operation, and when the duty of the PWM signal 1 output from the output terminal of the AND circuit 53 is 100%, the PWM signal that repeatedly switches on / off in the FET 11 Is output from the output terminal of the AND circuit 53. In the on / off switching of the FET 11 performed by the PWM signal, the sum of the on period in the FET 11 and the off period adjacent to the on period is longer than the period of the PWM signal 1 generated by the generation unit 51.

  Further, the output circuit 16 outputs the PWM signal 2 generated by the generation unit 51 from the output terminal of the OR circuit 54 while the boosting operation is performed. The output circuit 16 switches from the step-up operation to the step-down operation, and when the duty of the PWM signal 2 output from the output terminal of the OR circuit 54 is zero%, the PWM signal that repeatedly switches on / off in the FET 14 Is output from the output terminal of the OR circuit 54. In the on / off switching of the FET 14 performed by the PWM signal, the sum of the on period in the FET 14 and the off period adjacent to the on period is longer than the period of the PWM signal 2 generated by the generation unit 51.

  In the first embodiment, when the duty of the PWM signal 1 generated by the generation unit 51 is 100%, the sum of the ON period in the FET 11 and the OFF period adjacent to the ON period is It does not have to be 5 times the cycle, and may be longer than the cycle of the PWM signal 1. That is, in the PWM signal changed by the change unit 52 outputting the change signal 1, the sum of the high level period and the low level period adjacent to the high level period is not five times the period of the PWM signal 1. It may be longer than the period of the PWM signal 1.

  Similarly, when the duty of the PWM signal 2 generated by the generation unit 51 is zero%, the sum of the ON period in the FET 14 and the OFF period adjacent to the ON period is five times the period in the PWM signal 2. It does not have to be, and only needs to be longer than the period of the PWM signal 2. That is, in the PWM signal changed by the change unit 52 outputting the change signal 2, the sum of the high level period and the low level period adjacent to the high level period is not five times the period of the PWM signal 1. It may be longer than the period of the PWM signal 2.

  In addition, when the duty of the PWM signal 1 generated by the generation unit 51 is 100%, the sum of the ON period in the FET 11 and the OFF period adjacent to the ON period may not be constant. That is, in the PWM signal changed by the change unit 52 outputting the change signal 1, the sum of the high level period and the low level period adjacent to the high level period may not be constant. Even in this case, a period in which the FETs 11 and 12 are off and on is always provided during a certain period, and furthermore, the number of times the FETs 11 and 12 are switched is small.

  Similarly, when the duty of the PWM signal 2 generated by the generation unit 51 is zero%, the sum of the ON period in the FET 14 and the OFF period adjacent to the ON period may not be constant. That is, the sum of the high level period and the low level period adjacent to the high level period may not be constant in the PWM signal changed by the change unit 52 outputting the change signal 2. Even in this case, a period during which the FETs 13 and 14 are off and on is always provided during a certain period, and the number of times the FETs 13 and 14 are switched is small.

  Further, the output circuit 16 may not be configured to change each of the PWM signal 1 and the PWM signal 2 generated by the generation unit 51. When the duty of the PWM signal 1 to be output is 100%, the output circuit 16 repeatedly switches on / off in the FET 11, and the sum of the on period in the FET 11 and the off period adjacent to the on period is the PWM signal 1. When the duty of the output PWM signal 2 is 0%, the on / off switching of the FET 14 is repeatedly performed, and the on period of the FET 14 and the off period adjacent to the on period are Any configuration may be used as long as the PWM signal is longer than the period of the PWM signal 2.

(Embodiment 2)
FIG. 6 is a block diagram showing a configuration of the step-down device according to the second embodiment. The step-down device 8 is separately connected to both ends of the battery 3 and the load 4, and steps down the voltage applied by the battery 3 and applies the stepped-down voltage to the load 4. The step-down device 8 differs from the transformer device 1 according to the first embodiment in that only the voltage applied by the battery 3 is stepped down.

  Hereinafter, the step-down device 8 according to the second embodiment will be described while referring to differences from the transformer device 1 according to the first embodiment. The same reference numerals are given to the configurations of the second embodiment common to the first embodiment, and detailed description thereof will be omitted.

  The step-down device 8 is similar to the transformer device 1 in the first embodiment, the FETs 11 and 12, the differential amplifier 15, the drive circuits 17 and 21, the inverter 18, the capacitors C1, C2, and C3, the diode D1, the coil L1, and the resistor. R1 is provided. The step-down device 8 further includes an output circuit 8a instead of the output circuit 16, and the output circuit 8a includes an AND circuit 53, a generation unit 81, and a change unit 82.

  In the step-down device 8, the FETs 11 and 12, the drive circuits 17 and 21, the inverter 18, the capacitors C2 and C3, the diode D1, and the coil L1 are connected in the same manner as in the first embodiment. The source of the FET 12 is grounded. The other end of the coil L1 whose one end is connected to the source of the FET 11 and the drain of the FET 12 is connected to one end of each of the capacitor C1 and the resistor R1, and the other end of the resistor R1 is connected to one end of the load 4. .

  The source of the FET 12 is connected to the other end of each of the capacitor C1 and the load 4. One end and the other end of the resistor R1 are connected to the plus terminal and the minus terminal of the differential amplifier 15, respectively, and the output terminal of the differential amplifier 15 is connected to the output circuit 8a. The output circuit 8a is further connected to the drain of the FET 11, the other end of the coil L1, the drive circuit 17, and the input terminal of the inverter 18.

  In the output circuit 8 a, the output terminal of the differential amplifier 15 is connected to the generation unit 81. The generation unit 81 is further connected to one input terminal of the AND circuit 53. The drain of the FET 11 and the other end of the coil L1 are connected to the changing unit 82 separately. The changing unit 82 is further connected to the other input terminal of the AND circuit 53. The output terminal of the AND circuit 53 is connected to the input terminals of the drive circuit 17 and the inverter 18. Each of the generation unit 81 and the change unit 82 is grounded.

  In the step-down device 8, the battery 3 is connected to the drain of the FET 11 by repeating complementary ON / OFF operations of the FET 11 whose source is connected to one end of the coil L 1 and the FET 12 whose drain is connected to one end of the coil L 1. And the voltage applied between the FET 12 and the source of the FET 12 are stepped down. The stepped down voltage is output from between the source of the FET 12 and the other end of the coil L1. Thereby, the stepped down voltage is applied to the load 4 via the resistor R1, and the load 4 is fed.

  When the FETs 11 and 12 are on and off, current flows from the positive terminal of the battery 3 in the order of the FET 11, the coil L 1, the resistor R 1, and the load 4, and returns to the negative terminal of the battery 3. At this time, energy is accumulated in the coil L1.

  When the FETs 11 and 12 are switched on and off from the state where the FETs 11 and 12 are switched off and on, the current flowing to the coil L1 is cut off, and the coil L1 is to maintain the amount of current flowing to itself. , Energy is released, and a current is generated from the coil L1. The current flows from the coil L1 in the order of the resistor R1, the load 4, and the FET 12, and returns to the coil L1. At this time, a voltage is applied between the source of the FET 12 and the other end of the coil L1, and the voltage between the source of the FET 12 and the other end of the coil L1 is stepped down as the energy of the coil L1 is released.

  When complementary ON / OFF of the FETs 11 and 12 is repeated, the voltage applied between the source of the FET 12 and the other end of the coil L1 is smoothed by the capacitor C1, and then applied to the load 4 via the resistor R1. Applied. At this time, the average voltage applied between the source of the FET 12 and the other end of the coil L1, that is, the voltage smoothed by the capacitor C1, is a voltage obtained by stepping down the voltage applied by the battery 3. The step-down width is increased or decreased according to the period during which the FETs 11 and 12 are off and on.

  As in the first embodiment, the differential amplifier 15 amplifies the voltage across the resistor R1, that is, the voltage proportional to the amount of output current flowing through the load 4, and outputs the amplified voltage from the output terminal to the output circuit 8a. Output to. The output circuit 8a outputs a PWM signal based on the voltage between the drain of the FET 11 and the source of the FET 12, the voltage between the source of the FET 12 and the other end of the coil L1, and the voltage input from the differential amplifier 15. Specifically, the output circuit 8 a outputs, from the output terminal of the AND circuit 53, a PWM signal used for on / off switching of the FETs 11 and 12 to the drive circuit 17 and the input terminal of the inverter 18.

  In the output circuit 8 a, the generation unit 81 generates a PWM signal that is configured by high-level and low-level voltages and is used for on / off switching in the FET 11 based on the voltage input from the differential amplifier 15. The duty of the PWM signal generated by the generation unit 81, that is, the ratio of the period during which the PWM signal is at a high level voltage in one cycle is 0% or more and 100% or less. The generation unit 81 outputs the generated PWM signal to one input terminal of the AND circuit 53.

  The changing unit 82 generates a change signal for changing the PWM signal generated by the generating unit 81 based on the voltage between the drain of the FET 11 and the source of the FET 12 and the voltage between the source of the FET 12 and the other end of the coil L1. The generated change signal is output to the other input terminal of the AND circuit 53. The change signal is composed of high-level and low-level voltages, like the PWM signal generated by the generation unit 81.

  The AND circuit 53 outputs a high level voltage when both the PWM signal and the change signal input to the two input terminals indicate a high level voltage, and at least one of the PWM signal and the change signal is at a low level. A low level voltage is output when the voltage is indicated. As in the first embodiment, the AND circuit 53 outputs to the input terminal of the inverter 18 and the input terminal of the inverter 61 of the drive circuit 17, and the AND circuit 53 outputs the switch S1 of the drive circuit 17. The signal is turned on and off according to the high level and low level voltages output from.

  When the PWM signal output from the output terminal of the AND circuit 53 is a low level voltage, as in the first embodiment, the FET 12 is turned on, the capacitor C3 is discharged, the FET 11 is turned off, and the capacitor C2 is charged. . When the PWM signal output from the output terminal of the AND circuit 53 is a high level voltage, the FET 12 is turned off, the capacitor C2 is discharged and the capacitor C3 is charged, and the FET 11 is turned on, as in the first embodiment. Become.

  The generation unit 81 outputs the PWM signal 1 shown in FIG. 2 or FIG. 4 to one input terminal of the AND circuit 53 in accordance with the voltage output from the output terminal by the differential amplifier 15. Specifically, when the PWM signal generated by the generation unit 81 is less than 100%, the duty is increased or decreased according to the level of the voltage output from the differential amplifier 15 as in the PWM signal 1 of FIG. A PWM signal is generated.

  When the amount of output current flowing through the load 4 via the resistor R1 is sufficiently small and the voltage output from the differential amplifier 15 is low, the generator 81 generates a PWM with a higher duty in order to increase the amount of output current. Repeat signal generation. When the duty of the PWM signal generated by the generation unit 81 is already 100% and the amount of output current is still small, the generation unit 81 has a duty of 100% as in the PWM signal 1 shown in FIG. A certain PWM signal is generated, and the generated PWM signal is output to one input terminal of the AND circuit 53.

  When the duty of the PWM signal generated by the generation unit 81 is less than 100%, the change unit 82 outputs a change signal that is constant at a high level voltage to the other of the AND circuit 53 as in the change signal 1 shown in FIG. Input to the input terminal. Therefore, the AND circuit 53 outputs the PWM signal generated by the generation unit 81 as it is from the output terminal to the drive circuit 17 and the input terminal of the inverter 18. Thereby, the FETs 11 and 12 are complementarily turned on / off according to the PWM signal generated by the generation unit 81, and the step-down width is adjusted so that a predetermined amount of current flows through the load 4.

  The changing unit 82 reduces the step-down width when a PWM signal having a duty of 100% is output from the output terminal of the AND circuit 53, that is, the voltage between the drain of the FET 11 and the source of the FET 12, and the source of the FET 12 and the coil L1. The difference from the voltage between the other ends is stored in advance.

  When the difference between the voltage between the drain of the FET 11 and the source of the FET 12 and the voltage between the source of the FET 12 and the other end of the coil L1 is equal to or less than the step-down width stored in advance, the changing unit 82 It is determined that the duty of the generated PWM signal is 100%. When the difference between the voltage between the drain of the FET 11 and the source of the FET 12 and the voltage between the source of the FET 12 and the other end of the coil L1 is larger than the pre-stored step-down width, the changing unit 82 It is determined that the duty of the PWM signal generated by 81 is less than 100%.

  When the changing unit 82 determines that the duty of the PWM signal generated by the generating unit 81 is 100%, in the first embodiment, the changing unit 82 determines that the duty of the PWM signal 1 generated by the generating unit 51 is 100%. In this case, a change signal similar to the change signal 1 of FIG. When the changing unit 82 determines that the duty of the PWM signal generated by the generating unit 81 is less than 100%, the duty of the PWM signal 1 generated by the generating unit 51 is less than 100% in the first embodiment. A change signal similar to the change signal 1 of FIG.

Accordingly, the step-down device 8 operates in the same manner as the transformer device 1 with respect to the configuration for turning on / off the FETs 11 and 12.
Therefore, when the duty of the PWM signal generated by the generation unit 81 is 100%, the change unit 82 outputs the change signal to switch the PWM signal generated by the generation unit 81 on / off in the FET 11. Is changed to a PWM signal that is repeatedly executed. In the on / off switching of the FET 11 performed by the PWM signal, the sum of the on period in the FET 11 and the off period adjacent to the on period is constant longer than the period of the PWM signal generated by the generation unit 81. . The output circuit 8a outputs the PWM signal generated by the generation unit 81 when the duty of the PWM signal generated by the generation unit 81 is less than 100%, and the duty of the PWM signal generated by the generation unit 81 is 100%. In some cases, the changing unit 82 outputs the changed PWM signal.

  Thereby, when the duty of the output PWM signal is 100%, the output circuit 8a repeatedly switches on / off in the FET 11, and the sum of the on period in the FET 11 and the off period adjacent to the on period is The PWM signal longer than the cycle of the PWM signal generated by the generation unit 81 is output from the output terminal of the AND circuit 53.

  As described above, when the step-down device 8 acts, the step-down device 8 obtains the same effect as that of the transformer device 1 in the first embodiment. Specifically, since a period during which the FETs 11 and 12 are off and on and the capacitor C2 is charged is always provided during a certain period, the charge pump that charges the capacitor C2 regardless of the on / off state of the FETs 11 and 12 No circuit is required. Therefore, the step-down device 8 is small and inexpensive, and the configuration of the step-down device 8 is simple.

Further, the number of on / off switchings of the FETs 11 and 12 repeated during a certain period is small, and the loss caused by the on / off switching repeated during the certain period is low for each of the FETs 11 and 12.
Furthermore, a period in which the FETs 11 and 12 are turned off and on is provided periodically. Thereby, the capacitor C2 for turning on the FET 11 is stably charged, and the voltage applied between the drain of the FET 11 and the source of the FET 12 is more appropriately stepped down.

  In the second embodiment, when the duty of the PWM signal generated by the generation unit 81 is 100%, the generation unit 81 generates the sum of the ON period in the FET 11 and the OFF period adjacent to the ON period. The period of the PWM signal may not be five times as long as it is longer than the period of the PWM signal. That is, in the PWM signal changed by the change unit 82 outputting the change signal, the sum of the high level period and the low level period adjacent to the high level period is the period of the PWM signal generated by the generation unit 81. It does not have to be five times as long as it is longer than the period of the PWM signal generated by the generation unit 81.

  Further, when the duty of the PWM signal generated by the generation unit 81 is 100%, the sum of the ON period in the FET 11 and the OFF period adjacent to the ON period may not be constant. That is, in the PWM signal changed by the changing unit 82 outputting the change signal, the sum of the high level period and the low level period adjacent to the high level period may not be constant. Even in this case, a period in which the FETs 11 and 12 are off and on is always provided during a certain period, and furthermore, the number of times the FETs 11 and 12 are switched is small.

  Furthermore, the output circuit 8a may not be configured to change the PWM signal generated by the generation unit 81. When the duty of the output PWM signal is 100%, the output circuit 8a repeatedly performs on / off switching in the FET 11, and the sum of the on period in the FET 11 and the off period adjacent to the on period is the generation unit 81. Any configuration may be used as long as it outputs a PWM signal longer than the period of the PWM signal generated by.

(Embodiment 3)
FIG. 7 is a block diagram showing the configuration of the booster according to the third embodiment. The booster 9 is connected to both ends of the battery 3 and the load 4, boosts the voltage applied by the battery 3, and applies the boosted voltage to the load 4. The booster 9 is different from the transformer 1 of the first embodiment in that only the voltage applied by the battery 3 is boosted.

  Below, the booster 9 in the third embodiment will be described with respect to differences from the transformer 1 in the first embodiment. The same reference numerals are given to the configurations of the third embodiment common to the first and second embodiments, and detailed description thereof will be omitted.

  As with the voltage transformer 1 in the first embodiment, the voltage booster 9 includes FETs 13 and 14, a differential amplifier 15, drive circuits 19 and 22, an inverter 20, capacitors C1, C4 and C5, a diode D2, a coil L1, and a resistor. R1 is provided. The booster 9 further includes an output circuit 9 a instead of the output circuit 16, and the output circuit 9 a includes an OR circuit 54, a generation unit 91, and a change unit 92.

  In the booster 9, the FETs 13 and 14, the differential amplifier 15, the drive circuits 19 and 22, the inverter 20, the capacitors C1, C4 and C5, the diode D2, the coil L1, and the resistor R1 are connected in the same manner as in the first embodiment. ing. The source of the FET 14 is grounded. One end of the coil L1 whose other end is connected to the source of the FET 13 and the drain of the FET 14 is connected to the anode of the diode D2 and the positive terminal of the battery 3, and the negative terminal of the battery 3 is connected to the source of the FET 14. It is.

  The output terminal of the differential amplifier 15 is connected to the output circuit 9a. The output circuit 9 a is further connected to one end of the coil L 1 on the battery 3 side, the drain of the FET 13, the drive circuit 19, and the input terminal of the inverter 20.

  In the output circuit 9 a, the output terminal of the differential amplifier 15 is connected to the generation unit 91. The generation unit 91 is further connected to one input terminal of the OR circuit 54. One end of the coil L1 on the battery 3 side and the drain of the FET 13 are connected to the changing unit 92 separately. The changing unit 92 is further connected to the other input terminal of the OR circuit 54. The output terminal of the OR circuit 54 is connected to the input terminals of the drive circuit 19 and the inverter 20. Each of the generation unit 91 and the change unit 92 is grounded.

  In the booster 9, the battery 3 is connected to the coil 3 by repeating complementary ON / OFF operations of the FET 13 whose source is connected to the other end of the coil L1 and the FET 14 whose drain is connected to the other end of the coil L1. The voltage applied between the other end of L1 and the source of the FET 14 is boosted. The boosted voltage is output from between the drain of the FET 13 and the source of the FET 14. Thereby, the boosted voltage is applied to the load 4 via the resistor R1, and the load 4 is fed.

  When the FETs 13 and 14 are off and on, current flows from the positive terminal of the battery 3 in the order of the coil L1 and the FET 14, and returns to the negative terminal of the battery 3. At this time, a large amount of current flows through the coil L1, and energy is accumulated in the coil L1.

  When the FETs 13 and 14 are turned off and on, and the FETs 13 and 14 are turned on and off, current flows from the positive terminal of the battery 3 in the order of the coil L1, the FET 13, the resistor R1, and the load 4. Return to the negative terminal of the battery 3. At this time, since the current flows through the resistor R1 and the load 4, the amount of current flowing through the coil L1 decreases. Therefore, the coil L1 boosts the voltage at the other end of the coil L1 on the FET 13 side with reference to the voltage applied to the one end of the coil L1 on the battery 3 side in order to maintain the amount of current flowing therethrough. As a result, the voltage applied between the drain of the FET 13 and the source of the FET 14 is higher than the voltage applied by the battery 3 between one end of the coil L1 and the source of the FET 14.

  When the on / off operations of the FETs 13 and 14 are repeated, the voltage applied between the drain of the FET 13 and the source of the FET 14 is smoothed by the capacitor C1 and then applied to the load 4 via the resistor R1. Applied. At this time, the average voltage applied between the drain of the FET 13 and the source of the FET 14, that is, the voltage smoothed by the capacitor C 1 is a voltage obtained by boosting the voltage applied by the battery 3. The step-up width becomes larger or smaller depending on the period during which the FETs 13 and 14 are off and on.

  Similarly to the first embodiment, the differential amplifier 15 amplifies the voltage across the resistor R1, that is, a voltage proportional to the amount of output current flowing through the load 4, and outputs the amplified voltage from the output terminal to the output circuit 9a. Output to. The output circuit 9a outputs a PWM signal based on the voltage between one end of the coil L1 and the source of the FET 14, the voltage between the drain of the FET 13 and the source of the FET 14, and the voltage input from the differential amplifier 15. Specifically, the output circuit 9 a outputs, from the output terminal of the OR circuit 54, a PWM signal used for on / off switching in the FETs 13 and 14 to the input terminal of the inverter 20 and the drive circuit 19.

  In the output circuit 9 a, the generation unit 91 is configured with high-level and low-level voltages based on the voltage input from the differential amplifier 15, and generates a PWM signal used for on / off switching in the FET 14. The duty of the PWM signal generated by the generation unit 91, that is, the ratio of the period in which the PWM signal is at a high level voltage in one cycle is 0% or more and 100% or less. The generation unit 91 outputs the generated PWM signal to one input terminal of the OR circuit 54.

  The changing unit 92 changes the PWM signal generated by the generating unit 91 based on the voltage between the one end of the coil L1 applied by the battery 3 and the source of the FET 14 and the voltage between the drain of the FET 13 and the source of the FET 14. And the generated change signal is output to the other input terminal of the OR circuit 54. The change signal is composed of high-level and low-level voltages, like the PWM signal generated by the generation unit 91.

  The OR circuit 54 outputs a high level voltage when at least one of the PWM signal and the change signal input to each of the two input terminals indicates a high level voltage, and both the PWM signal and the change signal are at a low level. A low level voltage is output when the voltage is indicated. As in the first embodiment, the OR circuit 54 outputs to the drive circuit 19 and the input terminal of the inverter 20, and the switch S4 of the drive circuit 19 outputs the high and low levels output from the output terminal of the OR circuit 54. It turns on and off according to the level voltage.

  When the PWM signal output from the output terminal of the OR circuit 54 is a high level voltage, as in the first embodiment, the FET 14 is turned on, the capacitor C5 is discharged, the FET 13 is turned off, and the capacitor C4 is charged. . Even when the PWM signal output from the output terminal of the OR circuit 54 is a low level voltage, the FET 14 is turned off, the capacitor C4 is discharged and the capacitor C5 is charged, and the FET 13 is turned on, as in the first embodiment. Become.

  The generation unit 91 outputs the PWM signal 2 shown in FIG. 2 or 4 to one input terminal of the OR circuit 54 according to the voltage output from the output terminal by the differential amplifier 15. Specifically, when the PWM signal generated by the generation unit 91 exceeds zero%, the duty is reduced according to the level of the voltage output from the differential amplifier 15 as in the PWM signal 2 of FIG. A PWM signal is generated.

  When the amount of output current flowing to the load 4 via the resistor R1 is sufficiently large and the voltage output from the differential amplifier 15 is high, the generator 91 generates a PWM with a higher duty in order to reduce the amount of output current. Repeat signal generation. When the duty of the PWM signal generated by the generation unit 91 is already 0% and the output current amount is still large, the generation unit 91 has a duty of 0% as in the PWM signal 2 shown in FIG. A certain PWM signal is generated, and the generated PWM signal is output to one input terminal of the OR circuit 54.

  When the duty of the PWM signal generated by the generation unit 91 exceeds zero%, the change unit 92 generates a change signal that is constant at a low level voltage as shown in the change signal 2 in FIG. Input to the other input terminal. Therefore, the OR circuit 54 outputs the PWM signal generated by the generation unit 91 as it is from the output terminal to the input terminal of the inverter 20 and the drive circuit 19. Thereby, the FETs 13 and 14 are complementarily turned on / off according to the PWM signal generated by the generation unit 91, and the boosting width is adjusted so that a predetermined amount of current flows through the load 4.

  The changing unit 92 has a step-up width when a PWM signal having a duty of zero% is output from the output terminal of the OR circuit 54, that is, a voltage between one end of the coil L1 and the source of the FET 14, and a drain of the FET 13 and the FET 14 The difference with the voltage between the sources is stored in advance.

  The changing unit 92 generates the changing unit 92 when the difference between the voltage between the one end of the coil L1 and the source of the FET 14 and the voltage between the drain of the FET 13 and the source of the FET 14 is equal to or less than the boosted width stored in advance. It is determined that the duty of the PWM signal is zero%. When the difference between the voltage between the one end of the coil L1 and the source of the FET 14 and the voltage between the drain of the FET 13 and the source of the FET 14 is larger than the boosting width stored in advance, the changing unit 92 It is determined that the duty of the generated PWM signal exceeds zero%.

  When the changing unit 92 determines that the duty of the PWM signal generated by the generating unit 91 is zero%, in the first embodiment, the changing unit 92 determines that the duty of the PWM signal 2 generated by the generating unit 51 is zero%. In this case, a change signal similar to the change signal 2 of FIG. Further, when the changing unit 92 determines that the duty of the PWM signal generated by the generating unit 91 exceeds zero%, the duty of the PWM signal 2 generated by the generating unit 51 is zero% in the first embodiment. A change signal similar to the change signal 2 shown in FIG.

Accordingly, the booster 9 operates in the same manner as the transformer 1 with respect to the configuration for turning on / off the FETs 13 and 14.
Therefore, when the duty of the PWM signal generated by the generation unit 91 is zero%, the change unit 92 outputs the change signal, thereby switching the PWM signal generated by the generation unit 91 on / off in the FET 14. Is changed to a PWM signal that is repeatedly executed. In the ON / OFF switching of the FET 14 performed by the PWM signal, the sum of the ON period in the FET 14 and the OFF period adjacent to the ON period is constant longer than the period of the PWM signal generated by the generation unit 91. . The output circuit 9a outputs the PWM signal generated by the generation unit 91 when the duty of the PWM signal generated by the generation unit 91 exceeds zero%, and the duty of the PWM signal generated by the generation unit 91 is zero%. In this case, the changing unit 92 outputs the changed PWM signal.

  As a result, when the duty of the output PWM signal is 0%, the output circuit 9a repeatedly switches on / off in the FET 14, and the sum of the on period in the FET 14 and the off period adjacent to the on period is The PWM signal longer than the period of the PWM signal generated by the generation unit 91 is output from the output terminal of the OR circuit 54.

  As described above, when booster 9 operates, booster 9 obtains the same effect as transformer 1 in the first embodiment. Specifically, since a period during which the FETs 13 and 14 are off and on and the capacitor C4 is charged is always provided during a certain period, the charge pump charges the capacitor C4 regardless of the on / off state of the FETs 13 and 14. No circuit is required. Therefore, the booster 9 is small and inexpensive, and the configuration of the booster 9 is simple.

In addition, the number of on / off switchings of the FETs 13 and 14 repeated during a certain period is small, and the loss caused by the on / off switching repeated during the certain period is low for each of the FETs 13 and 14.
Furthermore, a period in which the FETs 13 and 14 are turned off and on is provided periodically. As a result, the capacitor C4 for turning on the FET 13 is stably charged, and the voltage applied to the battery 3 between one end of the coil L1 and the source of the FET 14 is boosted more appropriately.

  In the third embodiment, when the duty of the PWM signal generated by the generation unit 91 is zero%, the generation unit 91 generates the sum of the ON period in the FET 14 and the OFF period adjacent to the ON period. The period of the PWM signal may not be five times as long as it is longer than the period of the PWM signal. That is, in the PWM signal changed by the change unit 92 outputting the change signal, the sum of the high level period and the low level period adjacent to the high level period is the period of the PWM signal generated by the generation unit 91. It does not have to be five times as long as it is longer than the period of the PWM signal generated by the generation unit 91.

  Further, when the duty of the PWM signal generated by the generation unit 91 is zero%, the sum of the on period in the FET 14 and the off period adjacent to the on period may not be constant. That is, in the PWM signal changed by the changing unit 92 outputting the change signal, the sum of the high level period and the low level period adjacent to the high level period may not be constant. Even in this case, a period during which the FETs 13 and 14 are off and on is always provided during a certain period, and the number of times the FETs 13 and 14 are switched is small.

  Furthermore, the output circuit 9a may not be configured to change the PWM signal generated by the generation unit 91. When the duty of the output PWM signal is zero%, the output circuit 9a repeatedly switches on / off of the FET 14, and the sum of the on period of the FET 14 and the off period adjacent to the on period is the generation unit 91. Any configuration may be used as long as it outputs a PWM signal longer than the period of the PWM signal generated by.

  In the first to third embodiments, each of the FETs 11, 12, 13, and 14 may be an NPN bipolar transistor instead of an N-channel FET.

  The disclosed embodiments 1 to 3 should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

DESCRIPTION OF SYMBOLS 1 Transformer 11 FET (The other switch of Claim 1, 1st switch)
12 FET (one switch of claim 1, second switch)
13 FET (the other switch of claim 4, the third switch)
14 FET (one switch according to claim 4, fourth switch)
16, 8a, 9a Output circuit 51 generator (first generator, second generator)
52 changing section (first changing means, second changing means)
8 Voltage Step-Down Device 81, 91 Generation Unit 82, 92 Change Unit 9 Step-up Device L1 Coil

Claims (11)

By repeating complementary ON / OFF of two switches each having one end connected to one end of the coil, the voltage applied between the other ends of the two switches is stepped down, and the stepped down voltage is In the step-down device that outputs from between the other end of one of the two switches and the other end of the coil,
An output circuit for outputting a PWM signal used for switching on / off in the other switch of the two switches;
When the duty of the output PWM signal is 100%, the output circuit repeatedly performs on / off switching in the other switch, and an on period of the other switch and an off period adjacent to the on period are A step-down device characterized in that a PWM signal whose total is longer than the period of the output PWM signal is output. The output circuit is
A generator for generating a first PWM signal used for on / off switching in the other switch;
When the duty of the first PWM signal generated by the generator is 100%, the first PWM signal is repeatedly switched on / off in the other switch, and the sum of the on period and the off period is the first PWM signal. A changing unit for changing to a second PWM signal that is longer than the period of the signal,
The output circuit is
When the duty of the first PWM signal generated by the generating unit is less than 100%, the first PWM signal is output,
The step-down device according to claim 1, wherein the step-down device is configured to output the second PWM signal when the duty of the first PWM signal generated by the generation unit is 100%. The step-down device according to claim 1, wherein the sum of the on period and the off period is constant. By repeating complementary on / off of two switches, each having one end connected to one end of the coil, between the other end of the coil and the other end of one of the two switches. In the boosting device that boosts the applied voltage and outputs the boosted voltage from between the other ends of the two switches,
An output circuit that outputs a PWM signal used for on / off switching in the one switch;
When the duty of the output PWM signal is zero%, the output circuit repeatedly performs on / off switching in the one switch, and an on period in the one switch and an off period adjacent to the on period A booster characterized in that the PWM signal is configured to output a PWM signal whose total is longer than the period of the output PWM signal. The output circuit is
A generator for generating a first PWM signal used for on / off switching in the one switch;
When the duty of the first PWM signal generated by the generation unit is zero%, the first PWM signal is repeatedly switched on / off in the one switch, and the sum of the on period and the off period is the first PWM signal. A changing unit for changing to a second PWM signal that is longer than the period of the signal,
The output circuit is
When the duty of the first PWM signal generated by the generation unit exceeds zero%, the first PWM signal is output,
5. The boosting device according to claim 4, wherein the second PWM signal is output when a duty of the first PWM signal generated by the generation unit is zero%. The boosting device according to claim 4 or 5, wherein the sum of the on period and the off period is constant. A first switch and a second switch each having one end connected to one end of the coil, a third switch having one end connected to the other end of the coil, and a connection between the other ends of the coil and the second switch The first and second switches, and the first and second switches are repeatedly turned on and off, and the third and fourth switches are turned on and off repeatedly. In a transformer for transforming a voltage applied between the other ends of the second switches, and outputting the transformed voltage from between the other end of the third switch and one end of the fourth switch on the second switch side,
An output circuit that outputs a first PWM signal used for on / off switching in the first switch and a second PWM signal used for on / off switching in the fourth switch;
The output circuit is
When the duty of the first PWM signal to be output is 100%, ON / OFF switching in the first switch is repeatedly performed, and the sum of the ON period in the first switch and the OFF period adjacent to the ON period is the first switch. Output a PWM signal longer than the period of one PWM signal,
When the duty of the second PWM signal to be output is zero%, the on / off switching of the fourth switch is repeatedly performed, and the sum of the on period of the fourth switch and the off period adjacent to the on period is the first number. 2. A transformer apparatus configured to output a PWM signal longer than a period of 2 PWM signals. The output circuit is
First generation means for generating a third PWM signal used for on / off switching in the first switch;
When the duty of the third PWM signal generated by the first generation means is 100%, the third PWM signal is repeatedly switched on and off in the first switch, and the on period and the off period in the first switch And a first changing means for changing to a fourth PWM signal whose total is longer than the period of the third PWM signal,
The output circuit is
When the duty of the third PWM signal generated by the first generation means is less than 100%, the third PWM signal is output,
The transformer according to claim 7, wherein the fourth PWM signal is output when the duty of the third PWM signal generated by the first generation means is 100%. The transformer device according to claim 7 or 8, wherein a sum of an ON period and an OFF period in the first switch is constant. The output circuit is
Second generation means for generating a fifth PWM signal used for on / off switching in the fourth switch;
When the duty of the fifth PWM signal generated by the second generation means is 0%, the fifth PWM signal is repeatedly switched on / off in the fourth switch, and the on period and the off period in the fourth switch Second changing means for changing to a sixth PWM signal whose total is longer than the cycle of the fifth PWM signal,
The output circuit is
When the duty of the fifth PWM signal generated by the second generation means exceeds zero%, the fifth PWM signal is output.
10. The configuration according to claim 7, wherein the sixth PWM signal is output when the duty of the fifth PWM signal generated by the second generation means is zero%. The transformer device described in 1. The transformer device according to any one of claims 7 to 10, wherein the sum of the ON period and the OFF period in the fourth switch is constant.

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