JP2015037175A - Multilayer ceramic electronic component, and method for manufacturing the same and mounting board for the same - Google Patents

Multilayer ceramic electronic component, and method for manufacturing the same and mounting board for the same Download PDF

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JP2015037175A
JP2015037175A JP2013222411A JP2013222411A JP2015037175A JP 2015037175 A JP2015037175 A JP 2015037175A JP 2013222411 A JP2013222411 A JP 2013222411A JP 2013222411 A JP2013222411 A JP 2013222411A JP 2015037175 A JP2015037175 A JP 2015037175A
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width
electronic component
ceramic body
multilayer ceramic
ceramic electronic
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JP5725678B2 (en
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ヒュク シム、ジェ
Jae Hyuk Shim
ヒュク シム、ジェ
小野 雅章
Masaaki Ono
雅章 小野
ヨル チョイ、ジェ
Jae Yeol Choi
ヨル チョイ、ジェ
ジュン パーク、ミュン
Myung Jun Park
ジュン パーク、ミュン
ソーク リー、ヤン
Young Sook Lee
ソーク リー、ヤン
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Samsung Electro Mechanics Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/018Dielectrics
    • H01G4/06Solid dielectrics
    • H01G4/08Inorganic dielectrics
    • H01G4/12Ceramic dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G2/00Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02Mountings
    • H01G2/06Mountings specially adapted for mounting on a printed-circuit support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G2/00Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02Mountings
    • H01G2/06Mountings specially adapted for mounting on a printed-circuit support
    • H01G2/065Mountings specially adapted for mounting on a printed-circuit support for surface mounting, e.g. chip capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • H01G4/232Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/43Electric condenser making

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer ceramic electronic component, and a method for manufacturing the same and a mounting board for the same.SOLUTION: A multilayer ceramic electronic component 100 comprises: a ceramic body 110 which includes a plurality of dielectric layers 111 laminated in a thickness direction and satisfies T/W>1.0, where W is the width thereof and T is the thickness thereof; a plurality of first and second internal electrodes 121, 122 which are arranged to face each other through the dielectric layers 111 in the ceramic body 110 and exposed alternately through both end surfaces of the ceramic body 110; and first and a second external electrodes 131, 132 which includes head parts 131a, 132a formed on both end surfaces of the ceramic body and two band parts 131b, 132b connected to head parts and formed on upper and lower main surfaces of the ceramic body while being separated from each other in the width direction, and are electrically connected to first and second internal electrodes.

Description

本発明は、積層セラミック電子部品、その製造方法及びその実装基板に関する。   The present invention relates to a multilayer ceramic electronic component, a manufacturing method thereof, and a mounting substrate thereof.

最近、電子製品の小型化の傾向により、該電子製品に用いられる積層セラミック電子部品にも小型化及び高容量化が求められている。   Recently, due to the trend toward miniaturization of electronic products, there has been a demand for miniaturization and high capacity of multilayer ceramic electronic components used in the electronic products.

これにより、誘電体層と内部電極の薄膜化及び多層化が多様な方法で試みられており、近来では誘電体層は薄く、その積層数は増加した積層セラミック電子部品が製造されている。   As a result, thinning and multilayering of dielectric layers and internal electrodes have been attempted by various methods, and recently, multilayer ceramic electronic parts having a thin dielectric layer and an increased number of laminated layers have been manufactured.

上記積層セラミック電子部品の小型化、及び誘電体層と内部電極の薄膜化が可能でありながら、高容量化の具現のために積層数を増加させることができるようになった。   While the multilayer ceramic electronic component can be miniaturized and the dielectric layer and the internal electrode can be made thin, the number of layers can be increased in order to realize high capacity.

しかし、上記のように誘電体層及び内部電極を薄くしながら積層数を増加させると、積層セラミック電子部品の高容量は具現できるが、積層数の増加により積層セラミック電子部品の厚さが幅より大きい形態となる。   However, if the number of stacks is increased while the dielectric layers and internal electrodes are thinned as described above, the high capacity of the multilayer ceramic electronic component can be realized. It becomes a big form.

上記のように、積層セラミック電子部品の厚さが幅より大きく形成される場合、一般的に積層セラミック電子部品の両端面に形成された外部電極はその周縁面が突出したラウンド状になる。   As described above, when the thickness of the multilayer ceramic electronic component is formed to be larger than the width, generally, the external electrodes formed on both end faces of the multilayer ceramic electronic component have a round shape with protruding peripheral surfaces.

従って、積層セラミック電子部品を印刷回路基板などに実装する際、積層セラミック電子部品が実装された状態を保持できずに倒れる問題が頻繁に起こり、積層セラミック電子部品の実装不良率が増加するという問題点がある。   Therefore, when mounting a multilayer ceramic electronic component on a printed circuit board or the like, there is a frequent problem that the multilayer ceramic electronic component cannot be maintained in a state where it is mounted, and the mounting failure rate of the multilayer ceramic electronic component increases. There is a point.

下記特許文献1は、小型化及び高容量化に対応した積層セラミックコンデンサを開示しているが、積層セラミックコンデンサを印刷回路基板に実装したときに倒れる問題を解決するための手段は開示していない。   Patent Document 1 below discloses a multilayer ceramic capacitor corresponding to downsizing and high capacity, but does not disclose means for solving the problem of falling when the multilayer ceramic capacitor is mounted on a printed circuit board. .

特開2005−129802号公報JP 2005-129802 A

当該技術分野では、積層数が増加するに伴って厚さが幅より大きくなり、高容量を具現しながらも、積層セラミック電子部品を印刷回路基板などに実装する際に倒れる問題を解決し、実装不良及びショートの発生を低減させる新しい方案が求められてきた。   In this technical field, as the number of stacks increases, the thickness becomes larger than the width, and while realizing high capacity, it solves the problem of falling down when mounting multilayer ceramic electronic components on printed circuit boards, etc. There has been a demand for new ways to reduce the occurrence of defects and shorts.

本発明の一側面は、厚さ方向に積層された複数の誘電体層を含み、幅をW、厚さをTと規定するとき、T/W>1.0を満たすセラミック本体と、上記セラミック本体内で上記誘電体層を介して対向配置され、上記セラミック本体の両端面を通じて交互に露出した複数の第1及び第2内部電極と、上記セラミック本体の両端面に形成された頭部、及び上記頭部と連結され、上記セラミック本体の上下の主面に幅方向に相互離隔されて形成された2個のバンド部を含み、上記第1及び第2内部電極とそれぞれ電気的に連結された第1及び第2外部電極と、を含む積層セラミック電子部品を提供する。   One aspect of the present invention includes a ceramic body that includes a plurality of dielectric layers stacked in the thickness direction, satisfying T / W> 1.0 when the width is defined as W and the thickness is defined as T, and the ceramic A plurality of first and second internal electrodes disposed opposite to each other through the dielectric layer in the body and exposed alternately through both end faces of the ceramic body; and heads formed on both end faces of the ceramic body; and The upper and lower main surfaces of the ceramic body are connected to the head, and include two band portions formed to be spaced apart from each other in the width direction, and are electrically connected to the first and second internal electrodes, respectively. Provided is a multilayer ceramic electronic component including first and second external electrodes.

本発明の他の側面は、幅方向に積層された複数の誘電体層を含み、幅をW、厚さをTと規定するとき、T/W>1.0を満たすセラミック本体と、上記セラミック本体内で上記誘電体層を介して対向配置され、上記セラミック本体の両端面を通じて交互に露出した複数の第1及び第2内部電極と、上記セラミック本体の両端面に形成された頭部、及び上記頭部と連結され、上記セラミック本体の上下の主面に幅方向に相互離隔されて形成された2個のバンド部を含み、上記第1及び第2内部電極とそれぞれ電気的に連結された第1及び第2外部電極と、を含む積層セラミック電子部品を提供する。   Another aspect of the present invention includes a ceramic body that includes a plurality of dielectric layers stacked in the width direction and satisfies T / W> 1.0 when the width is defined as W and the thickness is defined as T, and the ceramic A plurality of first and second internal electrodes disposed opposite to each other through the dielectric layer in the body and exposed alternately through both end faces of the ceramic body; and heads formed on both end faces of the ceramic body; and The upper and lower main surfaces of the ceramic body are connected to the head, and include two band portions formed to be spaced apart from each other in the width direction, and are electrically connected to the first and second internal electrodes, respectively. Provided is a multilayer ceramic electronic component including first and second external electrodes.

本発明のさらに他の側面は、第1及び第2内部電極が形成された複数のセラミックシートを上記セラミックシートを介して上記第1及び第2内部電極が対向配置されるように積層し加圧して積層体を設ける段階と、上記積層体を1個のキャパシタに対応する領域ごとに切断して焼成し、対向する厚さ方向の第1及び第2主面、上記第1及び第2内部電極が交互に露出する長さ方向の第1及び第2端面、及び幅方向の第1及び第2側面を有するセラミック本体を設ける段階と、上記セラミック本体に上記第1及び第2内部電極と電気的に連結されるように第1及び第2外部電極を形成する段階と、を含み、上記第1及び第2外部電極を形成する段階は、上記セラミック本体の厚さ−幅断面において、上記第1及び第2主面と上記第1及び第2側面が接する両角部に導電性ペーストを塗布して上記第1及び第2端面に頭部を形成し、上記第1及び第2主面に相互離隔されるように2個のバンド部を形成する積層セラミック電子部品の製造方法を提供する。   According to still another aspect of the present invention, a plurality of ceramic sheets on which the first and second internal electrodes are formed are stacked and pressed so that the first and second internal electrodes are arranged to face each other through the ceramic sheet. Providing a multilayer body, cutting the multilayer body into regions corresponding to one capacitor, firing, and opposing the first and second main surfaces in the thickness direction, the first and second internal electrodes. Providing a ceramic body having first and second end faces in the lengthwise direction, and first and second side faces in the widthwise direction that are alternately exposed, and electrically connecting the first and second internal electrodes to the ceramic body. Forming the first and second external electrodes to be connected to each other, and forming the first and second external electrodes in the thickness-width cross section of the ceramic body. And the second main surface and the first and second sides. A laminate in which a conductive paste is applied to both corners in contact with each other to form heads on the first and second end faces and to form two band parts so as to be separated from each other on the first and second main faces A method for manufacturing a ceramic electronic component is provided.

本発明の一実施例において、上記積層体を設ける段階は、上記セラミックシートを厚さ方向に積層したり、幅方向に積層してもよい。   In one embodiment of the present invention, in the step of providing the laminate, the ceramic sheets may be laminated in the thickness direction or in the width direction.

本発明の一実施例において、上記セラミック本体の幅をW、上記バンド部の幅をaと規定するとき、0.10≦a/W≦0.45を満たすことができる。   In one embodiment of the present invention, when the width of the ceramic body is defined as W and the width of the band portion is defined as a, 0.10 ≦ a / W ≦ 0.45 can be satisfied.

本発明の一実施例において、上記バンド部の厚さをSと規定するとき、2≦S≦40μmを満たすことができる。   In one embodiment of the present invention, when the thickness of the band portion is defined as S, 2 ≦ S ≦ 40 μm can be satisfied.

本発明の一実施形態によると、積層数を増加させて高容量を具現しながらも、外部電極が相互離隔された2個のバンド部を含むように形成することで、積層セラミック電子部品を印刷回路基板などに実装した際に倒れる現象を防止し、実装不良率及びショート発生を低減させる効果がある。   According to an embodiment of the present invention, the multilayer ceramic electronic component is printed by forming the external electrode to include two band portions that are spaced apart from each other, while increasing the number of layers to realize a high capacity. This prevents the phenomenon of falling when mounted on a circuit board or the like, and reduces the mounting defect rate and occurrence of short circuits.

本発明の一実施形態による積層セラミックキャパシタの一部を切開して概略的に示した斜視図である。1 is a perspective view schematically showing a multilayer ceramic capacitor in accordance with an embodiment of the present invention by cutting a part thereof. 図1のA−A'線の断面図である。It is sectional drawing of the AA 'line of FIG. 本発明の他の実施形態による積層セラミックキャパシタの一部を切開して概略的に示した斜視図である。FIG. 5 is a perspective view schematically showing a multilayer ceramic capacitor in accordance with another embodiment of the present invention cut away. 図3のB−B'線の断面図である。It is sectional drawing of the BB 'line | wire of FIG. 本発明の一実施形態による積層セラミックキャパシタが印刷回路基板に実装された様子を積層セラミックキャパシタの一部を切開して概略的に示した斜視図である。1 is a perspective view schematically showing a state in which a multilayer ceramic capacitor according to an embodiment of the present invention is mounted on a printed circuit board by cutting a part of the multilayer ceramic capacitor.

以下では、添付の図面を参照し、本発明の好ましい実施形態について説明する。しかし、本発明の実施形態は様々な他の形態に変形されることができ、本発明の範囲は以下で説明する実施形態に限定されない。また、本発明の実施形態は、当該技術分野で平均的な知識を有する者に本発明をより完全に説明するために提供されるものである。図面における要素の形状及び大きさなどはより明確な説明のために誇張されることがある。   Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiments of the present invention can be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. In addition, the embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. The shape and size of elements in the drawings may be exaggerated for a clearer description.

以下では、本発明の一実施形態による積層セラミック電子部品を、特に積層セラミックキャパシタで説明するが、本発明はこれに限定されない。   Hereinafter, a multilayer ceramic electronic component according to an embodiment of the present invention will be described using a multilayer ceramic capacitor, but the present invention is not limited to this.

積層セラミックキャパシタ
図1は本発明の一実施形態による積層セラミックキャパシタの一部を切開して概略的に示した斜視図である。
Multilayer Ceramic Capacitor FIG. 1 is a perspective view schematically showing a part of a multilayer ceramic capacitor according to an embodiment of the present invention.

図1を参照すると、本発明の一実施形態による積層セラミックキャパシタ100は、セラミック本体110と、複数の第1及び第2内部電極121、122と、第1及び第2外部電極131、132と、を含む。   Referring to FIG. 1, a multilayer ceramic capacitor 100 according to an embodiment of the present invention includes a ceramic body 110, a plurality of first and second internal electrodes 121 and 122, first and second external electrodes 131 and 132, including.

セラミック本体110は、複数の誘電体層111を厚さ方向に積層した後焼成したものであって、隣接する誘電体層111同士の境界は走査電子顕微鏡(SEM:Scanning Electron Microscope)を用いずには確認できない程に一体化されていてもよい。   The ceramic body 110 is formed by laminating a plurality of dielectric layers 111 in the thickness direction and then firing, and a boundary between adjacent dielectric layers 111 is not used by using a scanning electron microscope (SEM: Scanning Electron Microscope). May be integrated so as not to be confirmed.

該セラミック本体110の形状は特に制限されず、例えば、六面体状であってもよい。   The shape of the ceramic body 110 is not particularly limited, and may be a hexahedral shape, for example.

本発明の実施形態を明確に説明するためにセラミック本体110の六面体の方向を定義すると、図面上に示されたL、W及びTは、それぞれ長さ方向、幅方向及び厚さ方向である。   In order to clearly describe the embodiment of the present invention, the hexahedral direction of the ceramic body 110 is defined. L, W, and T shown in the drawing are a length direction, a width direction, and a thickness direction, respectively.

また、本実施形態では、説明の便宜のために、セラミック本体110の対向する厚さ方向の面を第1及び第2主面、第1及び第2主面を連結し対向する長さ方向の面を第1及び第2端面、対向する幅方向の面を第1及び第2側面と定義する。   Further, in the present embodiment, for convenience of explanation, the opposing surfaces in the thickness direction of the ceramic body 110 are connected to the first and second main surfaces, and the first and second main surfaces are connected in the opposing length direction. Surfaces are defined as first and second end surfaces, and opposing width-direction surfaces are defined as first and second side surfaces.

セラミック本体110は、高容量を具現するために誘電体層111の積層数を増加させた形態であって、幅をW、厚さをTと規定するとき、T/W>1.0を満たし、セラミック本体110の幅より厚さが大きく形成される。   The ceramic body 110 has a configuration in which the number of stacked dielectric layers 111 is increased in order to realize a high capacity. When the width is defined as W and the thickness is defined as T, T / W> 1.0 is satisfied. The thickness is larger than the width of the ceramic body 110.

誘電体層111は高い誘電率のセラミック材料を含むことができ、例えば、チタン酸バリウム(BaTiO)系セラミック粉末などを含んでもよく、十分な静電容量が得られるものであればよい。 The dielectric layer 111 can include a ceramic material having a high dielectric constant. For example, the dielectric layer 111 may include a barium titanate (BaTiO 3 ) -based ceramic powder or the like as long as a sufficient capacitance can be obtained.

また、誘電体層111には、上記セラミック粉末と共に、必要に応じて、遷移金属酸化物または炭化物、希土類元素、マグネシウム(Mg)またはアルミニウム(Al)などのような多様な種類のセラミック添加剤、有機溶剤、可塑剤、結合剤及び分散剤などがさらに添加されてもよい。   In addition to the ceramic powder, the dielectric layer 111 may include various types of ceramic additives such as transition metal oxides or carbides, rare earth elements, magnesium (Mg), aluminum (Al), and the like, if necessary. Organic solvents, plasticizers, binders, dispersants and the like may be further added.

第1及び第2内部電極121、122は異なる極性を有する電極であって、誘電体層111を形成するセラミックシートを介して対向配置され、セラミック本体110内でセラミック本体110の第1及び第2端面を通じてそれぞれ露出するように形成されてもよい。   The first and second internal electrodes 121 and 122 are electrodes having different polarities, and are arranged to face each other through a ceramic sheet forming the dielectric layer 111, and the first and second of the ceramic body 110 are within the ceramic body 110. You may form so that it may each expose through an end surface.

このとき、第1及び第2内部電極121、122は、中間に配置された誘電体層111により互いに電気的に絶縁されてもよい。   At this time, the first and second internal electrodes 121 and 122 may be electrically insulated from each other by the dielectric layer 111 disposed in the middle.

また、第1及び第2内部電極121、122は導電性金属で形成され、例えば、銀(Ag)、パラジウム(Pd)、白金(Pt)、ニッケル(Ni)及び銅(Cu)のうち一つまたはこれらの合金などからなるものを用いてもよいが、本発明はこれに限定されない。   In addition, the first and second internal electrodes 121 and 122 are formed of a conductive metal, for example, one of silver (Ag), palladium (Pd), platinum (Pt), nickel (Ni), and copper (Cu). Alternatively, an alloy made of these alloys may be used, but the present invention is not limited to this.

第1及び第2外部電極131、132は、セラミック本体110の第1及び第2端面に形成された第1及び第2頭部131a、132aと、第1及び第2頭部131a、132aとそれぞれ連結され、セラミック本体110の第1及び第2主面に幅方向に相互離隔されて形成された2個の第1及び第2バンド部131b、132bと、を含む。   The first and second external electrodes 131 and 132 are respectively formed with first and second heads 131a and 132a formed on the first and second end surfaces of the ceramic body 110, and first and second heads 131a and 132a, respectively. And two first and second band portions 131b and 132b that are connected to each other and are spaced apart from each other in the width direction on the first and second main surfaces of the ceramic body 110.

第1及び第2頭部131a、132aは、第1及び第2端面を通じて交互に露出した複数の第1及び第2内部電極121、122と電気的に連結される。第1及び第2バンド部131b、132bは、印刷回路基板などに実装する際に実装部となる。   The first and second heads 131a and 132a are electrically connected to the plurality of first and second internal electrodes 121 and 122 that are alternately exposed through the first and second end faces. The first and second band portions 131b and 132b become mounting portions when mounted on a printed circuit board or the like.

このとき、第1及び第2外部電極131、132は、耐湿性の向上のため、セラミック本体110の第1及び第2側面に第1及び第2頭部131a、132a及び第1及び第2バンド部131b、132bと連結されるように形成される第1及び第2側面連結部131c、132cを含んでもよい。   At this time, the first and second external electrodes 131 and 132 are provided on the first and second side surfaces of the ceramic body 110 to improve moisture resistance, and the first and second heads 131a and 132a and the first and second bands. The first and second side surface connection parts 131c and 132c may be included so as to be connected to the parts 131b and 132b.

また、第1及び第2外部電極131、132は導電性金属で形成され、例えば、銀(Ag)、ニッケル(Ni)及び銅(Cu)などで形成されてもよい。このような第1及び第2外部電極131、132は、上記導電性金属粉末にガラスフリットを添加して用意した導電性ペーストを塗布した後に焼成して形成してもよいが、本発明はこれに限定されない。   The first and second external electrodes 131 and 132 are made of a conductive metal, and may be made of, for example, silver (Ag), nickel (Ni), copper (Cu), or the like. The first and second external electrodes 131 and 132 may be formed by applying a conductive paste prepared by adding glass frit to the conductive metal powder, followed by baking. It is not limited to.

一方、第1及び第2バンド部131b、132b上には、必要に応じて、第1及び第2めっき層(不図示)が形成されてもよい。   Meanwhile, first and second plating layers (not shown) may be formed on the first and second band portions 131b and 132b as necessary.

上記第1及び第2めっき層は、積層セラミックキャパシタ100を印刷回路基板に半田付けにより実装する際、相互間の接着強度を上げるためのものである。   The first and second plating layers are for increasing the adhesive strength between the multilayer ceramic capacitor 100 when it is mounted on the printed circuit board by soldering.

上記第1及び第2めっき層は、例えば、第1及び第2バンド部131b、132b上に形成されたニッケル(Ni)めっき層と、上記ニッケルめっき層上に形成されたすず(Sn)めっき層を含んでもよく、本発明はこれに限定されない。   The first and second plating layers include, for example, a nickel (Ni) plating layer formed on the first and second band portions 131b and 132b, and a tin (Sn) plating layer formed on the nickel plating layer. The present invention is not limited to this.

図2は図1のA−A'線の断面図であり、本発明の一実施形態による積層セラミックキャパシタの厚さ−幅断面を示したものである。   FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. 1 and shows a thickness-width cross section of the multilayer ceramic capacitor according to the embodiment of the present invention.

図2を参照すると、セラミック本体110の幅をW、外部電極のバンド部131b、132bの幅をaと規定するとき、0.10≦a/W≦0.45を満たすことができる。   Referring to FIG. 2, when the width of the ceramic body 110 is defined as W and the width of the band portions 131b and 132b of the external electrode is defined as a, 0.10 ≦ a / W ≦ 0.45 can be satisfied.

Figure 2015037175
Figure 2015037175

上記表1は、a/W値による実装時のチップ倒れ有無、及び信頼性不良有無を実験し、その結果を示したものである。   Table 1 above shows the results of experiments on the presence or absence of chip collapse and the presence or absence of reliability failure during mounting based on the a / W value.

上記表1を参照すると、a/Wが0.05であるサンプル1は、実装時に50個のチップのうち3個が倒れ、信頼性不良の実験では、200個のうち2個で不良が発見された。   Referring to Table 1 above, sample 1 with an a / W of 0.05 collapses 3 out of 50 chips when mounted, and in an experiment with poor reliability, 2 out of 200 chips found defects It was done.

また、a/Wが0.50であるサンプル10は、実装時に50個のチップのうち4個が倒れ、信頼性不良の実験では、200個のうち1個で不良が発見された。   Further, in the sample 10 in which a / W is 0.50, four of the 50 chips collapsed during mounting, and in the reliability failure experiment, one of the 200 chips was found defective.

一方、a/Wが本発明の範囲内であるサンプル2〜9は、実装時にチップ倒れ及び信頼性不良が発見されなかった。   On the other hand, in Samples 2 to 9 in which a / W is within the scope of the present invention, chip collapse and poor reliability were not found during mounting.

また、バンド部131b、132bの厚さをSと規定するとき、2≦S≦40μmの範囲を満たすことができる。   Further, when the thickness of the band portions 131b and 132b is defined as S, the range of 2 ≦ S ≦ 40 μm can be satisfied.

Figure 2015037175
Figure 2015037175

上記表2は、S値による実装時のチップ倒れ有無、及び基準容量を満たすか否かを実験し、その結果を示したものである。   Table 2 above shows the results of experiments on whether or not the chip collapses during mounting based on the S value and whether or not the reference capacity is satisfied.

上記表2を参照すると、Sが1μmであるサンプル1は、実装時に50個のチップのうち5個が倒れ、Sが40μmを超えるサンプル8及び9は、基準容量を満たさないことが分かる。特に、サンプル9は、基準容量を満たさないだけでなく、実装時に50個のうち3個が倒れた。   Referring to Table 2 above, it can be seen that Sample 1 with S of 1 μm collapses five of the 50 chips when mounted, and Samples 8 and 9 with S over 40 μm do not satisfy the reference capacity. In particular, not only the sample 9 did not satisfy the reference capacity, but also 3 of the 50 collapsed during mounting.

変形例
図3は本発明の他の実施形態による積層セラミックキャパシタの一部を切開して概略的に示した斜視図である。
Modification FIG. 3 is a perspective view schematically showing a multilayer ceramic capacitor in accordance with another embodiment of the present invention.

ここで、第1及び第2外部電極131、132が形成された構造は、上述の実施形態と同一であるため、重複を避けるためにその具体的な説明を省略し、上述した実施形態と異なる構造を有する第1及び第2内部電極121'、122'について具体的に説明する。   Here, since the structure in which the first and second external electrodes 131 and 132 are formed is the same as that in the above-described embodiment, a specific description thereof is omitted to avoid duplication and is different from the above-described embodiment. The first and second internal electrodes 121 ′ and 122 ′ having a structure will be specifically described.

図3を参照すると、本発明の他の実施形態による積層セラミックキャパシタ100'は、複数の誘電体層111が幅方向に積層されたセラミック本体110を含む。   Referring to FIG. 3, a multilayer ceramic capacitor 100 ′ according to another embodiment of the present invention includes a ceramic body 110 in which a plurality of dielectric layers 111 are stacked in the width direction.

従って、第1及び第2内部電極121'、122'は、誘電体層111を形成するセラミックシートを介して対向するように幅方向に配置され、セラミック本体110内でセラミック本体110の第1及び第2端面を通じてそれぞれ露出するように形成されてもよい。このとき、第1及び第2内部電極121'、122'は、中間に配置された誘電体層111により互いに電気的に絶縁されてもよい。   Accordingly, the first and second internal electrodes 121 ′ and 122 ′ are arranged in the width direction so as to face each other with the ceramic sheet forming the dielectric layer 111 therebetween. It may be formed so as to be exposed through the second end face. At this time, the first and second internal electrodes 121 ′ and 122 ′ may be electrically insulated from each other by the dielectric layer 111 disposed in the middle.

図4は図3のB−B'線の断面図であり、本発明の他の実施形態による積層セラミックキャパシタの厚さ−幅断面を示したものである。   FIG. 4 is a cross-sectional view taken along the line BB ′ of FIG. 3 and shows a thickness-width cross section of a multilayer ceramic capacitor according to another embodiment of the present invention.

図4を参照すると、セラミック本体110の幅をW、外部電極のバンド部131b、132bの幅をaと規定するとき、0.10≦a/W≦0.45を満たすことができる。   Referring to FIG. 4, when the width of the ceramic body 110 is defined as W and the width of the band portions 131b and 132b of the external electrode is defined as a, 0.10 ≦ a / W ≦ 0.45 can be satisfied.

また、バンド部131b、132bの厚さをSと規定するとき、2≦S≦40μmの範囲を満たすことができる。   Further, when the thickness of the band portions 131b and 132b is defined as S, the range of 2 ≦ S ≦ 40 μm can be satisfied.

積層セラミックキャパシタの製造方法
以下では、本発明の一実施形態による積層セラミックキャパシタの製造方法について説明する。
Method for Manufacturing Multilayer Ceramic Capacitor Hereinafter, a method for manufacturing a multilayer ceramic capacitor according to an embodiment of the present invention will be described.

先ず、複数のセラミックシートを用意する。上記セラミックシートはセラミック本体110の誘電体層111を形成するためのもので、セラミック粉末、ポリマー及び溶剤などを混合してスラリーを製造し、上記スラリーをドクターブレードなどの工法でキャリアフィルム上に塗布及び乾燥して数μm厚さのシート状に製作する。   First, a plurality of ceramic sheets are prepared. The ceramic sheet is used to form the dielectric layer 111 of the ceramic body 110. A ceramic powder, a polymer and a solvent are mixed to produce a slurry, and the slurry is applied onto a carrier film by a method such as a doctor blade. And it dries and manufactures in the sheet form of thickness of several micrometers.

次に、上記セラミックシートの少なくとも一面に、導電性ペーストを長さ方向に一定の間隔、且つ所定の厚さに印刷して第1及び第2内部電極121、122パターンを形成する。   Next, the first and second internal electrodes 121 and 122 are formed on at least one surface of the ceramic sheet by printing a conductive paste at a predetermined interval and a predetermined thickness in the length direction.

上記内部電極パターンを形成するための導電性ペーストの印刷方法としては、スクリーン印刷法またはグラビア印刷法などを用いてもよく、本発明はこれに限定されない。   As a printing method of the conductive paste for forming the internal electrode pattern, a screen printing method or a gravure printing method may be used, and the present invention is not limited to this.

次に、上記内部電極パターンが形成された複数のセラミックシートを積層し積層方向から加圧して積層体を設ける。このとき、上記積層体は、実装される面を基準として、上記内部電極パターンが厚さ方向に積層されるようにするか、それとも幅方向に積層されるようにすることができる。   Next, a plurality of ceramic sheets on which the internal electrode patterns are formed are stacked and pressed from the stacking direction to provide a stack. At this time, the stacked body may be configured such that the internal electrode patterns are stacked in the thickness direction or stacked in the width direction with reference to the mounting surface.

次に、上記積層体を0603(長さ×幅)規格で、1個のキャパシタに対応する領域ごとに切断して、厚さ/幅が1.0を超え、対向する厚さ方向の第1及び第2主面、第1及び第2内部電極121、122が交互に露出する長さ方向の第1及び第2端面、及び幅方向の第1及び第2側面を有するチップを作る。それから、1050〜1200℃の高温で焼成した後に研磨してセラミック本体110を設ける。   Next, the laminate is cut into regions corresponding to one capacitor in accordance with 0603 (length × width) standard, and the thickness / width exceeds 1.0, and the first in the opposing thickness direction is cut. Then, a chip having first and second end surfaces in the length direction and first and second side surfaces in the width direction in which the first and second inner electrodes 121 and 122 are alternately exposed is formed. Then, after firing at a high temperature of 1050 to 1200 ° C., the ceramic body 110 is provided by polishing.

次に、セラミック本体110の第1及び第2端面に、第1及び第2内部電極121、122の露出した部分とそれぞれ電気的に連結されるように第1及び第2外部電極131、132を形成する。   Next, the first and second external electrodes 131 and 132 are electrically connected to the exposed portions of the first and second internal electrodes 121 and 122 on the first and second end surfaces of the ceramic body 110, respectively. Form.

このとき、第1及び第2外部電極131、132は、セラミック本体110の厚さ−幅断面において、上記第1及び第2主面と上記第1及び第2側面が接する両角部に導電性ペーストを塗布して上記第1及び第2端面に頭部131a、132aを形成し、上記第1及び第2主面に相互離隔されるように2個のバンド部131b、132bを形成する。   At this time, the first and second external electrodes 131 and 132 are electrically conductive paste at both corners where the first and second main surfaces and the first and second side surfaces are in contact with each other in the thickness-width section of the ceramic body 110. To form head portions 131a and 132a on the first and second end surfaces, and to form two band portions 131b and 132b so as to be spaced apart from each other on the first and second main surfaces.

また、必要に応じて、第1及び第2外部電極131、132を形成する段階後に、第1及び第2バンド部131b、132bの表面を電気めっきなどの方法でめっき処理して第1及び第2めっき層(不図示)を形成することができる。   In addition, if necessary, after the step of forming the first and second external electrodes 131 and 132, the surfaces of the first and second band portions 131b and 132b are plated by a method such as electroplating to form the first and first external electrodes 131 and 132. Two plating layers (not shown) can be formed.

このとき、セラミック本体110の幅をW、外部電極のバンド部131b、132bの幅をaと規定するとき、0.10≦a/W≦0.45を満たすようにすることができる。   At this time, when the width of the ceramic body 110 is defined as W and the width of the band portions 131b and 132b of the external electrode is defined as a, 0.10 ≦ a / W ≦ 0.45 can be satisfied.

積層セラミックキャパシタの実装基板
図5は、本発明の一実施形態による積層セラミックキャパシタが印刷回路基板に実装された様子を積層セラミックキャパシタの一部を切開して概略的に示した斜視図である。
FIG. 5 is a perspective view schematically showing a state in which a multilayer ceramic capacitor according to an embodiment of the present invention is mounted on a printed circuit board by partially cutting the multilayer ceramic capacitor.

図5を参照すると、本実施形態による積層セラミックキャパシタ100の実装基板200は、積層セラミックキャパシタ100が水平または垂直に実装される印刷回路基板210と、印刷回路基板210の上面に相互離隔されて形成された第1及び第2電極パッド221、222と、を含む。   Referring to FIG. 5, the mounting substrate 200 of the multilayer ceramic capacitor 100 according to the present embodiment is formed on the upper surface of the printed circuit board 210 and the printed circuit board 210 on which the multilayer ceramic capacitor 100 is mounted horizontally or vertically. First and second electrode pads 221 and 222.

このとき、積層セラミックキャパシタ100は、第1及び第2外部電極131、132の第1及び第2バンド部131b、132bがそれぞれ第1及び第2電極パッド221、222上に接触されるように位置した状態で半田付け230により印刷回路基板210と電気的に連結されてもよい。   At this time, the multilayer ceramic capacitor 100 is positioned such that the first and second band portions 131b and 132b of the first and second external electrodes 131 and 132 are in contact with the first and second electrode pads 221 and 222, respectively. In this state, the printed circuit board 210 may be electrically connected by soldering 230.

以上、本発明の実施形態について詳細に説明したが、本発明の権利範囲はこれに限定されず、特許請求の範囲に記載された本発明の技術的思想から外れない範囲内で多様な修正及び変形が可能であるということは、当技術分野の通常の知識を有する者には明らかである。   Although the embodiment of the present invention has been described in detail above, the scope of the right of the present invention is not limited to this, and various modifications and modifications can be made without departing from the technical idea of the present invention described in the claims. It will be apparent to those skilled in the art that variations are possible.

100、100' 積層セラミックキャパシタ
110 セラミック本体
111 誘電体層
121、121'、122、122' 第1及び第2内部電極
131、132 第1及び第2外部電極
131a、132a 第1及び第2頭部
131b、132b 第1及び第2バンド部
131c、132c 第1及び第2側面連結部
100, 100 'Multilayer ceramic capacitor 110 Ceramic body 111 Dielectric layers 121, 121', 122, 122 'First and second internal electrodes 131, 132 First and second external electrodes 131a, 132a First and second heads 131b, 132b first and second band portions 131c, 132c first and second side surface connecting portions

Claims (14)

厚さ方向に積層された複数の誘電体層を含み、幅をW、厚さをTと規定するとき、T/W>1.0を満たすセラミック本体と、
前記セラミック本体内で前記誘電体層を介して対向配置され、前記セラミック本体の両端面に交互に露出した複数の第1及び第2内部電極と、
前記セラミック本体の両端面に形成された頭部、及び前記頭部と連結され、前記セラミック本体の上下主面に幅方向に相互離隔されて形成された2個のバンド部を含み、前記第1及び第2内部電極とそれぞれ電気的に連結された第1及び第2外部電極と、
を含む積層セラミック電子部品。
A ceramic body that includes a plurality of dielectric layers stacked in the thickness direction and satisfies T / W> 1.0 when the width is defined as W and the thickness is defined as T;
A plurality of first and second internal electrodes disposed opposite to each other through the dielectric layer in the ceramic body, and alternately exposed at both end faces of the ceramic body;
A head portion formed on both end surfaces of the ceramic body; and two band portions connected to the head portion and formed on the upper and lower main surfaces of the ceramic body so as to be spaced apart from each other in the width direction. And first and second external electrodes electrically connected to the second internal electrode, respectively.
Including multilayer ceramic electronic components.
前記セラミック本体の幅をW、前記バンド部の幅をaと規定するとき、0.10≦a/W≦0.45を満たすことを特徴とする、請求項1に記載の積層セラミック電子部品。   2. The multilayer ceramic electronic component according to claim 1, wherein 0.10 ≦ a / W ≦ 0.45 is satisfied when the width of the ceramic body is defined as W and the width of the band portion is defined as a. 前記バンド部の厚さをSと規定するとき、2≦S≦40μmを満たすことを特徴とする、請求項1または2に記載の積層セラミック電子部品。   The multilayer ceramic electronic component according to claim 1, wherein when the thickness of the band portion is defined as S, 2 ≦ S ≦ 40 μm is satisfied. 幅方向に積層された複数の誘電体層を含み、幅をW、厚さをTと規定するとき、T/W>1.0を満たすセラミック本体と、
前記セラミック本体内で前記誘電体層を介して対向配置され、前記セラミック本体の両端面に交互に露出した複数の第1及び第2内部電極と、
前記セラミック本体の両端面に形成された頭部、及び前記頭部と連結され、前記セラミック本体の上下の主面に幅方向に相互離隔されて形成された2個のバンド部を含み、前記第1及び第2内部電極とそれぞれ電気的に連結された第1及び第2外部電極と、
を含む積層セラミック電子部品。
A ceramic body that includes a plurality of dielectric layers stacked in the width direction and satisfies T / W> 1.0 when the width is defined as W and the thickness is defined as T;
A plurality of first and second internal electrodes disposed opposite to each other through the dielectric layer in the ceramic body, and alternately exposed at both end faces of the ceramic body;
A head portion formed on both end surfaces of the ceramic body, and two band portions connected to the head portion and formed on the upper and lower main surfaces of the ceramic body so as to be spaced apart from each other in the width direction; First and second external electrodes electrically connected to the first and second internal electrodes, respectively;
Including multilayer ceramic electronic components.
前記セラミック本体の幅をW、前記バンド部の幅をaと規定するとき、0.10≦a/W≦0.45を満たすことを特徴とする、請求項4に記載の積層セラミック電子部品。   5. The multilayer ceramic electronic component according to claim 4, wherein 0.10 ≦ a / W ≦ 0.45 is satisfied when the width of the ceramic body is defined as W and the width of the band portion is defined as a. 前記バンド部の厚さをSと規定するとき、2≦S≦40μmを満たすことを特徴とする、請求項4または5に記載の積層セラミック電子部品。   The multilayer ceramic electronic component according to claim 4, wherein when the thickness of the band portion is defined as S, 2 ≦ S ≦ 40 μm is satisfied. 上部に第1及び第2電極パッドを有する印刷回路基板と、
前記第1及び第2電極パッド上に設けられた請求項1から6の何れか一項に記載の積層セラミック電子部品と、を含む積層セラミック電子部品の実装基板。
A printed circuit board having first and second electrode pads on top;
A multilayer ceramic electronic component mounting board comprising: the multilayer ceramic electronic component according to any one of claims 1 to 6 provided on the first and second electrode pads.
第1及び第2内部電極が形成された複数のセラミックシートを前記セラミックシートを介して前記第1及び第2内部電極が対向配置されるように積層し加圧して積層体を形成する段階と、
前記積層体を1個のキャパシタに対応する領域ごとに切断して焼成し、対向する厚さ方向の第1及び第2主面と、前記第1及び第2内部電極が交互に露出する長さ方向の第1及び第2端面と、幅方向の第1及び第2側面とを有するセラミック本体を形成する段階と、
前記セラミック本体に前記第1及び第2内部電極と電気的に連結されるように第1及び第2外部電極を形成する段階と、を含み、
前記第1及び第2外部電極を形成する段階は、前記セラミック本体の厚さ−幅断面において、前記第1及び第2主面と前記第1及び第2側面が接する両端部に導電性ペーストをそれぞれ塗布して前記第1及び第2端面に頭部を形成し、前記第1及び第2主面に幅方向に相互離隔されるように2個のバンド部を形成する積層セラミック電子部品の製造方法。
Laminating a plurality of ceramic sheets on which the first and second internal electrodes are formed so that the first and second internal electrodes are opposed to each other through the ceramic sheet, and pressing to form a laminate;
The multilayer body is cut and fired for each region corresponding to one capacitor, and the first and second main surfaces in the thickness direction facing each other and the lengths at which the first and second internal electrodes are alternately exposed. Forming a ceramic body having first and second end faces in the direction and first and second side faces in the width direction;
Forming first and second external electrodes on the ceramic body so as to be electrically connected to the first and second internal electrodes;
In the step of forming the first and second external electrodes, in the thickness-width section of the ceramic body, a conductive paste is applied to both end portions where the first and second main surfaces are in contact with the first and second side surfaces. Manufacturing a multilayer ceramic electronic component in which a head is formed on each of the first and second end surfaces by coating and two band portions are formed on the first and second main surfaces so as to be spaced apart from each other in the width direction. Method.
前記積層体を設ける段階は、前記セラミックシートを厚さ方向に積層することを特徴とする、請求項8に記載の積層セラミック電子部品の製造方法。   The method of manufacturing a multilayer ceramic electronic component according to claim 8, wherein the step of providing the multilayer body includes laminating the ceramic sheets in a thickness direction. 前記セラミック本体の幅をW、前記バンド部の幅をaと規定するとき、0.10≦a/W≦0.45を満たすことを特徴とする、請求項9に記載の積層セラミック電子部品の製造方法。   10. The multilayer ceramic electronic component of claim 9, wherein when the width of the ceramic body is defined as W and the width of the band portion is defined as a, 0.10 ≦ a / W ≦ 0.45 is satisfied. Production method. 前記バンド部の厚さをSと規定するとき、2≦S≦40μmを満たすことを特徴とする、請求項9または10に記載の積層セラミック電子部品の製造方法。   11. The method for manufacturing a multilayer ceramic electronic component according to claim 9, wherein when the thickness of the band portion is defined as S, 2 ≦ S ≦ 40 μm is satisfied. 前記積層体を設ける段階は、前記セラミックシートを幅方向に積層することを特徴とする、請求項8に記載の積層セラミック電子部品の製造方法。   The method of manufacturing a multilayer ceramic electronic component according to claim 8, wherein the step of providing the multilayer body includes laminating the ceramic sheets in a width direction. 前記セラミック本体の幅をW、前記バンド部の幅をaと規定するとき、0.10≦a/W≦0.45を満たすことを特徴とする、請求項12に記載の積層セラミック電子部品の製造方法。   13. The multilayer ceramic electronic component of claim 12, wherein 0.10 ≦ a / W ≦ 0.45 is satisfied when the width of the ceramic body is defined as W and the width of the band portion is defined as a. Production method. 前記バンド部の厚さをSと規定するとき、2≦S≦40μmを満たすことを特徴とする、請求項12または13に記載の積層セラミック電子部品の製造方法。   14. The method of manufacturing a multilayer ceramic electronic component according to claim 12, wherein when the thickness of the band portion is defined as S, 2 ≦ S ≦ 40 μm is satisfied.
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