JP2015032015A - Processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of connection terminals to be connected to a plurality of memories in the case of executing the reading or writing of data to those memories.SOLUTION: In an image forming apparatus, clock terminals L1 to L3 of a serial ROM control part 42 are connected to clock terminals L1 to L3 of serial ROM 32A to 32C for each serial ROM 32, and data terminals D1 to D4 of the serial ROM 32A to 32C are commonly connected to the corresponding data terminals D1 to D4 of the serial ROM control part 42. Thus, when transmitting an instruction received from a CPU via the data terminals D1 to D4, the serial ROM control part 42 transmits a clock signal via a clock terminal L only to the serial ROM 32 corresponding to the instruction, and allows the serial ROM 32 corresponding to the instruction to receive the instruction.

Description

  The invention disclosed in this specification relates to a processing device that performs reading or writing of data with respect to a plurality of memories.

  2. Description of the Related Art Conventionally, an interface circuit that is connected between a CPU and a memory and executes data reading or writing in a memory in a serial format according to a command from the CPU has been used (for example, Patent Document 1). ). In this circuit, for example, when data is read from the memory, the read command and the read address are transmitted to the memory in accordance with a command from the CPU, and after these are transmitted, the read data at the read address is transmitted from the memory. read out. In addition, when writing data to the memory, in response to a command from the CPU, the write command, the write address, and the write data are transmitted to the memory in the order, and the write data is stored in the memory at the write address. Write. Therefore, in the serial format, an interface circuit that is required for connection to the memory as compared with the parallel format in which the read command and the read address are transmitted simultaneously or the write command, the write address, and the write data are transmitted simultaneously. The number of terminals can be reduced.

JP 2010-92342 A

  In a processing circuit such as an interface circuit, one processing circuit is connected to a plurality of memories, and data reading or writing may be performed on the plurality of memories. In this case, if each memory is connected to the processing circuit separately, the number of terminals of the processing circuit increases, which increases the manufacturing cost. Therefore, there is a demand for a technique for reducing the number of connection terminals in a processing circuit connected to a plurality of memories.

  The invention disclosed in this specification is to disclose a technique for reducing the number of connection terminals connected to a plurality of memories when data is read or written.

  The processing device disclosed in this specification includes a control unit including a CPU and a memory control unit, and a plurality of memories, and the memory control units are connected to at least the same number of control unit side connections as the memories. A plurality of control side I / O terminals, and each memory has a memory side connection terminal and a plurality of memory side I / Os corresponding to each of the plurality of control side I / O terminals. The control unit side connection terminal and the memory side connection terminal are connected for each memory, and a plurality of the memory side input / output terminals corresponding to the respective control unit side input / output terminals The memory control unit outputs a command received from the CPU to all the memories and receives from the CPU via the control unit side input / output terminal. From the instruction, the plurality of memories That is, it determines information indicating which memory is designated, and transmits a signal via the control unit side connection terminal corresponding to the memory, and the memory transmits the signal to the memory side control unit terminal included in the memory. When the signal is received, the command input via the memory side input / output terminal is validated.

  In this processing apparatus, since a plurality of memory side input / output terminals corresponding to each control unit side input / output terminal are connected in common to the control unit side input / output terminal, the memory side input / output terminal and the control unit side input / output terminal are connected. The number of control unit side input / output terminals can be reduced compared to the case where the terminals are connected to each memory. In this case, the command received from the CPU is transmitted to all memories by the memory control unit via the control unit side input / output terminal, but the memory control unit transmits the command received from the CPU, A signal is output to the memory designated by the instruction via the control unit side connection terminal connected to each memory. In each memory, an instruction is validated only when a signal is received, so that the instruction can be validated only in a memory designated by the instruction, and data is read or written. be able to.

  In the processing device, the control unit side connection terminals are at least as many control unit side clock terminals as the memory that transmits a clock signal, and the memory side connection terminals are a memory side clock terminal that receives the clock signal. And the control unit side clock terminal and the memory side clock terminal are connected in a one-to-one correspondence for each memory, and the memory control unit receives, from the instructions received from the CPU, the plurality of memories, Information on which memory is designated is determined, and the clock signal is transmitted via the control unit side clock terminal corresponding to the memory, and the memory is connected to the memory side clock terminal of the memory. When the clock signal is received, the command input via the memory side input / output terminal may be validated.

  According to this processing apparatus, information indicating which memory is designated using a clock signal is shown. A control unit side clock terminal for outputting a clock signal is conventionally provided in the memory control unit for the operation of the memory. Therefore, since a special signal for indicating information indicating which memory is specified is used, and a clock signal that has been conventionally provided is used, compared to a case where a special terminal for outputting the signal is provided. It is possible to suppress an increase in the number of control unit side input / output terminals.

  In the above processing device, the memory control unit further includes a control unit side clock terminal that transmits a clock signal, and each of the memories further includes a memory side clock terminal that receives the clock signal, The connection side connection terminals are at least the same number of control unit side select terminals that transmit a select signal, and the memory side connection terminals are memory side select terminals that receive the select signal, and a plurality of the memory side terminals A clock terminal is commonly connected to the control unit side clock terminal, the control unit side select terminal and the memory side select terminal are connected in a one-to-one correspondence for each memory, and the memory control unit further includes: The clock signal is transmitted to all the memories via the control unit side clock terminal, and the plurality of instructions are received from the instruction received from the CPU. It is determined which memory of the memory is designated, and the select signal is transmitted via the control unit side select terminal corresponding to the memory, and the memory has the memory side When the select signal is received at the select terminal, the command input via the memory side input / output terminal may be validated.

  According to this processing apparatus, information indicating which memory is designated using the select signal is shown. A control unit side select terminal for outputting a select signal is conventionally provided in a memory control unit for selecting a memory. For this reason, a special signal for indicating information indicating which memory is designated is used, and a conventional select signal is used as compared with the case where a special terminal for outputting the signal is provided. It is possible to suppress an increase in the number of control unit side input / output terminals.

  In the above processing device, the CPU transmits a read command including a read command and a read address or a write command including a write command, a write address, and write data to the memory control unit, and Prior to receiving the command from the CPU, the memory control unit transmits either the read command or the write command to all the memories via the control unit side input / output terminal, When the command from the CPU is received, if the command included in the command from the CPU matches the command transmitted in advance, the command excluding the command via the control unit side input / output terminal May be transmitted to all the memories.

  According to this processing device, when reading data from the memory or writing data to the memory, a command of either a read command or a write command that is conventionally transmitted after waiting for a command from the CPU, Prior to receiving a command from the CPU, it is sent to all memories. Therefore, if a read command is received from the CPU after sending a read command, or if a write command is received from the CPU after sending a write command, the read time or write time is shortened. can do.

  In the above processing device, when the memory control unit receives a command from the CPU, and the command included in the command from the CPU does not match the command transmitted in advance, the memory control unit inputs A configuration may be adopted in which a command from the CPU is transmitted to all the memories via an output terminal.

  According to this processing apparatus, when a command including a command different from the command is received from the CPU after transmitting either the read command or the write command prior to receiving the command from the CPU, All the instructions from the CPU including different commands are transmitted to all memories. Therefore, data can be read or written according to a command from the CPU.

  In the above processing device, prior to receiving the command from the CPU, the memory control unit transmits the read command to all the memories via the control unit side input / output terminal, When the command from the CPU is received when the command from the CPU is received, the read command below the read command is sent to all the memories via the control unit side input / output terminal. When the command from the CPU is the write command, the write command from the CPU is transmitted to all the memories via the control unit side input / output terminal. Also good.

  According to this processing apparatus, when a read command is received from the CPU, the read time can be shortened. When a write command is received from the CPU, data can be written according to the write command by transmitting a write command including the write command to all the memories.

  According to the processing device disclosed in this specification, when data reading or writing is performed on a plurality of memories, the number of connection terminals connected to the memories can be reduced.

Schematic block diagram of image forming apparatus Connection diagram of serial ROM control unit and serial ROM of embodiment 1 The figure which shows the storage capacity of serial ROM32A typically The flowchart which shows the control processing of Embodiment 1. The flowchart which shows the control processing of Embodiment 1. Time chart in control processing of embodiment 1 Time chart in control processing of embodiment 1 Connection diagram between serial ROM control unit and serial ROM of embodiment 2 The flowchart which shows the control processing of Embodiment 2. The flowchart which shows the control processing of Embodiment 2. Time chart in control processing of embodiment 2

<Embodiment 1>
The first embodiment will be described with reference to FIGS.

1. Configuration of Image Forming Apparatus As shown in FIG. 1, the image forming apparatus 10 includes an ASIC (Application Specific Integrated Circuit) 30 that controls each part of the image forming apparatus 10 and a plurality of serial ROMs 32 </ b> A to 32 provided outside the ASIC 30. 32C, DRAM 34, recording unit 36, operation unit 38, and display unit 39. The image forming apparatus 10 is an example of a processing apparatus. The ASIC 30 is an example of a control unit, and the serial ROMs 32A to 32C are examples of a plurality of memories.

  Data such as various control programs for controlling the operation of the image forming apparatus 10 is stored in the serial ROM 32A. A central processing unit (hereinafter referred to as CPU) 40 of the ASIC 30 to be described later is configured according to the control program. Take control. When controlling the image forming apparatus 10, the CPU 40 copies the control program stored in the serial ROM 32 </ b> A to the DRAM 34 having a higher communication speed than the serial ROMs 32 </ b> A to 32 </ b> C, and performs control according to the control program read from the DRAM 34. Further, the DRAM 34 temporarily stores data such as image data input from the outside of the image forming apparatus 10 such as the PC 20 via an external USB interface (hereinafter referred to as I / F). The recording unit 36 forms an image on a print target such as paper using the image data stored in the DRAM 34.

  The serial ROM 32B stores data used for transmission / reception with an external communication system via the telephone line 58. The serial ROM 32C stores data used for display on the display unit 39 and data input by the user via the operation unit 38. The display unit 39 includes a liquid crystal display or the like, and displays the status of the image forming apparatus 10 using image data stored in the serial ROM 32C. The operation unit 38 includes various setting buttons, receives various instructions from the user, and stores data input along with the instructions in the serial ROM 32C.

  The ASIC 30 includes a CPU 40, a serial ROM control unit 42, a RAM control unit 44, a recording control unit 46, a display control unit 48, a USB control unit 50, and a FAX control unit 52. Connected through. The serial ROM control unit 42 is an example of a memory control unit.

  The CPU 40 performs various processes for controlling the image forming apparatus 10 such as transmitting a read command having a read command to the serial ROM control unit 42 and transmitting a write command having a write command to the serial ROM control unit 42. Do. The RAM control unit 44 is connected to the DRAM 34, and writes data to the DRAM 34 and reads data from the DRAM 34 in accordance with a command from the CPU 40. The recording control unit 46 is connected to the recording unit 36, and transmits image data read from the DRAM 34 to the recording unit 36 in accordance with a command from the CPU 40, and causes the recording unit 36 to form an image.

  The display control unit 48 is connected to the display unit 39 and transmits data read from the serial ROM 32C to the display unit 39 in response to a command from the CPU 40 to display the display unit 39. The USB control unit 50 is connected to an external device such as the PC 20 via the USB cable 56, and transmits and receives data to and from the external device in accordance with commands from the CPU 40 and the external device. The FAX control unit 50 is connected to an external communication system via a telephone line 58, and performs data transmission / reception with the communication system using the serial ROM 32C in accordance with commands from the CPU 40 and the communication system.

  The serial ROM control unit 42 is connected to each of the serial ROMs 32 </ b> A to 32 </ b> C, reads data stored in the serial ROMs 32 </ b> A to 32 </ b> C in response to a read command transmitted from the CPU 40, and responds to a write command transmitted from the CPU 40. The data is written to the serial ROMs 32A to 32C. 2, the serial ROM controller 42 and the serial ROMs 32A to 32C are connected by select lines SL1 to SL3, clock lines CL1 to CL3, and data lines DL1 to DL4.

  The serial ROM controller 42 has the same number of three select terminals S1 to S3 as the serial ROMs 32A to 32C, and three clock terminals L1 to L3. In addition, the serial ROM control unit 42 has data terminals D1 to D4 that are a set of four. In the present embodiment, the clock terminals L1 to L3 included in the serial ROM control unit 42 are an example of a control unit side connection terminal and a control unit side clock terminal. The set of data terminals D1 to D4 included in the serial ROM control unit 42 is an example of a plurality of control unit side input / output terminals.

  Each serial ROM 32A-32C has one select terminal S and one clock terminal L. Each of the serial ROMs 32A to 32C has a set of data terminals D1 to D4 that have a one-to-one correspondence with each of the set of data terminals D1 to D4 that the serial ROM control unit 42 has. In the present embodiment, the clock terminal L included in each of the serial ROMs 32A to 32C is an example of a memory side connection terminal and a memory side clock terminal. A set of data terminals D1 to D4 included in each of the serial ROMs 32A to 32C is an example of a plurality of memory side input / output terminals.

  The select terminals S1 to S3 included in the serial ROM control unit 42 and the select terminals S included in the serial ROMs 32A to 32C are connected to each serial ROM 32. Specifically, the select terminal S1 of the serial ROM controller 42 is connected to the select terminal S1 of the serial ROM 32A via the select line SL1, and the select terminal S2 of the serial ROM controller 42 is serially connected via the select line SL2. The select terminal S3 of the serial ROM control unit 42 is connected to the select terminal S3 of the serial ROM 32B via the select line SL3.

  Similarly, clock terminals L1 to L3 included in the serial ROM control unit 42 and clock terminals L included in the serial ROMs 32A to 32C are connected to each serial ROM 32. Specifically, the clock terminal L1 of the serial ROM controller 42 is connected to the clock terminal L1 of the serial ROM 32A via the clock line CL1, and the clock terminal L2 of the serial ROM controller 42 is serially connected via the clock line CL2. Connected to the clock terminal L2 of the ROM 32B, the clock terminal L3 of the serial ROM control unit 42 is connected to the clock terminal L3 of the serial ROM 32C via the clock line CL3.

  On the other hand, a set of data terminals D1 to D4 included in each of the serial ROMs 32A to 32C is commonly connected to a set of data terminals D1 to D4 included in the serial ROM control unit 42. Specifically, the data terminal D1 of the serial ROM control unit 42 is connected to the data terminal D1 of each of the serial ROMs 32A to 32C via the data line DL1, and the data terminal D2 of the serial ROM control unit 42 is connected to the data line DL2. And connected to the data terminal D2 of each of the serial ROMs 32A to 32C. The same applies to the data terminals D3 and D4.

  The serial ROM control unit 42 transmits individual selection signals CS1 to CS3 to the serial ROMs 32A to 32C via the select terminals S1 to S3, and the ROMs 32A to 32C are transmitted via the select terminals S of the ROMs 32A to 32C. A corresponding selection signal CS is received. Similarly, the serial ROM control unit 42 transmits individual clock signals CLK1 to CLK3 to the serial ROMs 32A to 32C via the clock terminals L1 to L3, and the ROMs 32A to 32C are clock terminals L included in the ROMs 32A to 32C. The corresponding clock signal CLK is received via. The serial ROM control unit 42 and the serial ROMs 32A to 32C transmit and receive various data in units of 8 bits via the data terminals D of the set of data terminals D1 to D4.

  For example, when reading data stored in the serial ROM 32A, the serial ROM control unit 42 transmits a selection signal CS1 from the select terminal S1 to the serial ROM 32A, and transmits a clock signal CLK1 from the clock terminal L1 to the serial ROM 32A. A read command and a read address are transmitted in this order from the terminal D1. After transmitting these signals to the serial ROM 32A, the serial ROM control unit 42 reads data stored in the serial ROM 32A via the data terminals D1 to D4.

  Each serial ROM 32A to 32C has a storage area 80 (see FIG. 3) for storing data. For example, as shown in FIG. 3, the storage area 80 of the serial ROM 32A stores program data that is data of a control program and data other than the control program, such as standard data such as fonts and music. Read region 82 is included. Further, the read area 82 is divided into a first read area 82A where program data is stored and a second read area 82B where standard data is stored.

  In the storage area 80 of each of the serial ROMs 32A to 32C, a 24-bit memory address that specifies a position in the storage area 80 is set. In FIG. 3, the memory address of the storage area 80 is indicated by a 6-digit hexadecimal number following the symbol “0x” indicating that it is a hexadecimal number. In the present embodiment, the first read area 82A is set to an area with memory addresses from “0x000000” to “0x00FFFF”. Similarly, the second read area 82A is set to an area with memory addresses from “0x010000” to “0x01FFFF”.

  In other words, in the storage area 80, of the 24-bit memory addresses, the area specified by the upper 8 bits “00” is the first read area 82A, and the area specified by the upper 8 bits “01” is the second read. Region 82B. Therefore, of the 24-bit memory address, when the upper 8 bits are referred to as the upper address and the lower 16 bits are referred to as the lower address, by specifying the upper address, any one of the first read area 82A and the second read area 82B can be read. Data can be read by specifying 82.

  In FIG. 3, the unit data SD surrounded by a dotted line is 8-bit data, and in the storage area 80, a memory address is set for each unit data SD. In the storage area 80, as shown by being surrounded by a solid line in FIG. 3, 32-bit data composed of four unit data SD is used as reference data KD, and data is read for each reference data KD, or as described later. Write data.

  Further, for example, when writing data to the serial ROM 32A, the serial ROM control unit 42 transmits the selection signal CS1 from the select terminal S1 to the serial ROM 32A, transmits the clock signal CLK1 from the clock terminal L1 to the serial ROM 32A, and the data terminal A write command and a write address are transmitted in this order from D1. After transmitting the write address, the serial ROM control unit 42 transmits data from the data terminals D1 to D4 to the serial ROM 32A and writes the data to the serial ROM 32A.

  As shown in FIG. 3, the storage area 80 of the serial ROM 32A includes a write area 84 into which data can be written. In the present embodiment, the write area 84 is set to an area having memory addresses “0x020000” to “0x02FFFF”. That is, in other words, in the storage area 80, the area where the upper 8 bits of the 24-bit memory address are specified by “02” is the write area 84. Therefore, the data can be written by specifying the write area 84 of the serial ROM 32A by specifying the upper address.

  In each of the serial ROMs 32 </ b> A to 32 </ b> C, the storage area 80 includes a read area 82 and a write area 84, and different memory addresses are set in the areas 82 and 84. For example, a memory address whose upper 8 bits are “03” is set in the reading area 82 of the serial ROM 32B, and a memory address whose upper 8 bits is “04” is set in the writing area 84 of the serial ROM 32B. The read address 82 of the serial ROM 32C is set with a memory address whose upper 8 bits are “05”, and the write address 84 of the serial ROM 32C is set with a memory address whose upper 8 bits are “06”. Therefore, by specifying the upper address, it is possible to read data by specifying any read area 82 of the serial ROMs 32A to 32C, and to write data by specifying any write area 84 of the serial ROMs 32A to 32C. Can do.

2. Serial ROM Control Processing of Image Forming Apparatus Next, control processing of the serial ROMs 32A to 32C executed by the serial ROM control unit 42 will be described with reference to FIGS. In the present embodiment, a control process for the serial ROMs 32A to 32C mainly used for reading data will be described, and a description will be given using a case where data is read from or written to the serial ROM 32B according to a command from the CPU 40. .
4 and 5 show flowcharts of the control process. The serial ROM control unit 42 starts control processing when power is supplied to the image forming apparatus 10 by the user.

  Prior to describing the control processing of the serial ROMs 32A to 32C, a first communication period TK1 (see FIGS. 6 and 7) for transmitting a read command from the serial ROM control unit 42 to the serial ROMs 32A to 32C, and a read address to the serial ROM 32B. A second communication period TK2 (see FIGS. 6 and 7) for transmitting and reading read data or transmitting a write command to the serial ROM 32B, and clock signals CLK1 to CLK3 and a select signal CS1 to the serial ROMs 32A to 32C A period during which CS3 is transmitted will be described. In the present embodiment, the second communication period TK2 includes a preparation period JK (see FIG. 5) from when a read address is transmitted until read data corresponding to the read address is read.

  As shown in FIGS. 6 and 7, the serial ROM control unit 42 transmits clock signals CLK1 to CLK3 having a predetermined cycle to all the serial ROMs 32A to 32C in the first communication period TK1. In the second communication period TK2, the clock signal CLK2 is transmitted to the serial ROM 32B to be read or written, while the transmission of the clock signals CLK1, 3 to the serial ROMs 32A, 32C is stopped. The serial ROM control unit 42 stops transmission of the clock signals CLK1 to CLK3 to all the serial ROMs 32A to 32C in a period other than the first communication period TK1 and the second communication period TK2.

  Further, the serial ROM control unit 42 switches the selection signals CS1 to CS3 to ON (logic value 0) over at least the first communication period TK1. In the second communication period TK2, the selection signal CS2 transmitted to the serial ROM 32B to be read or written is turned on, while the selection signals CS1 and 3 transmitted to the serial ROMs 32A and 32C are turned off.

  As shown in FIG. 6, when the read data is read from the serial ROM 32B after transmitting the read command to the serial ROMs 32A to 32C, the serial ROM control unit 42 selects the serial ROMs 32A to 32C for the selection signal CS2 corresponding to the serial ROM 32B. After the transmission of the read command is started, the signal is kept on for a period from the start of reading of the read data from the serial ROM 32B. The selection signals CS1 and 3 are kept on for a period from the start of transmission of the read command to the serial ROMs 32A to 32C until the command is received from the CPU 40, and turned off after the command is received from the CPU 40. Switch.

  On the other hand, as shown in FIG. 7, when writing the write data to the serial ROM 32B after transmitting the read command to the serial ROMs 32A to 32C, the serial ROM control unit 42 receives an instruction from the CPU 40 for the selection signal CS2. Switch off very later. The serial ROM control unit 42 performs switching of these signals together with transmission of a read command, a read address, or reading of read data.

  When the control process is started, the serial ROM control unit 42 transmits a read command to all the serial ROMs 32A to 32C via the data line DL1 prior to receiving the command from the CPU 40 (S2). The serial ROM control unit 42 switches on the selection signals CS1 to CS3 simultaneously with the transmission of the read command, and transmits the clock signals CLK1 to CLK3 to all the serial ROMs 32A to 32C. Thereby, the transmission of the read command is temporarily stored in all the serial ROMs 32A to 32C.

  After transmitting the read command, the serial ROM control unit 42 waits for either a read command or a write command to be received from the CPU 40 (S4, S5: NO). When the serial ROM control unit 42 receives a read command including a read command and a read address from the CPU 40 (S4: YES, S5: NO), the read address included in the read command is any of the serial ROMs 32A to 32C. It is determined whether the memory address is for designating the serial ROM 32 (S6, S8).

  Specifically, the serial ROM control unit 42 reads the upper address of the read address included in the read command, and reads the upper 8-bit address of the upper address. When the read upper 8-bit address is “00” “01”, the serial ROM control unit 42 determines that the read address included in the read command is a memory address corresponding to the serial ROM 32A (S6: YES). . In this case, the serial ROM control unit 42 switches off the selection signals CS2 and 3 corresponding to the serial ROMs 32B and 32C, and then transmits a read address to the serial ROM 32A (S10).

  Similarly, when it is determined that the read address included in the read command is a memory address corresponding to the serial ROM 32B (S6: NO, S8: YES), the serial ROM control unit 42 selects corresponding to the serial ROMs 32A, 32C. The signals CS1, 3 are switched off, and then the read address is transmitted to the serial ROM 32B (S12). When it is determined that the memory address corresponds to the serial ROM 32C (S6: NO, S8: NO), the selection signals CS1 and 2 corresponding to the serial ROMs 32A and 32B are switched off, and then the read address is set to the serial ROM 32C. (S14).

  A case where the read address is transmitted to the serial ROM 32B will be described as a representative with reference to FIG. In this case, the selection signal CS2 transmitted from the select terminal S2 of the serial ROM control unit 42 to the select terminal S2 of the serial ROM 32B is kept on. When transmitting the read address to the serial ROM 32B, the serial ROM control unit 42 transmits the clock signal CLK2 from the clock terminal L2 of the serial ROM control unit 42 to the clock terminal L2 of the serial ROM 32B. Simultaneously with the transmission of the clock signal CLK2, the serial ROM control unit 42 transmits the read address to all the serial ROMs 32A to 32C via the data line DL1, and continues to the upper 8 bits of the upper address and the upper 8 bits of the lower address. The middle 8 bits are transmitted in the order of 8 bits following the middle 8 bits of the lower address (S12).

  As a result, the read address is received by the serial ROM 32B which has been activated by the transmission of the clock signal CLK2. On the other hand, the read address is not received by the serial ROMs 32A and 32C that are in the dormant state without transmitting the clock signal CLK and the select signal. The serial ROM control unit 42 receives read data corresponding to the read address from the serial ROM 32B via the data lines DL1 to DL4 after a predetermined preparation period JK has elapsed since the lower address was transmitted to the serial ROM 32B (S16).

  When the reception of the read data is completed, the serial ROM control unit 42 switches off the selection signal CS2 and stops transmission of the clock signal CLK2 to the serial ROM 32B. The CPU 40 detects the completion of reception of the read data from the switching of the selection signal CS2 to OFF, and sends back a signal indicating the completion of reception of the read data to the serial ROM control unit 42. In response to the reception of the signal, the serial ROM control unit 42 transmits a read command to all the serial ROMs 32A to 32C again (S2), and repeats the processing from S2.

  On the other hand, when the serial ROM control unit 42 receives a write command comprising a write command, a write address, and write data from the CPU 40 after transmitting the read command (S4: NO, S5: YES) As shown in FIG. 7, the selection signals CS1 to CS3 are switched off, and the read command transmitted before receiving the write command from the CPU 40 is reset (S18).

  After the reset, the serial ROM control unit 42 determines which of the serial ROMs 32A to 32C the memory address that designates which serial ROM 32 is specified (S20, S22). The serial ROM control unit 42 determines the serial ROM 32 corresponding to the write address included in the write command from the upper 8 bits of the write address included in the write command, and transmits the write command to the serial ROM 32. (S24-S30).

  A case where a write command is transmitted to the serial ROM 32B will be described as a representative with reference to FIG. The serial ROM control unit 42 switches the selection signal CS2 on again when transmitting the write command to the serial ROM 32B, and then the clock signal CLK2 from the clock terminal L2 of the serial ROM control unit 42 to the clock terminal L2 of the serial ROM 32B. Is transmitted (S26). The serial ROM control unit 42 transmits the write command and the write address to all the serial ROMs 32A to 32C via the data line DL1 simultaneously with the transmission of the clock signal CLK2, and the data line is transmitted following the transmission of the write address. Write data is transmitted to all the serial ROMs 32A to 32C via DL1 to DL4 (S30).

  As a result, the write command is received in the serial ROM 32B that has been activated by the transmission of the clock signal CLK2. On the other hand, the write command is not received by the serial ROMs 32A and 32C which are not in transmission of the clock signal CLK and the select signal and remain in the dormant state. When receiving the write command, the serial ROM 32B writes the write data in the area corresponding to the write address in the storage area 80.

  When the transmission of the write data is completed, the serial ROM control unit 42 stops transmitting the clock signal CLK2 to the serial ROM 32B and switches the selection signal CS2 off. The CPU 40 detects the completion of writing of the write data from the switching of the selection signal CS2 to OFF, and sends back a signal indicating the completion of reception of the write data to the serial ROM control unit 42. In response to the reception of the signal, the serial ROM control unit 42 transmits a read command to all the serial ROMs 32A to 32C again (S2), and repeats the processing from S2.

3. Advantages of the present embodiment (1) In the image forming apparatus 10 of the present embodiment, the data terminals D1 to D4 of the serial ROMs 32A to 32C are connected in common to the corresponding data terminals D1 to D4 of the serial ROM control unit 42. Yes. Therefore, as compared with the case where the data terminals D1 to D4 of each serial ROM 32 and the data terminals D1 to D4 of the serial ROM control unit 42 are connected to each serial ROM 32, the data terminals D1 to D4 of the serial ROM control unit 42 are connected. The number can be reduced. As a result, the number of terminals required for the serial ROM control unit 42 can be reduced, the size of the serial ROM control unit 42 can be reduced, and image formation by reducing the area occupied by the serial ROM control unit 42 can be realized. Miniaturization of the device 10 can be realized.

  On the other hand, when the data terminals D1 to D4 of each serial ROM 32 are connected in common to the corresponding data terminals D1 to D4 of the serial ROM control unit 42, an instruction received from the CPU 40 is transmitted to the data terminal D1 of the serial ROM control unit 42. When trying to transmit to each serial ROM 32A to 32C via .about.D4, the command is transmitted to all the serial ROMs 32A to 32C. For this reason, the command is also transmitted to the serial ROM 32 that does not correspond to an address such as a read address or a write address included in the command, so that erroneous read data is read or write data is written to the wrong serial ROM 32. For example, an unexpected malfunction may occur.

  In the image forming apparatus 10, the serial ROM control unit 42 includes clock terminals L1 to L3 connected to the serial ROMs 32A to 32C for each serial ROM 32. Then, when transmitting the command received from the CPU 40, the serial ROM control unit 42 determines the serial ROM 32 corresponding to the address included in the command and transmits the clock signal CLK to the serial ROM 32. In each of the serial ROMs 32 </ b> A to 32 </ b> C, only the serial ROM 32 that has received the clock signal CLK is in an operating state and receives a command. Thus, only the serial ROM 32 corresponding to the address included in the command can receive the content of the command, and the occurrence of the malfunction can be suppressed.

(2) In the image forming apparatus 10 of the present embodiment, the serial ROM 32A to 32C is designated using the clock signal CLK. The clock signal CLK is conventionally used as a reference timing signal for the serial ROM 32, and is conventionally transmitted from the serial ROM control unit 42 to each of the serial ROMs 32A to 32C via the clock terminals L1 to L3 of the serial ROM control unit 42. Has been. Therefore, it is necessary for the serial ROM control unit 42 as compared with the case where a special signal for indicating information indicating which serial ROM 32A to 32C is specified and a special terminal for transmitting the signal is provided. It is possible to reduce the number of terminals.

(3) In the image forming apparatus 10 of the present embodiment, when the serial ROM control unit 42 transmits the command received from the CPU 40 to all the serial ROMs 32A to 32C, conventionally, the command is transmitted after waiting for the command from the CPU 40. The read command is transmitted to all the serial ROMs 32A to 32C prior to receiving the command from the CPU 40. Therefore, when a read command is received from CPU 40 after the read command is transmitted, the read command is received from CPU 40 until the read data is received from serial ROM 32 corresponding to the read address included in the read command. The reading time YK (see FIG. 5) can be shortened.

(4) On the other hand, when the write command is received from the CPU 40 after transmitting the read command, the serial ROM control unit 42 resets the read command transmitted prior to the reception of the write command from the CPU 40. Then, after waiting for the write command from the CPU 40, the contents of the write command, that is, the write command, the write address, and the write data are transmitted to all the serial ROMs 32A to 32C. Write data can be written according to an instruction.

<Embodiment 2>
The second embodiment will be described with reference to FIGS. In this embodiment, as shown in FIG. 8, the serial ROM control unit 42 has one clock terminal L, and one clock terminal L that each serial ROM 32 </ b> A to 32 </ b> C has has one serial ROM control unit 42. The difference from the first embodiment is that the clock terminal L is commonly connected.

  Therefore, when the serial ROM control unit 42 transmits the clock signal CLK via the clock terminal L, the serial ROM control unit 42 transmits the clock terminal L to all the serial ROMs 32A to 32C simultaneously. In the present embodiment, the select terminals S1 to S3 included in the serial ROM control unit 42 are examples of the control unit side connection terminal and the control unit side select terminal, and the clock terminal L included in the serial ROM control unit 42 is the control unit side. It is an example of a clock terminal. The select terminals S included in the serial ROMs 32A to 32C are examples of memory side connection terminals and memory side select terminals, and the clock terminals L included in the serial ROMs 32A to 32C are examples of memory side clock terminals. In the following description, the same description as that of the first embodiment will not be repeated.

1. Serial ROM Control Processing of Image Forming Apparatus Also in the present embodiment, as in the first embodiment, control processing to serial ROMs 32A to 32C mainly used for reading data will be described, and from serial ROM 32B according to a command from CPU 40 The description will be made using the case where data is read or written.

  As shown in FIG. 11, in this embodiment, the serial ROM control unit 42 transmits the clock signal CLK in the first communication period TK1 and the second communication period TK2, and transmits the clock signal CLK in other periods. Stop.

  As shown in FIG. 9, in the present embodiment, when the control process is started, the serial ROM control unit 42 transmits a read command to all the serial ROMs 32A to 32C prior to receiving a command from the CPU 40 (S32). The serial ROM control unit 42 switches on the selection signals CS1 to CS3 and transmits the clock signal CLK simultaneously with the transmission of the read command. Thereby, the transmission of the read command is temporarily stored in all the serial ROMs 32A to 32C.

  When serial ROM control unit 42 transmits a read command and receives a read command from CPU 40 (S4: YES, S5: NO), serial ROM control unit 42 has a read address included in serial ROM 32A- It is determined which of the 32C memory addresses designates the serial ROM 32 (S6, S8). The serial ROM control unit 42 determines the serial ROM 32 corresponding to the read address from the upper 8 bits of the read address, and transmits the read address to the serial ROM 32 (S34 to S40).

  A case where the read address is transmitted to the serial ROM 32B will be described as a representative with reference to FIG. When transmitting the read address to the serial ROM 32B, the serial ROM controller 42 keeps the selection signal CS2 transmitted from the select terminal S2 of the serial ROM controller 42 to the select terminal S2 of the serial ROM 32B on (S36). ). The serial ROM control unit 42 transmits the clock signal CLK and the read address to all the serial ROMs 32A to 32C while the selection signal CS2 in the on state is transmitted (S40).

  As a result, the read address is received by the serial ROM 32B that has been selected by transmitting the selection signal CS2 in the on state. On the other hand, the read address is not received by the serial ROMs 32A and 32C which are in the non-selected state by transmitting the selection signal CS in the off state. The serial ROM control unit 42 receives read data corresponding to the read address from the serial ROM 32B after a predetermined preparation period JK has elapsed since the lower address was transmitted to the serial ROM 32B (S16).

  When the reception of the read data is completed, the serial ROM control unit 42 switches off the selection signal CS2 and stops transmitting the clock signal CLK. The CPU 40 detects the completion of reception of the read data from the stop of the transmission of the clock signal CLK, and sends back a signal indicating the completion of reception of the read data to the serial ROM control unit 42. In response to receiving the signal, the serial ROM control unit 42 transmits a read command to all the serial ROMs 32A to 32C again (S32), and repeats the processing from S32.

  On the other hand, when a write command is received from the CPU 40 after transmitting the read command (S4: NO, S5: YES), the serial ROM control unit 42 switches off the selection signals CS1 to CS3 and writes from the CPU 40. The read command transmitted before receiving the command is reset (S18). After the reset, the serial ROM control unit 42 determines which of the serial ROMs 32A to 32C the write address included in the write command is a memory address that designates the serial ROM 32 (S20, S22). A write command is transmitted to the serial ROM 32 (S24 to S30).

  Hereinafter, a case where a write command is transmitted to the serial ROM 32B will be described as a representative. The serial ROM control unit 42 switches the selection signal CS2 on again when transmitting the write command to the serial ROM 32B, and then the clock terminals L of the serial ROM control unit 42 to the clock terminals L of all the serial ROMs 32A to 32C. The clock signal CLK is transmitted to (S44). The serial ROM control unit 42 transmits a write command and a write address to all of the serial ROMs 32A to 32C via the data line DL1 simultaneously with the transmission of the clock signal CLK. Write data is transmitted to all the serial ROMs 32A to 32C via DL1 to DL4 (S48).

  As a result, the write command is received in the serial ROM 32B that has been selected by transmission of the selection signal CS2 in the on state. On the other hand, the write command is not received by the serial ROMs 32A and 32C that are in the non-selected state by transmitting the selection signal CS in the off state. When receiving the write command, the serial ROM 32B writes the write data in the area corresponding to the write address in the storage area 80.

2. Advantages of the present embodiment (1) In the image forming apparatus 10 of the present embodiment, the clock terminals L of the serial ROMs 32A to 32C are commonly connected to the clock terminal L of the serial ROM control unit 42. Therefore, as in the first embodiment, the serial ROM control is performed as compared with the case where the clock terminals L1 to L3 of the serial ROMs 32A to 32C and the clock terminals L1 to L3 of the serial ROM control unit 42 are connected to each serial ROM 32. The number of terminals required for the unit 42 can be reduced.

  On the other hand, when the clock terminal L of each of the serial ROMs 32A to 32C is commonly connected to the clock terminal L of the serial ROM control unit 42, which serial ROM 32A to 32C receives an instruction as in the first embodiment. Cannot be specified using the clock signal CLK.

(2) In the image forming apparatus 10, the serial ROM control unit 42 includes select terminals S <b> 1 to S <b> 3 connected to the serial ROMs 32 </ b> A to 32 </ b> C for each serial ROM 32. Then, the serial ROM control unit 42 designates which serial ROM 32A to 32C receives the command using the select signal SC.

  The select signal SC has been conventionally used as a control signal indicating the selection state of the serial ROMs 32A to 32C. Conventionally, each serial ROM controller 42 receives each serial signal from the serial ROM controller 42 via select terminals S1 to S3. It is transmitted to the ROMs 32A to 32C. Therefore, it is necessary for the serial ROM control unit 42 as compared with the case where a special signal for indicating information indicating which serial ROM 32A to 32C is specified and a special terminal for transmitting the signal is provided. It is possible to reduce the number of terminals.

<Other embodiments>
The present invention is not limited to the embodiments described with reference to the above description and the drawings, and for example, the following various aspects are also included in the technical scope of the present invention.
(1) Although the above embodiment has been described using the image forming apparatus 10 having a print function and a fax function, the present invention is not limited to this. The present invention only needs to have at least one of a print function, a fax function, a scan function, and a copy function, and the apparatus itself does not have these functions, and these functions of other apparatuses. It may be a device that executes processing for the purpose.

  In other words, the present invention includes a CPU, a plurality of storage units, and a control unit that controls reading or writing of data to the storage units. The present invention can be applied to any device that reads out or writes data and executes processing. It does not matter whether the storage unit is a ROM or a RAM.

(2) In the above embodiment, the image forming apparatus 10 includes the three serial ROMs 32A to 32C, and the serial ROM control unit 42 reads data from or writes data to the three serial ROMs 32A to 32C. Although the description has been given using an example in which processing is executed, the number of serial ROMs 32 is not limited to three, and may be two or four or more.

(3) Although the above embodiment has been described using an example in which a read command is transmitted prior to reception of a command from the CPU 40, the present invention is not limited to this. If the serial ROMs 32A to 32C are mainly used for writing data, a write command may be transmitted prior to receiving a command from the CPU 40.

(4) Also, what is transmitted prior to the reception of the instruction from the CPU 40 is not limited to the read command or the write command, and the upper address or the upper 8 bits of the upper address is received together with the read command or the write command. You may send it. As the upper 8 bits of the upper address, for example, the upper 8 bits of the read address included in the forward read instruction or the upper 8 bits of the write address included in the forward write instruction can be used.

(5) Although the first embodiment has been described using an example in which different selection signals CS1 to CS3 are transmitted to the serial ROMs 32A to 32C, the same selection signal CS may be transmitted. In this case, the serial ROM control unit 42 has one select terminal S, and one select terminal S included in each of the serial ROMs 32A to 32C is commonly connected to one select terminal S included in the serial ROM control unit 42. May be. As a result, as in the first embodiment, the serial ROMs 32A to 32C are connected to the select terminals S1 to S3 and the select terminals S1 to S3 of the serial ROM control unit 42 for each serial ROM 32. The number of terminals required for the control unit 42 can be reduced.

10: Image forming apparatus, 32: Serial ROM, 40: CPU, 42: Serial ROM control unit, 80: Storage area, 82: Reading area, 84: Writing area, S: Select terminal, SL: Select line, CS: Selection signal, L: clock terminal, CL: clock line, CLK: clock signal, D: data terminal, DL: data line

Claims (6)

A control unit including a CPU and a memory control unit;
Multiple memories,
With
The memory control unit has at least the same number of control unit side connection terminals as the memory, and a plurality of control unit side input / output terminals.
Each memory has a memory side connection terminal and a plurality of memory side input / output terminals corresponding to each of the plurality of control unit side input / output terminals,
The control unit side connection terminal and the memory side connection terminal are connected for each memory,
A plurality of the memory side input / output terminals corresponding to each control unit side input / output terminal are connected in common to the control unit side input / output terminals,
The memory control unit
The instruction received from the CPU is output to all the memories via the control unit side input / output terminal.
and,
From the instruction received from the CPU, it is determined which one of the plurality of memories is designated, and a signal is transmitted through the control unit side connection terminal corresponding to the memory,
The memory validates the command input via the memory side input / output terminal when the signal is received at the memory side control unit terminal of the memory.
Processing equipment. The processing apparatus according to claim 1,
The control unit side connection terminals are at least as many control unit side clock terminals as the memory that transmits a clock signal,
The memory side connection terminal is a memory side clock terminal that receives the clock signal,
The control unit side clock terminal and the memory side clock terminal are connected in a one-to-one correspondence for each memory,
The memory control unit
From the instruction received from the CPU, determine which of the plurality of memories is designated, and send the clock signal via the control unit side clock terminal corresponding to the memory,
The memory validates the instruction input via the memory side input / output terminal when the clock signal is received at the memory side clock terminal of the memory;
Processing equipment. The processing apparatus according to claim 1,
The memory control unit further includes a control unit side clock terminal for transmitting a clock signal,
Each of the memories further includes a memory side clock terminal that receives the clock signal,
The connection side connection terminals are at least the same number of control unit side select terminals as the memory for transmitting a select signal,
The memory side connection terminal is a memory side select terminal that receives the select signal,
A plurality of the memory side clock terminals are commonly connected to the control unit side clock terminals,
The control unit side select terminal and the memory side select terminal are connected in a one-to-one correspondence for each memory,
The memory control unit
Furthermore,
The clock signal is transmitted to all the memories via the control unit side clock terminal,
From the instruction received from the CPU, it is determined which one of the plurality of memories is designated, and the select signal is transmitted through the control unit side select terminal corresponding to the memory,
The memory validates the instruction input via the memory side input / output terminal when the select signal is received at the memory side select terminal of the memory;
Processing equipment. The processing apparatus according to any one of claims 1 to 3,
The CPU
A read command consisting of a read command and a read address or a write command consisting of a write command, a write address and write data is sent to the memory control unit;
The memory control unit
Prior to receiving the command from the CPU, either the read command or the write command is transmitted to all the memories via the control unit side input / output terminal,
When receiving a command from the CPU,
When the command included in the command from the CPU matches the command transmitted in advance, the command excluding the command is transmitted to all the memories via the control unit side input / output terminal. ,
Processing equipment. The processing apparatus according to claim 4, wherein
The memory control unit
When receiving a command from the CPU,
When the command included in the command from the CPU does not match the command transmitted in advance, the command from the CPU is transmitted to all the memories via the control unit side input / output terminal.
Processing equipment. The processing apparatus according to claim 5, wherein
The memory control unit
Prior to receiving the command from the CPU, the read command is transmitted to all the memories via the control unit side input / output terminal,
When receiving a command from the CPU,
When the command from the CPU is the read command, the read command below the read command is transmitted to all the memories via the control unit side input / output terminal,
When the command from the CPU is the write command, the write command from the CPU is transmitted to all the memories via the control unit side input / output terminal.
Processing equipment.

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