JP2015027058A - Image processing apparatus, control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processing apparatus in which the access order and the response order of a memory access request to a memory issued by the same master can be protected.SOLUTION: An image processing apparatus includes a shared storage unit in which image data is stored, a transfer path determination unit for determining through which path, connected with the shared storage unit, the image data is transferred, a selection unit for selecting the transfer path, through which the image data is transferred, based on the transfer path thus determined, and an access request control unit for issuing an access request to the next shared storage unit while waiting a response to an access request to an issued shared storage unit, when the transfer path thus determined has been changed from a transfer path used in the previous transfer of the image data.

Description

  The present invention relates to an image processing apparatus and a control method.

  In general, since a scanner reads an image at a constant speed, the read image becomes an abnormal image if it cannot be written to the shared memory at a constant speed. Also, the plotter image needs to be output periodically in line units, and if the output is not in time, an abnormal image will be generated. Therefore, an adjustment method giving a high priority to the transfer of the scanner image and the plotter image is often used for the shared memory accessed by a plurality of functions.

  On the other hand, when an image temporarily stored in the memory is rotated and then output as a plotter image, when output is started after the image for one page is rotated, output is started until the rotation processing is completed. There is a problem that it is necessary to wait and the printing speed decreases. Further, in order to rotate an image for one page, it is necessary to secure a memory capacity for two pages of the original image and the image after the rotation process. On the other hand, Patent Document 1 discloses a method of starting image output after waiting for the completion of rotation processing for several lines without waiting for completion of rotation processing for one page.

  In this way, when other functions operate in conjunction with functions that need to guarantee constant image transfer in units of lines, the other functions also perform constant image processing in units of lines, and Processing capability to follow image input and plotter image output is required. On the other hand, for functions that operate in conjunction with the transfer of plotters and scanner images, a memory access request is issued to a port with a high priority for bus arbitration only during the interlocking operation, and priorities when not interlocked A method for changing the priority order of issuing a memory access request to a low port is already known.

  In addition, the command transfer method called non-posted, in which the distance to the shared memory is long and the next command is issued after waiting for the read data (= response) for the read command or the completion notification (= response) for the write command, is slow. In this case, there is already known a method of improving the bus transfer efficiency and improving the image processing speed by adopting a command issuing method called Posted which issues the next command one after another without waiting for a response. Patent Document 2 discloses a data transfer method using a multiplexed bus configuration capable of selectively transferring images via a plurality of paths. In this method, the transfer path is multiplexed to widen the transfer band, the multiplexed transfer path is efficiently selected, and the memory write requests issued from a plurality of masters pass through different paths. An effect of preventing the writing order from being reversed can be obtained.

  However, in the conventional priority changing means, when a plurality of requests are thrown ahead without waiting for a response to the memory access request, each request is transferred from different ports via different data paths. Therefore, depending on the timing, the memory access request issued later reaches the memory earlier than the memory access request issued by the master function first, overwriting data on the memory for writing, and response data for reading There is a problem in that an image abnormality may occur before and after the order.

  The present invention has been made in view of the above, and protects the memory access order and response order of memory access requests issued by the same master even in a bus configuration having a plurality of paths to the memory. It is an object of the present invention to provide an image processing apparatus that can perform the above processing.

  In order to solve the above-described problems and achieve the object, the present invention provides a shared storage unit in which image data is stored, and the image data through any path from a plurality of transfer paths connected to the shared storage unit. A transfer path determination unit that determines whether to transfer, a selection unit that selects the transfer path for transferring the image data based on the determined transfer path, and the determined transfer path that includes the previous image When the transfer path used in the data transfer is changed, access request control that waits for a response to the issued access request to the shared storage unit and then issues the next access request to the shared storage unit And a section.

  According to the present invention, even in a bus configuration having a plurality of paths to the memory, the memory access request issued by the same master and the response order to the memory can be maintained.

FIG. 1 is a block diagram illustrating a functional configuration of the image processing apparatus according to the first embodiment. FIG. 2 is a diagram illustrating a detailed functional configuration of the first image processing unit according to the first embodiment. FIG. 3 is a flowchart showing a flow of processing relating to image transfer route selection according to the first embodiment. FIG. 4 is a block diagram illustrating a functional configuration of the image processing apparatus according to the second embodiment. FIG. 5 is a diagram illustrating a detailed functional configuration of the first image processing unit according to the second embodiment. FIG. 6 is a block diagram illustrating a functional configuration of the image processing apparatus according to the third embodiment. FIG. 7 is a block diagram illustrating a functional configuration of the first image processing unit according to the fourth embodiment.

(First embodiment)
A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram of an image processing apparatus 1 according to the present invention. As shown in FIG. 1, the image processing apparatus 1 includes an engine unit 200 and a system controller 100. The system controller 100 includes a shared memory 105, a first arbitration unit 106, a scanner image transfer device 101, a plotter image transfer device 102, a CPU 103, a first image processing unit 104, a second image processing unit 108, and a third image processing unit 109. ing. The engine unit 200 includes a scanner 201, an image input device 202, a plotter 204, and an image output device 205. In the image processing apparatus 1, image data read by the engine unit 200 is input to the system controller 100, and the system controller 100 controls writing of data to the shared memory (shared storage unit) 105. . The document data read by the scanner 201 is transferred to the system controller 100, and the output data image-processed by the system controller 100 is printed on paper by the plotter 204.

  The image input device 202 transfers the document image read by the scanner 201 to the system controller 100. The image output device 205 receives the output image transferred from the plotter image transfer device 102 of the system controller 100 and transfers it to the plotter 204.

  The first arbitration unit 106 controls access to the shared memory 105. The scanner image transfer device 101, the plotter image transfer device 102, the CPU 103, the first image processing unit 104, the second image processing unit 108, the third image processing unit 109, and the like correspond to a master and access the shared memory 105. The scanner image transfer apparatus 101 performs control to receive an image read by the engine unit 200 and write it to the shared memory 105. The plotter image transfer apparatus 102 performs control to read an output image temporarily stored in the shared memory 105 and transfer it to the engine unit 200.

  The CPU 103 performs operation mode setting and activation instruction to the apparatus such as the scanner image transfer apparatus 101 and the first arbitration unit 106, address management of the shared memory 105, and the like. There may be a plurality of first image processing units 104, each having functions such as image compression / decompression, image rotation, image encryption, and image processing. When the first image processing unit 104 operates in conjunction with the plotter image transfer device 102, it is necessary to perform image processing following the transfer speed of the plotter image transfer device 102. For this reason, the first image processing unit 104 has a data path for speeding up memory access only when linked, and the selector 110 selects a path to be used from a plurality of transfer paths. The first image processing unit 104 receives whether or not the plotter image transfer apparatus 102 is operating by an operation information signal, determines whether or not the plotter image transfer apparatus 102 is operating in conjunction with a parameter set by the CPU 103, and transfers it to the selector 110. An instruction signal is transmitted.

  Further, there may be a plurality of second image processing units 108 and third image processing units 109, each having functions such as image compression / decompression, image rotation, image encryption, and image processing. The shared memory 105 is a main storage unit that temporarily stores images and programs for the CPU 103. The image data input to the scanner image transfer apparatus 101 is once expanded in the shared memory 105.

  The first arbitration unit 106 is a data bus that controls the access order of each master that accesses the shared memory 105, and arbitrates priorities so that the shared memory 105 can be used efficiently. The second arbitration unit 107 is a data bus that controls the order in which access requests are issued to the port 5 of the first arbitration unit 106, and has a role of arbitrating priorities so that the shared memory 105 can be used efficiently.

  The selector 110 selects a connection destination from either the first arbitration unit 106 or the second arbitration unit 107 in accordance with the transfer path instruction signal received from the first throw number control unit 111. In a system in which a plurality of first image processing units 104 exist, the same number of selectors 110 as the first image processing units 104 are required. The first throw number control unit 111 (access request control unit) controls the number of first throws without waiting for a response to a memory access request (read command / write command). The first throw number control unit 111 counts the number of transferred memory access requests and the number of responses, and manages the difference to determine whether a response is returned in response to the memory access request. When a transfer path instruction signal to the shared memory 105 is instructed by the transfer path instruction signal, the first throw number control unit 111 issues the next request until all responses of the request (command) issued before switching are collected. Control not to. When the selector 110 is instructed to switch the transfer path, the first throw number control unit 111 collects all responses to the request (command) and then performs switching before issuing the next request.

  The second image processing unit 108 and the third image processing unit 109 have a memory access priority lower than that of the first image processing unit 104, and after the arbitration by the second arbitration unit 107, Connected to port 5. The first image processing unit 104 transfers data via the port 4 of the first arbitration unit 106 having a high priority only when operating in conjunction with the plotter image transfer apparatus 102. Further, when the first image processing unit 104 operates independently of the plotter image transfer apparatus 102, the first image processing unit 104 is arbitrated by the second arbitration unit 107 and then undergoes arbitration by the first arbitration unit 106.

  Therefore, it is possible to access the shared memory 105 via the port 4 with less response time to the shared memory 105 than via the port 5 via the second arbitration unit 107. In addition, when the second arbitration unit 107 is passed, arbitration is performed with another master connected to the second arbitration unit 107, so the memory access speed is reduced because the ratio of acquiring the memory access right is reduced. Sometimes. Furthermore, when the functions having low priority are collected in the second arbitration unit 107, the priority of the port 5 may be set lower than the ports 1 to 4 of the first arbitration unit 106.

  The first image processing unit 104 receives the operation information indicating that the image is being transferred from the plotter image transfer apparatus 102, further determines whether or not the plotter image transfer apparatus 102 is interlocked, and performs first arbitration with respect to the selector 110. The transfer path instruction information indicating whether to directly transfer the memory access request to the unit 106 or to transfer the memory access request via the second arbitration unit 107 is output. The image data read by the scanner 201 of the engine unit 200 is once stored in the shared memory 105 via the scanner image transfer device 101, processed in a format that can be output by the first image processing unit 104, and then transferred to the plotter image. The data is output to the plotter 204 of the engine unit 200 via the device 102. The image processing executed by each of the image processing units 104, 108, and 109 may be an image rotation function or a compression / decompression function. Further, although not shown, an HDD controller and a network I / F may be provided.

  FIG. 2 is a more detailed block diagram of FIG. The first image processing unit 104 further includes an interlock setting unit 301 and a transfer route determination unit 302. The interlock setting unit 301 is parameter-set by the CPU 103, and is instructed whether to perform the interlock operation or the function alone, and holds the instruction content. The interlocking operation is to start the next image processing step (rotation or compression processing) before storing the scanner image for one page in the memory for the purpose of reducing the memory capacity and processing time. Control is performed so that the process does not overtake scanner image input. Or, when the plotter image is output, the image of the next page is written sequentially so as not to overtake the memory area where the plotter has been output, thereby increasing the productivity of the multifunction device without increasing the memory capacity. is there.

  The transfer path determination unit 302 determines a transfer path based on the link setting of the link setting unit 301 and the operation information of the plotter image transfer apparatus 102, and issues a transfer path instruction to the first throw number control unit 111. When switching the path to the shared memory 105 by the transfer path instruction, the first throw number control unit 111 waits for a response to a memory access request (read command / write command) that has already been issued before the next previous memory access and transfer path. Request issuance to the selector 110 to issue different memory access requests.

  FIG. 3 is a flowchart showing the flow of image transfer control processing. As shown in FIG. 3, it is first determined whether or not the first image processing unit 104 operates in conjunction with the plotter image transfer apparatus 102 (step S01). If it is determined to operate in conjunction (step S01: Yes), the CPU 103 sets the interlock operation with the plotter image transfer apparatus 102 in the interlock setting unit 301 (step S02). In this case, since the image processing speed of the first image processing unit 104 needs to follow the plotter image transfer speed, it is also necessary to increase the priority of memory access. During the operation of the plotter image transfer apparatus 102 (= during the interlocking operation), the setting in step S02 is performed in order to change to a transfer path in which the memory access request of the first image processing unit 104 is preferentially processed.

  On the other hand, when it is determined not to operate in conjunction (step S01: No), the CPU 103 sets a single operation in the interlock setting unit 301 (step S03). Next, the CPU 103 instructs activation of the first image processing unit 104 (step S04). Then, the plotter image transfer apparatus 102 updates the operation information signal in real time (step S05). Specifically, since it becomes High during activation and becomes Low when the operation is completed, the operation information signal controlled in real time is updated immediately before the transfer path determination unit 302 refers to it.

  The transfer path determination unit 302 confirms whether or not a linked operation instruction with the plotter image transfer apparatus 102 set by the linked setting unit 301 is set, and confirms an operation information signal from the plotter image transfer apparatus 102, and there is a linked operation instruction. In addition, it is determined whether the operation information is High (= plotter image transfer apparatus 102 is being activated) (step S06). When it is determined that there is an interlocking operation instruction and the operation information is High (step S06: Yes), the transfer route determination unit 302 transfers the route directly connected to the first arbitration unit 106 to the first throw number control unit 111. This is instructed as a route instruction signal (step S07). On the other hand, when the interlocking operation instruction is a single operation or when the operation information is Low (= the plotter image transfer apparatus 102 is not operating) (step S06: No), the transfer path determination unit 302 A path for accessing the shared memory 105 via the second arbitration section 107 is instructed to the throwing number control section 111 as a transfer path instruction signal (step S08).

  Next, the first throw number control unit 111 determines the route according to the transfer route instruction signal, but the first throw number control unit 111 confirms which route the memory access request issued immediately before is issued, and this route Are determined to be the same route (step S09). When a transfer path different from the previous memory access request is instructed (step S09: No), the first throw number control unit 111 waits for the next memory access request until all responses to the already issued memory access request are collected. (Step S10). Further, after collecting all responses to the already issued memory access request, the first throw number control unit 111 instructs the selector 110 to change the path (step S11). Note that the timing of the transfer path instruction signal input to the selector 110 is shifted once by the first throw number control unit 111 because the response of the read or write is returned through the transfer path of the previously issued request. To wait. When the response path and the request issuance path have different configurations, there is no problem even if the transfer path instruction signal for the selector 110 is updated at the timing notified by the transfer path determination unit 302.

  On the other hand, when the same transfer path as the previous memory access request is instructed (step S09: Yes), the first throw number control unit 111 does not perform the processes of steps S10 and S11, and the memory access is performed on the specified transfer path. A request is issued (step S12). Until the data transfer for one page is completed (step S13: Yes), the flow from step S05 to step S11 is repeated every time a memory access request is issued. When the data transfer for one page is completed, the first image processing is performed. The unit 104 notifies the CPU 103 of completion of image processing using a completion interrupt or the like, and completes the operation.

  In the image processing apparatus 1 of the present embodiment described above, when issuing a memory access request that passes through a transfer path different from the previous memory access request, the master confirms that the previous memory access has been completed. Wait for a memory access request to be issued. Therefore, the order of the memory access issued first and the memory access issued next can be guaranteed, and even if the bus configuration has multiple paths to the memory, the memory access request issued by the same master is accessed to the memory. The order and response order can be observed.

  In addition, the shared memory 105 can be preferentially accessed only when the first image processing unit 104 operates in conjunction with the plotter 204, and the priority is lowered before or after the image output of the plotter 204 is completed. Compared with other masters, it is possible to perform control so as not to give access authority to the shared memory excessively, and it is possible to optimize the memory access of the system within a range in which no abnormal image is generated.

(Second Embodiment)
Next, an information processing apparatus 1a according to the second embodiment will be described with reference to FIG. In the following description, the description of the same parts as those of the first embodiment will be omitted, and the description will be focused on a different system controller 100a. In the first embodiment, the transfer path is changed by the selector 110. However, in the second embodiment, the second arbitration unit 107a is different.

  When the transfer path change is implemented in a function that cannot be directly controlled from the first image processing unit 104a, or when another mediation unit or image processing function is added in the middle, the transfer path instruction is not directly notified, The path 112 is attached to the request as an attribute of the memory access request (= command) itself, and controls which transfer path the second arbitration unit 107a that has received the request transfers to the shared memory 105. Even in this configuration without a selector, the role of the first throw number control unit 111 does not change, the transfer path information attached to the memory access request is referred to, and when the transfer path changes, all responses of the previously issued memory access request are all received. After collection, control is performed to issue the next memory access request whose transfer path changes.

  Port 4 of the first arbitration unit 106 is set to have a higher priority than port 5. The attribute information is added to the first image processing unit 104a so as to access the shared memory 105 via the port 4 while operating in conjunction with the plotter image transfer apparatus 102, and the priority order is set during the single operation. The shared memory 105 is accessed via the low port 5.

  FIG. 5 is a diagram showing a detailed configuration of the first image processing unit 104a. As shown in FIG. 5, the first image processing unit 104 a newly includes a route information adding unit 303. The interlock setting unit 301 has the same function as that of the first embodiment. The transfer route determination unit 302 has the same function as that of the first embodiment, and notifies the route information addition unit 303 of the transfer route instruction signal, not the first throw number control unit 111. The path information adding unit 303 adds information indicating the transfer path to the memory access request issued from the first image processing unit 104a.

  The first throw number control unit 111 performs the same control as that of the first embodiment with reference to the transfer path information added to the memory access request. The second arbitration unit 107a distributes the request transfer path to the shared memory 105 based on the transfer path information added to the memory access request.

  In the configuration of the present embodiment, even when there is no selector or when it is not possible to directly instruct the transfer path to the selector, data transfer based on information on an appropriate transfer path can be performed. It becomes like this.

(Third embodiment)
Next, an information processing apparatus 1b according to a third embodiment of the present invention will be described with reference to FIG. In the following description, the description of the same parts as those of the first embodiment will be omitted, and the description will be focused on a different system controller 100b. In the first embodiment, the case where the access path to the shared memory 105 is changed in conjunction with the plotter image transfer apparatus 102 has been described. On the other hand, the third embodiment is different in that the access path to the shared memory 105 is changed in conjunction with the scanner image transfer apparatus 101. Then, before the scanner image is completely written in the shared memory 105, the first image processing unit 104 controls the image being written to be processed in parallel while following the scanner image transfer apparatus 101. The functions of the first image processing unit 104, the first throw number control unit 111, and the selector 110 are the same as those in the first embodiment. The linkage with the scanner image may use the same configuration as in the second embodiment.

  That is, before the scanner image is completely written to the shared memory 105, the image being written is processed in parallel while following the scanner image transfer apparatus 101 by the first image processing unit 104. Such processing time can be shortened. Further, it is not necessary to develop one page of the image input from the scanner in the shared memory 105. Therefore, the memory area can be reduced by configuring the scanner image writing area with a ring buffer, or by overwriting the scanner image before image processing with the image processed by the first image processing unit 104. become.

(Fourth embodiment)
Next, a system controller 100c of the information processing apparatus 1c according to the fourth embodiment will be described with reference to FIG. In this embodiment, the port 4 and the port 5 of the first arbitration unit 106 are connected to the selector 110 that changes the transfer path. Further, the port 4 of the first arbitration unit 106 is set to have a higher memory access priority than the port 5. The first arbitration unit 106 includes a data buffer and a command (request) buffer in each master port, and can receive and buffer one or more commands.

  As shown in FIG. 7, when the transfer path is changed from the port 4 having a high priority to the port 5 having a low priority, the port 4 issued first by the first throw number control unit 111. The request issued via port 5 issued next time cannot be overtaken by the memory access request passed via. That is, the memory access request via the port 4 always reaches the shared memory 105 first. If the selector 110 selects a path for only the memory access request and transfers the response data to the first image processing unit 104 regardless of which route is returned, the first throw number control unit 111 changes the transfer path. Even in this case, it is not necessary to collect all responses of memory access requests that have already been issued, and it is possible to subsequently issue memory access requests with different transfer paths.

  On the other hand, when the transfer route instruction is changed from port 5 which is a low priority route to port 4 which is a high priority route, when it is accumulated in the data buffer and command buffer of the first arbitration unit 106, A situation may occur in which a memory access request accessed via the port 4 with a high priority overtakes a memory access request issued via the port 5 with a lower priority issued earlier. Therefore, when the transfer route instruction is changed from a route with a low priority to a route with a high priority, the first-throw number controller 111 waits for a response to an already issued memory access request before the next memory access request. Is configured to issue.

  Therefore, in the present embodiment, in a configuration that has a plurality of paths and is guaranteed that a memory access request issued by a path with a high priority does not overtake a memory access request issued by a path with a low priority. The first-throw control unit 111 controls to issue a next memory access request after waiting for a response to a memory access request that has already been issued only when a route with a lower priority is changed to a route with a higher priority.

  The image processing apparatus according to the present embodiment includes a control device such as a CPU, a storage device such as a ROM (Read Only Memory) and a RAM, an external storage device such as an HDD and a CD drive device, and a display device such as a display device. It has an input device such as a keyboard and a mouse, and has a hardware configuration using a normal computer.

  The program executed in the image processing apparatus of the present embodiment is a file in an installable format or an executable format, and is a computer such as a CD-ROM, a flexible disk (FD), a CD-R, or a DVD (Digital Versatile Disk). It is recorded on a readable recording medium and provided.

  Further, the program executed by the image processing apparatus according to the present embodiment may be provided by being stored on a computer connected to a network such as the Internet and downloaded via the network. The program executed by the image processing apparatus according to the present embodiment may be configured to be provided or distributed via a network such as the Internet.

  Further, the program of this embodiment may be configured to be provided by being incorporated in advance in a ROM or the like.

  The program executed by the image processing apparatus according to the present embodiment has a module configuration including the above-described units. As actual hardware, a CPU (processor) reads the program from the storage medium and executes it. Each of the above parts is loaded on the main storage device, and each part is generated on the main storage device.

  In the above embodiment, the image forming apparatus according to the present invention is described by taking an example in which the image forming apparatus is applied to a multifunction machine having at least two functions among a copy function, a printer function, a scanner function, and a facsimile function. The present invention can be applied to any image forming apparatus such as a printer, a scanner apparatus, and a facsimile apparatus.

DESCRIPTION OF SYMBOLS 1 Image processing apparatus 100 System controller 101 Scanner image transfer apparatus 102 Plotter image transfer apparatus 104 1st image processing part 105 Shared memory 106 1st arbitration part 107 2nd arbitration part 108 2nd image processing part 109 3rd image processing part 110 Selector DESCRIPTION OF SYMBOLS 111 First throw number control part 112 Path | route 200 Engine part 201 Scanner 202 Image input device 204 Plotter 205 Image output apparatus 301 Interlock setting part 302 Transfer path determination part 303 Path | route information addition part

JP 2001-127773 A JP 2004-046851 A

Claims (6)

A shared storage unit for storing image data;
A transfer path determination unit that determines which path to transfer the image data from a plurality of transfer paths connected to the shared storage unit;
A selection unit that selects the transfer path for transferring the image data based on the determined transfer path;
When the determined transfer path is changed from the transfer path used in the previous transfer of the image data, the next shared is waited for a response to the issued access request to the shared storage unit An access request control unit that issues an access request to the storage unit;
An image processing apparatus comprising: The transfer path determination unit determines whether or not the processing for outputting the image data and the transfer of the image data are linked, and when linked, the transfer path determination unit determines the priority of the shared storage unit. It is decided to use the transfer path to which a high access authority is granted, and when not linked, to use the transfer path to which an access authority with a low priority is assigned to the shared storage unit. The image processing apparatus according to claim 1, wherein the determination is performed. The transfer route determination unit adds the determined transfer route as attribute information of an access request to the shared storage unit,
The image processing apparatus according to claim 1, wherein the selection unit selects the transfer path from the attribute information of the acquired access request. The transfer path determination unit determines whether or not the processing for reading the image data and the transfer of the image data are linked, and when linked, the transfer path determination unit determines the priority of the shared storage unit. It is decided to use the transfer path to which a high access authority is granted, and when not linked, to use the transfer path to which an access authority with a low priority is assigned to the shared storage unit. The image processing apparatus according to claim 2, wherein the determination is performed. The access request is configured so that the access request having the access authority with the higher priority does not reach the shared storage unit before the access request having the access authority with the lower priority. Configured,
When the access request control unit changes from an access request with a low priority access privilege to an access request with a high priority access privilege, the access request control unit waits for a response to the issued access request before transferring to the next shared storage unit. The image processing apparatus according to claim 1, wherein an access request is issued. A transfer path determining step for determining which path to transfer the image data from a plurality of transfer paths connected to a shared storage unit in which the image data is stored;
A selection step of selecting the transfer path for transferring the image data based on the determined transfer path;
When the determined transfer path is changed from the previously used transfer path, the access request to the next shared storage unit is made after waiting for a response to the access request to the shared storage unit that has been issued. An access request control step to be issued;
The control method characterized by including.

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