JP2015026870A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve characteristics of a semiconductor device having a nonvolatile memory.SOLUTION: A semiconductor device is configured to comprise: control gate electrodes CG, memory gate electrodes MG disposed so as to be adjacent to the control gate electrodes CG, insulating films 3, and insulating films 5 each having a charge storage portion in its inside. The memory gate electrodes MG are composed of a silicon film having first silicon regions 6a disposed on the insulating films 5 and second silicon regions 6b disposed above the first silicon regions 6a. The second silicon regions 6b contain a p-type impurity. Concentration of the p-type impurity of the first silicon regions 6a is configured to be lower than that of the second silicon regions 6b.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a nonvolatile memory.

  A flash memory is widely used as a kind of EEPROM (Electrically Erasable and Programmable Read Only Memory) which is a nonvolatile semiconductor memory device that can be electrically written and erased. This flash memory has a conductive floating gate electrode and a trapping insulating film surrounded by an oxide film under the gate electrode of the MISFET. Information is stored by utilizing the difference in threshold value of the MISFET depending on the presence or absence of electric charges (electrons or holes) in the floating gate and the trapping insulating film.

  For example, in Japanese Patent Application Laid-Open No. 2006-303918 (Patent Document 1), in a MONOS type nonvolatile memory, a memory gate electrode is formed of a doped polycrystalline silicon film, and the doped polycrystalline silicon film is formed as a lower high-concentration layer. A technique that consists of two layers, an upper layer and a low concentration layer, is described.

  Japanese Patent Laying-Open No. 2006-19373 (Patent Document 2) discloses a polycrystalline MONOS nonvolatile memory in which a memory gate is made of a doped polycrystalline silicon film, and impurities are ion-implanted into the undoped silicon film. A technique for lowering sheet resistance than a control gate made of a silicon film is described.

  Japanese Patent Laid-Open No. 2004-186252 (Patent Document 3) discloses that in a MONOS type nonvolatile memory, after forming a selection gate electrode, a polycrystalline silicon film doped with an n-type impurity is deposited, and a semiconductor in that state is deposited. A p-type impurity is ion-implanted into the substrate, and then a polycrystalline silicon film doped with an n-type impurity is further deposited, and the two deposited n-type impurities are anisotropically etched to form a memory gate. The technology is described.

JP 2006-303918 A JP 2006-19373 A JP 2004-186252 A

  The present inventor is engaged in research and development of flash memory. In particular, improvement of the characteristics of the split gate nonvolatile memory is being studied. The memory gate electrode of this split gate type nonvolatile memory has been formed of a doped silicon film containing impurities in order to reduce the resistance.

  In recent years, in the semiconductor device having the nonvolatile memory, it is desired to improve characteristics such as an improvement in operation speed and data retention characteristics of the nonvolatile memory.

  Therefore, an object of the present invention is to provide a technique capable of improving the characteristics of a semiconductor device.

  Another object of the present invention is to provide a method of manufacturing a semiconductor device that manufactures a semiconductor device having good characteristics in a better manufacturing process.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  Among the inventions disclosed in this application, a semiconductor device shown in a typical embodiment includes a semiconductor substrate, a first gate electrode disposed above the semiconductor substrate, and a first gate electrode above the semiconductor substrate. And a second gate electrode arranged adjacent to each other. Further, a first insulating film formed between the first gate electrode and the semiconductor substrate, a first insulating film formed between the second gate electrode and the semiconductor substrate, and between the first gate electrode and the second gate electrode. A second insulating film having a charge storage portion therein. The second gate electrode is made of a silicon film having a first silicon region located on the second insulating film and a second silicon region located above the first silicon region. The second silicon region contains a p-type impurity, and the concentration of the p-type impurity in the first silicon region is lower than the concentration of the p-type impurity in the second silicon region.

  Among the inventions disclosed in this application, a method for manufacturing a semiconductor device shown in a representative embodiment includes: (a) a step of forming a first gate electrode on a semiconductor substrate with a first insulating film interposed therebetween; and b) forming a second insulating film having a charge storage portion therein on the first gate electrode. (C) a multilayer silicon film having a first silicon layer and a second silicon layer disposed on the first silicon layer and having an impurity concentration higher than the impurity concentration of the first silicon layer on the second insulating film; Forming. And (d) forming a second gate electrode by selectively removing the multilayer silicon film and leaving the multilayer silicon film on the side wall of the first gate electrode via the second insulating film. .

  Among the inventions disclosed in this application, a method for manufacturing a semiconductor device shown in a representative embodiment includes: (a) a step of forming a first gate electrode on a semiconductor substrate with a first insulating film interposed therebetween; b) forming a second insulating film having a charge storage portion therein on the first gate electrode; and (c) forming a silicon film containing no impurities on the second insulating film. . Further, (d) a step of implanting impurity ions into the silicon film, and (e) a step of performing heat treatment and diffusing the impurity ions after the step (d). And (f) forming a second gate electrode by selectively removing the silicon film and leaving the silicon film on the side wall of the first gate electrode via the second insulating film.

  Among the inventions disclosed in the present application, according to the semiconductor device described in the following representative embodiment, the characteristics of the semiconductor device can be improved.

  In addition, among the inventions disclosed in the present application, according to the method for manufacturing a semiconductor device shown in the following representative embodiment, a semiconductor device having good characteristics can be manufactured in a better manufacturing process.

FIG. 3 is a main-portion cross-sectional view showing the semiconductor device of First Embodiment; It is the elements on larger scale which expanded a part of FIG. It is an equivalent circuit diagram of a memory cell. 6 is a table showing an example of voltage application conditions to each part of a selected memory cell during “write”, “erase”, and “read”. 7 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device of First Embodiment; FIG. FIG. 6 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the first embodiment, following the step shown in FIG. 5; FIG. 7 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the first embodiment, following the step shown in FIG. 6; FIG. 8 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the first embodiment, following the step shown in FIG. 7; FIG. 9 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 8; FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 9 and showing the manufacturing process of the semiconductor device; FIG. 11 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 10; FIG. 12 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 11; FIG. 13 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 12; FIG. 14 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the first embodiment, following the step shown in FIG. 13; FIG. 15 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the first embodiment, following the step shown in FIG. 14; (A) is a band diagram in the case where the memory gate electrode is a p-type gate electrode. (B) is a band diagram in the case where the memory gate electrode is an n-type gate electrode. FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 18 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the second embodiment, following the step shown in FIG. 17; FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 3; FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 4; FIG. 21 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 4, which is subsequent to FIG. 20; FIG. 22 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the fourth embodiment, following the step shown in FIG. 21; FIG. 23 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the fourth embodiment, following the step shown in FIG. 22; It is the elements on larger scale which expanded a part of FIG. FIG. 25 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 5; FIG. 26 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the fifth embodiment, following the step shown in FIG. 25; FIG. 27 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 26; FIG. 28 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 27; FIG. 29 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 28;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same or related reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

  In addition, the impurity concentration used in the embodiment is assumed to be a concentration measured by energy dispersive X-ray spectroscopy (EDX) using a transmission electron microscope (TEM).

(Embodiment 1)
Hereinafter, the structure and manufacturing method of the semiconductor device of the present embodiment will be described in detail with reference to the drawings.

[Description of structure]
FIG. 1 is a main part sectional view showing a semiconductor device of the present embodiment, and FIG. 2 is a partly enlarged sectional view in which a part of FIG. 1 is enlarged. 1 and 2 are cross-sectional views of the final process in the description of the semiconductor device manufacturing process described later.

  First, the semiconductor device described in this embodiment includes a nonvolatile memory (nonvolatile semiconductor memory device (EEPROM, flash memory, nonvolatile memory element)) and a peripheral circuit.

  The nonvolatile memory uses a trapping insulating film (an insulating film capable of storing charges) as a charge storage portion. The memory cell MC is a split gate type memory cell. That is, two MISFETs of a control transistor (selection transistor) having a control gate electrode (selection gate electrode) CG and a memory transistor having a memory gate electrode (memory gate electrode) MG are connected.

  Here, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) including a gate insulating film including a charge storage portion (charge storage layer) and a memory gate electrode MG is referred to as a memory transistor (memory transistor). The MISFET including the gate electrode CG is referred to as a control transistor (selection transistor, memory cell selection transistor).

  The peripheral circuit is a circuit for driving the nonvolatile memory, and is configured by various logic circuits, for example. The various logic circuits are configured by, for example, an n-channel type MISFET Qn, a p-channel type MISFET, etc., which will be described later.

  As shown in FIG. 1, the semiconductor device of the present embodiment includes a memory cell MC of a nonvolatile memory arranged in a memory cell region 1A of a semiconductor substrate 1, an n-channel MISFET Qn arranged in a peripheral circuit region 2A, have. In the left part of the figure, a main part sectional view of two memory cells MC sharing a source region (MS) is shown, and in the right part of the figure, a main part sectional view of an n-channel MISFET Qn constituting a peripheral circuit is shown. . The two memory cells are arranged almost symmetrically with the source region (MS) in between. A plurality of memory cells MC are further arranged in the memory cell region 1A. For example, a memory cell (not shown) sharing the drain region (MD) is arranged further to the left of the memory cell MC on the left side of the memory cell region 1A shown in FIG. Thus, the memory cells MC are arranged in the left-right direction (gate length direction) in FIG. 1 so that the shared source regions (MS) and the shared drain regions (MD) are alternately arranged, and the memory A cell column is configured. A plurality of memory cell columns are also arranged in a direction (gate width direction) perpendicular to the paper surface of FIG. Thus, a plurality of memory cells MC are formed in an array.

  As shown in FIG. 1, a semiconductor substrate (semiconductor wafer) 1 is formed with an element isolation region 2 for isolating elements. The active region partitioned (isolated) by the element isolation region 2 is formed in p Mold wells PW1 and PW2 are formed.

  In the cross section shown in the memory cell region 1A, the element isolation region 2 does not appear, but the entire memory cell region in which the memory cells MC are formed in an array is partitioned by the element isolation region 2. Further, for example, an element isolation region 2 is appropriately disposed at a place where electrical isolation is required, such as an element isolation region 2 between memory cell columns (except for the source region (MS)). Is done.

  First, the configuration of the memory cell MC in the memory cell region 1A will be described.

  The memory cell MC is disposed above the semiconductor substrate 1 (p-type well PW1) and the control gate electrode (first gate electrode) CG disposed above the semiconductor substrate 1 (p-type well PW1). The memory gate electrode (second gate electrode) MG adjacent to the CG is included. The memory cell MC is further disposed between the control gate electrode CG and the semiconductor substrate 1 (p-type well PW1), and between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1). The insulating film 5 is disposed between the memory gate electrode MG and the control gate electrode CG. The memory cell MC further includes a source region MS and a drain region MD formed in the p-type well PW1 of the semiconductor substrate 1.

  The control gate electrode CG and the memory gate electrode MG are arranged in the horizontal direction (gate length direction) in FIG. 1 on the main surface of the semiconductor substrate 1 with the insulating film 5 interposed between the opposing side surfaces (side walls). They are arranged side by side. The extending direction of the control gate electrode CG and the memory gate electrode MG is a direction (gate width direction) perpendicular to the paper surface of FIG. The control gate electrode CG and the memory gate electrode MG are formed above the semiconductor substrate 1 (p-type well PW1) between the drain region MD and the source region MS via the insulating films 3 and 5 (however, the control gate electrode CG is an insulating film). 3, the memory gate electrode MG is formed via the insulating film 5), the memory gate electrode MG is located on the source region MS side, and the control gate electrode CG is located on the drain region MD side. In this specification, the source region MS and the drain region MD are defined on the basis of the reading operation. A semiconductor region to which a high voltage is applied during a write operation, which will be described later, is collectively referred to as a source region MS, and a semiconductor region to which a low voltage is applied during a write operation is referred to as a drain region MD.

  The control gate electrode CG and the memory gate electrode MG are adjacent to each other with the insulating film 5 interposed therebetween, and the memory gate electrode MG is connected to the side wall portion of the control gate electrode CG via the insulating film 5 via the sidewall spacer. Arranged in a shape. The insulating film 5 extends over both the region between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) and the region between the memory gate electrode MG and the control gate electrode CG. .

  An insulating film 3 (that is, an insulating film 3 under the control gate electrode CG) formed between the control gate electrode CG and the semiconductor substrate 1 (p-type well PW1) functions as a gate insulating film of the control transistor, and is a memory gate. The insulating film 5 between the electrode MG and the semiconductor substrate 1 (p-type well PW1) (that is, the insulating film 5 under the memory gate electrode MG) is a gate insulating film of the memory transistor (a gate insulating film having a charge storage portion inside). ).

  The insulating film 3 can be formed of, for example, a silicon oxide film or a silicon oxynitride film. Further, as the insulating film 3, a metal oxide film having a dielectric constant higher than that of the silicon nitride film, such as a hafnium oxide film, an aluminum oxide film (alumina), or a tantalum oxide film, other than the above-described silicon oxide film or silicon oxynitride film. May be used.

  As shown in FIG. 2, the insulating film 5 includes, for example, a silicon oxide film (oxide film) 5a, a silicon nitride film (nitride film, charge storage layer) 5b on the silicon oxide film 5a, and silicon nitride. It consists of a laminated film having a silicon oxide film (oxide film) 5c on the film 5b.

  In FIG. 1, in order to make the drawing easier to see, the laminated film of the silicon oxide film 5a, the silicon nitride film 5b, and the silicon oxide film 5c is simply shown as the insulating film 5 (the same applies to FIGS. 5 to 15). ).

  Of the insulating film 5, the silicon nitride film 5b is an insulating film for accumulating charges and functions as a charge accumulating layer (charge accumulating portion). That is, the silicon nitride film 5 b is a trapping insulating film formed in the insulating film 5. Therefore, the insulating film 5 can be regarded as an insulating film having a charge storage portion (charge storage layer, here, the silicon nitride film 5b) inside.

  The silicon oxide film 5c and the silicon oxide film 5a located above and below the silicon nitride film 5b function as a charge block layer (charge block film, charge confinement layer).

  As described above, the silicon nitride film 5b is sandwiched between the silicon oxide film 5c and the silicon oxide film 5a, whereby charges can be accumulated in the silicon nitride film 5b. The laminated film of the silicon oxide film 5a, the silicon nitride film 5b, and the silicon oxide film 5c may be referred to as an ONO (oxide-nitride-oxide) film.

  Among the insulating films 5, the insulating film 5 between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) is a memory transistor in a state of retaining charges (electrons or holes) or not retaining charges. Functions as a gate insulating film. The insulating film 5 between the memory gate electrode MG and the control gate electrode CG functions as an insulating film for insulating (electrically separating) the memory gate electrode MG and the control gate electrode CG.

  A channel region of the memory transistor is formed under the insulating film 5 under the memory gate electrode MG, and a channel region of the control transistor is formed under the insulating film 3 under the control gate electrode CG. In the channel formation region of the control transistor under the insulating film 3 under the control gate electrode CG, a semiconductor region (p-type semiconductor region or n-type semiconductor region) for adjusting the threshold value of the control transistor is formed as necessary. ing. In the channel formation region of the memory transistor under the insulating film 5 under the memory gate electrode MG, a semiconductor region for adjusting the threshold value of the memory transistor (p-type semiconductor region or n-type semiconductor region) is formed as necessary. ing.

  As described above, in the write operation, the source region MS is a semiconductor region to which a high voltage is applied, and the drain region MD is a semiconductor region to which a low voltage is applied. These regions MS and MD are formed of a semiconductor region (n-type impurity diffusion layer) into which an n-type impurity is introduced.

Among these, the drain region MD is a region having an LDD (lightly doped drain) structure. That is, the drain region MD includes an n ⁻ type semiconductor region (low concentration impurity diffusion layer) 7b and an n ⁺ type semiconductor region (high concentration impurity diffusion layer) 8b having an impurity concentration higher than that of the n ⁻ type semiconductor region 7b. Have. The n ⁺ type semiconductor region 8b has a deeper junction depth and a higher impurity concentration than the n ⁻ type semiconductor region 7b.

On the other hand, the source region MS does not have an LDD structure, and is composed only of an n ⁻ type semiconductor region (low concentration impurity diffusion layer) 7a. The n ⁻ type semiconductor region 7a is an n type impurity region having a lower concentration than the n ⁺ type semiconductor region (high concentration impurity diffusion layer) 8b. For example, the n ⁻ type semiconductor region 7a has an order of n × E20 / cm ³ (n: 1 to 10). It is an area | region below a density | concentration, More preferably, it is an area | region below a 2 * E20 / cm < ³ > density | concentration. E20 represents 10 to the 20th power (10 ²⁰ ). Further, for example, the n ⁻ type semiconductor region 7a can have a junction depth similar to that of the n ⁻ type semiconductor region 7b. Further, n ^- -type semiconductor regions 7a has a lower impurity concentration than the ^{n +} -type semiconductor region 8b, also a shallow junction depth than ^{the n +} -type semiconductor region 8b.

  A sidewall insulating film (sidewall, sidewall spacer) SW made of an insulator (silicon oxide film, insulating film) such as silicon oxide is formed on the sidewall portion of the combined pattern of the memory gate electrode MG and the control gate electrode CG. Yes. That is, the side (side surface) of the memory gate electrode MG opposite to the side adjacent to the control gate electrode CG via the insulating film 5 and the side adjacent to the memory gate electrode MG via the insulating film 5 are opposite. A sidewall insulating film SW is formed on the sidewall (side surface) of the control gate electrode CG on the side.

The n ⁻ type semiconductor region 7a of the source region MS is formed in a self-aligned manner with respect to the sidewall of the memory gate electrode MG. Therefore, the low-concentration n ⁻ type semiconductor region 7a is formed under the side wall insulating film SW on the side wall portion of the memory gate electrode MG. Therefore, the low concentration n ⁻ type semiconductor region 7a is formed adjacent to the channel region of the memory transistor.

The n ⁻ type semiconductor region 7b of the drain region MD is formed in a self-aligned manner with respect to the side wall of the control gate electrode CG, and the n ⁺ type semiconductor region 8b is self-aligned with respect to the side surface of the side wall insulating film SW on the control gate electrode CG side. It is formed consistently. For this reason, the low-concentration n ⁻ type semiconductor region 7b is formed under the side wall insulating film SW on the control gate electrode CG side. Further, the high concentration n ⁺ type semiconductor region 8b is formed outside the low concentration n ⁻ type semiconductor region 7b. Therefore, the low concentration n ⁻ type semiconductor region 7b is formed adjacent to the channel region of the control transistor, the high concentration n ⁺ type semiconductor region 8b is in contact with the low concentration n ⁻ type semiconductor region 7b, and the control transistor The n ⁻ type semiconductor region 7b is formed so as to be separated from the channel region.

  The control gate electrode CG is made of a conductive film (conductor film), but is preferably made of a silicon film 4 such as an n-type polycrystalline silicon film (polycrystalline silicon film doped with n-type impurities, doped polysilicon film). Become. The silicon film 4 is an n-type silicon film and has a low resistivity by introducing n-type impurities. Specifically, the control gate electrode CG is made of a patterned silicon film 4.

  The memory gate electrode MG is formed of a silicon film 6 as shown in FIGS. The silicon film 6 is formed by a non-doped silicon film 6 a in the vicinity of a region in contact with the insulating film 5, and the region extends along the surface of the semiconductor substrate 1. The region on the non-doped silicon film 6a is formed by the doped silicon film 6b into which p-type impurities are introduced. In other words, the silicon film 6 is a laminated film of a non-doped silicon film 6a and a doped silicon film 6b, with the non-doped silicon film 6a being the lower layer and the doped silicon film 6b being the upper layer. The non-doped silicon film 6a is made of a non-doped (undoped) silicon film, and the doped silicon film 6b is made of a silicon film into which p-type impurities are introduced (doped). The p-type impurity is, for example, boron (B) or indium (In).

  Here, the non-doped silicon film means a silicon film (intrinsic silicon film) that does not contain impurities (introduction, addition, doping, implantation). Note that the term “non-doped silicon film” does not exclude the case where a small amount of unintentional impurities are included. On the other hand, the silicon film into which impurities are introduced (doped) means a silicon film intentionally containing impurities (introduced, added, doped, implanted).

  Therefore, the impurity concentration of the doped silicon film 6b is higher than the impurity concentration of the non-doped silicon film 6a, and the resistivity (specific resistance) of the doped silicon film 6b is lower than the resistivity (specific resistance) of the non-doped silicon film 6a. ing.

  As described above, the non-doped silicon film 6a is the lower layer and the doped silicon film 6b is the upper layer. That is, the non-doped silicon film 6a is located on the insulating film 5, and the doped silicon film 6b is located on the non-doped silicon film 6a.

  In the present embodiment, the non-doped silicon film 6a and the insulating film 5 are also interposed between the doped silicon film 6b and the control gate electrode CG (FIGS. 1 and 2). That is, the non-doped silicon film 6a is positioned in parallel to the surface of the semiconductor substrate 1 (p-type well PW1), that is, extends horizontally to a horizontal portion formed horizontally and to the surface of the semiconductor substrate 1. And a vertical portion. The insulating film 5 includes a horizontal portion that is positioned in parallel with the surface of the semiconductor substrate 1, that is, is formed horizontally, and a vertical portion that extends substantially perpendicular to the surface of the semiconductor substrate 1. In other words, the insulating film 5 and the non-doped silicon film 6a are respectively arranged in an L shape or an inverted L shape in the cross section in the gate length direction.

A metal silicide layer (metal silicide film) 11 is formed on the upper portion (upper surface) of the memory gate electrode MG, the upper portion (upper surface) of the control gate electrode CG, and the upper surfaces (front surfaces) of the n ⁻ type semiconductor region 7a and the n ⁺ type semiconductor region 8b. Is formed. The metal silicide layer 11 is made of, for example, a cobalt silicide layer or a nickel silicide layer. The metal silicide layer 11 can reduce diffusion resistance and contact resistance. In addition, from the viewpoint of preventing a short circuit between the memory gate electrode MG and the control gate electrode CG as much as possible, the metal silicide layer 11 may not be formed on one or both of the memory gate electrode MG and the control gate electrode CG. obtain.

  Next, the n-channel MISFET Qn in the peripheral circuit region 2A will be described.

  As shown on the right side of FIG. 1, the n-channel MISFET Qn includes a gate electrode GE disposed above the semiconductor substrate 1 (p-type well PW2), and between the gate electrode GE and the semiconductor substrate 1 (p-type well PW2). The insulating film 3 is disposed, and the source and drain regions (7, 8) formed in the semiconductor substrate 1 (p-type well PW2) on both sides of the gate electrode GE.

  The extending direction of the gate electrode GE is a direction (gate width direction) perpendicular to the paper surface of FIG. The insulating film 3 disposed between the gate electrode GE and the semiconductor substrate 1 (p-type well PW2) functions as a gate insulating film of the n-channel type MISFET Qn. A channel region of the n-channel type MISFET Qn is formed under the insulating film 3 under the gate electrode GE.

The source and drain regions (7, 8) have an LDD structure and are composed of an n ⁺ type semiconductor region 8 and an n ⁻ type semiconductor region 7. The n ⁺ type semiconductor region 8 has a deeper junction depth and a higher impurity concentration than the n ⁻ type semiconductor region 7.

  A sidewall insulating film (sidewall, sidewall spacer) SW made of an insulator (silicon oxide film, insulating film) such as silicon oxide is formed on the sidewall portion of the gate electrode GE.

The n ⁻ type semiconductor region 7 is formed in a self-aligned manner with respect to the side wall of the gate electrode GE. For this reason, the low-concentration n ⁻ type semiconductor region 7 is formed under the side wall insulating film SW on the side wall portion of the gate electrode GE. Therefore, the low concentration n ⁻ type semiconductor region 7 is formed adjacent to the channel region of the MISFET. The n ⁺ type semiconductor region 8 is formed in a self-aligned manner with respect to the side surface of the sidewall insulating film SW. Thus, the low concentration n ⁻ type semiconductor region 7 is formed adjacent to the channel region of the MISFET, the high concentration n ⁺ type semiconductor region 8 is in contact with the low concentration n ⁻ type semiconductor region 7, and the MISFET The n ⁻ type semiconductor region 7 is formed so as to be separated from the channel region.

  The gate electrode GE is composed of a conductive film (conductor film). For example, similarly to the control gate electrode CG, an n-type polycrystalline silicon film (polycrystalline silicon film doped with n-type impurities, doped polysilicon film) It is preferable to use the silicon film 4 as described above.

A metal silicide layer 11 is formed on the top (upper surface) of the gate electrode GE and the upper surface (front surface) of the n ⁺ -type semiconductor region 8. The metal silicide layer 11 is made of, for example, a cobalt silicide layer or a nickel silicide layer. The metal silicide layer 11 can reduce diffusion resistance and contact resistance.

[Description of operation]
FIG. 3 is an equivalent circuit diagram of the memory cell MC. As shown in the figure, a memory transistor and a control transistor are connected in series between a drain region (MD) and a source region (MS) to constitute one memory cell. FIG. 4 is a table showing an example of voltage application conditions to each part of the selected memory cell during “write”, “erase”, and “read” in the present embodiment. In the table of FIG. 4, the voltage Vmg applied to the memory gate electrode MG, the voltage Vs applied to the source region (source region MS), and the control gate electrode at the time of “write”, “erase”, and “read”, respectively. A voltage Vcg applied to CG, a voltage Vd applied to the drain region (drain region MD), and a voltage Vb applied to the p-type well PW1 are described. Note that what is shown in the table of FIG. 4 is a preferred example of the voltage application conditions, and is not limited to this, and can be variously changed as necessary. In the present embodiment, the electron injection into the silicon nitride film 5b which is the charge storage layer (charge storage portion) in the insulating film 5 of the memory transistor is “writing”, and the hole is injected. Is defined as “erase”.

  As the writing method, hot electron writing called a so-called SSI (Source Side Injection) method can be used. For example, a voltage as shown in the “write” column of FIG. 4 is applied to each part of the selected memory cell to be written, and electrons (electrons) are contained in the silicon nitride film 5b in the insulating film 5 of the selected memory cell. Inject. Hot electrons are generated in the channel region (between the source and drain) between the two gate electrodes (memory gate electrode MG and control gate electrode CG), and the charge storage layer in the insulating film 5 below the memory gate electrode MG. Hot electrons are injected into the silicon nitride film 5b which is a (charge storage portion). The injected hot electrons (electrons) are captured by the trap level in the silicon nitride film 5b in the insulating film 5, and as a result, the threshold voltage of the memory transistor rises.

  As an erasing method, a BTBT (Band-To-Band Tunneling) hot hole injection erasing method can be used. That is, erasing is performed by injecting holes generated by BTBT (band-to-band tunneling phenomenon) into the charge storage portion (the silicon nitride film 5b in the insulating film 5). For example, a voltage as shown in the “erase” column of FIG. 4 is applied to each part of the selected memory cell to be erased, holes are generated by the BTBT phenomenon, and the electric field is accelerated, whereby the insulating film 5 of the selected memory cell is Holes are injected into the silicon nitride film 5b, thereby lowering the threshold voltage of the memory transistor.

  At the time of reading, for example, a voltage as shown in the “read” column of FIG. 4 is applied to each part of the selected memory cell to be read. By setting the voltage Vmg applied to the memory gate electrode MG at the time of reading to a value between the threshold voltage of the memory transistor in the writing state and the threshold voltage of the memory transistor in the erasing state, current flows in the memory cell. The writing state and the erasing state can be discriminated depending on whether or not it flows.

  In the present embodiment, as described above, the writing method is described as the SSI method, and the erasing method is the BTBT hot hole injection erasing method. However, the present invention is not limited to these, and the FN (Fowler Nordheim) method is used. It is also possible to perform writing or erasing by an operation method by electron or hole tunneling.

[Product description]
Next, the method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 5 to 15 and the configuration of the semiconductor device will be further clarified. 5 to 15 are main-portion cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment.

  First, as shown in FIG. 5, as a semiconductor substrate (semiconductor wafer) 1, a silicon substrate made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm is prepared. A semiconductor substrate 1 other than the silicon substrate may be used.

  The semiconductor substrate 1 has a memory cell region 1A where a memory cell MC of a nonvolatile memory is formed, and a peripheral circuit region 2A where an n-channel MISFET Qn constituting a peripheral circuit is formed.

  Next, the element isolation region 2 is formed on the main surface of the semiconductor substrate 1. For example, an element isolation region 2 is formed by forming an element isolation groove in the semiconductor substrate 1 and embedding an insulating film in the element isolation groove. Such an element isolation method is called an STI (Shallow Trench Isolation) method. In addition, the element isolation region 2 may be formed using a LOCOS (Local Oxidization of Silicon) method or the like.

  Next, a p-type well PW1 is formed in the memory cell region 1A of the semiconductor substrate 1, and a p-type well PW2 is formed in the peripheral circuit region 2A of the semiconductor substrate 1, respectively. The p-type wells PW1 and PW2 are formed by ion implantation of a p-type impurity (for example, boron (B)).

  Next, after cleaning the surface of the semiconductor substrate 1 (p-type wells PW1, PW2) by dilute hydrofluoric acid cleaning or the like, as shown in FIG. 6, the main surface of the semiconductor substrate 1 (surfaces of the p-type wells PW1, PW2) Further, as the insulating film (gate insulating film) 3, for example, a silicon oxide film is formed with a film thickness of about 2 to 3 nm by a thermal oxidation method. As the insulating film 3, in addition to the silicon oxide film, another insulating film such as a silicon oxynitride film may be used. Further, in addition to the thermal oxidation method, a CVD (Chemical Vapor Deposition) method may be used.

  Next, a silicon film 4 is formed on the entire surface of the semiconductor substrate 1 as a conductive film (conductor film). As the silicon film 4, for example, a polycrystalline silicon film containing an n-type impurity (for example, arsenic (As) or phosphorus (P)) is formed with a film thickness of about 100 to 200 nm using a CVD method or the like. As the silicon film 4, an amorphous silicon film may be deposited and crystallized by heat treatment. When n-type impurities are introduced when the silicon film 4 is formed, the doping gas (gas for adding n-type impurities) is included in the film-forming gas so that the silicon film 4 containing n-type impurities is added. A film can be formed. Note that n-type impurities (impurity ions) may be introduced by an ion implantation method or the like after the silicon film is formed.

  Next, a photoresist film (not shown) is formed using a photolithography method in a region where the control gate electrode CG of the silicon film 4 is to be formed, and the silicon film 4 is etched using this photoresist film as a mask. . Subsequently, the control gate electrode CG is formed by removing the photoresist film by ashing or the like. A series of steps from photolithography to removal of the photoresist film is called patterning.

  Here, in the memory cell region 1A, the insulating film 3 remaining under the control gate electrode CG becomes the gate insulating film of the control transistor. The insulating film 3 other than the portion covered with the control gate electrode CG can be removed by a subsequent patterning process or the like.

  Next, if necessary, channel dope ion implantation is performed on the surface portion (surface layer portion) of the p-type well PW1 in the memory cell region 1A in order to adjust the threshold voltage of the memory transistor.

  Next, after cleaning the main surface of the semiconductor substrate 1, as shown in FIG. 7, an insulating film (gate insulating film) 5 is formed on the semiconductor substrate 1 including the surface (upper surface and side surfaces) of the control gate electrode CG. Then, an insulating film having a charge storage portion is formed inside. Here, as the insulating film 5, a laminated film in which a silicon oxide film 5a, a silicon nitride film 5b, and a silicon oxide film 5c are laminated in order from the bottom is formed. For example, first, the silicon oxide film 5a is oxidized on the surface of the semiconductor substrate 1 (p-type well PW1) and the surface (side surface and upper surface) of the control gate electrode CG by a thermal oxidation method (preferably ISSG (In Situ Steam Generation)). ), For example, with a film thickness of about 3 to 6 nm. Next, a silicon nitride film 5b is deposited with a thickness of about 5 to 10 nm by a CVD method, and a silicon oxide film 5c is formed with a thickness of about 4 to 7 nm by a CVD method. Thereby, the insulating film 5 made of a laminated film of the silicon oxide film 5a, the silicon nitride film 5b, and the silicon oxide film 5c can be formed (see FIG. 2). Note that the silicon oxide film 5a may be formed by a CVD method. Alternatively, the silicon oxide film 5c may be formed by oxidizing the upper layer portion of the silicon nitride film 5b. In this case, the breakdown voltage of the silicon oxide film 5c increases.

  In the present embodiment, the silicon nitride film 5b is formed as a charge storage portion (charge storage layer, insulating film having a trap level) inside the insulating film 5. However, for example, an aluminum oxide film, an oxide film Other insulating films such as a hafnium film or a tantalum oxide film may be used. These films are high dielectric constant films having a higher dielectric constant than the silicon nitride film. Further, the charge storage layer may be formed of silicon nanodots.

  The insulating film 5 formed in the memory cell region 1A functions as a gate insulating film of the memory gate electrode MG and has a charge holding (charge storage) function. Therefore, it has a laminated structure of at least three layers and is configured such that the potential barrier height of the inner layer (silicon nitride film 5b) is lower than the potential barrier height of the outer layers (silicon oxide films 5a and 5c). To do.

  Next, a non-doped polycrystalline silicon film is formed as a non-doped silicon film 6a on the insulating film 5 with a film thickness of about 30 to 80 nm using a CVD method or the like. That is, at the time of film formation, the polycrystalline silicon film (6a) is formed without including a doping gas (impurity addition gas) in the source gas.

  Next, as shown in FIGS. 8 and 9, a doped silicon film (doped silicon layer, doped silicon portion) 6b is formed on the surface of the non-doped silicon film 6a. The doped silicon film 6b is formed by implanting p-type impurities (for example, boron (B) or indium (In)) into the surface of the non-doped silicon film 6a by oblique ion implantation (FIG. 8).

  As the oblique ion implantation step, as shown in FIG. 8, p-type impurities are implanted into the semiconductor substrate 1 at a predetermined angle θ (for example, 45 °) of less than 90 °. A p-type impurity is implanted at an angle of 180-θ (for example, 135 °). According to this oblique ion implantation, p-type impurities are also implanted into the surface of the non-doped silicon film 6a located on the side surface of the control gate electrode CG.

When boron is ion-implanted, for example, it is implanted at a concentration of about 5E15 / cm ² with an energy of 4 keV. Note that 5E15 represents 5 × 10 ¹⁵ . Further, in the case of ion implantation of indium, for example, it is implanted at a concentration of about 5E15 / cm ² with an energy of 50 keV.

  By this step, the non-doped silicon film 6a is present in the region in contact with the insulating film 5, and the doped silicon film 6b is formed in the region on the non-doped silicon film 6a. As shown in FIG. 9, a stacked film (multilayer silicon film) made of the silicon film 6 is formed on the surface (side surface and upper surface) of the control gate electrode CG with the insulating film 5 interposed therebetween. It can be said that the lower side of the laminated film is the non-doped silicon film 6a and the upper side is the doped silicon film 6b.

  The implantation region of the p-type impurity is, for example, about 20 to 50 nm from the surface of the non-doped silicon film 6a. In other words, the film thickness (thickness) t2 of the doped silicon film 6b is about 20 to 50 nm. As a result, a non-doped polycrystalline silicon film remains as a non-doped silicon film 6a on the insulating film 5 with a film thickness (thickness) t1 of about 10 to 30 nm (FIG. 9).

  In the relationship between t1 and t2, it is preferable that t1 <t2. This p-type impurity implantation region (t2) can be adjusted by controlling implantation conditions, impurity ion implantation (implantation) energy, impurity ion implantation concentration (implantation amount, dose amount), and the like.

  In forming the non-doped silicon film 6a, an amorphous silicon film may be formed and polycrystallized by heat treatment. In addition to the above implantation conditions, the p-type impurity implantation region (t2) takes into account the thermal diffusion of impurity ions due to the subsequent thermal load (heat treatment step), and has the predetermined film thickness in the final step. Preferably it is formed.

  Next, the silicon film 6 which is a laminated film of the non-doped silicon film 6a and the doped silicon film 6b is etched back (selectively removed). In this etch back step, the silicon film 6 is removed from the surface by anisotropic dry etching by a predetermined thickness. By this step, as shown in FIG. 10, the silicon film 6 can be left in the form of a side wall spacer on the side wall portions on both sides of the control gate electrode CG via the insulating film 5. The memory gate electrode MG is formed by the silicon film 6 (6a, 6b, sidewall film) remaining on one of the sidewall portions of the control gate electrode CG. Further, the silicon spacer SP1 is formed by the silicon film 6 (6a, 6b, sidewall film) remaining on the other sidewall portion. The memory gate electrode MG and the silicon spacer SP1 are formed on side walls opposite to each other of the control gate electrode CG, and have a substantially symmetrical structure with the control gate electrode CG interposed therebetween.

  The insulating film 5 under the memory gate electrode MG becomes a gate insulating film of the memory transistor. The memory gate length (gate length of the memory gate electrode MG) is determined by the deposited film thickness of the silicon film 6 (that is, the film thickness of 6a and 6b). Therefore, the memory gate length can be adjusted by adjusting the deposited film thickness of the silicon film 6 (that is, t1 + t2).

  Next, using a photolithography technique, a photoresist film (not shown) that covers the memory gate electrode MG and exposes the silicon spacer SP1 is formed on the semiconductor substrate 1. By dry etching using this photoresist film as an etching mask, the silicon spacer SP1 is removed as shown in FIG. Thereafter, the photoresist film is removed by ashing or the like.

  Next, a portion of the insulating film 5 that is exposed without being covered with the memory gate electrode MG is removed by etching (for example, wet etching). At this time, the insulating film 5 is etched and the silicon film 4 is exposed in the peripheral circuit region 2A.

  Next, in the peripheral circuit region 2A, a photoresist film (not shown) is formed using a photolithography method in a region where the gate electrode GE of the n-channel MISFET Qn of the silicon film 4 is to be formed, and this photoresist film is masked. Then, the silicon film 4 is etched. Subsequently, the gate electrode GE is formed by removing the photoresist film by ashing or the like. The insulating film 3 remaining under the gate electrode GE becomes the gate insulating film of the n-channel type MISFET Qn. The insulating film 3 other than the portion covered with the gate electrode GE may be removed when the gate electrode GE is formed, or may be removed by a subsequent patterning process or the like.

Next, as shown in FIG. 12, in the memory cell region 1A, an n-type impurity such as arsenic (As) or phosphorus (P) is implanted into the semiconductor substrate 1 (p-type well PW1) on the control gate electrode CG side. Thus, the n ⁻ type semiconductor region 7b is formed. Also, an n ⁻ type semiconductor region 7a is formed by implanting an n type impurity such as arsenic (As) or phosphorus (P) into the semiconductor substrate 1 (p type well PW1) between adjacent memory gate electrodes MG. To do. At this time, n ^- -type semiconductor regions 7a are (is and adjacent side control gate electrode CG via the insulating film 5 opposite side wall of) the sidewalls of the memory gate electrode MG are formed self-aligned to, n ^- -type The semiconductor region 7b is formed in self-alignment with the side wall of the control gate electrode CG (the side wall opposite to the side adjacent to the memory gate electrode MG via the insulating film 5). The n ⁻ type semiconductor region 7a and the n ⁻ type semiconductor region 7b may be formed by the same ion implantation process, but here are formed by different ion implantation processes. As described above, the n ⁻ -type semiconductor region 7a and the n ⁻ -type semiconductor region 7b can be formed with a desired impurity concentration and a desired junction depth by forming them in different ion implantation steps. On the other hand, when implanting impurities in different ion implantation steps, it is preferable to form a photoresist film in a region that is not implanted in the n ⁻ type semiconductor region 7a or the n ⁻ type semiconductor region 7b (not shown). Here, in the case where the n ⁻ type semiconductor region 7a aligned with the memory gate electrode MG is formed by different ion implantation processes, at least the n ⁻ type semiconductor region 7b can be considered as a region where it is preferable to form a photoresist film. However, in the present embodiment, as described above, since the p-type impurity is introduced as the impurity into the silicon film 6 that forms the memory gate electrode MG, the doped silicon film 6b that constitutes the memory gate electrode MG. In order not to cancel (cancel) the p-type impurity therein and the n-type impurity implanted when forming the n ⁻ type semiconductor region 7a, the photoresist film is formed to cover the memory gate electrode MG. It is desirable to do. However, it may be difficult to form a photoresist film so that the memory gate electrode MG is just covered depending on the accuracy of photolithography. In that case, a photoresist film is not formed on a part of the memory gate electrode MG, and a part of the n-type impurity at the time of forming the n ⁻ -type semiconductor region 7a is implanted into the memory gate electrode MG, It is conceivable to cancel the p-type impurity in the doped silicon film 6b constituting the memory gate electrode MG. However, even in such a case, the p-type impurity concentration in the doped silicon film 6b constituting the <1> memory gate electrode MG is sufficiently higher than the impurity concentration in the n ⁻ type semiconductor region 7a. is there. <2> As shown in FIG. 12, the junction depth t4 of the n ⁻ type semiconductor region 7a is formed smaller than the height t3 of the doped silicon film 6b in the memory gate electrode MG. Because of the above <1> and <2>, it is considered that the characteristics of the memory cell MC formed in the present embodiment are hardly affected.

Further, in the peripheral circuit region 2A, an n ⁻ type semiconductor is implanted by injecting an n type impurity such as arsenic (As) or phosphorus (P) into the semiconductor substrate 1 (p type well PW2) on both sides of the gate electrode GE. Region 7 is formed. At this time, the n ⁻ type semiconductor region 7 is formed in self-alignment with the sidewall of the gate electrode GE.

  Next, as shown in FIG. 13, in the memory cell region 1 </ b> A, for example, a silicon oxide or silicon nitride film or a stack of a silicon oxide film and a silicon nitride film is formed on the side wall portion of the combined pattern of the control gate electrode CG and the memory gate electrode MG. A sidewall insulating film SW made of an insulating film such as a film is formed. In the peripheral circuit region 2A, a sidewall insulating film SW is formed on the sidewall portion of the gate electrode GE. For example, an insulating film such as a silicon oxide film is deposited on the entire main surface of the semiconductor substrate 1, and the insulating film is etched back to thereby form the side wall portion of the synthetic pattern (CG, MG) and the side wall portion of the gate electrode GE. Then, the sidewall insulating film SW is formed.

Next, as shown in FIG. 14, in the memory cell region 1A, a photoresist film PR1 is formed so as to cover at least the n ⁻ type semiconductor region 7a exposed from between the sidewall insulating films SW and the memory gate electrodes MG on both sides thereof. To do. Note that when an n-type impurity to be described later is implanted, it is necessary to cover a p-channel MISFET formation region (not shown) with a photoresist film in the peripheral circuit region 2A. If the photoresist film PR1 is left during the formation of the photoresist film, the photoresist film formation process (exposure mask) does not increase.

Next, using this photoresist film (mask film) PR1, control gate electrode CG, memory gate electrode MG and sidewall insulating film SW as a mask, an n-type impurity such as arsenic (As) or phosphorus (P) is added to the semiconductor substrate 1 ( By implantation into the p-type well PW1), a high impurity concentration n ⁺ -type semiconductor region 8b is formed. At this time, the n ⁺ type semiconductor region 8b is formed in self-alignment with the sidewall insulating film SW on the control gate electrode CG side in the memory cell region 1A. The n ⁺ type semiconductor region 8b is formed as a semiconductor region having a higher impurity concentration and a deeper junction than the n ⁻ type semiconductor region 7a and the n ⁻ type semiconductor region 7b. In the peripheral circuit region 2A, an n ⁺ type semiconductor such as arsenic (As) or phosphorus (P) is implanted into the semiconductor substrate 1 (p type well PW2) on both sides of the gate electrode GE. Region 8 is formed. At this time, the n ⁺ type semiconductor region 8 is formed in self-alignment with the sidewall insulating film SW on the sidewall portion of the gate electrode GE in the peripheral circuit region 2A. As a result, in the peripheral circuit region 2A, source and drain regions (7, 8) having an LDD structure are formed on both sides of the gate electrode GE.

On the other hand, in the memory cell region 1A, since the photoresist film PR1 is formed so as to cover the n ⁻ type semiconductor region 7a and the memory gate electrodes MG on both sides thereof, the region, that is, between the memory gate electrodes MG, is formed. In the semiconductor substrate 1 (p-type well PW1) located, a high concentration impurity region is not formed. Further, the n-type impurity is not implanted into the memory gate electrode MG, and the p-type impurity in the doped silicon film 6b constituting the memory gate electrode MG is not canceled (cancelled).

By the above process, the n ⁻ type semiconductor region 7b and the n ⁺ type semiconductor region 8b having a higher impurity concentration constitute an n type drain region MD that functions as the drain region of the memory transistor, and the n ⁻ type semiconductor region Only 7a constitutes an n-type source region MS that functions as a source region of the control transistor.

Next, the impurities introduced into the source region MS (n ⁻ type semiconductor region 7a), the drain region MD (n ⁻ type semiconductor region 7b and n ⁺ type semiconductor region 8b), and the source and drain regions (7, 8) are activated. A heat treatment is performed to make it.

  Through the above steps, the memory cell MC of the nonvolatile memory is formed in the memory cell region 1A, and the n-channel MISFET Qn is formed in the peripheral circuit region 2A (see FIG. 15).

Next, if necessary, wet etching using, for example, diluted hydrofluoric acid is performed to clean the main surface of the semiconductor substrate 1. Thereby, the upper surface of the n ⁻ type semiconductor region 7a, the upper surface of the n ⁺ type semiconductor region 8b, the upper surface of the control gate electrode CG, and the upper surface of the memory gate electrode MG are cleaned, and unnecessary substances such as a natural oxide film are removed. The Further, the upper surface of the n ⁺ type semiconductor region 8 and the upper surface of the gate electrode GE are cleaned, and unnecessary materials such as a natural oxide film are removed.

Next, metal silicide layers (metal silicide films) 11 are respectively formed on the control gate electrode CG, the memory gate electrode MG, the n ⁻ type semiconductor region 7a, and the n ⁺ type semiconductor region 8b by using the salicide technique. In addition, metal silicide layers 11 are formed on the gate electrode GE and the n ⁺ type semiconductor region 8, respectively. With this metal silicide layer 11, diffusion resistance, contact resistance, and the like can be reduced. The metal silicide layer 11 can be formed as follows.

For example, a metal film (not shown) is formed on the entire main surface of the semiconductor substrate 1, and the semiconductor substrate 1 is subjected to heat treatment, whereby the control gate electrode CG, the memory gate electrode MG, the gate electrode GE, n The upper layer portion of the ⁻ type semiconductor region 7a and the n ⁺ type semiconductor regions 8 and 8b are reacted with the metal film. As a result, the metal silicide layers 11 are formed on the control gate electrode CG, the memory gate electrode MG, the gate electrode GE, the n ⁻ type semiconductor region 7a, and the n ⁺ type semiconductor regions 8 and 8b, respectively. The metal film is made of, for example, a cobalt (Co) film or a nickel (Ni) film, and can be formed using a sputtering method or the like.

  Next, after removing the unreacted metal film, an insulating film (interlayer insulating film) 12 is formed on the entire main surface of the semiconductor substrate 1, for example, a single film of a silicon oxide film or a silicon nitride film and the silicon nitride. A stacked film with a silicon oxide film formed thicker than the silicon nitride film is formed on the film by using, for example, a CVD method. After the formation of the insulating film 12, the upper surface of the insulating film 12 is flattened using a CMP (Chemical Mechanical Polishing) method or the like as necessary.

Next, the insulating film 12 is dry etched to form contact holes (openings, through holes) in the insulating film 12. Next, a laminated film of the barrier conductor film 13a and the main conductor film 13b is formed in the contact hole. Next, the unnecessary main conductor film 13b and barrier conductor film 13a on the insulating film 12 are removed by a CMP method, an etch back method, or the like, thereby forming a plug PG. For example, the plug PG is formed above the n ⁺ type semiconductor regions 8 and 8b. Although not shown in the cross section shown in FIG. 1, the plug PG is also formed, for example, on the n ⁻ type semiconductor region 7a, the control gate electrode CG, the memory gate electrode MG, and the gate electrode GE. As the barrier conductor film 13a, for example, a titanium film, a titanium nitride film, or a laminated film thereof can be used. Further, a tungsten film or the like can be used as the main conductor film 13b.

  Next, by forming the wiring (wiring layer) M1 on the insulating film 12 in which the plug PG is embedded, the semiconductor device of the present embodiment shown in FIGS. 1 and 2 is formed. The wiring M1 is formed using, for example, damascene technology (here, single damascene technology).

  First, an insulating film (interlayer insulating film) 14 is formed on the insulating film 12 in which the plug PG is embedded, and a wiring trench is formed in the insulating film 14 using a photolithography technique and a dry etching technique. Next, a barrier conductor film (not shown) is formed on the main surface of the semiconductor substrate 1 including the inside of the wiring trench, and then a copper seed layer (not shown) is formed on the barrier conductor film by a CVD method or a sputtering method. Z). Next, a copper plating film is formed on the seed layer using an electrolytic plating method or the like, and the inside of the wiring groove is embedded with the copper plating film. Thereafter, the copper plating film, the seed layer, and the barrier metal film in a region other than the inside of the wiring trench are removed by CMP to form a first layer wiring M1 using copper as a main conductive material. For example, a titanium nitride film, a tantalum film, or a tantalum nitride film can be used as the barrier conductor film.

  Thereafter, the second and subsequent wirings are formed by a dual damascene method or the like, but illustration and description thereof are omitted here. In addition to the damascene technique, the wiring M1 and the wiring higher than the wiring M1 can be formed by patterning a conductive film for wiring. In this case, for example, tungsten or aluminum can be used as the conductive film.

  Thus, according to the present embodiment, the memory gate electrode MG into which the p-type impurity is introduced is formed. Thereby, the following effects are produced.

  By forming the memory gate electrode MG as a p-type gate electrode into which a p-type impurity is introduced, the hole retention characteristics of the memory cell MC are improved. FIG. 16A is a band diagram when the memory gate electrode MG is a p-type gate electrode and the semiconductor substrate 1 is a p-type as in the present embodiment. On the other hand, FIG. 16B is a band diagram when the memory gate electrode MG is an n-type gate electrode and the semiconductor substrate 1 is a p-type. The arrows in the drawing indicate that the electric field in FIG. 16A is weaker from the memory gate electrode to the semiconductor substrate than in FIG. As shown in FIG. 16A, by forming the memory gate electrode MG as a p-type gate electrode, the memory gate electrode MG is formed as an n-type gate electrode as shown in FIG. In comparison, the electric field applied to the insulating film 5 is relaxed and acts in a direction in which the electric field weakens against holes in the erased state. Therefore, the hole retention characteristics of the memory cell MC can be further improved. That is, the erased state can be maintained well and the retention is improved.

  In particular, as the semiconductor device is miniaturized, that is, the memory gate length is miniaturized, the hole retention characteristic tends to be deteriorated rather than the electron retention characteristic. Therefore, the memory gate electrode MG is made p-type, that is, the memory gate electrode. It is effective for improving retention characteristics to include MG with p-type impurities to improve hole retention characteristics.

  In addition to the above effects, in the present embodiment, in the silicon film 6 that forms the memory gate electrode MG, the vicinity of the region in contact with the insulating film 5 is formed by the non-doped silicon film 6a, and the region is a semiconductor. By extending along the surface of the substrate 1, the following effects are further obtained.

  That is, by forming the lower part of the memory gate electrode MG in contact with the insulating film 5 with the non-doped silicon film 6a, the charge retention characteristics of the memory are improved. This is because depletion is likely to occur in a region immediately above the insulating film 5, that is, below the memory gate electrode MG, and an electric field is less likely to be applied to the charge storage layer (here, the silicon nitride film 5b) in the insulating film 5. This is because charges (electrons or holes) accumulated in the charge accumulating portion are difficult to escape and charge retention characteristics are improved. In other words, the electric field in the insulating film 5 (silicon nitride film 5b) is relaxed, and it becomes difficult for charges to move from the charge storage layer to the memory gate electrode MG, so that the data retention characteristics of the nonvolatile memory can be improved.

  In this way, the memory gate electrode is formed of a p-type gate electrode, the region in contact with the insulating film 5 is formed with the non-doped silicon film 6a, and the region is formed along the surface of the semiconductor substrate 1. In each case, the above-described independent effects are obtained. However, by forming the memory cell MC as a combination of these, the hole retention characteristic is improved and the retention characteristic is further improved. It becomes possible.

  Further, by forming the memory cell MC as a combined structure, p-type impurities are introduced into the upper layer portion of the memory gate electrode MG (a doped silicon film containing p-type impurities in the upper layer portion of the memory gate electrode MG). 6b is formed), the resistance of the memory gate electrode MG can be reduced. For this reason, the operation speed of the nonvolatile memory can be improved. The memory gate electrode MG is formed in a long wiring shape (wiring that connects the memory gate electrodes MG of a plurality of memory cells arranged in the extending direction of the memory gate electrode MG). Therefore, since the resistance of the wiring itself can be reduced, the operation speed of the entire nonvolatile memory can be improved.

Further, since the source region (MS) of the memory transistor is configured only by the n ⁻ type semiconductor region 7a, the memory gate electrode MG can be covered with the photoresist film PR1, and the memory gate electrode MG (containing p-type impurities) is included. It is possible to avoid a high resistance n-type impurity being introduced into the doped silicon film 6b) to increase the resistance of the memory gate electrode MG.

  In the present embodiment, since the non-doped silicon film 6a is also interposed between the doped silicon film 6b containing the p-type impurity of the memory gate electrode MG and the control gate electrode CG, the memory gate electrode The breakdown voltage between the MG and the control gate electrode CG can be improved, and the breakdown voltage of the memory cell MC can be improved.

Further, it has been described that, when the n ⁻ type semiconductor region 7a is formed in the process shown in FIG. In the present embodiment, in order to form the memory gate electrode MG as a p-type gate electrode, p-type impurities are introduced into the silicon film 6 constituting the memory gate electrode MG. It is preferable to avoid introducing n-type impurities. However, even if it is difficult to avoid the introduction of the n-type impurity into the memory gate electrode MG as described above, it is conceivable that the following effects can be obtained.

In the process of FIG. 12, when the n-type impurity is introduced in the process of forming the n ⁻ -type semiconductor region 7a into the memory gate electrode MG into which the p-type impurity is introduced, the n-type impurity is introduced into the memory gate electrode MG. The region is a region having the same degree as the junction depth of the n ⁻ type semiconductor region 7a. That is, an n-type impurity is introduced into a region having a depth of about t4 from the upper surface in the memory gate electrode MG. In this case, the p-type impurity already introduced into the memory gate electrode and the n-type impurity introduced into the memory gate electrode MG at the time of forming the n ⁻ type semiconductor region 7a cancel each other. It can be considered that the concentration of the p-type impurity is reduced. As a result, the region where the n-type impurity is introduced into the memory gate electrode MG (the region where the concentration of the p-type impurity is considered to be thin) is likely to be depleted when a negative voltage is applied to the memory gate electrode MG. When performing an erase operation by the erase method, the voltage applied between the memory gate electrode MG and the control gate electrode CG is relaxed. Accordingly, it is difficult for a leak current to flow between the memory gate electrode MG and the control gate electrode CG, and the electrical performance of the memory cell MC can be improved. Such an effect is also achieved in the embodiments described later.

  Thus, according to the present embodiment, the characteristics of a semiconductor device having a nonvolatile memory can be improved. In addition, a semiconductor device having a nonvolatile memory with favorable characteristics can be formed by a simple process.

  Here, by forming a depletion layer on the insulating film 5, the charge (electrons or holes) stored in the charge storage layer (here, the silicon nitride film 5b) moves to the memory gate electrode MG and the data is inverted. From the viewpoint of improving the data retention characteristics by suppressing the above, if the thickness t1 of the non-doped silicon film 6a in the region in contact with the insulating film 5 is larger than 0 in the silicon film 6 forming the memory gate electrode MG, the effect is obtained. Have. However, in order to obtain a certain effect, it is preferable that the thickness t1 of the non-doped silicon film 6a is formed to be equal to or greater than the thickness of the silicon oxide film 5c in the insulating film 5. Furthermore, in consideration of obtaining a more sufficient effect and the ease of manufacturing in consideration of the possibility of diffusion of p-type impurities in the silicon film 6 in the heat treatment during the manufacturing process, the thickness of the non-doped silicon film 6a ( The deposited film thickness t1 is preferably 10 nm or more. From this viewpoint, the thickness (deposited film thickness) t1 of the non-doped silicon film 6a formed during the manufacturing process is described as 10 nm or more (the same applies to the following embodiments). From the viewpoint of reducing the resistance of the memory gate electrode MG, the thickness (deposited film thickness) t2 of the doped silicon film 6b is preferably 20 nm or more (that is, t2 ≧ 20 nm).

  Further, since the memory gate length (gate length of the memory gate electrode MG) is determined by the sum of the film thickness t1 of the non-doped silicon film 6a and the film thickness t2 of the doped silicon film 6b, the non-doped silicon film 6a and the doped silicon film 6b. T2 is preferably half or more of the total thickness (ie, t1 + t2).

(Embodiment 2)
In the first embodiment, when the memory gate electrode MG is formed, a p-type impurity is obliquely ion-implanted into the surface of the non-doped silicon film 6a, so that the silicon film 6 for forming the memory gate electrode MG is converted into a non-doped silicon film. Although formed as a laminated film of 6a and doped silicon film 6b (FIG. 9), these films (6a, 6b) may be formed individually. 17 and 18 are fragmentary cross-sectional views showing the manufacturing steps of the semiconductor device of the present embodiment.

  Since the structure of the semiconductor device of this embodiment is the same as that of Embodiment 1, description thereof is omitted (see FIGS. 1 and 2). Further, the manufacturing process of the semiconductor device of the present embodiment is the same as that of the first embodiment up to the step of forming the insulating film 5, and therefore detailed description thereof is omitted. That is, after forming the control gate electrode CG (see FIG. 6), the insulating film 5 is formed on the main surface of the semiconductor substrate 1 including the upper surface and side surfaces of the control gate electrode CG, as in the first embodiment. .

  Next, as shown in FIG. 17, a non-doped (undoped) polycrystalline silicon film is formed on the insulating film 5 as a non-doped silicon film 6a with a film thickness t1 of about 10 to 30 nm using a CVD method or the like. That is, at the time of film formation, the polycrystalline silicon film is formed in a state where the source gas does not contain a p-type doping gas (p-type impurity addition gas). Next, as shown in FIG. 18, as a doped silicon film 6b, a polycrystalline silicon film into which a p-type impurity (for example, boron (B) or indium (In)) is implanted is formed to a thickness of 20 to 50 nm using a CVD method or the like. The film is formed with a film thickness t2. That is, when the doped silicon film 6b is formed, the film is formed in a state in which a doping gas (impurity addition gas) is included in the source gas. It is preferable to make the thickness t2 of the doped silicon film 6b thicker (that is, t1 <t2) than the thickness t1 of the non-doped silicon film 6a. In forming the non-doped silicon film 6a and the doped silicon film 6b, an amorphous silicon film may be formed and polycrystallized by heat treatment.

  Here, the impurity concentration of the doped silicon film 6b is higher than the impurity concentration of the non-doped silicon film 6a, and the resistivity (specific resistance) of the doped silicon film 6b is lower than the resistivity (specific resistance) of the non-doped silicon film 6a. It has become.

  Through the above process, the laminated film 6 of the non-doped silicon film 6a and the doped silicon film 6b is formed on the surface (side surface and upper surface) of the control gate electrode CG via the insulating film 5 (FIG. 18). Thereafter, the memory gate electrode MG and the like are formed by etching back the laminated film 6 of the non-doped silicon film 6a and the doped silicon film 6b. The steps after the formation of the laminated film 6 are described in the embodiment. 1, detailed description thereof is omitted (see FIGS. 9 to 15, and FIGS. 1 and 2).

  As described above, also in this embodiment, a semiconductor device having the same configuration as that of the first embodiment can be formed, and the same effect as that of the first embodiment can be obtained. Furthermore, according to the present embodiment, the film thickness of the non-doped silicon film 6a and the doped silicon film 6b can be easily controlled. In addition, the impurity concentration of the doped silicon film 6b can be easily controlled.

In the first and second embodiments, the boundary between the non-doped silicon film 6a and the doped silicon film 6b containing the p-type impurity is clearly shown in FIGS. 1 and 18, but the impurity constitutes a concentration profile. Therefore, it is difficult to clearly define the boundary. Here, the non-doped silicon film 6a is a region having an impurity concentration of n × E17 / cm ³ order (n: 1 to 10) or less, more preferably n × E16 / cm ³ order (n: 1 to 10) or less. Say it.

  Therefore, a small amount of p-type impurities may be contained in the non-doped silicon film 6a. Also in this case, there is an effect in accordance with the first and second embodiments. Such a small amount of p-type impurity can be generated by, for example, diffusion from the doped silicon film 6b.

  Further, a small amount of n-type impurities may be contained in advance in the non-doped silicon film 6a in order to offset the p-type impurities diffused from the doped silicon film 6b. This process will be described in Embodiment 3 below.

(Embodiment 3)
In the first embodiment, the non-doped silicon film 6a is formed. Alternatively, a silicon film 6an containing a small amount of n-type impurities may be formed. FIG. 19 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device of the present embodiment.

  The structure of the semiconductor device of the present embodiment is the same as that of the first embodiment except that the non-doped silicon film 6a of the memory gate electrode MG of the first embodiment is a silicon film 6an containing a small amount of n-type impurities. The description is omitted (see FIGS. 1 and 2).

  Further, the manufacturing process of the semiconductor device of the present embodiment is the same as that of the first embodiment up to the step of forming the insulating film 5, and therefore detailed description thereof is omitted. That is, after forming the control gate electrode CG (see FIG. 6), the insulating film 5 is formed on the main surface of the semiconductor substrate 1 including the upper surface and side surfaces of the control gate electrode CG, as in the first embodiment. .

Next, as shown in FIG. 19, a silicon film 6an containing a small amount of n-type impurity is formed on the insulating film 5 with a film thickness t1 of about 10 to 30 nm using a CVD method or the like. For example, the polycrystalline silicon film is formed in a state in which a small amount of n-type doping gas (n-type impurity addition gas) is introduced into the source gas. Next, a polycrystalline silicon film into which a p-type impurity (for example, boron (B) or indium (In) or the like) is implanted is formed as the doped silicon film 6b with a film thickness t2 of about 20 to 50 nm by using a CVD method or the like. To do. That is, when the doped silicon film 6b is formed, the source gas is formed in a state where a p-type doping gas (p-type impurity addition gas) is included. The impurity concentration of the n-type impurity in the silicon film 6an is preferably n × E16 / cm ³ order (n: 1 to 10) or less. Further, it is preferable to make the thickness t2 of the doped silicon film 6b thicker than the thickness t1 of the silicon film 6an (that is, t1 <t2). In forming the silicon film 6an and the doped silicon film 6b, an amorphous silicon film may be formed and polycrystallized by heat treatment.

  Through the above process, a laminated film (silicon film) of a silicon film 6an and a doped silicon film 6b containing a trace amount of n-type impurities on the surface (side surface and upper surface) of the control gate electrode CG via the insulating film 5 6 is formed. Thereafter, the memory gate electrode MG and the like are formed by etching back the laminated film (silicon film) 6 of the non-doped silicon film 6a and the doped silicon film 6b. Since the process is the same as that of Embodiment 1, the detailed description is abbreviate | omitted (refer FIGS. 9-15, FIG. 1, FIG. 2).

  Thus, according to the present embodiment, there is an effect equivalent to that of the first embodiment. Furthermore, according to the present embodiment, in the memory gate electrode MG, the p-type impurity in the doped silicon film 6b is diffused into the underlying silicon film 6an due to some factor (for example, the thermal load of the subsequent process). However, it is offset by a small amount of n-type impurities in the silicon film 6an. Therefore, even if the p-type impurity diffuses into the silicon film 6an, the electric field relaxation effect in the memory gate electrode MG described in the first embodiment or the like can be maintained.

  As described above in the first to third embodiments, the impurity concentration in the lower silicon film (6a, 6an) constituting the memory gate electrode MG will be collectively described below.

As described in the first embodiment, the lower silicon film (6a) constituting the memory gate electrode MG is desirably intrinsic, but as described in the second embodiment, a small amount of p film is used. It may contain mold impurities. Further, as described in Embodiment 3, a trace amount of n-type impurities may be contained. The trace amount of p-type or n-type impurity means at least a concentration lower than the impurity concentration of the doped silicon film 6b, preferably an impurity concentration of n × E16 / cm ³ order (n: 1 to 10) or less. .

(Embodiment 4)
In the first embodiment, doped silicon film 6b is formed on the surface of non-doped silicon film 6a by oblique ion implantation of p-type impurities (FIGS. 8 and 9), but p-type impurities are ionized vertically. It may be injected. 20 to 23 are main-portion cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment. 24 is a partially enlarged cross-sectional view in which a part of FIG. 23 is enlarged.

  Since the structure of the semiconductor device of the present embodiment is the same as that of the first embodiment except for the configuration of the memory gate electrode MG, the configuration of the memory gate electrode MG will be described below.

  As shown in FIGS. 23 and 24 which are final process cross-sectional views in the description of the present embodiment, the memory gate electrode MG is formed of the silicon film 6. The silicon film 6 is formed by a non-doped silicon film 6 a in the vicinity of a region in contact with the insulating film 5, and the region extends along the surface of the semiconductor substrate 1. The region on the non-doped silicon film 6a is formed by the doped silicon film 6b into which p-type impurities are introduced. In other words, the silicon film 6 is a laminated film of a non-doped silicon film 6a and a doped silicon film 6b, with the non-doped silicon film 6a being the lower layer and the doped silicon film 6b being the upper layer. The non-doped silicon film 6a is made of a non-doped (undoped) silicon film, and the doped silicon film 6b is made of a silicon film into which p-type impurities are introduced (doped). The p-type impurity is, for example, boron (B) or indium (In).

  Therefore, the impurity concentration of the doped silicon film 6b is higher than the impurity concentration of the non-doped silicon film 6a, and the resistivity (specific resistance) of the doped silicon film 6b is lower than the resistivity (specific resistance) of the non-doped silicon film 6a. ing.

  As described above, the non-doped silicon film 6a is the lower layer and the doped silicon film 6b is the upper layer. That is, the non-doped silicon film 6a is located on the insulating film 5 in contact with the insulating film 5, and the doped silicon film 6b is located on the non-doped silicon film 6a. The first embodiment (FIG. 2) Unlike this, in the present embodiment, the non-doped silicon film 6a is not interposed between the non-doped silicon film 6b and the control gate electrode CG (FIG. 24). That is, the non-doped silicon film 6a is positioned in parallel with the surface of the semiconductor substrate 1, that is, has a horizontal portion that is formed horizontally, but on the surface of the semiconductor substrate 1 as in the first embodiment (FIG. 2). On the other hand, it does not have a vertical part positioned substantially perpendicularly. The insulating film 5 has a horizontal portion that is parallel to the surface of the semiconductor substrate 1, that is, a horizontal portion that is formed horizontally, and a vertical portion that is positioned substantially perpendicular to the surface of the semiconductor substrate 1.

  Further, the manufacturing process of the semiconductor device of the present embodiment is the same as that of the first embodiment up to the step of forming the insulating film 5, and therefore detailed description thereof is omitted. That is, after forming the control gate electrode CG (see FIG. 6), the insulating film 5 is formed on the main surface of the semiconductor substrate 1 including the upper surface and side surfaces of the control gate electrode CG, as in the first embodiment. .

  Next, a non-doped (undoped) polycrystalline silicon film is formed as a non-doped silicon film 6a on the insulating film 5 with a film thickness of about 30 to 70 nm using a CVD method or the like. That is, at the time of film formation, a polycrystalline silicon film is formed without containing a doping gas (impurity addition gas) in the source gas (see FIG. 7). In forming the non-doped silicon film 6a, an amorphous silicon film may be formed and polycrystallized by heat treatment.

Next, as shown in FIG. 20, a p-type impurity (for example, boron (B) or indium (In)) is ion-implanted almost vertically into the surface of the non-doped silicon film 6a. That is, the p-type impurity is implanted at an angle θ substantially perpendicular (about 0 ° to 5 °) to the semiconductor substrate 1. When boron is ion-implanted, for example, it is implanted at a concentration of about 5E15 / cm ² with an energy of 4 keV. Note that 5E15 represents 5 × 10 ¹⁵ . Further, in the case of ion implantation of indium, for example, it is implanted at a concentration of about 5E15 / cm ² with an energy of 50 keV.

  According to this vertical ion implantation, the p-type impurity is not implanted into the surface of the non-doped silicon film 6a corresponding to the side surface portion of the control gate electrode CG, and continues to the flat portion, that is, the upper portion of the control gate electrode CG. In the non-doped silicon film 6a located above the side wall of the control gate electrode CG and above the insulating film 5, p-type impurities are implanted from the surface of the non-doped silicon film 6a to a predetermined depth (here, about 30 to 70 nm). Is done.

  Next, as shown in FIG. 21, heat treatment is performed to diffuse p-type impurities into the non-doped silicon film 6a located on the side wall of the control gate electrode CG. At this time, in the non-doped silicon film 6a located on the side wall of the control gate electrode CG, the heat treatment conditions are adjusted so that the p-type impurity diffuses from the bottom surface (the surface of the insulating film 5) to the position of the thickness t. In other words, in the non-doped silicon film 6a located on the side wall portion of the control gate electrode CG, p-type impurities are diffused to such an extent that a region of thickness t not containing impurities remains at the bottom portion. This t is preferably about 10 to 30 nm.

  That is, in the non-doped silicon film 6a corresponding to the side wall of the control gate electrode CG, the non-doped silicon film 6a remains from the bottom surface (the surface of the insulating film 5) to the thickness t, and in the region above t, A doped silicon film 6b is formed. Further, the non-doped silicon film 6a other than the side surface portion of the control gate electrode CG also becomes the doped silicon film 6b (FIG. 21).

  Here, the impurity concentration of the doped silicon film 6b is higher than the impurity concentration of the non-doped silicon film 6a, and the resistivity (specific resistance) of the doped silicon film 6b is lower than the resistivity (specific resistance) of the non-doped silicon film 6a. It has become.

  Thereafter, as in the first embodiment, the non-doped silicon film 6a and the doped silicon film 6b are etched back to form the memory gate electrode MG and the silicon spacer (SP1). As shown in FIG. The spacer SP1 is removed. Further, the gate electrode GE is formed in the peripheral circuit region 2A.

  Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted (see FIGS. 12 to 14).

  Through the above steps, the semiconductor device shown in FIGS. 23 and 24 is formed.

  As described above, according to the present embodiment, since the memory gate electrode MG is formed of the laminated film of the non-doped silicon film 6a and the doped silicon film 6b containing p-type impurities, the following effects can be obtained.

  By forming the memory gate electrode MG as a p-type gate electrode having a p-type impurity, it acts in a direction in which the electric field is weakened with respect to the holes, and the hole retention characteristics of the memory cell MC are improved. That is, the erased state can be maintained well and the retention is improved.

  Further, the lower part of the memory gate electrode MG in contact with the insulating film 5 is formed of the non-doped silicon film 6a, thereby improving the charge retention characteristics of the memory. That is, depletion tends to occur in the lower layer portion of the memory gate electrode MG, and an electric field is hardly applied. Therefore, the charges (electrons or holes) accumulated in the charge accumulation portion are difficult to escape and the charge retention characteristics are improved. In particular, in the case where the upper layer portion includes the doped silicon film 6b containing a p-type impurity, the electric field with respect to the holes is further relaxed, thereby further improving the hole holding characteristics. That is, the erased state can be maintained well and the retention is improved.

  Further, by configuring the upper layer portion of the memory gate electrode MG with the doped silicon film 6b containing a p-type impurity, the resistance of the memory gate electrode MG can be reduced. For this reason, the operation speed of the nonvolatile memory can be improved. The memory gate electrode MG is formed in a long wiring shape (wiring that connects the memory gate electrodes MG of a plurality of memory cells arranged in the extending direction of the memory gate electrode MG). Therefore, the operation speed of the entire nonvolatile memory can be improved.

Furthermore, by forming the source region (MS) of the memory transistor only by the n ⁻ type semiconductor region 7a, the n ⁺ type semiconductor region 8b having a high impurity concentration can be formed in the step shown in FIG. 14 as in the first embodiment. When forming, the memory gate electrode MG can be covered with the photoresist film PR1, and the memory gate electrode MG (doped silicon film 6b containing p-type impurities) has a higher concentration than the n ⁻ type semiconductor region 7a. It can be avoided that the n-type impurity is introduced and the resistance of the memory gate electrode MG is increased.

  Further, unlike the case of the first embodiment and the like, in this embodiment, the non-doped silicon film 6a is provided between the doped silicon film 6b containing the p-type impurity of the memory gate electrode MG and the control gate electrode CG. No intervention. That is, since there is no vertical portion constituting the non-doped silicon film 6a of the first embodiment, the writing characteristics are improved. In other words, the amount of charge injected into the charge storage portion during writing increases. Alternatively, a desired charge amount can be injected even when the writing voltage is lowered.

  Thus, according to the present embodiment, the characteristics of a semiconductor device having a nonvolatile memory can be improved. In addition, a semiconductor device having a nonvolatile memory with favorable characteristics can be formed by a simple process.

  Further, from the viewpoint of improving the data retention characteristics by suppressing the phenomenon that charges (electrons or holes) stored in the charge storage layer (here, the silicon nitride film 5b) move to the memory gate electrode MG to invert data, If the film thickness t of the non-doped silicon film 6a in the region in contact with the insulating film 5 is larger than 0 in the silicon film 6 forming the memory gate electrode MG, there is an effect. However, in order to obtain a certain effect, it is preferable that the thickness t of the non-doped silicon film 6 a be formed to be equal to or greater than the thickness of the silicon oxide film 5 c in the insulating film 5. Further, in consideration of obtaining a more sufficient effect and the ease of manufacturing in consideration of the possibility of diffusion of p-type impurities in the silicon film 6 in the heat treatment during the manufacturing process, the film thickness t of the non-doped silicon film 6a. Is preferably 10 nm or more. From this viewpoint, the thickness (deposited film thickness) t of the non-doped silicon film 6a formed during the manufacturing process is described as 10 nm or more.

  Further, it is preferable that t is half or more of the memory gate length (the gate length of the memory gate electrode MG).

  In addition, although it is desirable that the non-doped silicon film 6a of this embodiment is also intrinsic, it may contain a small amount of p-type impurities as described in the second embodiment. Further, as described in Embodiment 3, a trace amount of n-type impurities may be contained.

(Embodiment 5)
In the first embodiment, the source region MS of n-type functioning as a source region of the control transistor n ^- -type semiconductor regions 7a is constituted only by, n ^- polycrystal containing a n-type impurity on the semiconductor region 7a A silicon film 22 may be formed. 25 to 29 are main-portion cross-sectional views illustrating the manufacturing steps of the semiconductor device of the present embodiment.

The structure of the semiconductor device of this embodiment, n ^- for type polycrystalline silicon film 22 and the metal silicide layer other than 11 construction of the upper part of the semiconductor regions 7a are the same as in the first embodiment, n ^- The configuration in the vicinity of the type semiconductor region 7a will be described below.

As shown in FIG. 29 which is a final process cross-sectional view in the description of the present embodiment, the semiconductor device of the present embodiment includes n n disposed in the semiconductor substrate 1 (p-type well PW1) between the memory gate electrodes MG. ^{It has a} -type semiconductor region 7a. A polycrystalline silicon film 22 is disposed between the sidewall insulating films SW on the n ⁻ type semiconductor region 7a. Further, a metal silicide layer 11 is disposed on the polycrystalline silicon film 22. That is, in the first embodiment, the metal silicide layer 11 is disposed on the n ⁻ type semiconductor region 7a (see FIG. 15), whereas in the present embodiment, the metal silicide layer 11 is an n ⁻ type. Instead of being disposed on the semiconductor region 7 a, it is disposed on the polycrystalline silicon film 22.

About the manufacturing process of the semiconductor device of this Embodiment, since it is the same as that of Embodiment 1 until the formation process of side wall insulating film SW, the detailed description is abbreviate | omitted. That is, after an n ⁻ type semiconductor region (impurity diffusion layer) 7a is formed by implanting an n type impurity into the semiconductor substrate 1 (p type well PW1) between adjacent memory gate electrodes MG (see FIG. 12). ) A sidewall insulating film SW is formed on the sidewall portion of the combined pattern of the control gate electrode CG and the memory gate electrode MG (see FIG. 13). In the peripheral circuit region 2A, a sidewall insulating film SW is formed on the sidewall portion of the gate electrode GE.

Next, as shown in FIG. 25, for example, a silicon oxide film is formed as a protective film 21 on the entire main surface of the semiconductor substrate 1 using a CVD method or the like. Next, a photoresist film PR2 having an opening OA is formed above the n ⁻ type semiconductor region 7a by using a photolithography method.

Next, the protective film 21 is etched using the photoresist film PR2 as a mask. By this etching, the n ⁻ type semiconductor region 7a between the memory gate electrodes MG (between the sidewall insulating films SW) is exposed. Thereafter, the photoresist film PR2 is removed by ashing or the like.

  Next, as shown in FIG. 26, a polycrystalline silicon film 22 containing an n-type impurity is formed on the entire main surface of the semiconductor substrate 1. The polycrystalline silicon film 22 is formed with a film thickness that can be embedded between the memory gate electrodes MG (between the sidewall insulating films SW) by using, for example, a CVD method. That is, at the time of film formation, the polycrystalline silicon film 22 is formed with the above film thickness in a state where the source gas contains n-type doping gas (n-type impurity addition gas). Note that a non-doped polycrystalline silicon film may be formed and an n-type impurity may be contained by ion implantation. Alternatively, an amorphous silicon film may be formed and polycrystallized by heat treatment.

Next, using a photolithography method, a photoresist film PR3 is formed above the n ⁻ type semiconductor region 7a. For example, the planar shape (pattern) of the photoresist film PR3 corresponds to the planar shape of the opening OA of the photoresist film PR2.

Next, as shown in FIG. 27, the polycrystalline silicon film 22 is etched using the photoresist film PR3 as a mask. Thereafter, the photoresist film PR3 is removed by ashing or the like to form a polycrystalline silicon film 22 containing an n-type impurity on the n ⁻ -type semiconductor region 7a.

Next, if necessary, wet etching using, for example, dilute hydrofluoric acid is performed to clean the main surface of the semiconductor substrate 1, and then, as shown in FIG. 28, using the salicide technique, the control gate electrode CG The metal silicide layers 11 are formed on the memory gate electrode MG, the polycrystalline silicon film 22 and the n ⁺ type semiconductor region 8b, respectively. In addition, metal silicide layers 11 are formed on the gate electrode GE and the n ⁺ type semiconductor region 8, respectively. This metal silicide layer 11 can be formed in the same process as in the first embodiment.

  Thereafter, as shown in FIG. 29, the insulating film 12 is formed on the entire main surface of the semiconductor substrate 1, and the upper surface is planarized as necessary, and then the plug PG is formed. Next, the insulating film 14 is formed, and the wiring M <b> 1 is formed in the insulating film 14. Further, the second and subsequent wirings (not shown) are formed by a dual damascene method or the like. The insulating film 12, the plug PG, the wiring M1, and the second and subsequent wirings can be formed in the same process as in the first embodiment.

  As described above, according to the present embodiment, the memory gate electrode MG is formed of the laminated film of the non-doped silicon film 6a and the doped silicon film 6b containing the p-type impurity as in the first embodiment. As in the first embodiment, the data retention characteristics of the nonvolatile memory can be improved. Further, as in the first embodiment, the upper layer portion of the memory gate electrode MG is formed of the doped silicon film 6b containing the p-type impurity, so that the resistance of the memory gate electrode MG can be reduced, and the non-volatile property is achieved. The operating speed of the memory can be improved.

Similarly to the first embodiment, since the source region (MS) of the memory transistor is formed by the n ⁻ type semiconductor region 7b, the memory gate electrode (doped silicon film 6b containing p-type impurities) MG is formed in the memory gate electrode MG. It can be avoided that the n-type impurity is introduced and the resistance of the memory gate electrode MG is increased.

Furthermore, since the polycrystalline silicon film 22 containing n-type impurities is formed on the n ⁻ type semiconductor region 7a of the memory transistor, the resistance of the source region (MS, n ⁻ type semiconductor region 7a) can be reduced. it can. Note that the n ⁻ type semiconductor region 7a and the polycrystalline silicon film 22 containing an n type impurity may be regarded as a source region (MS).

Furthermore, since the metal silicide layer 11 is formed on the polycrystalline silicon film 22, the resistance of the source region MS (polycrystalline silicon film 22 and n ⁻ type semiconductor region 7a) can be reduced.

The source region MS (polycrystalline silicon film 22 and n ⁻ -type semiconductor region 7a) has a long wiring (wiring that connects the source regions of a plurality of memory cells arranged in the extending direction of the memory gate electrode MG, a source line). However, since the resistance of the wiring itself can be reduced, the operation speed of the entire nonvolatile memory can be improved.

In addition, since the metal silicide layer 11 is formed on the polycrystalline silicon film 22, the leakage current can be reduced. That, n ^- in the case of forming a metal silicide layer 11 over the semiconductor region 7a (see FIG. 15), n ^- -type semiconductor regions 7a are formed shallow, or, when the metal silicide layer 11 is formed thickly There is a possibility that a leak current may be generated in the semiconductor substrate (p-type well PW1) 1 through the metal silicide layer 11. On the other hand, according to the present embodiment, since the metal silicide layer 11 is formed on the polycrystalline silicon film 22, the leakage current can be avoided.

  The configuration and manufacturing method of polycrystalline silicon film 22 and metal silicide layer 11 in the present embodiment can be applied not only to the first embodiment but also to the semiconductor devices of other second to fourth embodiments. Needless to say.

(Embodiment 6)
In the first to fifth embodiments, boron (B), indium (In), and the like are exemplified as the p-type impurity contained in the doped silicon film 6b. The following effects are obtained for each ion species.

  Since boron has a small atomic weight, it is easy to inject and activate. Further, when indium is used, since the atomic weight is large, it is easy to control the implantation region during ion implantation.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to a semiconductor device and a method for manufacturing a semiconductor device.

1 Semiconductor substrate 1A Memory cell region 2 Element isolation region 2A Peripheral circuit region 3 Insulating film 4 Silicon film 5 Insulating film 5a, 5c Silicon oxide film 5b Silicon nitride film 6 Silicon film 6a Non-doped silicon film 6b Doped silicon film 6an Silicon film 7 7a, 7b n ⁻ type semiconductor regions 8, 8b n ⁺ type semiconductor regions 11 Metal silicide layer 12 Insulating film 13a Barrier conductor film 13b Main conductor film 14 Insulating film 21 Protective film 22 Polycrystalline silicon film CG Control gate electrodes PR1, PR2 Photoresist film GE Gate electrode M1 Wiring MC Memory cell MD Drain region MS Source region MG Memory gate electrode OA Opening PG Plug PW1, PW2 p-type well SP1 Silicon spacer SW Side wall insulating films t, t1, t2 Thickness (film thickness)
Qn n-channel MISFET

Claims (22)

A semiconductor substrate;
A first gate electrode disposed above the semiconductor substrate;
A second gate electrode disposed adjacent to the first gate electrode above the semiconductor substrate;
A first insulating film formed between the first gate electrode and the semiconductor substrate;
A second insulating film formed between the second gate electrode and the semiconductor substrate and between the first gate electrode and the second gate electrode, the second insulating film having a charge storage portion therein; An insulating film;
Have
The second gate electrode is
A first silicon region located on the second insulating film;
A silicon film having a second silicon region located above the first silicon region,
The second silicon region contains a p-type impurity;
The semiconductor device, wherein a concentration of the p-type impurity in the first silicon region is lower than a concentration of the p-type impurity in the second silicon region. The second insulating film and the first silicon region of the second gate electrode are interposed between the second silicon region of the second gate electrode and the semiconductor substrate,
The second insulating film and the first silicon region of the second gate electrode are interposed between the second silicon region of the second gate electrode and the first gate electrode. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein the first silicon region is a p-type impurity region having a concentration lower than that of the p-type impurity in the second silicon region.   2. The semiconductor device according to claim 1, wherein the first silicon region is an n-type impurity region having a concentration lower than that of the p-type impurity in the second silicon region.   2. The semiconductor device according to claim 1, wherein the first silicon region is a region containing no impurities. A drain region disposed in the semiconductor substrate on the first gate electrode side and having a high concentration impurity diffusion layer and a first low concentration impurity diffusion layer;
A source region disposed in the semiconductor substrate on the second gate electrode side and comprising a second low-concentration impurity diffusion layer;
The semiconductor device according to claim 1, comprising:   The semiconductor device according to claim 6, wherein the drain region and the source region contain an n-type impurity.   The semiconductor device according to claim 6, further comprising a silicon film containing an n-type impurity disposed on the source region.   9. The semiconductor device according to claim 8, further comprising a metal silicide film disposed on the silicon film containing the n-type impurity.   The semiconductor device according to claim 1, wherein the p-type impurity is boron (B) or indium (In). (A) forming a first gate electrode on a semiconductor substrate via a first insulating film;
(B) forming the second insulating film having a charge storage portion therein on the first gate electrode;
(C) A multilayer silicon film having a first silicon layer on the second insulating film, and a second silicon layer disposed on the first silicon layer and having an impurity concentration higher than that of the first silicon layer. Forming a step;
(D) forming the second gate electrode by selectively removing the multilayer silicon film and leaving the multilayer silicon film on the sidewall portion of the first gate electrode via the second insulating film; ,
A method for manufacturing a semiconductor device, comprising: The step (c)
(C1) forming a non-doped silicon film containing no impurities on the second insulating film;
(C2) obliquely implanting impurity ions into the non-doped silicon film;
Have
12. The semiconductor device according to claim 11, wherein the layer into which the impurity ions are implanted serves as the second silicon layer, and a region not containing impurities below the second silicon layer serves as the first silicon layer. Manufacturing method. The step (c)
(C1) forming the first silicon layer containing no impurities on the second insulating film;
(C2) depositing the second silicon layer containing impurities on the first silicon layer;
The method of manufacturing a semiconductor device according to claim 11, comprising: The step (d)
(D1) By selectively removing the multilayer silicon film, a first sidewall film is formed on the first sidewall portion of the first gate electrode via the second insulating film, and the first gate electrode Forming a second sidewall film on the second sidewall portion via the second insulating film;
(D2) removing the second insulating film and the second sidewall film on the second sidewall portion of the first gate electrode;
Have
12. The method of manufacturing a semiconductor device according to claim 11, wherein the first side wall film remaining on the first side wall portion of the first gate electrode via the second insulating film becomes the second gate electrode. After the step (d),
(E) forming a drain region having a high concentration impurity region and a first low concentration impurity region in the semiconductor substrate on the first gate electrode side, and forming a second low concentration in the semiconductor substrate on the second gate electrode side. Forming a source region comprising an impurity region;
Have
The step (e)
(E1) The second low-concentration impurity region is formed by ion-implanting an impurity having a conductivity type opposite to that of the impurity in the second silicon layer into the semiconductor substrate on the second gate electrode side at a first concentration. And a process of
(E2) Implanting the reverse conductivity type impurity into the semiconductor substrate on the first gate electrode side at a second concentration higher than the first concentration in a state where a mask film is formed on the second gate electrode. A step of forming the high concentration impurity region;
The method of manufacturing a semiconductor device according to claim 11, comprising: After the step (e),
(F) forming a silicon layer containing impurities on the source region;
16. The method of manufacturing a semiconductor device according to claim 15, further comprising: After the step (f),
(G) forming a metal silicide film on the silicon layer;
17. The method of manufacturing a semiconductor device according to claim 16, further comprising:   12. The method of manufacturing a semiconductor device according to claim 11, wherein the impurity in the second silicon layer is a p-type impurity.   19. The method of manufacturing a semiconductor device according to claim 18, wherein the p-type impurity is boron (B) or indium (In). (A) forming a first gate electrode on a semiconductor substrate via a first insulating film;
(B) forming the second insulating film having a charge storage portion therein on the first gate electrode;
(C) forming a silicon film containing no impurities on the second insulating film;
(D) implanting impurity ions into the silicon film;
(E) after the step (d), performing a heat treatment to diffuse the impurity ions;
(F) forming the second gate electrode by selectively removing the silicon film and leaving the silicon film on the side wall of the first gate electrode via the second insulating film;
A method for manufacturing a semiconductor device, comprising:   21. The method of manufacturing a semiconductor device according to claim 20, wherein the step (d) is a step of implanting the impurity ions perpendicularly to the silicon film.   The diffusion of the impurity ions in the step (e) is such that a region not containing impurities remains at the bottom of the silicon film on the side wall of the first gate electrode. 20. A method for manufacturing a semiconductor device according to 20.

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