JP2015023345A - Receiver and communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique capable of sharing exact time with little error from each other among nodes.SOLUTION: A master node and a slave node constituting a communication system are bus connected with a common communication path, and configured to be capable of communicating by PWM communication with each other. The master node operates based on a reference clock signal supplied by a crystal oscillator and outputs a periodic PWM signal. On the other hand, the slave node 50 detects falling edges of the PWM signal by an edge detection circuit 75, and generates a reference clock signal RCK2 of a cycle corresponding to the edge interval by a clock generation circuit 72. A microcomputer 60 of the slave node 50 operates and clocks on the basis of the reference clock signal RCK2. Furthermore, the microcomputer 60 of the slave node 50 corrects time clocked by itself on the basis of clock information included in data RxD received from the master node by PWM communication.

Description

  The present invention relates to a communication system and a receiving apparatus using a pulse width modulation (PWM) signal.

  Conventionally, a communication system that performs data communication between nodes by communication using a PWM signal (that is, PWM communication) is known. In addition, as a vehicle communication system, a technique is known in which a timer in each ECU is synchronized in order to cause a plurality of ECUs (electronic control units) to cooperate with each other with high accuracy (see, for example, Patent Document 1). According to this technique, the master ECU stores its own local timer value in the message frame, and transmits the frame to the slave ECU. The slave ECU determines its own local timer value based on the local timer value included in the received frame. Update the value.

JP 2004-64123 A

  By the way, a high-precision oscillator such as a crystal oscillator is provided in a device that requires a high-precision time counting operation (clocking operation). However, if a high-precision oscillator is provided at each node in order to share a time with little error between nodes, the construction cost of the communication system increases.

  An object of the present invention is to provide a technology that can share accurate time with little error between nodes without providing a high-precision oscillator at all nodes.

  A receiving apparatus according to the present invention is a receiving apparatus capable of receiving a PWM (pulse width modulation) signal from a transmitting apparatus, and includes a receiving unit, a generating unit, and a processing unit. The transmission device outputs a periodic PWM signal to the communication path. Specifically, a PWM signal to which pulse width modulation corresponding to transmission data is added is output.

  The receiving unit receives and demodulates the PWM signal output from the transmitting device via the communication path. The processing unit executes processing based on transmission data from the transmission device obtained by the receiving unit demodulating the PWM signal.

  The generation unit detects a specific edge of the PWM signal input from the communication path, and generates a reference clock signal corresponding to the detection cycle of the specific edge. The processing unit operates and clocks based on the reference clock signal generated by the generating unit, while as one of the processes based on the transmission data, the time at which the processing unit clocks based on the time information included in the transmission data. Execute the process to correct.

  According to the present invention, the processing unit clocks based on the reference clock signal generated based on the PWM signal from the transmitting device. The PWM signal from the transmission device has a period according to the time axis of the transmission device. Therefore, according to this receiving apparatus, the clocking operation based on the reference clock signal can perform the clocking operation synchronized with the transmission apparatus with a time accuracy corresponding to the period of the PWM signal.

  However, with such a time-accurate clock operation alone, when a long time elapses, an error in the time when the receiver clocks the transmitter increases. Therefore, in the present invention, the time information of the transmission device is received by the reception device, and time correction is performed based on the received time information.

  According to the present invention, in addition to the correction of the clock operation based on the PWM signal (clock error correction), in order to perform such time correction, between the transmission device and the reception device that gradually increases with time, Time error can be corrected. Therefore, according to the present invention, an accurate time with little error can be shared between one transmission device and one or a plurality of reception devices without providing a high-accuracy oscillator in the reception device. Thus, a communication system capable of realizing a highly accurate synchronous operation can be configured.

  In addition, using the above technical idea, the communication system can be configured as follows. The communication system of the present invention includes a master node and a slave node connected to each other via a communication path. The slave node includes a receiving unit that receives and demodulates the PWM signal from the master node via the communication path. The slave node further includes a generation unit that detects a specific edge of the PWM signal input from the communication path and generates a reference clock signal corresponding to the detection cycle of the specific edge.

  The processing unit included in the slave node operates and clocks based on the reference clock signal generated by the generating unit, and executes processing based on transmission data from the master node obtained by demodulating the PWM signal by the receiving unit. . As one of the processes based on the transmission data, this processing unit executes a process of correcting the time that the clock itself is based on the time information included in the transmission data.

  On the other hand, the master node includes an oscillator, a processing unit, and a transmission unit that outputs a PWM signal to the communication path. The processing unit of the master node operates based on the reference clock signal input from the oscillator and clocks it. On the other hand, when a predetermined transmission condition is satisfied, the master node processing unit stores time information corresponding to the clocking time of the master node. Input the transmission data to the transmission unit.

  Further, the transmission unit of the master node generates a periodic PWM signal based on the reference clock signal from the oscillator, and outputs the PWM signal to the communication path. Specifically, from the processing unit of the master node A PWM signal with pulse width modulation corresponding to the input transmission data is output.

  According to this communication system, a PWM signal including a clock component generated with accuracy corresponding to the oscillator of the master node is provided to the slave node and used for the clocking operation at the slave node. Further, the time at the slave node is corrected based on the time at the master node having time accuracy corresponding to the oscillator.

  Therefore, even if a slave node is not provided with a high-precision oscillator, a high-precision clock operation can be realized in each of the master node and the slave node, and there is little error between the master node and the slave node. Accurate time can be shared. Therefore, according to this communication system, for example, a highly accurate synchronization operation can be performed in terms of time.

It is a block diagram showing schematic structure of a communication system. It is a block diagram showing schematic structure of a vehicle-mounted system. It is a wave form diagram which shows a recessive / dominant signal. It is a block diagram showing schematic structure of a master node. It is a block diagram showing schematic structure of a slave node. It is the figure which showed the detection edge with the waveform of the PWM signal. It is a flowchart showing the time transmission process (left) performed in a master node, and the reception correction process (right) performed in a slave node. It is a figure which shows the correspondence of the error change of the time which a slave node clocks, the transmission / reception operation | movement of time data, and the correction | amendment operation of time. It is the figure explaining embodiment which correct | amends several different time which each task of a slave node has separately by reception correction | amendment process.

Embodiments of the present invention will be described below with reference to the drawings.
As shown in FIG. 1, the communication system 1 of the present embodiment is one in which one master node 10 and a plurality of slave nodes 50 are bus-connected to a common communication path LN.

  The communication system 1 is configured as, for example, an in-vehicle system 100 (see FIG. 2) that performs vehicle control by cooperation of a plurality of control devices. As the master node 10, a well-known body ECU 110 can be cited as an example. The body ECU 110 is a control device (electronic control unit) that comprehensively controls the locking / unlocking of each door in the vehicle and the opening / closing of the power window device 150 provided in each door.

  On the other hand, an example of the slave node 50 is a power window device 150 that opens and closes a window in accordance with a command from the body ECU 110. The power window device 150 for each window shown in FIG. 2 includes a PW control device 151 and an actuator 153 that opens and closes the corresponding window. The PW control device 151 controls the actuator 153 according to a command included in transmission data from the body ECU 110 received via the communication path LN.

  The communication system 1 of the present embodiment configured as described above realizes communication between the master node 10 and the slave node 50 by PWM communication. A PWM (pulse width modulation) signal having a predetermined period T is output from the master node 10 to the communication path LN. As shown in FIG. 3, in the PWM signal propagating through the communication path LN, one bit is represented by a recessive (corresponding to 1 in this embodiment) signal or a dominant (corresponding to 0 in this embodiment) signal having a different duty ratio. .

  The period T of the PWM signal corresponds to 1 bit time. As shown in FIG. 3, the recessive signal has a low signal level of 1/3 hour from the beginning of 1 bit time, and the remaining 2/3 time signal. This is a signal whose level is high. On the other hand, the dominant signal is a signal in which the signal level for 2/3 hours from the beginning of the 1-bit time is low and the signal level for the remaining 1/3 hours is high.

  The communication system 1 of the present embodiment is configured such that the dominant signal wins arbitration when the recessive signal and the dominant signal collide. That is, the recessive signal is overwritten by the dominant signal.

  At the time of data transmission, the master node 10 outputs a PWM signal (a PWM signal composed of a combination of a recessive signal and a dominant signal corresponding to transmission data) to which the pulse width modulation corresponding to the transmission data is applied, to the communication path LN, and the others During this period, a recessive signal having a period T is continuously output as a PWM signal. By continuously outputting the recessive signal in this way, the master node 10 functions as a clock master and supplies a signal including a clock component necessary for reproducing the bus clock signal to the communication path LN.

  The slave node 50 detects the falling edge of the PWM signal and reproduces the bus clock signal, while overwriting the recessive signal output to the communication path LN by the master node 10 with the dominant signal, Data transmission.

  A frame (transmission data) used for the PWM communication includes a header including a data identifier (ID) and a variable-length response in which data specified by the data identifier is stored. The response includes size information indicating the size of the response and a CRC code for checking whether there is an error.

  More specifically, as shown in FIG. 4, the master node 10 includes a microcomputer 20 as a processing unit, a transceiver 30 as a transmission / reception unit, and a crystal oscillator 40.

  The crystal oscillator 40 generates and inputs a reference clock signal RCK1 to the microcomputer 20. The transceiver 30 generates the PWM signal corresponding to the transmission data TxD input from the microcomputer 20 and outputs the PWM signal to the communication path LN. On the other hand, the transceiver 30 demodulates the PWM signal input from the communication path LN to obtain the reception data RxD. Input to the microcomputer 20.

  The microcomputer 20 is mainly composed of the CPU 21, the ROM 23, and the RAM 25, and further divides / multiplies the reference clock signal RCK1 input from the clock signal source (crystal oscillator 40) and supplies it to the internal or peripheral circuit. A circuit (not shown) is provided. The microcomputer 20 operates based on the reference clock signal RCK 1 input from the crystal oscillator 40 and generates a clock signal CK to be supplied to the transceiver 30. The clock signal CK is generated, for example, by dividing the reference clock signal RCK1.

  The microcomputer 20 further includes a UART (Universal Asynchronous Receiver Transmitter) 27 and a counter 29 which are serial communication circuits for the transceiver 30. Transmission data TxD and reception data RxD are exchanged between the microcomputer 20 and the transceiver 30 via the UART 27.

  In addition, the counter 29 operates based on the reference clock signal RCK1 or a clock signal generated by dividing / multiplying the reference clock signal RCK1, and performs a clock operation (counting operation) at a period corresponding to the reference clock signal RCK1. Do. In this specification, what operates based on a reference clock signal or a clock signal generated by dividing / multiplying a reference clock signal is also simply expressed as “operates based on a reference clock signal”.

  Various programs are stored in the ROM 23 provided in the microcomputer 20, and the CPU 21 executes processing based on the programs stored in the ROM 23. The RAM 25 is used as a working memory when the CPU 21 executes processing. The CPU 21 executes tasks according to various programs stored in the ROM 23, and inputs transmission data TxD generated by each task to the transceiver 30.

  On the other hand, the transceiver 30 includes a main circuit 31 and an analog processing circuit 33. The main circuit 31 operates based on the clock signal CK supplied from the microcomputer 20, generates a PWM signal having a period T synchronized with the clock signal CK as the transmission signal Tx, and transmits the PWM signal via the transmission buffer 33A. Output to the communication path LN. When the transmission data TxD is input from the microcomputer 20, the main circuit 31 generates the PWM signal to which the pulse width modulation corresponding to the transmission data TxD is added as the transmission signal Tx, and transmits the PWM signal to the transmission buffer 33A. Via the communication path LN.

  In addition, the main circuit 31 demodulates the PWM signal as the reception signal Rx input from the communication path LN via the reception buffer 33B to generate reception data RxD, and this reception data RxD is transmitted to the microcomputer via the UART 27. Input to 20 CPUs 21.

  The analog processing circuit 33 includes a transmission buffer 33A and a reception buffer 33B. The transmission buffer 33A outputs a PWM signal, which is a transmission signal Tx subjected to PWM encoding in the main circuit 31, to the communication path LN. The transmission buffer 33A is configured using, for example, a known open collector circuit so that bus arbitration is possible.

  The reception buffer 33B is a circuit that captures a PWM signal on the communication path LN. For example, a well-known comparator that outputs a high level if the signal level of the communication path LN is larger than a preset threshold and a low level if the signal level is smaller than the threshold. Consists of.

  On the other hand, as shown in FIG. 5, the slave node 50 includes a microcomputer 60 as a processing unit and a transceiver 70 as a transmission / reception unit. The slave node 50 is different from the master node 10 in that it does not include the crystal oscillator 40.

  As illustrated in FIG. 5, the transceiver 70 includes a main circuit 71, an analog processing circuit 73, and an edge detection circuit 75. The analog processing circuit 73 is configured in the same manner as the analog processing circuit 33 of the master node 10, and a transmission buffer 73A that outputs a transmission signal (PWM signal) Tx from the main circuit 71 to the communication path LN, and on the communication path LN A reception buffer 73B that captures the PWM signal as the reception signal Rx is provided.

  On the other hand, as shown in FIG. 6, the edge detection circuit 75 detects a falling edge which is a bit boundary of the PWM signal (reception signal Rx) input via the reception buffer 73B, and uses the detected signal as the main circuit 71. To enter.

  The main circuit 71 operates based on the clock component included in the PWM signal without receiving the input of the clock signal CK from the microcomputer 60, and sends the PWM signal corresponding to the transmission data TxD from the microcomputer 60 to the transmission buffer 73A. The received data RxD is generated by demodulating the PWM signal received via the communication path LN, and the received data RxD is input to the microcomputer 60.

  The main circuit 71 includes a clock generation circuit 72 as shown in FIG. The clock generation circuit 72 generates a clock signal synchronized with the clock component of the PWM signal based on the input signal from the edge detection circuit 75. That is, the clock generation circuit 72 generates a bus clock signal corresponding to the detection cycle of the falling edge of the PWM signal. The main circuit 71 performs the above-described modulation and demodulation according to the bus clock signal.

  In addition, the clock generation circuit 72 may be configured to measure the time interval of the falling edge and generate a bus clock signal having a period corresponding to this time interval. Time measurement and generation of the bus clock signal can be realized by using a simple oscillation circuit (ring oscillator circuit or the like) (not shown) in the transceiver 70.

  The clock generation circuit 72 generates the bus clock signal as a reference clock signal RCK2 for the microcomputer 60 of the slave node 50 or for the microcomputer 60 generated in the same manner as the bus clock signal based on the input signal from the edge detection circuit 75. A reference clock signal RCK2 (for example, a signal having a frequency that is an integral multiple of the bus clock signal) is input to the microcomputer 60.

  The microcomputer 60 of the slave node 50 operates based on the reference clock signal RCK2 input from the transceiver 70. The microcomputer 60 is composed mainly of a CPU 61, a ROM 63, and a RAM 65, and divides / multiplies a reference clock signal RCK2 input from a clock signal source (clock generation circuit 72) and supplies it to an internal or peripheral circuit (see FIG. Not shown).

  The microcomputer 60 further includes a UART 67 and a counter 69. Similarly to the master node 10, the microcomputer 60 inputs the transmission data TxD to the transceiver 70 via the UART 67 and acquires the reception data RxD from the transceiver 70.

  In addition, the counter 69 operates based on the reference clock signal RCK2 generated from the clock component of the PWM signal and performs a clock operation. By this clocking operation, the counter 69 of the slave node 50 performs a clocking operation synchronized with the clocking operation of the counter 29 of the master node 10 with time accuracy corresponding to the period T of the PWM signal.

  Various programs are stored in the ROM 63 included in the microcomputer 60, and the CPU 61 executes processing based on the programs stored in the ROM 63. The RAM 65 is used as a working memory when the CPU 61 executes processing. The CPU 61 executes tasks according to various programs. In each task, for example, processing based on the received data RxD from the master node 10 is executed.

  For example, when the CPU 61 of the PW control device 151 receives data instructing opening of the window from the body ECU 110, the CPU 61 controls the actuator 153 according to this data to open the window. For example, when the CPU 61 of the PW control device 151 receives data specifying the time at which the window is to be opened from the master node 10, the actuator 61 operates on the condition that the current time specified from the counter 69 matches the specified time. Control 153 to open the window.

  By the way, in the in-vehicle system 100 that performs window opening / closing control by such time designation, if the PW control devices 151 do not share the same time, the body ECU 110 sends the windows to the PW control devices 151 at the same time. Even if it is instructed to open and close, each window is opened and closed at different timings, which may cause discomfort to the vehicle occupant.

  In the communication system 1 of this embodiment, in order to suppress the occurrence of the problem due to the low accuracy of the synchronous operation, each slave node 50 generates a clock error with the master node 10 based on the clock component of the PWM signal. Suppressing and performing clocking operation with high accuracy. Furthermore, based on the time information of the master node 10 included in the data received from the master node 10, the time that the timer itself clocks is corrected.

  According to the present embodiment, the clock error correction and the time correction share a time with little error between the nodes 10 and 50 so that a highly accurate synchronous operation can be realized between the nodes 10 and 50. Thereby, for example, it is possible to prevent the windows from being opened and closed at different timings and to prevent the vehicle occupant from feeling uncomfortable.

  Here, processing executed by the master node 10 and the slave node 50 for time correction will be described with reference to FIG. The CPU 21 of the master node 10 repeatedly executes time transmission processing according to the flowchart shown in the left area of FIG.

  According to the time transmission process, the CPU 21 of the master node 10 stands by until the time data transmission timing arrives (S110). When the time data transmission timing arrives, the CPU 21 of the master node 10 specifies the time data as a response from the counter 29. The transmission data storing the time information (for example, the count value of the counter 29) representing the current time is generated, and the transmission data describing the data identifier corresponding to the time information is generated. Then, by inputting this transmission data to the transceiver 30, transmission data (time data) including time information is output to the communication path LN as a PWM signal (S120).

  Whether or not the transmission timing has arrived can be determined based on, for example, the elapsed time from the previous transmission of the time data. For example, time data is transmitted (output) every time the elapsed time reaches a predetermined time. For example, time data can be output with a period of about 10 milliseconds with respect to a period T (one bit time) of about 50 microseconds. As another example, the CPU 21 can operate to output time data in accordance with a request from a task based on various application programs.

  The CPU 21 of the master node 10 repeatedly executes the time transmission process having such contents to transmit the time information representing the current time specified from the counter 29 at a time interval longer than the 1-bit time. Data (time data) is output to the communication path LN.

  On the other hand, the CPU 61 of the slave node 50 repeatedly executes the reception correction process according to the flowchart shown in the right area of FIG. According to this reception correction process, the CPU 61 stands by until time data is received via the communication path LN and the transceiver 70 (S210). Whether or not the received data is time data can be determined by referring to the data identifier.

  If it is determined that the time data has been received (Yes in S210), the current time specified from the counter 69 is corrected to match the time of the master node 10 indicated by the received time data (S220). Thereafter, the reception correction process is temporarily terminated.

  In the correction operation in S220, for example, the reference value of the current time specified as an addition value of the count value of the counter 69 and the reference value is matched with the time of the master node 10 indicated by the time information of the reception data, while the counter This can be realized by resetting the count value of 69 to zero.

  As another example, the correction operation in S220 can be realized by an operation of correcting the count value itself of the counter 69 representing the current time. As another example, in the correction operation in S220, the reference time is corrected without resetting the counter 69, so that the current time specified as the addition value of the count value of the counter 69 and the reference value is changed to the time of the master node 10. It can be realized by an operation to match the above.

  The time correction may be performed in consideration of a time lag from when the time data is generated at the master node 10 until the time correction based on this time data is performed at the slave node 50 as necessary.

  The slave node 50 corrects the time clocked by its own counter 69 on the basis of the time data received from the master node 10 in this way, thereby generating a clock component of the PWM signal as shown in FIG. Only the clocking operation based on this eliminates the disadvantage that the time error between the nodes 10 and 50 is widened. That is, a time with little error is shared between the nodes 10 and 50 so that a highly accurate synchronous operation can be realized.

  As described above, according to the present embodiment, even if the high-precision oscillator (crystal oscillator 40) is not provided in the slave node 50, there is an error between the nodes 10 and 50 to the extent that the high-precision oscillator is provided in the master node 10. You can share accurate time with less. Therefore, for example, the communication system 1 capable of time synchronization with high accuracy between the nodes 10 and 50 can be configured at low cost.

[Other embodiments]
As mentioned above, although the Example of this invention was described, this invention is not limited to the said Example, It can take a various aspect.

  For example, in the above-described embodiment, an example has been described in which attention is paid to one time that the slave node 50 clocks, and this time is corrected based on time data from the master node 10. An environment in which a plurality of times with different base points (a plurality of times based on different time points) is calculated based on the count value is conceivable. For example, as shown in FIG. 9, an environment in which a plurality of times corresponding to each of a plurality of types of tasks are clocked is conceivable.

  Corresponding to such an environment, the master node 10 is configured to describe an ID for designating the correction target time in the data identifier and transmit time data storing correct time information to be corrected in the response. obtain.

  On the other hand, the slave node 50 that receives such time data can be configured to correct the time in the correction mode specified by the data identifier in the time data in S220. That is, the time specified by the data identifier among the plurality of times can be corrected based on the time information included in the received data.

  Further, the data identifier can be used as an identifier for specifying a correction method, such as an identifier for instructing to reset the time to zero or an identifier for instructing to correct the time to the time indicated by the time information included in the response. . In this case, the slave node 50 can be configured to correct the time in S220 by a correction method according to the command represented by the data identifier.

  In addition, a programmable logic controller (PLC) can be used instead of the microcomputers 20 and 60. The technical idea described above is not limited to the in-vehicle system 100 in which the power window device 150 is the slave node 50, and can be applied to various systems.

  For example, as an in-vehicle system, a system that estimates a situation around a vehicle based on a plurality of object detection devices (a radar device or a clearance sonar) is known. In this system, if the time error in each object detection device is large, an error occurs in the object detection time in each object detection device, so that the estimation accuracy when estimating the situation around the vehicle deteriorates. Therefore, if the above-described technical idea is applied to a system in which the object detection device is the slave node 50 and the estimation device that estimates the situation around the vehicle based on the detection results is the master node 10, the above-described situation estimation accuracy is obtained. Will improve.

  The above-described embodiment has an advantage in that accurate time with little error can be shared between the nodes 10 and 50 by clock error correction using the clock component of the PWM signal and time correction by transmission / reception of time data. This is excellent in that the synchronization operation can be appropriately performed. The present invention is not limited to the vehicle field, and can be applied to various fields in which such features can be utilized.

DESCRIPTION OF SYMBOLS 1 ... Communication system 10, 50 ... Node, 20, 60 ... Microcomputer, 21, 61 ... CPU, 23, 63 ... ROM, 25, 65 ... RAM, 27, 67 ... UART, 29, 69 ... Counter, 30, 70 ... transceivers 31, 71 ... main circuit, 33, 73 ... analog processing circuit, 33A, 73A ... transmission buffer, 33B, 73B ... reception buffer, 40 ... crystal oscillator, 72 ... clock generation circuit, 75 ... edge detection circuit, DESCRIPTION OF SYMBOLS 100 ... Vehicle-mounted system, 110 ... Body ECU, 150 ... Power window apparatus, 151 ... PW control apparatus, 153 ... Actuator, LN ... Communication path.

Claims (4)

The transmission device (10) that outputs a periodic pulse width modulation (PWM) signal to a communication path, the PWM output from the transmission device that outputs the PWM signal to which pulse width modulation corresponding to transmission data is added A receiving unit (70) for receiving and demodulating a signal via the communication path;
A generation unit (72, 75) for detecting a specific edge of the PWM signal input from the communication path and generating a reference clock signal corresponding to a detection cycle of the specific edge;
A processing unit that executes processing based on the transmission data from the transmission device obtained by demodulating the PWM signal by the reception unit, and operates based on the reference clock signal generated by the generation unit. On the other hand, as one of the processes based on the transmission data, a processing unit (60) that executes a process of correcting the time of the clock based on time information included in the transmission data;
A receiving apparatus comprising: The transmission data including the time information further includes a data identifier,
The receiving device according to claim 1, wherein the processing unit corrects the time in a correction mode corresponding to the data identifier based on the data identifier and the time information included in the transmission data. The transmission data including the time information further includes a data identifier,
The processing unit clocks a plurality of different types of time, and corrects the time corresponding to the data identifier among the plurality of times based on the data identifier and the time information included in the transmission data. The receiving apparatus according to claim 1, wherein: Master node (10) and slave node (50) connected to each other via a communication path
With
The master node is
An oscillator (40);
A processing unit (20);
A transmission unit (30) for outputting a pulse width modulation (PWM) signal to the communication path, and outputting the PWM signal obtained by applying pulse width modulation corresponding to transmission data inputted from the processing unit; ,
With
While the processing unit operates based on the first reference clock signal input from the oscillator and clocks, when a predetermined transmission condition is satisfied, time information corresponding to the clocking time of the processing unit itself Input the transmission data stored in the transmission unit,
The transmission unit generates the periodic PWM signal based on the first reference clock signal and outputs the PWM signal to the communication path;
The slave node is
A receiving unit (70) for receiving and demodulating the PWM signal from the master node via the communication path;
A generation unit (72, 75) for detecting a specific edge of the PWM signal input from the communication path and generating a second reference clock signal corresponding to a detection period of the specific edge;
A processing unit that executes processing based on the transmission data from the master node obtained by demodulating the PWM signal by the receiving unit, and operates based on the second reference clock signal generated by the generating unit On the other hand, as one of the processes based on the transmission data, a processing unit (60) for executing a process of correcting the clocking time based on the time information included in the transmission data, ,
A communication system characterized by comprising:

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