JP2015018940A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce parasitic capacitance generated between bit lines and inhibit a short circuit of neighboring contacts through an air gap.SOLUTION: A semiconductor device comprises: capacitors formed in an upper layer above bit lines BT; and capacitor contacts CCON2 each of which connects the capacitor and a substrate and located between neighboring bit lines BT. The neighboring bit lines BT have first parts PT1 in each of which the capacitor contact CCON2 is sandwiched between the neighboring bit lines BT and second parts PT2 in each of which the capacitor contact CCON2 is not sandwiched between the neighboring bit lines BT. In an insulation layer between the second parts PT2, an air gap GT is formed, and in an insulation layer between the first parts PT1, an air gap GP is not formed at apart where the insulation layer overlaps capacitor contact CCON2.

Description

  The present invention relates to a semiconductor device, and is a technology applicable to a semiconductor device having a memory, for example.

  One of the memories is a DRAM (Dynamic Random Access Memory) using a capacitor. As a technology related to a semiconductor device using a DRAM, for example, there are technologies described in Patent Documents 1 and 2.

  Japanese Patent Application Laid-Open No. 2005-228561 describes that the interval between the bit lines in the portion where the contact connecting to the capacitor is provided is wider than the interval between the bit lines in the portion where the contact connecting to the bit line is provided.

  In Patent Document 2, when a contact connected to a capacitor is divided into an upper contact and a lower contact, the upper contact is connected to the lower contact from the bit line connected to the capacitor. It is described that it is shifted away.

JP 2008-227477 A JP 2010-161173 A

  In recent years, since the miniaturization of semiconductor devices has progressed, the interval between bit lines is also narrowed. When the interval between the bit lines is reduced, the parasitic capacitance generated between the bit lines is increased. One method for reducing this parasitic capacitance is to provide an air gap in an insulating film located between bit lines. However, the present inventor has considered that when an air gap is provided between the bit lines, adjacent contacts may be short-circuited through the air gap when a contact connected to the capacitor is formed. .

  According to one embodiment, the capacitor is formed above the bit line. A capacitor contact connecting the capacitor and the substrate is located between adjacent bit lines. The adjacent bit lines have a first portion that sandwiches a capacitor contact between them and a second portion that does not sandwich a capacitor contact between them. An air gap is formed in the insulating layer positioned between the second portions, and no air gap is formed in a portion of the insulating layer positioned between the first portions that overlaps the capacitor contact.

  According to the embodiment, the parasitic capacitance generated between the bit lines can be reduced, and the adjacent contacts can be prevented from being short-circuited through the air gap.

It is a top view which shows the structure of the semiconductor device which concerns on embodiment. It is AA 'sectional drawing of FIG. It is BB 'sectional drawing of FIG. It is sectional drawing which shows the manufacturing method of a semiconductor device. It is sectional drawing which shows the manufacturing method of a semiconductor device. It is sectional drawing which shows the manufacturing method of a semiconductor device.

  Hereinafter, embodiments will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  FIG. 1 is a plan view showing a configuration of a semiconductor device SD according to the embodiment. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1, and FIG. 3 is a cross-sectional view taken along the line BB ′ of FIG. The semiconductor device SD according to the present embodiment includes a substrate SUB, a plurality of bit lines BT, an interlayer insulating film INS3, a capacitor CND, and a capacitor contact CCON2. The bit line BT is formed above the substrate SUB. The interlayer insulating film INS3 is located between the plurality of bit lines BT. The capacitor CND is formed in an upper layer than the bit line BT. The capacitor contact CCON2 is located between the bit lines BT adjacent to each other in plan view, penetrates the interlayer insulating film INS3, and connects the capacitor CND and the substrate SUB.

  Adjacent bit lines BT have a first portion PT1 and a second portion PT2. The first parts PT1 sandwich the capacitor contact CCON2 between them. The second part PT2 does not sandwich the capacitor contact CCON2 between them. An air gap GP is formed in the interlayer insulating film INS3 facing the second portion PT2. The air gap GP is located between adjacent bit lines BT.

  Further, in one bit line BT, one first part PT1 is sandwiched between two second parts PT2. In the direction in which the bit line BT extends, no air gap GP is formed in the portion of the interlayer insulating film INS3 facing this one first portion PT1 that overlaps the capacitor contact CCON2. Details will be described below.

  As shown in FIGS. 2 and 3, the semiconductor device SD is formed using a substrate SUB. The substrate SUB is a semiconductor substrate such as a silicon substrate. A multilayer wiring layer MINS is formed on the substrate SUB. In the example shown in this figure, the multilayer wiring layer MINS has a configuration in which interlayer insulating films INS1, INS2, INS3, and INS4 are stacked in this order. The interlayer insulating films INS1, INS2, INS3, and INS4 are formed of, for example, a film made of at least one of SiO2, SiOC, SiOCN, SiCOH, and SiCOHN, or a film obtained by making this film porous. The interlayer insulating films INS1, INS2, INS3, and INS4 may be formed of the same material as each other, or at least one may be formed of a material different from the other.

  A capacitor contact CCON1 and a bit contact BCON1 are embedded in the interlayer insulating film INS1. The upper surface of the capacitor contact CCON1 is connected to the lower surface of the capacitor contact CCON2, and the upper surface of the bit contact BCON1 is connected to the lower surface of the bit contact BCON2. The capacitor contact CCON2 passes through the interlayer insulating films INS2 and INS3, and the bit contact BCON2 passes through the interlayer insulating film INS2. Each of these contacts is formed of W, for example. However, at least one contact may be formed of another conductive material.

  The capacitor CND has a configuration in which a lower electrode LE, a dielectric layer CINS, and an upper electrode UE are stacked in this order, and is formed in a recess formed in the interlayer insulating film INS4. Specifically, the lower electrode LE and the dielectric layer CINS are formed along the bottom and side surfaces of the recess. The upper electrode UE fills the remaining space of this recess. The lower electrode LE is, for example, a Ti film, a TiN film, a Ta film, a TaN film, a Ru film, or at least two laminated films thereof. The dielectric layer CINS is, for example, a film obtained by adding lanthanoids such as Tb, Er, and Yb to zirconium dioxide (ZrO2), zirconium aluminate (ZrAlOx), or zirconium dioxide. The upper electrode UE is, for example, a Ti film, a TiN film, a Ta film, a TaN film, a Ru film, a W film, or at least two laminated films thereof. The upper electrode UE may have a laminated structure of this film and a Cu film. In this case, the former film is formed along the bottom and side surfaces of the recess, and the Cu film fills the remaining space of the recess.

  The above-described recess penetrates the interlayer insulating film INS4, and the upper end of the capacitor contact CCON2 is located on the bottom surface thereof. The upper end of the capacitor contact CCON2 is connected to the lower electrode LE of the capacitor CND.

  The bit line BT is formed on the interlayer insulating film INS2, and is connected to the upper surface of the bit contact BCON2. The bit line BT is, for example, a laminated film of a titanium nitride film and a tungsten film, but is not limited to this.

  Further, the semiconductor device SD has a plurality of memory cells MC. Each memory cell MC has a transistor TR shown in FIG. 3 in addition to the capacitor CND.

  As shown in FIG. 3, the transistor TR includes a gate electrode GE and two diffusion layers DIF serving as a source / drain. The gate electrode GE is a part of the word line WD and is formed using, for example, polysilicon. A plurality of word lines WD extend in parallel with each other. The diffusion layer DIF is formed in the substrate SUB and has a silicide SIL in the surface layer. The silicide SIL is, for example, Ni silicide, but may be Co silicide. Note that the silicide SIL may not be formed on the surface layer of the diffusion layer DIF. One diffusion layer DIF (for example, drain) is connected to the bit line BT via the bit contacts BCON1, BCON2, and the other diffusion layer DIF (for example, source) is connected to the capacitor via the capacitor contacts CCON1, CCON2. It is connected to the lower electrode LE of CND.

  The plurality of transistors TR are separated from each other by the element isolation film EI. The element isolation film EI is, for example, a silicon oxide film, and is embedded in the substrate SUB using, for example, the STI method.

Next, the layout of the bit line BT will be described with reference to FIGS. The plurality of bit lines BT extend in the first direction (X direction in FIG. 1) and are substantially orthogonal to the word line WD. The transistor TR is provided obliquely with respect to the bit line BT. The interval or center distance between the bit lines BT in the first portion PT1 is larger than the interval or center distance between the bit lines BT in the second portion PT2. If it does in this way, it will become easy to form air gap GP in 2nd part PT2, without forming air gap GP in 1st part PT1, as mentioned later. Incidentally, _{d 1} is, for example, 30nm or more 120nm or less, _{d 2} is, for example, 60nm or more 240nm or less.

The distance d ₂ of the bit line BT in the second part PT2 is twice or less is preferably the height h of the bit line BT, In this way, it is easy to form the air gap GP to the first part PT1 Become.

  As shown in FIG. 1, the bit contacts BCON1 and BCON2 are connected to the second portion PT2 of the bit line BT. Since the bit contacts BCON1 and BCON2 are provided in a layer below the air gap GP, even if the bit contacts BCON1 and BCON2 are provided in the second portion PT2, the adjacent bit contacts BCON1 and BCON2 pass through the air gap GP. Will not cause a short circuit. For this reason, it is not necessary to arrange the bit contacts BCON1 and BCON2 at a place other than the second portion PT2, and thus the semiconductor device SD can be reduced in size.

  In plan view, a direction in which the bit line BT extends (X direction in FIG. 1) is a first direction, and a direction orthogonal to the first direction (Y direction in FIG. 1) is a second direction. Each time the bit line BT crosses the word line WD in plan view, the bit line BT shifts along the second direction, and the shift direction is reversed every time it crosses the two word lines WD. When comparing two adjacent bit lines BT, the first bit line BT is shifted by one pitch in the shift direction in the second direction with respect to the second bit line BT. In the first bit line, the second portion PT2 is reversed until the displacement direction of the first bit line BT is reversed in the direction approaching the second bit line BT and then the displacement direction is reversed. The part between. The first portion PT1 is a portion from when the shift direction of the first bit line BT is reversed in the direction away from the first bit line BT until the shift direction is reversed next. In this way, the memory cell can be further reduced.

  The semiconductor device SD is, for example, a memory chip, but may be a chip in which a memory cell and a logic circuit are mixedly mounted.

  4, 5 and 6 are cross-sectional views showing a method for manufacturing the semiconductor device SD. First, as shown in FIG. 4, the transistor TR is formed on the substrate SUB. This process is as follows, for example.

  First, the element isolation film EI is formed on the substrate SUB. Thereby, regions (element formation regions) where the transistors TR are formed are separated from each other. Next, a gate insulating film and a gate electrode GE are formed on the substrate SUB located in the element formation region. The gate insulating film may be a silicon oxide film or a high dielectric constant film (for example, a hafnium silicate film) having a higher dielectric constant than that of the silicon oxide film. When the gate insulating film is a silicon oxide film, the gate electrode GE is formed of a polysilicon film. When the gate insulating film is a high dielectric constant film, the gate electrode GE is formed of a laminated film of a metal film (for example, TiN) and a polysilicon film. Further, when the gate electrode GE is formed of polysilicon, a polysilicon resistor may be formed on the element isolation film EI in the step of forming the gate electrode GE. Note that the word line WD is also formed in the step of forming the gate electrode GE.

  Next, source and drain extension regions are formed in the substrate SUB located in the element formation region. Next, sidewalls are formed on the sidewalls of the gate electrode. Next, a diffusion layer DIF serving as a source and a drain is formed on the substrate SUB located in the element formation region. Next, a silicide SIL is formed. In this way, the transistor TR is formed on the substrate SUB.

  Next, an interlayer insulating film INS1 is formed on the substrate SUB, the element isolation film EI, and the transistor TR. Next, a resist pattern (not shown) is formed on the interlayer insulating film INS1, and the interlayer insulating film INS1 is etched using the resist pattern as a mask. Thereby, a connection hole is formed in the interlayer insulating film INS1. Thereafter, the resist pattern is removed.

  Next, a conductive film (for example, a W film) is formed in the connection hole and on the interlayer insulating film INS1. Next, a portion of the conductive film located on the interlayer insulating film INS1 is removed using, for example, a CMP method. As a result, the capacitor contact CCON1 and the bit contact BCON1 are embedded in the interlayer insulating film INS1.

  Next, as shown in FIG. 5, an interlayer insulating film INS2 is formed on the interlayer insulating film INS1. Next, a bit contact BCON2 is embedded in the interlayer insulating film INS2. The method for filling the bit contact BCON2 is the same as the method for filling the capacitor contact CCON1.

  Next, a conductive film is formed over the interlayer insulating film INS2. Next, a resist pattern (not shown) is formed on the conductive film, and the conductive film is etched. Thereby, a plurality of bit lines BT are formed. Thereafter, the resist pattern is removed.

  Next, as shown in FIG. 6, an interlayer insulating film INS3 is formed on the interlayer insulating film INS2 and the bit line BT. At this time, an air gap GP is formed in a portion of the bit line BT positioned between the second portions PT2, but no air gap GP is formed in a portion positioned between the first portions PT1. . In particular, in the present embodiment, the interval d2 between the bit lines BT in the second portion PT2 is narrower than the interval d1 between the bit lines BT in the first portion PT1. For this reason, it becomes easy to form the air gap GP only in the portion of the interlayer insulating film INS3 located between the first portions PT1 in plan view. In other words, the air gap GP is hardly formed in the first portion PT1.

  Thereafter, a resist pattern (not shown) is formed on the interlayer insulating film INS3, and the interlayer insulating film INS3 is etched using the resist pattern as a mask. As a result, a connection hole to be the capacitor contact CCON1 is formed in the interlayer insulating film INS3. As described above, the air gap GP is formed only in a portion located between the first portions PT1 in plan view. For this reason, adjacent connection holes are not connected to each other via the air gap GP.

  Next, a conductive film (for example, a W film) is formed in these connection holes and on the interlayer insulating film INS3. Next, a portion of the conductive film located on the interlayer insulating film INS3 is removed using, for example, a CMP method. Thereby, the capacitor contact CCON2 is embedded in the interlayer insulating film INS3.

  Next, an interlayer insulating film INS4 is formed over the interlayer insulating film INS3. Next, a recess is formed on the interlayer insulating film INS4. In this step, the upper surface of the capacitor contact CCON2 is exposed on the bottom surface of the recess. Next, the lower electrode LE is formed on the bottom and side surfaces of the recess. Next, the dielectric layer CINS and the upper electrode UE are formed on the lower electrode LE upper electrode UE and the interlayer insulating film INS4. In this way, the capacitor CND is formed.

  Next, the operation and effect of this embodiment will be described. According to the present embodiment, the air gap GP is formed in at least a part of the region where the capacitor contact CCON2 does not penetrate in the interlayer insulating film INS3 positioned between the adjacent bit lines BT. Therefore, the parasitic capacitance generated between the adjacent bit lines BT can be reduced. The air gap GP does not overlap with the capacitor contact CCON2 in plan view. Therefore, it is possible to suppress a short circuit between adjacent capacitor contacts CCON2 through the air gap GP.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the configuration of the capacitor CND is not limited to the example shown in the present embodiment.

BCON1 Bit contact BCON2 Bit contact BT Bit line CCON1 Capacitor contact CCON2 Capacitor contact CINS Dielectric layer CND Capacitor DIF Diffusion layer EI Element isolation film GE Gate electrode GP Air gap GT Air gap LE Lower electrode MC Memory cell MINS Multilayer wiring layer PT1 First part PT2 Second part SD Semiconductor device SIL Silicide SUB Substrate TR Transistor UE Upper electrode WD Word line

Claims (6)

A substrate,
A plurality of bit lines formed above the substrate;
An insulating layer positioned between the plurality of bit lines;
A capacitor formed above the bit line;
A capacitor contact located between the adjacent bit lines in plan view, penetrating through the insulating layer, and connecting the capacitor and the substrate;
With
The adjacent bit lines have a first portion that sandwiches the capacitor contact between each other, and a second portion that does not sandwich the capacitor contact between each other,
An air gap located between the adjacent bit lines is formed in at least a part of the insulating layer facing the second portion,
In the same bit line, one first portion is sandwiched between two second portions,
A semiconductor device in which the air gap is not formed in a portion overlapping the capacitor contact in the insulating layer facing the one first portion in a direction in which the bit line extends. The semiconductor device according to claim 1,
The semiconductor device wherein an interval between the adjacent bit lines in the first portion is larger than an interval between the adjacent bit lines in the second portion. The semiconductor device according to claim 2,
The interval between the bit lines in the second portion is a semiconductor device that is not more than twice the height of the bit lines. The semiconductor device according to claim 3.
The interval between the adjacent bit lines in the first portion is not less than 30 nm and not more than 120 nm,
The semiconductor device, wherein an interval between the adjacent bit lines in the second portion is not less than 60 nm and not more than 240 nm. The semiconductor device according to claim 1,
A bit contact connecting the bit line and the substrate;
The bit contact is a semiconductor device connected to the second portion of the bit line. The semiconductor device according to claim 1,
In a plan view, when the direction in which the bit line extends is a first direction and the direction orthogonal to the first direction is a second direction,
A plurality of word lines that overlap the plurality of bit lines in plan view and extend in the second direction;
The plurality of bit lines are displaced along the second direction each time they intersect the word line in plan view, and the displacement direction is reversed each time the two word lines intersect.
The first bit line has a shift period of one pitch shift in the second direction with respect to the second bit line located next to the first bit line,
In the first bit line, the second portion is a period from when the shift direction of the first bit line is reversed in a direction approaching the second bit line until the next shift direction is reversed. A semiconductor device that is in between.

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