JP2015014924A - Topology display program and information processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make topology display for a printed circuit board easy to understand.SOLUTION: A method of the present invention includes processes of: (A) identifying one or a plurality of symbols corresponding to components other than components of interest in topology data stored in a data storage unit storing therein the topology data, the topology data being on at least a part of wiring elements and components on a design target wiring board; (B) grouping a route to a nearest branch point along a route connected to each symbol in the topology for each symbol or each of the symbols; (C) replacing the grouped route by a second type of symbol; and (D) displaying topology data including the second type of symbols.

Description

  The present invention relates to a technique for supporting the design of a wiring board.

  As the printed wiring board is miniaturized and densified, the structure and wiring of the printed wiring board have become complicated. Factors for complication include the fact that wiring, which has been one-to-one transmission so far, has become one-to-many transmission, and that a single-layer board has become a multilayer board.

  In addition, topology display is complicated even when topology information is displayed on transmission line information of complicated printed wiring boards. When the topology display becomes complicated, various problems may occur. Specifically, it takes a long time to draw, resulting in a decrease in response, an inability to edit the topology easily, an increase in work time, and a work mistake caused by editing by a designer with little knowledge. It becomes easier.

JP 2010-39598 A

  Accordingly, an object of the present invention, according to one aspect, is to provide a technique for making it easy to understand the topology display of a wiring board.

  The display method according to one aspect of the present invention should be noted in (A) topology data stored in a data storage unit that stores topology data for at least some of the wirings and components in the wiring board to be designed. Identify one or more symbols corresponding to parts other than parts, and (B) for each of the one or more symbols, group the paths to the nearest branch point by following the path connected to the symbol in the topology , (C) replacing the grouped path with the second type symbol, and (D) displaying the topology data including the second type symbol.

  In one aspect, the topology display of the wiring board can be easily understood.

FIG. 1 is a functional block diagram of the information processing apparatus according to the embodiment. FIG. 2 is a diagram showing model assignment. FIG. 3 is a diagram showing a main processing flow according to the present embodiment. FIG. 4 is a diagram illustrating an example of layout data. FIG. 5 is a diagram illustrating an example of a normal topology display. FIG. 6 is a diagram illustrating a process flow of the simple display process. FIG. 7 is a diagram illustrating an example of a simple display group. FIG. 8 is a diagram illustrating a process flow of the simple display process. FIG. 9 is a diagram illustrating a state in which the simple display group is blocked. FIG. 10 is a diagram illustrating a state after merging the blocks of the simple display group. FIG. 11 is a diagram illustrating a state when further merging is performed. FIG. 12 is a diagram showing a main processing flow according to the present embodiment. FIG. 13 is a functional block diagram of a computer.

  FIG. 1 shows a configuration example of an information processing apparatus 100 according to an embodiment of the present invention.

  The information processing apparatus 100 according to the present embodiment includes a first data storage unit 101, a mounting design support unit 102, a second data storage unit 103, a topology editor 104, a third data storage unit 105, and an analysis process. Part 106.

  The first data storage unit 101 stores, for example, component information and connection information between components. In addition to information on the connected net, model data representing the characteristics of the pin is also assigned to each pin of the component. The mounting design support unit 102 has a conventional CAD (Computer-Aided Design) function, and uses the data stored in the first data storage unit 101 to perform wiring in accordance with an instruction from the designer. Set the position information of components and wiring between components on the board, information about the wiring (layer, type, etc.), information of symbols of the components on the wiring board (size, shape, etc.). 2 is stored in the data storage unit 103.

  When the layout design specifying the specific circuit portion is instructed by the designer during the mounting design by the mounting design support unit 102, the topology editor 104 reads the specific data from the data stored in the second data storage unit 103. Topology data for the circuit portion is generated, displayed on the display device, and stored in the third data storage unit 105. The processing for generating and displaying the topology data is the same as the conventional one. The topology data is data of a wiring form representing symbols corresponding to components, connection points, branch points, and the like and connection relations between them, and includes information such as impedance and length of the wiring. For topology display, data on the wiring form is used.

  When the normal topology display generated by the topology editor 104 is complicated, the simple display processing unit 1040 included in the topology editor 104 is activated in response to an instruction from the designer, and the third data storage unit 105 Data for simplified topology display is generated from the stored topology data and displayed on the display device. Note that simple topology display may be performed from the beginning.

  The analysis processing unit 106 performs, for example, noise analysis using the topology data stored in the third data storage unit 105, for example, and the result of the noise analysis (for example, data on a component to be corrected, etc.) Store in the data storage unit 105. The analysis processing such as noise analysis is the same as the conventional one.

  Next, processing contents of the information processing apparatus 100 according to the present embodiment will be described with reference to FIGS.

  Here, it is assumed that the circuit design has already been completed and the first data storage unit 101 stores the component information and the connection information between the components as described above. Each pin of the component is assigned model data representing the characteristics of the pin. For example, data as shown in FIG. 2 is also stored in the first data storage unit 101. In the example of FIG. 2, the model ID assigned to the pin of the component is associated with the component ID and the pin ID. However, in the present embodiment, as shown in the third line of FIG. 2, it is assumed that a model is not assigned to some pins.

  First, the designer instructs the mounting design support unit 102 to perform mounting design using the data stored in the first data storage unit 101, and wiring between components on the wiring board Position information, wiring information (layer, type, etc.), component symbol information (size, shape, etc.) on the wiring board are set, and such information is stored in the second data storage unit 103 ( FIG. 3: Step S1). For example, as shown in FIG. 4, components are arranged on a wiring board and wiring between components is performed. As shown in FIG. 4, parts may be wired through different layers using vias.

  When the packaging design is completed and the designer issues a layout cooperation instruction specifying at least a specific circuit portion, the packaging design support unit 102 accepts the layout cooperation instruction (step S3) and starts the topology editor 104 To do. The topology editor 104 generates topology data for a specific circuit portion, and performs normal topology display on the display device (step S4). Note that the topology data is stored in the third data storage unit 105. For example, a topology display as shown in FIG. 5 is made.

  In the example of FIG. 5, the symbols A to G of the active component and the symbol of the passive component represented by a rectangle are connected. In the present embodiment, attention is paid to active components, and the processing is actually performed on the pins of the active components. However, since the processing is performed on a specific circuit portion, one pin is handled as one component. The black circles represent branch points and other nodes (such as net connection points). Symbols C and F represented by dotted lines indicate parts that are not assigned a model.

  In this example, the symbol A is connected to the branch point a, and the symbol G is also connected to the branch point a via a passive component or the like. The branch point a is also connected to the branch point b via a passive component or the like. The branch point b is also connected to the branch point d and further connected to the branch point c via a passive component. The branch point d is connected to the symbol F and further connected to the branch point e. The branch point e is connected to the symbol E and the symbol D through passive components or the like. The branch point c is connected to the symbol C, and is connected to the symbol B via a passive component or the like. In this example, a simple example is shown for explanation, but it is assumed that a complicated and difficult-to-understand topology display is made.

  The designer instructs simple display for easy understanding, and the topology editor 104 accepts the simple display instruction (step S5) and causes the simple display processing unit 1040 to perform processing. The simple display processing unit 1040 specifies a part (specifically, a pin of the part) in which a model is not allocated in a specific circuit part based on the data (for example, FIG. 2) stored in the first data storage part 101. Then, a symbol corresponding to a part other than the part not assigned to the model is set as a processing target symbol (step S6).

  Then, the simple display processing unit 1040 executes simple display processing using the topology data stored in the third data storage unit 105 (step S7). The simple display process will be described with reference to FIGS.

  The simple display processing unit 1040 identifies one unprocessed symbol among the symbols to be processed (FIG. 6: Step S21). Then, the simple display processing unit 1040 specifies a branch point by tracing from the specified symbol (step S23). Data for branch points is retained for later processing. The simple display processing unit 1040 sets the route from the identified symbol to the branch point in the simple display group (step S25).

  In the example of FIG. 5, when processing is performed on the symbol B, the route from the symbol B to the branch point c is set in the simple display group 1000 as shown in FIG. 7. When processing is performed on the symbol D, a route from the symbol D to the branch point e is set in the simple display group 1100. Further, when processing is performed on the symbol E, a route from the symbol E to the branch point e is set in the simple display group 1200. When processing is performed on the symbol G, the route from the symbol G to the branch point a is set in the simple display group 1300.

  Thereafter, the simple display processing unit 1040 determines whether there is an unprocessed symbol to be processed (step S27). If there is an unprocessed symbol to be processed, the process returns to step S21. On the other hand, if there is no unprocessed symbol to be processed, the process proceeds to the process of FIG.

  The simple display processing unit 1040 identifies one unprocessed branch point among the branch points identified in step S23 (step S29). Then, the simple display processing unit 1040 determines whether or not there are a plurality of simple display groups directly connected to the specified branch point, and if there are a plurality of simple display groups directly connected to the specified branch point, these are displayed. Are merged (step S31). When the simple display group as shown in FIG. 7 is blocked, a state as shown in FIG. 9 is obtained. In FIG. 9, the simplified display group for symbol A is shown as block A ′, the simplified display group 1000 for symbol B is shown as block B ′, and the simplified display group 1100 for symbol D is shown as block D ′. The simplified display group 1200 for the symbol E is shown as a block E ′, and the simplified display group 1300 for the symbol G is shown as a block G ′. In addition, as in these examples, if all the blocks directly connected to the branch point are blocks in the simple display group, the branch points are also merged. However, even when a symbol other than the simple display group is connected to the branch point, if the other blocks are blocks of the simple display group, the blocks are merged with the branch point and the symbol remaining.

  In such a state, blocks A 'and G' satisfy the condition for branch point a, so they are merged. Further, since the blocks D ′ and E ′ satisfy the condition for the branch point e, they are merged. Then, the state shown in FIG. 10 is obtained. In FIG. 10, a block A′G ′ is a block obtained by merging blocks A ′ and G ′. The block D′ E ′ is a block obtained by merging the blocks D ′ and E ′.

  Furthermore, if there is a node on the route to the adjacent branch point, the simple display processing unit 1040 further merges it into the simple display group (step S33). When the state shown in FIG. 10 is processed, for example, the state shown in FIG. 11 is obtained. Since there are black and rectangular nodes between the block A'G 'and the adjacent branch point b, these nodes are merged into the block A'G'. Similarly, since there is a black circle node between the block D'E 'and the adjacent branch point d, this node is merged with the block D'E'. When the simplified topology display of FIG. 10 is processed, for example, a state as shown in FIG. 11 is obtained.

  Then, the simple display processing unit 1040 determines whether there is an unprocessed branch point (step S35). If there is an unprocessed branch point, the process returns to step S29. On the other hand, when there is no unprocessed branch point, the simple display processing unit 1040 replaces the simple display group with the simple display symbol, and stores the simple topology display data in the third data storage unit 105 (step S37). ). Then, the process returns to the caller process.

  According to this processing, simple topology display including simple display symbols (blocks with hatching) as shown in FIG. 11 is performed. Compared with the normal topology display shown in FIG. 5, it can be seen that the model can easily recognize unassigned symbols C and F.

  The simple display process can be varied, for example, when the process is completed up to step S27 (the process result is FIG. 9) or when step S33 is not performed (the process result is FIG. 10).

  Returning to the description of the processing in FIG. 3, the topology editor 104 causes the display device to display the data of the simple topology display generated by the simple display processing unit 1040 (step S <b> 9). As a result, the designer can easily specify the parts not assigned to the model. Therefore, the designer gives an instruction to the topology editor 104 or the like, and the topology editor 104 or the like assigns a model to a part that has not been assigned a model (step S11). For example, in the data structure as shown in FIG. 2, the model ID is registered for a record in which the model ID is not registered in the model column. The result of model assignment is also reflected in the topology data.

  Then, the analysis processing unit 106 performs analysis processing such as noise analysis, for example, using data stored in the third data storage unit 105, for example, in accordance with an instruction from the designer (step S13). This process is the same as in the prior art. However, the analysis processing unit 106 stores, in the third data storage unit 105, data about a component (for example, a pin of the component) to be corrected for noise countermeasures or the like as a processing result of the analysis processing. Then, the processing shifts to the processing in FIG.

  Shifting to the description of the processing in FIG. 12, the topology editor 104 identifies a component (specifically, a pin of the component) to be corrected from the data stored in the third data storage unit 105 (step S41). . Then, the simple display processing unit 1040 of the topology editor 104 sets a symbol other than the symbol of the component to be corrected as the processing target symbol in the topology data (step S43).

  Thereafter, the simple display processing unit 1040 executes simple display processing (step S45). This simple display process is the same as the process described above. In the example described above, the symbol of the part that has already been assigned the model is the symbol to be processed, but here the symbol of the part that does not need to be corrected is the symbol to be processed. That is, in any of FIGS. 9 to 11, it becomes possible to easily grasp that the symbols C and F indicated by dotted lines are symbols of parts to be corrected.

  Then, the topology editor 104 causes the display device to display the simple topology display data generated in step S45 (step S47). Then, the designer instructs the topology editor 104 and the like to perform correction work (step S49).

  By executing the processing as described above, the topology display can be simplified in the design of the printed wiring board, and the work efficiency can be improved by making it easier to identify the parts to be noted.

  Further, in the example described above, an example in which simple topology display is performed after performing normal topology display is shown, but simple topology display may be performed without performing normal topology display. In this case, since the number of symbols to be drawn is reduced, the drawing process is speeded up, and the response of the information processing apparatus 100 is also speeded up.

  Although the embodiment of the present invention has been described above, the present invention is not limited to this. For example, the functional block diagram shown in FIG. 1 is an example, and may not match the program module configuration.

  As for the processing flow, as long as the processing result does not change, the order of the steps may be changed or a plurality of steps may be executed in parallel.

  The information processing apparatus 100 described above is a computer apparatus, and as shown in FIG. 13, a memory 2501, a CPU 2503, a hard disk drive (HDD) 2505, and a display control unit 2507 connected to the display apparatus 2509. A drive device 2513 for the removable disk 2511, an input device 2515, and a communication control unit 2517 for connecting to a network are connected by a bus 2519. An operating system (OS) and an application program for executing the processing in this embodiment are stored in the HDD 2505, and are read from the HDD 2505 to the memory 2501 when executed by the CPU 2503. The CPU 2503 controls the display control unit 2507, the communication control unit 2517, and the drive device 2513 according to the processing content of the application program, and performs a predetermined operation. Further, data in the middle of processing is mainly stored in the memory 2501, but may be stored in the HDD 2505. In an embodiment of the present technology, an application program for performing the above-described processing is stored in a computer-readable removable disk 2511 and distributed, and installed from the drive device 2513 to the HDD 2505. In some cases, the HDD 2505 may be installed via a network such as the Internet and the communication control unit 2517. Such a computer apparatus realizes various functions as described above by organically cooperating hardware such as the CPU 2503 and the memory 2501 described above and programs such as the OS and application programs. .

  The above-described embodiment can be summarized as follows.

  In the display method according to the present embodiment, (A) a component to be noted in topology data stored in a data storage unit that stores topology data for at least a part of wirings and components in a wiring board to be designed Identifying one or more symbols corresponding to a component other than (B), for each of the one or more symbols, grouping the route to the nearest branch point by following the route connected to the symbol in the topology; (C) Substituting the grouped path with the second type symbol, and (D) displaying the topology data including the second type symbol.

  By performing such processing, the path extending from the symbol corresponding to the part other than the part to be noted is simplified to the branch point, so that the part to be noticed can be easily recognized.

  Further, the display method described above further includes (E) a process of integrating the plurality of second type symbols when a plurality of second type symbols are connected to the branch point. Also good. In this way, simplification can be further advanced.

  Further, the integration process described above includes a process of integrating the branch point and all the second type symbols when all the symbols connected to the branch point are the second type symbols. You may make it. This simplifies further.

  In addition, the display method described above includes: (F) for each of the second type symbols, the route to the nearest branch point is traced along the route connected to the second type symbol. A process of integrating the symbols into types may be further included. This simplifies further.

  Note that the part to be noted may be a part to which no characteristic data is assigned or a part for which correction is indicated.

  It is possible to create a program for causing a processor (or computer) to perform the processing according to the above method, and the program can be read by a computer such as a flexible disk, a CD-ROM, a magneto-optical disk, a semiconductor memory, and a hard disk. Stored in a storage medium or storage device. The intermediate processing result is temporarily stored in a storage device such as a main memory.

  Regarding the embodiments including the above-described embodiments, the following additional notes are disclosed.

(Appendix 1)
In the topology data stored in the data storage unit that stores the topology data for at least some of the wirings and components in the wiring board to be designed, one or more symbols corresponding to components other than the component to be noted are selected. Identify,
For each of the one or more symbols, group the paths to the nearest branch point following the path connected to the symbol in the topology;
Replace the grouped path with a second type of symbol,
A program for causing a computer to execute a process of displaying topology data including the second type of symbol.

(Appendix 2)
The program according to appendix 1, for causing the computer to further execute a process of integrating the plurality of second type symbols when a plurality of second type symbols are connected to the branch point.

(Appendix 3)
The integrating process is
The program according to appendix 2, including a process of integrating the branch point and all the second type symbols when all the symbols connected to the branch point are the second type symbols.

(Appendix 4)
For each of the second type symbols, the computer further includes a process of integrating a route from the path connected to the second type symbol to the nearest branch point into the second type symbol. The program according to attachment 2 for execution.

(Appendix 5)
The program according to any one of appendices 1 to 4, wherein the component to be noted is a component to which characteristic data is not assigned or a component for which correction is indicated.

(Appendix 6)
In the topology data stored in the data storage unit that stores the topology data for at least some of the wirings and components in the wiring board to be designed, one or more symbols corresponding to components other than the component to be noted are selected. Means to identify;
For each of the one or more symbols, means for grouping a route to the nearest branch point following a route connected to the symbol in the topology;
Means for replacing the grouped path with a second type of symbol;
Means for displaying topology data including the second type of symbols;
An information processing apparatus.

101 First data storage unit 102 Mounting design support unit 103 Second data storage unit 104 Topology editor 105 Third data storage unit 106 Analysis processing unit 1040 Simple display processing unit

Claims (6)

In the topology data stored in the data storage unit that stores the topology data for at least some of the wirings and components in the wiring board to be designed, one or more symbols corresponding to components other than the component to be noted are selected. Identify,
For each of the one or more symbols, group the paths to the nearest branch point following the path connected to the symbol in the topology;
Replace the grouped path with a second type of symbol,
A program for causing a computer to execute a process of displaying topology data including the second type of symbol. The program according to claim 1, further comprising: causing the computer to further execute a process of integrating the plurality of second type symbols when the plurality of second type symbols are connected to the branch point. The integrating process is
The program according to claim 2, further comprising a process of integrating the branch point and all the second type symbols when all of the symbols connected to the branch point are the second type symbols. For each of the second type symbols, the computer further includes a process of integrating a route from the path connected to the second type symbol to the nearest branch point into the second type symbol. The program according to claim 2 for execution. The program according to any one of claims 1 to 4, wherein the part to be noted is a part to which characteristic data is not assigned or a part with correction indication. In the topology data stored in the data storage unit that stores the topology data for at least some of the wirings and components in the wiring board to be designed, one or more symbols corresponding to components other than the component to be noted are selected. Means to identify;
For each of the one or more symbols, means for grouping a route to the nearest branch point following a route connected to the symbol in the topology;
Means for replacing the grouped path with a second type of symbol;
Means for displaying topology data including the second type of symbols;
An information processing apparatus.

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