JP2015011524A - Electronic control device and method of controlling writing data into non-volatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the frequency of writing into a writable non-volatile memory while reducing the risk accompanied by data loss.SOLUTION: A CPU 2 restricts writing of data A to D into each of memory blocks 5a to 5d of an EEPROM 5 so that the frequency of writing to the EEPROM 5 does not reach an upper limit early. When there is a writing request of data to each of the memory blocks 5a to 5d of the EEPROM 5, the CPU 2 performs restriction to retain execution of writing (not to write until the frequency of retainment reaches the frequency of no permission) on the basis of the frequency of no permission of writing set according to importance, frequency of data update, and an actual frequency of writing of the data A to D of each of the memory blocks 5a to 5d.

Description

  The present invention relates to an electronic control device and a data write control method for a nonvolatile memory that restrict data writing to a rewritable nonvolatile memory.

  For example, a microcomputer provided in an electronic control device such as an engine control device for a vehicle includes a rewritable nonvolatile memory such as an EEPROM in addition to a CPU, a ROM, a RAM, and the like. In this case, the data used for control is stored in the RAM buffer while being updated as needed, but a rewritable non-volatile memory is provided so as to cope with the loss of RAM data when the power is cut off. The buffer data is appropriately written (rewritten).

  By the way, in a rewritable nonvolatile memory such as an EEPROM, there is an upper limit (for example, 10,000 times) in the number of writing (rewriting). For this reason, in order to ensure a sufficient life for the product life of the electronic control device, a device is conceived so that the number of times of writing to the rewritable nonvolatile memory does not reach the upper limit early.

  That is, for example, in Patent Document 1, the storage area of the EEPROM is divided into a plurality of memory blocks, and when the number of times of writing in a certain memory block reaches a predetermined value, the memory content is replaced with another memory block having a lower number of times of writing. I am doing so. In Patent Document 2, the data stored in the EEPROM is divided into data X having a high rewrite frequency and data Y having a low rewrite frequency, and rewriting is performed unconditionally for the data Y having a low rewrite frequency. For high data X, rewriting is restricted. This restriction means that, at first, one rewrite is executed for 10 rewrite requests, and when the number of rewrites exceeds 20,000, one rewrite is executed for 35 rewrite requests. Is.

JP-A-6-338195 JP 2012-226575 A

  However, in the technique disclosed in Patent Document 1, it is necessary to add a configuration such as a mapping circuit and a write count counter in order to exchange the stored contents between the memory blocks. is there. Further, although the technique of Patent Document 2 restricts the number of times of rewriting, since it is limited only by the frequency of rewriting, there is a risk that important data and less important data may be similarly lost. From the viewpoint of avoiding risks due to data loss, it is not sufficiently effective.

  The present invention has been made in view of the above circumstances, and its purpose is to reduce the number of times of writing to a rewritable nonvolatile memory while reducing the risk associated with data loss and to prevent the number of times of writing from reaching the upper limit. It is an object of the present invention to provide an electronic control device and a data write control method for a non-volatile memory.

  An electronic control unit according to the present invention includes a restricting unit that restricts writing of data in a buffer memory to each memory block of a rewritable nonvolatile memory having a plurality of memory blocks that read and write data at the same timing. In addition, the restricting means is characterized in that data writing is restricted for each memory block in accordance with the importance of data related to each memory block of the nonvolatile memory (invention of claim 1).

  The nonvolatile memory data write control method of the present invention is a nonvolatile memory for writing buffer memory data to a rewritable nonvolatile memory having a plurality of memory blocks for reading and writing data at the same timing. A data write control method for a memory, characterized in that data write is limited for each memory block in accordance with the importance of data related to each memory block of the nonvolatile memory (invention of claim 5). .

  In the present invention, even when there is a data write request to a rewritable nonvolatile memory, control is performed not to perform (thinning out) data writing by the limiting means. Thereby, even in a rewritable nonvolatile memory, even if there is an upper limit on the number of times of writing (rewriting), the upper limit of the number of times of writing is prevented. At this time, the restricting means restricts data writing for each memory block in accordance with the importance of the data related to each memory block of the nonvolatile memory, so that the risk due to loss of important data can be reduced.

  The importance of data referred to in the present invention can be determined by the degree of risk associated with the loss of data (the greater the risk, the higher the importance). However, the upper limit of the number of times of writing is the same for both the memory block that stores highly important data and the memory block that stores less important data. In practice, it is important to determine what kind of pattern is used before reaching the upper limit.

  For example, the pattern of increasing the limit when the limit is reduced by reducing the limit at the beginning of use and keeping the frequency of rewriting high at the beginning of use for the entire length of the product life, that is, approaching the upper limit count relatively early. A pattern that reduces the risk associated with data loss in the first half of usage, and conversely, a pattern that initially increases the limit and decreases the limit in the second half to increase the frequency of rewriting. Although the risk involved is relatively large, the pattern that reduces the risk in the second half of use, the intermediate pattern, that is, the pattern that keeps the average rewriting frequency to equalize the risk associated with data loss throughout the use , Etc. are conceivable.

The block diagram which shows one Example of this invention and shows the electrical structure of a microcomputer roughly The figure which shows typically the correspondence between the memory block of EEPROM, and each data The flowchart which shows the whole process sequence of the data write control which CPU performs. Flow chart showing the detailed processing procedure of write execution determination The figure which shows the example of the non-permission count table in the case of importance 1

  Hereinafter, an embodiment in which the present invention is applied to an engine control device for a vehicle (automobile) will be described with reference to the drawings. As shown in FIG. 1, an engine control device for a vehicle as an electronic control device includes a microcomputer 1. The microcomputer 1 includes a CPU 2, a ROM 3, a RAM 4, and an EEPROM 5, which is a rewritable nonvolatile memory. The microcomputer 1 (RAM 4) is always supplied with operating power from an in-vehicle battery.

  Although detailed illustration and description are omitted, an input / output circuit is connected to the microcomputer 1 (CPU 2), and signals from various sensors that are open to engine control are input. The microcomputer 1 (CPU 2) executes various controls such as fuel injection control and ignition timing control for the engine based on signals from various sensors in accordance with a control program stored in the ROM 3. . In this case, data used for control, such as diagnostic data and data of various sensors, is stored in the buffer memory of the RAM 4 while being updated as needed.

  The data in the buffer memory is appropriately written (rewritten) in the EEPROM 5 so as to cope with the loss of data in the RAM 4 when the power is shut off. At this time, the EEPROM 5 is configured to have a plurality of memory blocks for reading and writing data at the same timing in the internal storage unit, and the data of the buffer memory is written in each memory block. ing. FIG. 2 shows an example in which the EEPROM 5 is provided with four memory blocks, that is, first to fourth memory blocks 5a to 5d, and each of the memory blocks 5a to 5d has data. A to D are written.

  The CPU 2 stores the data in the buffer memory of the RAM 4 in response to a write request that occurs when the data in the buffer memory of the RAM 4 is updated or when one trip (from one engine start to stop of the vehicle) ends. A process of writing (rewriting) the stored data into the corresponding memory blocks 5a to 5d of the EEPROM 5 is executed. Therefore, the CPU 2 functions as data writing means.

  In the EEPROM 5, there is an upper limit (for example, 10,000 times) in the number of times of writing (rewriting) to each of the memory blocks 5a to 5d. Therefore, if unlimited writing of data to the EEPROM 5 is performed, there is a possibility that a sufficient life cannot be obtained with respect to the life of the product (automobile). Therefore, in this embodiment, the CPU 2 limits the writing of the data A to D to the memory blocks 5a to 5d of the EEPROM 5 so that the number of times of writing to the EEPROM 5 does not reach the upper limit early.

  As will be described later in the explanation of the operation (flowchart explanation), when there is a data write request to each of the memory blocks 5a to 5d of the EEPROM 5, the CPU 2 determines the importance of the data A to D of each of the memory blocks 5a to 5d. Based on the number of write disapproval times set accordingly, the execution of the write is deferred (not written until the hold number reaches the non-permission number), thereby limiting. In the present embodiment, in addition to the importance of the data A to D of the memory blocks 5a to 5d, the data update frequency of the corresponding data A to D (each of the memory blocks 5a to 5d), and the corresponding memory block 5a to 5d. In 5d, the number of non-permissions is set according to the actual number of times of writing actually performed in the past.

  At this time, as shown in FIG. 2, regarding the first to fourth memory blocks 5a to 5d of the EEPROM 5, as the attached information, the importance of the stored data A to D, the data update frequency of the data A to D, Data of the actual write count and write hold count is stored. Among them, the data update frequency indicates how many times the corresponding data A to D are updated on average in one trip, and is set, for example, in five stages of 1 to 5. The higher the data update frequency, the greater the number of non-permissions.

  Regarding the importance of the data A to D of the first to fourth memory blocks 5a to 5d and the data update frequency data of the data A to D of the first to fourth memory blocks 5a to 5d, Since it is fixed data determined in advance from the control conditions, it is stored in the ROM 3. Further, the data of the actual write count is stored in the corresponding memory blocks 5a to 5d of the EEPROM 5, and is rewritten together with the data rewrite. Furthermore, the write pending count data of each of the memory blocks 5a to 5d is stored in the RAM 4 and is sequentially updated.

  Here, the importance of the data A to D of each of the memory blocks 5a to 5d can be determined by the degree of risk associated with the loss of the corresponding data (the greater the risk, the higher the importance). However, since the upper limit of the number of writings is the same for both the memory block that stores highly important data and the memory block that stores data that is not very important, in this embodiment, the upper limit is reached. The importance is set (determined) in three levels of 1, 2, and 3 depending on the pattern in which the restriction is actually applied.

  Importance level 1 is, for example, a pattern in which the limit is reduced at the beginning of use and the rewrite frequency is kept relatively high for the entire product life, and the limit is increased when the upper limit is approached. Although it approaches the upper limit number of times as early as possible, it is a pattern that reduces the risk associated with data loss in the first half of use. In severity 3, on the contrary, a pattern that increases the limit at the beginning and decreases the limit in the second half to increase the frequency of rewriting, that is, although the risk associated with data loss is relatively large in the first half, It is a pattern that makes the risk relatively small in the second half of use. The importance level 2 is an intermediate pattern, that is, a pattern in which the average rewrite frequency is continued and the risk associated with data loss is equalized over the entire period of use.

  The non-permission count is set according to a non-permission count table stored in advance in the ROM 3 as shown in FIG. FIG. 5 shows an example of the number of non-permissions set in accordance with data of the data update frequency and the actual write count when the importance level is 1. Here, for example, when the update frequency is 1 (the least), the number of non-permissions is 1 until the actual write count is 2000, and the number of disapprovals is 2 when the actual write count exceeds 2000 and reaches 4000. The number of times of disapproval is set. When the actual number of writes exceeds 8000, the number of non-permissions increases rapidly. Further, as the update frequency increases to 2, 3, 4, and 5, the number of non-permissions increases proportionally (stepwise).

  Although not shown in the figure, in the case of the importance level 3, contrary to the case of the importance level 1, the number of non-permissions is set to be relatively large when the actual write count is 2000 times. The degree of increase in the number of non-permissions as the number of actual writes increases is relatively small. In the case of importance 2, the intermediate value (degree of increase in the number of non-permissions) is used. Therefore, the CPU 2 also functions as a limiting unit according to the present invention, and the data write control method according to the present embodiment is executed by the CPU 2.

  Next, the operation of the above configuration will be described with reference to FIGS. The flowchart of FIG. 3 shows the flow of the entire process of data writing to the memory blocks 5a to 5d of the EEPROM 5, which is executed by the CPU 2 when there is a data write request. The flowchart of FIG. 4 shows the detailed procedure of the write execution determination process in step S2 of the flowchart of FIG.

  That is, in FIG. 3, when there is a data write request, first, in step S1, the actual write count, write hold count, data update frequency in the memory blocks 5a to 5d (data A to D) to which the data is written, Data of importance is acquired. In the next step S2, it is determined whether or not writing is performed. Details of the determination processing in step S2 will be described later (the flowchart in FIG. 4). In step S3, it is determined whether or not writing is to be performed. If writing is not performed (suspended) (No in step S3), the number of write suspensions is counted up in the next step S4, and the process ends. .

  On the other hand, when writing is performed (Yes in step S3), the actual write count of the corresponding memory block is counted up in step S5, and data is stored in the corresponding memory block in step S6. Is written. In step S7, the write suspension count in the RAM 4 is cleared, and the process ends.

  Next, in FIG. 4 which shows the detailed processing procedure of the writing execution determination of the said step S2, in step S11, it illustrates in FIG. 5 from the data of the real write frequency, data update frequency, and importance which were taken in in the said step S1. The number of non-permissions is obtained by referring to the non-permission number table. In the next step S12, it is determined whether or not the current write suspension count stored in the RAM 4 is equal to or greater than the non-permission count determined in step S11. If the write suspension count is equal to or greater than the non-permission count (Yes in step S12), it is determined in step S13 that “write is performed”. If the number of write suspensions is less than the number of non-permissions (No in step S12), it is determined in step S14 that "write is not performed".

  In the case of the importance level 1 shown in FIG. 5, when a specific example is given, for example, when the update frequency is 1 and the actual write count is up to 2000, the non-permission count is 1. Accordingly, writing is suspended in the first data write request, but when there is a second data write request, data is written. For example, if the update frequency is 4 and the actual write count is 4001 to 6000, the non-permission count is 12, and even if there is a data write request, the data write is suspended until the 12th and the 13th data write At the request, data writing is finally executed. Further, when the actual number of writes exceeds 8000, the number of non-permissions is set much higher than before regardless of the update frequency.

  As described above, according to the electronic controller and nonvolatile memory data write control method of the present embodiment, even when there is a data write request to the EEPROM 5, the CPU 2 does not write (thin) the data. Is done. As a result, even if there is an upper limit on the number of times of writing (rewriting) to the EEPROM 5, the number of times of writing can be reduced and the number of times of writing can be prevented from reaching the upper limit at an early stage. At this time, the CPU 2 limits the writing of data for each of the memory blocks 5a to 5d in accordance with the importance of the data relating to the memory blocks 5a to 5d of the EEPROM 5, thereby reducing the risk of loss of important data. be able to.

  In particular, in the present embodiment, in addition to the importance of data, the data update frequency of the corresponding data and the actual write count are limited, so that the data writing to each of the memory blocks 5a to 5d is limited. It becomes possible to perform finer control. Furthermore, according to the present embodiment, of course, in order to perform the above control, there is no particular complication of the configuration (increase in hardware configuration).

  In the above-described embodiment, the data writing is restricted according to the data update frequency and the actual number of times of writing in addition to the importance of the data. Further, the restriction may be performed according to the actual number of times of writing, or the restriction may be performed according to the importance and the data update frequency. Specific numerical values (FIG. 5) and the like in the above embodiment are merely examples, and can be set as appropriate. In addition, the rewritable non-volatile memory is not limited to the EEPROM, and can be implemented in the same manner even if it is a flash memory. The present invention can be applied to all electronic control devices other than the engine control device of the vehicle. Various modifications can be made without departing from the scope of the invention.

  In the drawings, 1 is a microcomputer (electronic control unit), 2 is a CPU, 3 is a ROM, 4 is a RAM, 5 is an EEPROM (rewritable nonvolatile memory), and 5 a to 5 d are memory blocks.

Claims (8)

A rewritable nonvolatile memory having a plurality of memory blocks for reading and writing data at the same timing;
A buffer memory for storing data for writing to the nonvolatile memory;
Data writing means for writing data of the buffer memory into the nonvolatile memory;
Limiting means for limiting data writing to each memory block of the non-volatile memory, and
The electronic control device according to claim 1, wherein the restricting means restricts data writing for each memory block in accordance with the importance of the data related to each memory block of the nonvolatile memory.   The restricting unit suspends execution of writing in response to a data write request based on the number of write disapprovals set according to the importance of the data for each memory block of the nonvolatile memory. The electronic control device according to claim 1.   In accordance with the data update frequency of the corresponding data in the buffer memory, in addition to the importance of the data, the restricting unit may reduce the number of times of writing as the data update frequency increases. 3. The electronic control device according to claim 1, wherein data writing is restricted.   The limiting means, in addition to the importance of the data, according to the actual number of times of writing performed in the corresponding memory block of the nonvolatile memory, so that the larger the number of actual writes, the smaller the number of writes, The electronic control device according to claim 1, wherein data writing to each memory block is restricted. A non-volatile memory data write control method for writing buffer memory data to a rewritable non-volatile memory having a plurality of memory blocks for reading and writing data at the same timing,
A data writing control method for a nonvolatile memory, wherein data writing is restricted for each memory block in accordance with the importance of data relating to each memory block of the nonvolatile memory.   Write data to each memory block by deferring execution of data write requests based on the number of write disapprovals set according to the importance of the data for each memory block of the nonvolatile memory The data write control method for a nonvolatile memory according to claim 5, wherein:   In addition to the importance of the data, according to the data update frequency of the corresponding data in the buffer memory, the data writing to each memory block is limited so that the number of times of writing decreases as the data update frequency increases. The data write control method for a non-volatile memory according to claim 5 or 6.   In addition to the importance of the data, according to the actual number of times of writing performed in the corresponding memory block of the nonvolatile memory, the number of times of writing is decreased as the actual number of times of writing increases. 8. The data write control method for a nonvolatile memory according to claim 5, wherein data write is limited.

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