JP2006291720A - Control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control device capable of shortening data refreshing time. <P>SOLUTION: Priority for executing refreshing process for every control condition of a control object for each data group divided into a block unit for every control process is established. When irregularity of data occurs in data stored in an internal memory, refreshing process is executed from the data group having higher priority established for current control condition. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a control device that executes various control processes related to an engine, for example.

Conventionally, for example, in the technique disclosed in Patent Document 1, the correction data stored in the EEPROM of the pump-mounted control device is transferred to the non-pump-mounted control device and stored in the RAM of the non-pump-mounted control device. Then, the correction data stored in the RAM is used to drive and control the injection amount control actuator and the injection timing control actuator.
JP-A-8-284731

  FIG. 10 is a diagram illustrating a main configuration of an engine ECU that executes various control processes related to the engine. The engine ECU executes various control processes using data stored in a static random access memory (SRAM) of the microcomputer.

  By the way, data in SRAM may cause data abnormality (data destruction, data corruption, etc.) during execution of control processing. In this case, data stored in EEPROM (electrically erasable programmable read-only memory) is read. The process of writing to the SRAM (refresh process) is executed. The EEPROM stores a lot of data used for various control processes and takes a long time to access the data, so that the data cannot be read quickly. Therefore, in the engine ECU, the control process is executed using the initial value data stored in the CPU until the refresh process is completed after the data abnormality occurs.

  However, unlike the data stored in the EEPROM, the initial value data is limited to the minimum number of data due to storage capacity restrictions. Accordingly, in order to quickly satisfy the control request in various control processes when an SRAM data abnormality occurs, it is necessary to shorten the control time with the initial value data as much as possible. That is, it is necessary to shorten the data refresh time.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a control device capable of shortening a data refresh time.

In order to achieve the above object, the control device according to claim 1 performs various control processes using data stored in the internal memory of the microcomputer, and data abnormality occurs in the data stored in the internal memory. A control device that executes a refresh process of reading data from an external memory that stores the same data as the data and writing the read data to the internal memory,
Priority setting that divides the data stored in the external memory into blocks for each control process, and sets the priority for executing the refresh process for each control state of the control target for each divided data group Means,
And a refresh processing unit for executing a refresh process in preference to a data group having a higher priority set by the priority order setting unit when a data abnormality occurs.

  As described above, when data abnormality occurs in the data stored in the internal memory such as SRAM, it is necessary to shorten the control time with the initial value data in order to quickly satisfy the control request in each control process. There is. For this purpose, the refresh process needs to be completed quickly, but it is not necessary to complete the refresh process for all data. In other words, at least if the refresh process is completed from the data necessary to satisfy the control request in the current control state of the control target, the control process for satisfying the control request is promptly executed using the data. Is possible.

  The present invention pays attention to this point. For each data group divided into block units for each control process, the priority order for executing the refresh process for each control state to be controlled is given priority. Set. When data abnormality occurs in the data stored in the internal memory, the refresh process is executed with priority from the data group having a higher priority set for the current control state.

  As a result, the refresh process is executed in preference to the data necessary to satisfy the control request in the current control state of the control target, so that the control request can be satisfied by using the data that has completed the refresh process. Processing can be executed promptly. As a result, it is possible to shorten the control time for the initial value data that is performed after the data abnormality occurs until the refresh process is completed.

  According to the control device of the second aspect, the priority order setting means sets the priority order for each data group based on the importance of each data group according to the control state of the control target. Features.

  Thereby, for example, the priority order can be set for each data group so that the refresh process is performed preferentially from the data group having high importance in the current control state of the control target.

  The control device according to claim 3 includes a data check cycle setting means for setting a check cycle for executing a data check for each control state of the control target for each data group stored in the external memory, and a current control target Data check processing means for performing data check of each data group for each check cycle for the control state. Thereby, the data check of each data group stored in the external memory can be executed at every check cycle set for the current control state.

  According to a fourth aspect of the present invention, there is provided a control device comprising a control processing means for executing a control process, wherein the control processing means is a microcomputer between the occurrence of a data abnormality in the data stored in the internal memory and the completion of the refresh process. Control processing is executed using initial value data stored in the CPU. Thereby, even during the refresh process, various control processes can be executed using the initial value data.

  According to the control device of the fifth aspect, when the data check cycle setting means sets the check cycle for each data group, the data check cycle setting means sets at least one of the allowable execution time of the control process using the initial value data and the importance. It sets based on.

  In this way, by setting the check cycle for executing the data check based on the importance of each data group according to the control state of the controlled object, for example, the data cycle with higher importance can be set to a shorter check cycle. Or, a check group can be set longer for a data group with lower importance.

  In addition, by setting a check cycle for executing a data check based on the allowable execution time, for example, a data group used for control processing with a short allowable execution time can be set to a shorter check cycle.

According to the control device of the sixth aspect, the data stored in the external memory is set with read time priority data indicating the priority of the read time for each data or each data group,
The refresh processing means changes the number of data when reading each data group based on at least one of the priority indicated by the read time priority data and the data check execution result by the data check processing means when executing the refresh processing. It is characterized by doing.

  As a result, the number of data to be read can be changed based on the priority indicated by the read time priority data and the execution result of the data check. Note that the priority of the read time may be set so that the read time is not prioritized by setting the priority low, for example, when ensuring data reliability.

  According to the control device of claim 7, the external memory stores a plurality of the same data for one data, and the refresh processing means has a high priority indicated by the read time priority data, When the execution result of the data check is normal, one normal data is read out from a plurality of the same data.

  For example, when three identical data are stored for one data, all three data are normally read, but the priority indicated by the read time priority data is high, and the data check execution result is normal. If so, one normal data is read out. Thereby, the time for reading data from the external memory can be shortened.

  Hereinafter, an embodiment of a control device of the present invention will be described with reference to the drawings. In the present embodiment, the case where the control device of the present invention is applied to an engine ECU that executes various control processes related to an engine that drives a vehicle such as an automobile will be described. However, the present invention is not limited to this. Absent.

  FIG. 1 is a diagram showing a main configuration of an engine ECU 1 that executes various control processes related to the engine 2. As shown in the figure, the engine ECU 1 operates by receiving power from a battery (+ B) (not shown), and mainly includes a microcomputer 11 and an EEPROM (electrically erasable programmable read-only memory) 14 as an external memory. Consists of. Further, the engine ECU 1 inputs an ignition switch (IG-SW) signal of the vehicle, a starter signal from a starter (not shown) that starts the engine 2, and a vehicle speed signal.

  The microcomputer 11 includes a static random access memory (SRAM) 12 and a CPU 13 as internal memories, and executes various control processes related to the engine 2 using data stored in the SRAM 12. The EEPROM 14 stores the same data as the data stored in the SRAM 12, and read time priority data indicating the priority of the read time is set for each data or each data group described later. For example, when the reliability of data is ensured, the priority of the reading time is set low so that the reading time is not prioritized.

  The engine ECU 1 executes a process (refresh process) of reading data from the EEPROM 14 and writing it to the SRAM 12 when data abnormality (data destruction, data corruption, etc.) of the SRAM 12 occurs during execution of various control processes related to the engine 2. The EEPROM 14 stores a large amount of data used for various control processes related to the engine 2 and takes a long time to access the data, so that the data cannot be read quickly.

  Therefore, the engine ECU 1 executes various control processes by using the initial value data stored in the CPU 13 until the refresh process is completed after the data abnormality of the SRAM 12 occurs. Thereby, even during the refresh process, various control processes can be executed using the initial value data.

  Next, the characteristic part of engine ECU1 of this embodiment is demonstrated. As described above, when a data abnormality occurs in the data in the SRAM 12, it is necessary to shorten the execution time of the control using the initial value data in order to quickly satisfy the control request in each control process. For this purpose, the refresh process needs to be completed quickly, but it is not necessary to complete the refresh process for all data. That is, at least if the refresh process is completed from data necessary to satisfy the control request in the current control state of the engine 2 that is the control target, the control process for satisfying the control request is quickly performed using the data. Can be executed.

  Therefore, first, the engine ECU 1 of the present embodiment manages the data used for each control process stored in the SRAM 12 and the EEPROM 14 in units of blocks for each control process, as shown in FIG. For example, when there are six types of control processes a to f, a data group of the control process a (data a1 to aN), a data group of the control process b (data b1 to bN),. As a data group (data f1 to fN), it is divided and managed in block units for each control process. As shown in the figure, the EEPROM 14 stores three identical data (in three locations) for one data as a countermeasure against data destruction.

  The engine ECU 1 sets priorities for executing the refresh process for each control state of the engine 2 for each data group divided into block units, and this setting is performed when a data abnormality occurs in the SRAM 12. The refresh process is executed with priority from the data group having the higher priority.

  FIG. 3 shows the control state of the engine 2. As shown in the figure, in the present embodiment, the power supply is kept in the control state of the engine 2 when power is turned on, before the engine is started, during the engine start, during idling, during traveling. The engine ECU 1 determines the control state of the engine 2 from the IG-SW signal, the starter signal, the vehicle speed signal, the power supply state to the engine ECU 1, and the like as shown in FIG.

  FIG. 4 shows a matrix used when calculating (setting) the priority of refresh processing. The priorities shown in the figure are set based on the importance of the data group used for each control process (b to f) in each control state (B to F). Accordingly, it is possible to set the priority order for each data group so that the refresh process is performed with priority from the data group having high importance in the current control state. In the control state at the time of power-on A, the priority of the data group used for the control processing (a to f) is the same, so the priority order is not shown in FIG.

  For example, when the control process necessary for starting the engine 2 in the control state C during engine start is the control process b, the data group used for the control process b is refreshed while the control state is B before the engine start. I want to complete the process. Therefore, in the control state before engine start B, the priority order of the data group used for the control process b is set to the highest (first). Further, in the control state during traveling E, the priority of the data group used for the important control process e during traveling is set to the highest.

  In the engine ECU 1, when a data abnormality occurs in the SRAM 12, the refresh process is executed with priority from the data group having a high priority in the current control state shown in FIG. 4. As a result, it is possible to shorten the control time using the initial value data that is performed after the data abnormality occurs until the refresh process is completed.

  FIG. 5 shows a timing chart in the case where the refresh process is executed based on the priority order of the control state B before starting the engine. As shown in the figure, when a data abnormality occurs in the data in the SRAM 12 at time T, the refresh process is started from the data group (block b data) used for the control process b having the highest priority of the refresh process B before engine start. Executed. In the time period from time T to time Tb, control processing based on the initial value data is executed. As shown in the figure, the higher the priority of the refresh process, the shorter the execution time of the control process using the initial value data.

  Further, in the engine ECU 1 of the present embodiment, a check cycle for executing a data check process is set for each control state (B to F) for each data group stored in the EEPROM 14 to check the current control state. Data check of each data group is executed at a cycle. Thereby, the data check of each data group stored in the EEPROM 14 can be executed at the check cycle set for the current control state.

  FIG. 7 shows a check cycle matrix for executing the data check processing. As shown in the figure, the check cycle includes the permissible execution time of each control process (b to f) using the initial value data in each control state (B to F) and each control in each control state (B to F). It is set based on the importance of the data group used for processing (b to f).

  In this way, by setting the check cycle based on the importance of each data group according to each control state, for example, a data group with higher importance can be set shorter or a data group with lower importance The check cycle can be set longer.

  In addition, by setting the check cycle based on (permitted) execution time, for example, a data group used for control processing with a shorter execution time can be set shorter.

  Next, data check processing of data stored in the EEPROM 14 will be described with reference to the flowchart shown in FIG. This data check process is executed at regular time intervals. First, in step (hereinafter referred to as S) 200, a current control state of the engine 2 is calculated from an IG-SW signal, a starter signal, a vehicle speed signal, a power supply state to the engine ECU 1, and the like.

  In S201, it is determined whether or not the current control state has changed from the previously calculated control state. If the determination is affirmative, the process proceeds to S202. If the determination is negative, the process proceeds to S203. In S202, a check cycle for each data group corresponding to the current control state is calculated with reference to the matrix shown in FIG.

  In S203, it is determined whether or not there is a data group that has reached the data check timing. If the determination is affirmative, the process proceeds to S204. If the determination is negative, the process ends. In S204, a check timing data group is read. As described above, the EEPROM 14 stores three identical data (in three locations) for one data as a countermeasure against data destruction. Therefore, when reading one piece of data, the same data is read at three locations. For example, when data a1 is read, data a1 (1) to data a1 (3) are read.

  In S205, data is checked by majority vote check. That is, if there is at least one set of matching data among the three read data, it is determined to be normal, and if there is no matching data (when all three data are different), it is determined to be abnormal. . In S206, it is determined whether or not the check result in S205 is normal. If the determination is affirmative, the process proceeds to S207. If the determination is negative, the process proceeds to S208.

  In S207, for the data checked in S205, the address for reading in the refresh process is updated (set), and the address is stored in the EEPROM. For example, if data a1 (1) and data a1 (2), or data a1 (1) and data a1 (3) match, the address of data a1 (1) is set, and data a1 (2) and If the data a1 (3) matches, the address of the data a1 (2) is set. If the data a1 (1) to data a1 (3) all match, the address of any of the data a1 (1) to data a1 (3) may be set. On the other hand, in S208, the data a1 (1) to data a1 (3) do not all match, and in this case, the fact that a data abnormality has occurred is stored in the EEPROM 14.

  Next, a refresh process executed when data abnormality occurs in the data in the SRAM 12 will be described with reference to the flowchart shown in FIG. First, in S100, the current control state of the engine 2 is calculated from the IG-SW signal, the starter signal, the vehicle speed signal, the power supply state to the engine ECU 1, and the like.

  In S101, it is determined whether or not the current control state has changed from the previously calculated control state. If the determination is affirmative, the process proceeds to S102. If the determination is negative, the process proceeds to S103. In S102, the priority for each data group corresponding to the current control state is calculated with reference to the matrix shown in FIG.

  In S103, in accordance with the priority order calculated in S102, the data group in the EEPROM 14 is read from the data group having a high priority order in the current control state and written in the SRAM 12. Here, processing when data is read from the EEPROM 14 will be described with reference to a flowchart shown in FIG.

  In S301, it is determined whether or not the priority of the read time is high with reference to the read time priority data set in the data to be read. If the determination is affirmative, the process proceeds to S302, and if the determination is negative, the process proceeds to S304. In S302, the read address set in S207 of FIG. 8 is acquired, and the data of the address is read in S303. That is, data to be read is read from one place. On the other hand, in S304, data to be read is read from three locations.

  As described above, when data is read from the EEPROM 14 in the refresh process, the number of data to be read from each data group is changed based on the priority indicated by the read time priority data and the execution result of the data check process. For example, as in the present embodiment, when three identical data are stored in the EEPROM 14 for one data, when the priority of the read time is low, three pieces of data are read and the read time priority data indicates When the priority is high and the execution result of the data check is normal (when the read address is set), one normal data out of the three data is read out. Thereby, since the number of data to be read from the EEPROM 14 is reduced, the time for reading data from the EEPROM 14 can be shortened.

  As described above, the engine ECU 1 according to the present embodiment manages the data used for each control process stored in the SRAM 12 and the EEPROM 14 by dividing the data into blocks for each control process, and for each data group divided into the blocks. A priority order for executing the refresh process is set for each control state of the engine 2, and when a data abnormality occurs in the SRAM 12, the refresh process is executed with priority from the set data group having a higher priority order. .

  As a result, the refresh process is executed in preference to the data necessary to satisfy the control request in the current control state of the engine 2, and therefore the control process that satisfies the control request is quickly performed using the data that has been subjected to the refresh process. Can be executed. As a result, it is possible to shorten the control time for the initial value data that is performed after the occurrence of the data abnormality until the refresh process is completed, and the data refresh time can be shortened.

2 is a diagram illustrating a main configuration of an engine ECU 1 that executes various control processes related to an engine 2; FIG. It is the figure which showed the example which divides | segments and manages the data used for each control process which SRAM12 and EEPROM14 memorize | store in the block unit for every control process. FIG. 3 is a diagram showing a control state of the engine 2. It is the figure which showed the matrix used when setting the priority of a refresh process. It is a timing chart at the time of performing a refresh process based on the priority of the control state before engine start. It is a flowchart which shows the flow of a refresh process. The matrix of the period which performs a data check process is shown. 4 is a flowchart showing a flow of data check processing for data stored in an EEPROM 14; 3 is a flowchart showing a flow of data read processing of data stored in an EEPROM 14; It is the figure which showed the main structures of engine ECU which performs engine control regarding the subject which invention intends to solve.

Explanation of symbols

1 Engine ECU
2 Engine 11 Microcomputer 12 SRAM
13 CPU
14 EEPROM

Claims (7)

Various control processes are executed using the data stored in the internal memory of the microcomputer, and when data abnormality occurs in the data stored in the internal memory, the data is read from the external memory storing the same data as the data A control device for executing a refresh process for writing the read data to the internal memory,
The data stored in the external memory is divided into blocks for each control process, and priorities for executing the refresh process are set for each divided control group for each control state to be controlled. Priority setting means;
And a refresh processing unit configured to execute the refresh processing in preference to a data group having a higher priority set by the priority order setting unit when the data abnormality occurs.   2. The priority order setting means, when setting the priority order for each data group, sets based on the importance of each data group according to the control state of the control target. Control device. Data check cycle setting means for setting a check cycle for executing a data check for each control state of the control target for each data group stored in the external memory;
The control apparatus according to claim 1, further comprising: a data check processing unit that performs a data check of each data group for each check cycle with respect to a current control state of the control target. Comprising control processing means for executing the control processing;
The control processing means performs the control processing using initial value data stored in the CPU of the microcomputer from when a data abnormality occurs in the data stored in the internal memory until the refresh processing is completed. The control device according to claim 1, wherein the control device is executed.   The data check cycle setting means sets the check cycle for each data group based on at least one of an allowable execution time of control processing using the initial value data and the importance. The control device according to claim 4. The data stored in the external memory is set with read time priority data indicating the priority of the read time for each data or each data group,
When the refresh processing unit executes the refresh processing, the refresh processing unit reads the data groups based on at least one of the priority indicated by the read time priority data and the data check execution result by the data check processing unit. The control apparatus according to claim 3, wherein the number of data is changed. The external memory stores a plurality of the same data for one data,
The refresh processing means reads the normal one of the plurality of the same data when the priority indicated by the read time priority data is high and the execution result of the data check is normal. The control device according to claim 6.

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