JP2015005716A - Multilayer printed circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a method of forming a capacitor layer by effectively utilizing a power source wiring layer and a ground wiring layer is extremely effective for noise suppression but unavailable if the power source wiring layer and the ground wiring layer are not adjacent, and it is difficult to provide in a versatile manner a method of forming the capacitor layer by adding the ground wiring layer and the power source wiring layer since cost may be increased by increasing the number of layers.SOLUTION: A capacitor layer is formed while effectively utilizing a free space of signal wiring layers within a multilayer printed circuit board without increasing the number of layers, a power source pattern is disposed in a signal wiring layer neighboring to a ground wiring layer, and a ground pattern is disposed in a signal wiring layer neighboring to a power source wiring layer, thereby suppressing radiation noise.

Description

  The present invention relates to a multilayer printed board including a capacitor and a design method thereof.

  In recent years, with the increase in speed and functionality of electronic devices, printed circuit boards are subject to many noise factors, such as power supply voltage fluctuations associated with semiconductor integrated circuit (LSI) operations, signal transmission speeds, and signal rise and fall. Therefore, it is important to take measures against radiation noise.

  Generally, a bypass capacitor is mounted near the power supply pin of an LSI as a countermeasure against power supply noise generated by LSI operation. However, by reducing the size and pitch of parts, and further reducing the size and density of the board. In some cases, a sufficient bypass capacitor cannot be arranged near the power supply pin. Even if the capacitor is arranged, since it is connected to the via via the wiring, the inductance component increases, and the series resonance frequency from the noise source or the power supply terminal is shifted to a low frequency. Therefore, there is a problem that the noise suppression effect is reduced.

  In order to solve these problems, efforts are being made to form capacitors in printed circuit boards.

  Patent Document 1 proposes a multilayer structure in which a capacitor multilayer body including two sheets made of a conductive material and an intermediate sheet made of a dielectric material is included in a printed wiring board to reduce power supply noise due to LSI operation. ing. Further, in Patent Document 2, a chip capacitor is built in an insulating layer between built-in capacitors formed by disposing a power wiring layer and a ground wiring layer in an insulating substrate formed by laminating a plurality of insulating layers. A multilayer wiring board in which the terminal electrodes are directly connected to the power wiring layer and the ground wiring layer, and the end of the power wiring layer is located inside the end of the ground wiring layer is proposed. Therefore, the concentration of the high-frequency current generated by the electromagnetic coupling at these ends is reduced, and the radiation noise generated from these ends is greatly reduced.

  Thus, effective reduction of radiation noise is expected by connecting the power supply pin of the LSI to the capacitor in the shortest time.

Japanese translation of PCT publication No. 5-500136 JP 2003-204163 A

  The method of forming the capacitor layer using the power wiring layer and the ground wiring layer as described above is very effective, but cannot be used unless the power wiring layer and the ground wiring layer are adjacent to each other. In the layer configuration of the multilayer printed board, considering the transmission characteristics of the signal wiring, depending on the number of layers, it may be difficult to dispose the power wiring layer and the ground wiring layer facing each other. In that case, it is necessary to add a ground wiring layer and a power supply wiring layer so as to face the power supply wiring layer and the ground wiring layer that are originally arranged, thereby forming a capacitor layer. This adds a power supply wiring layer and a ground wiring layer to the original layer structure, and increases the cost due to an increase in the number of layers, so that it is difficult to provide for general use.

  In the present invention, the capacitor layer is formed by utilizing the empty space of the signal wiring layer without increasing the number of layers, and a power supply pattern is disposed in the signal wiring layer adjacent to the ground wiring layer. A multilayer printed circuit board capable of suppressing radiation noise by arranging a ground pattern on an adjacent signal wiring layer and a design method thereof are provided.

  In order to solve the above-mentioned problems, a multilayer printed board according to the present invention is a multilayer structure in which a capacitor layer is formed, and uses a free space in a signal wiring layer inside the board to make use of a power pattern and a ground pattern. Form a built-in capacitor. That is, a power pattern is arranged in an empty space in the inner signal wiring layer with the ground layer as a reference, and a ground pattern is arranged in an empty space in the inner signal wiring layer with the power wiring layer as a reference. A capacitor is provided.

  In the multilayer printed circuit board of the present invention, since the capacitor layer is formed by utilizing the empty space of the signal wiring layer, there is no increase in cost due to the increase in the number of layers for making the power wiring layer and the ground wiring layer face each other, and radiation noise is reduced. It becomes possible to do.

It is sectional drawing which shows the multilayer printed circuit board of this invention. The radiation noise measurement result by the difference in the distance between insulating layers is shown. The relationship between the power supply pattern width arrange | positioned around a board | substrate by far-field analysis and radiation noise is shown. FIG. 5 is a pattern diagram for far field analysis of the relationship between the power supply pattern width arranged around the substrate and radiation noise. It is a solid pattern figure arrange | positioned at the signal wiring layer in embodiment (board | substrate a) of this invention. It is a solid pattern figure arrange | positioned at the signal wiring layer in other embodiment (board | substrate b) of this invention. The radiation noise measurement result of the board | substrate a is shown. The radiation noise measurement result of the board | substrate b is shown. FIG. 10 is a pattern diagram for far field analysis of the relationship between the distance between patterns arranged in the vicinity of an LSI and radiation noise. The relationship between the pattern distance from the LSI at a specific frequency and the radiation noise intensity is shown. It is a solid pattern figure arrange | positioned at the signal wiring layer in other embodiment (board | substrate d) of this invention. The radiation noise measurement result of the board | substrate d is shown. It is a solid pattern figure arrange | positioned at the signal wiring layer in other embodiment (board | substrate e) of this invention. The radiation noise measurement result of the board | substrate e is shown.

  Hereinafter, the multilayer printed board of the present invention will be described with reference to the drawings.

  In FIG. 1, a ground wiring layer 3 is formed in the second layer from the top, and a power wiring layer 4 is formed in the fifth layer. A first signal wiring layer 5 having the ground wiring layer 3 as a reference plane is formed in the third layer; A fourth signal wiring layer 6 having the power wiring layer 4 as a reference plane is arranged as a fourth layer by using a general multilayer printed circuit board manufacturing method. Here, FIG. 1 shows a six-layer substrate, but the number of layers is arbitrary as long as the substrate has a power wiring layer, a ground wiring layer, and an inner signal wiring layer.

  A power pattern 40 facing the ground wiring layer 3 is disposed in the empty space of the first signal wiring layer 5, and a ground pattern 30 facing the power wiring layer is disposed in the empty space of the second signal wiring layer 6. As a result, the capacitor layer 8 is formed.

  By taking the form as described above, the capacitor layer 8 is replaced with the ground wiring layer 3, the first signal wiring layer 5, the power supply wiring layer 4, and the second signal wiring layer 6 without the power wiring layer and the ground wiring layer being opposed to each other. Can be formed between.

In general, the distance between the opposing power supply pattern and ground pattern layers affects the capacitance formed in the substrate. FIG. 1 shows an insulating interlayer distance 10 between the ground wiring layer 3 and the first signal wiring layer 5 and between the power supply wiring layer 4 and the second signal wiring layer 6. The capacitance of the capacitor layer 8 is defined by the formula (1). When the area is the same, the smaller the insulating interlayer distance 10, the larger the capacitance, and the greater the radiation noise suppression effect. FIG. 2 shows the result of verifying the radiation noise suppression effect when the insulating interlayer distance 10 is 0.06 mm to 1.2 mm. When the insulating interlayer distance 10 is 0.1 mm and 0.06 mm, radiation noise can be greatly suppressed.

  Next, power supply and ground pattern arrangement in the empty space of the signal layer will be described.

  FIG. 3 shows the result of far-field analysis of the relationship between the width of the pattern arranged around the substrate and the radiation noise using a 2.5-dimensional electromagnetic field simulator Ansys SI wave (manufactured by Ansys Japan Co., Ltd.). Here, the noise source is arranged in the center of the substrate, and the first signal wiring layer of the third layer has a power supply pattern as shown in FIG. The power supply pattern conditions were five types: no power supply pattern, surrounding power supply pattern widths of 2 mm, 5 mm, 10 mm, and a solid surface. As the power supply pattern width increases, radiation noise tends to decrease. By providing a pattern with a width of 5 mm or more on the outer periphery of the substrate, the radiation noise is reduced by 70% compared to the case without a power supply pattern. A sufficient radiation noise reduction effect can be expected.

  FIG. 5 shows a pattern diagram of the power supply pattern, the ground pattern, the power supply wiring layer, and the ground wiring layer arranged in the signal wiring layer of the substrate a of the present embodiment. Here, the power supply pattern and the ground pattern are arranged so as to surround the periphery of the substrate from the result of the simulation. The width (301, 40A, 40B, 40C) of the power supply pattern and the ground pattern surrounding the periphery of the substrate is about 10 mm. The power supply patterns 40A, 40B, and 40C indicate different power supplies.

  FIG. 6 shows a pattern diagram of the power supply pattern, the ground pattern, the power supply wiring layer, and the ground wiring layer arranged in the signal wiring layer of the substrate b according to another embodiment of the present invention. Unlike the substrate a, the power supply pattern and the ground pattern are partially arranged so as not to fill the entire empty space or the periphery of the substrate. The power supply patterns 40A, 40B, and 40C indicate different power supplies.

  The noise measurement results of these substrates a and b and the substrate c in which the power supply pattern and the ground pattern are not arranged on the signal wiring layer are shown in FIGS.

  In both cases, compared to the substrate c, the radiation noise intensity is reduced, and a capacitor layer is formed by arranging a pattern having an attribute different from the signal wiring reference in the empty space of the signal wiring layer. This is a substrate with effective countermeasures against radiation noise.

  Next, in the pattern diagram of the ground wiring layer shown in FIG. 9, a far field analysis is performed on the relationship between the distance of the power supply pattern arranged near the LSI and the radiation noise, and at a specific frequency (frequency band in which the radiation noise is reduced by the pattern size). The relationship between the distance of the power supply pattern from the LSI and the radiation noise intensity is shown in FIG. A noise source is arranged in the center of the substrate, and a power supply pattern is created in the first signal wiring layer of the third layer. The power supply pattern conditions were six types in which a power supply pattern having a size of 15 mm × 12 mm was arranged at a distance of 2 mm, 15 mm, 30 mm, 45 mm, 60 mm, and 70 mm from the LSI. As the power supply pattern is moved away from the LSI, the radiation noise reduction effect tends to be weakened. Arranging the power supply pattern within 15 mm from the LSI shows a radiation noise reduction effect of 50% or more as compared with the case without the power supply pattern, and therefore a sufficient radiation noise reduction effect can be expected even in an actual machine.

  FIG. 11 is a pattern diagram of a power supply pattern and a ground pattern, a power supply wiring layer, and a ground wiring layer arranged on the signal wiring of the substrate d according to another embodiment of the present invention. A power supply pattern 40A is added to the signal wiring layer in the vicinity of the semiconductor that becomes a noise source based on the substrate a. Here, a pattern of 15 mm × 12 mm is arranged at a position 2 mm away from the LSI edge. The power supply patterns 40A, 40B, and 40C indicate different power supplies.

  As shown in FIG. 12, the radiation noise in the high frequency region is improved as compared with the substrate a. By providing the power supply pattern and the ground pattern around the substrate where the signal density of the signal wiring layer is reduced and in the vicinity of the semiconductor as a noise source, the radiation noise of the entire region up to 1000 MHz can be more effectively reduced.

  FIG. 13 shows a pattern diagram of the power supply pattern and the ground pattern, the power supply wiring layer, and the ground wiring layer arranged on the signal wiring of the substrate e according to another embodiment of the present invention. This is a pattern in which the power supply pattern is pulled out along the signal wiring and component shape instead of arranging the pattern so that the center of the solid is rectangular, and the power supply pattern and ground pattern are more similar to the actual machine Is arranged. The power supply patterns 40A, 40B, and 40C indicate different power supplies.

  As shown in FIG. 14, compared with the substrate c, the radiation noise intensity is remarkably reduced, and even if the shape is complicated, a power supply pattern having an attribute different from the reference of the signal wiring is arranged in the empty space of the signal wiring. Thus, by forming the capacitor layer 8, a substrate with effective radiation noise countermeasures is obtained. In addition, each layer and pattern is formed by a conventional method, and another capacitor is not disposed, so that the cost is not increased.

1: Multilayer printed circuit board 2: LSI
3: Ground wiring layer,
30, 31, 301: Ground pattern 4: Power supply wiring layer,
40, 4A, 4B, 4C, 40A, 40B, 40C: power supply pattern 5: first signal wiring layer 6: second signal wiring layer 7: signal wiring 8: capacitor layer 9: insulating layer 10: insulating interlayer distance

Claims (2)

  A multilayer printed board having a capacitor layer formed therein, wherein a built-in capacitor is formed by a power supply pattern and a ground pattern by utilizing an empty space of a signal wiring layer inside the board.   The power supply pattern is arranged in an empty space in an inner signal wiring layer with a ground layer as a reference, and the ground pattern is arranged in an empty space in an inner signal wiring layer with a power supply wiring layer as a reference. Item 8. A multilayer printed circuit board according to item 1.