JP2014241181A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of executing reading of data by a current sense amplifier with high accuracy.SOLUTION: A semiconductor device comprises: first and second reference current generation unit generating reference currents; a current-mirror circuit generating a memory cell current; a switching circuit connecting the current-mirror circuit to the second reference current generation unit or connecting the current-mirror circuit to memory cells; and an amplifier unit having a first input terminal to which a potential at a first connection node between the current-mirror circuit and the first reference current generation unit is input, and having a second input terminal to which a potential at a second connection node between the current-mirror circuit and the switching circuit is input. The amplifier unit retains an offset voltage generated between the first and second connection nodes if the second reference current generation unit is connected to the current-mirror circuit, and differentially amplifies a potential difference between the first and second connection nodes while reflecting the offset voltage if the current-mirror circuit is connected to the memory cells.

Description

  The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device including a memory element.

  In a semiconductor memory such as a DRAM (Dynamic Random Access Memory), a sense amplifier is provided for amplifying a minute signal read from a memory cell. In a resistance change type memory such as ReRAM (Resistance Random Access Memory) or STTRAM (Spin Transfer Torque RAM), a so-called current sense amplifier as disclosed in Patent Document 1 is used.

  The current sense amplifier realizes reading of data held in the memory cell by comparing a current flowing in the memory cell to be accessed with a reference current that is a reference for data determination. More specifically, the current sense amplifier uses a current mirror circuit to replicate the reference current flowing on the reference side to the memory cell side to be accessed, and determines the magnitude of the reference current and the memory cell current flowing through the memory cell. Thus, data reading is realized.

JP 2003-297090 A

  The disclosure of the above prior art document is incorporated herein by reference. The following analysis was made by the present inventors.

  As described above, the current sense amplifier is used when reading data from the memory cell. Usually, there are variations in the characteristics of the transistors constituting the current mirror circuit included in the current sense amplifier. Due to the variation in the characteristics of the transistors, the magnitude of the memory cell current may be erroneously determined.

  According to a first aspect of the present invention, a first and second reference current generation unit that generates a reference current, a current mirror circuit that is connected to the first reference current generation unit and generates a memory cell current, Connecting the current mirror circuit and the second reference current generator, or a switching circuit connecting the current mirror circuit and the memory cell, and the current mirror circuit and the first reference at a first input terminal. An amplifier unit to which a potential at a first connection node of a current generation unit is input, and a potential at a second connection node of the current mirror circuit and the switching circuit is input to a second input terminal; The amplifier unit holds an offset voltage generated between the first and second connection nodes when the second reference current generation unit and the current mirror circuit are connected to each other. If the Tomira circuit and the memory cells are connected, while reflecting the offset voltage to the differential amplifying a potential difference between the first and second connecting node, the semiconductor device is provided.

  According to one aspect of the present invention, there is provided a semiconductor device that contributes to performing data reading by a current sense amplifier with high accuracy.

3 is a diagram illustrating an example of an internal configuration of a current sense amplifier unit 36 included in the semiconductor device 10 according to the first embodiment. FIG. 1 is a diagram illustrating an example of a configuration of a semiconductor device 10 according to a first embodiment. 2 is a diagram illustrating an example of an internal configuration of a memory cell array 11. FIG. FIG. 8 is a layout diagram in which the memory cells 32-1 to 32-8 shown in FIG. 3 and their peripheral circuit configurations are formed of so-called planar type transistors. FIG. 8 is a structural diagram in which the memory cells 32-1 to 32-8 and the peripheral circuit configuration shown in FIG. 3 are formed by so-called vertical transistors, and a cross section in the word line WL direction of the memory cells 32-1 to 32-8 is shown. FIG. 2 is a diagram illustrating an example of a circuit configuration of a first reference current generation unit 201. FIG. 3 is a diagram illustrating an example of a circuit configuration of an amplifier unit 203 included in the semiconductor device 10. FIG. 3 is a diagram illustrating an example of a partial circuit configuration of a read / write amplifier 19. FIG. It is a figure which shows an example of the one part circuit structure of the read / write amplifier 19 contained in the semiconductor device 10a which concerns on 2nd Embodiment. It is a figure which shows an example of the circuit structure of the amplifier part 203a contained in the semiconductor device 10b which concerns on 3rd Embodiment.

  An outline of one embodiment will be described. As shown in FIG. 1, the semiconductor device includes first and second reference current generators that generate a reference current (for example, the first reference current generator 201 and the second reference current generator 202 in FIG. 1). A current mirror circuit (for example, P-channel MOS transistors P01 and P02 in FIG. 1) that is connected to the first reference current generator and generates a memory cell current, and the current mirror circuit and the second reference current generator. Or a switching circuit (for example, the transfer gate 37, the Y switch circuit 30, and the switch 204 in FIG. 1) for connecting the current mirror circuit and the memory cell, and the current mirror circuit and the first circuit at the first input terminal. The potential at the first connection node of the reference current generator is input, and the potential at the second connection node of the current mirror circuit and the switching circuit is input to the second input terminal. That includes amplifier unit (for example, amplifier 203 of FIG. 1), the. Further, the amplifier unit holds an offset voltage generated between the first and second connection nodes when the second reference current generation unit and the current mirror circuit are connected, and the current mirror circuit and the memory cell are connected. In this case, the potential difference between the first and second connection nodes is differentially amplified while reflecting the offset voltage.

  The semiconductor device includes two reference current generators that generate reference currents having substantially the same current value, and causes the two reference currents to flow through the current mirror circuit, thereby causing a characteristic difference between transistors constituting the current mirror circuit. The offset voltage resulting from the manifestation of is input to the amplifier unit. The amplifier unit holds an offset voltage inside before reading data from the memory cell. The current mirror circuit and the memory cell are connected in a state where the offset voltage is held, and a potential resulting from the memory cell current and the reference current is input to the amplifier unit. The amplifier unit compares and amplifies the input potential difference while reflecting the held offset voltage. In other words, the offset voltage is information including the characteristic difference of the transistors constituting the current mirror circuit. Therefore, by comparing the potential difference taking the offset voltage into account, the influence of the transistor characteristic difference is excluded, and the read data is excluded. Can be determined. As a result, it is possible to prevent erroneous determination of data due to a difference in characteristics of transistors constituting the current mirror circuit.

  Hereinafter, specific embodiments will be described in more detail with reference to the drawings.

[First Embodiment]
The first embodiment will be described in more detail with reference to the drawings.

  FIG. 2 is a diagram illustrating an example of the configuration of the semiconductor device 10 according to the first embodiment. A memory cell array 11 shown in FIG. 2 includes a plurality of resistance change memory cells arranged two-dimensionally. Each memory cell includes a resistance change element (reference numeral 34-1 and the like shown in FIG. 3) and a memory cell transistor (reference numeral 35-1 and the like shown in FIG. 3). Each resistance change element stores either a high resistance state “0” or a low resistance state “1”, and functions as a nonvolatile memory element.

  The semiconductor device 10 selects a memory cell and performs three operations: SET writing for changing the high resistance state to the low resistance state, RESET writing for changing the low resistance state to the high resistance state, and reading of the resistance state. In FIG. 2, blocks other than the memory cell array 11 control the above three operations for the memory cell array 11.

  The address input circuit 12 inputs an address ADD of a memory cell to be accessed. The address latch circuit 13 latches the input address ADD and separates it into a row address ADD_ROW and a column address ADD_COLUMN.

  The address latch circuit 13 outputs the row address ADD_ROW to the row control circuit 14 and the column address ADD_COLUMN to the column control circuit 15. The address latch circuit 13 may receive the row address ADD_ROW and the column address ADD_COLUMN in a time division manner.

  The row control circuit 14 includes a row decoder (not shown) and decodes a row selection signal from the row address ADD_ROW. Of the plurality of word lines WL, the word line WL selected by the row selection signal is activated.

  The column control circuit 15 includes a column decoder (not shown), and decodes the column selection signal YJ from the column address ADD_COLUMN. The column control circuit 15 outputs a column selection signal YJ to the memory cell array 11. The bit line BL selected by the column selection signal YJ is activated.

  The clock input circuit 16 receives complementary external clock signals CK and / CK supplied to the semiconductor device 10 from the outside, and generates an internal clock ICLK. The clock input circuit 16 supplies the generated internal clock ICLK to the timing generator 17.

  The timing generator 17 generates various timing signals necessary for the operation of the semiconductor device 10 based on the internal clock ICLK, and supplies the various timing signals to each unit (not shown). In this specification, the signal name “/” indicates that the signal is active at a low level.

  The data input / output terminal DQ is connected to the input / output circuit 18, and the write data is taken into the input / output circuit 18 in response to the write data being input to the data input / output terminal DQ. The input / output circuit 18 is connected to a read / write amplifier (RWAMP) 19. The read / write amplifier 19 outputs write data to the global bit line GBL that extends the memory cell array 11. The read / write amplifier 19 inputs data read from the memory cell via the global bit line GBL, amplifies the data, and outputs the amplified data to the input / output circuit 18. The input / output circuit 18 outputs the data amplified by the read / write amplifier 19 from the data input / output terminal DQ.

  The command input circuit 20 inputs a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, and the like as control signals.

  The command decode circuit 21 decodes these control signals and outputs control signals necessary for executing the decoded command to each unit in the semiconductor device 10. The command decode circuit 21 supplies a program (write) command signal PROG or a read command signal READ to the row control circuit 14 and the column control circuit 15 based on the decoding result of the control signal. Further, the command decode circuit 21 supplies various control signals of DETECT, CONT, and OFFCHK to the read / write amplifier 19. Details of these control signals will be described later.

  The row control circuit 14 and the column control circuit 15 select a memory cell to be accessed by an address signal (row address ADD_ROW, column address ADD_COLUMN) supplied together with the program command signal PROG or the read command signal READ. At the time of data programming, data amplified by the read / write amplifier 19 is written into the selected memory cell via the global bit line GBL and the local bit line LBL. On the other hand, when reading data, data read from the memory cell is read after being amplified by the read / write amplifier 19 via the local bit line LBL and the global bit line GBL.

  The internal power supply generation circuit 22 inputs power supply VDD and VSS supplied from the outside, generates voltages VPP, VREAD, VSET, VRESET, VCLMP, VSL, VPERI and the like necessary for each part in the semiconductor device 10 and supplies them to each part. Supply.

  The voltage VREAD is used when the sense amplifier included in the read / write amplifier 19 applies a predetermined voltage to the selected bit line BL and reads the resistance change of the variable resistance element. The voltage VSET is supplied to the read / write amplifier 19 and used during SET writing. The voltage VRESET is supplied to the read / write amplifier 19 and used at the time of RESET writing. The voltage VCLMP is supplied to a clamp circuit included in the read / write amplifier 19. The voltage VSL is used when precharging the global bit line GBL and the local bit line LBL via the common source line SL. The voltage VPERI is used as a power source for peripheral circuits of the memory cell array 11.

  Next, the internal configuration of the memory cell array 11 will be described.

  FIG. 3 is a diagram illustrating an example of the internal configuration of the memory cell array 11. Referring to FIG. 3, the memory cell array 11 includes a plurality of Y switch circuits 30-1 to 30-8, a plurality of precharge circuits 31-1 to 31-8, and a plurality of memory cells 32-1 to 32-8. And a plurality of coupled transistors 33-1 to 33-7. In the following description, when there is no particular reason for distinguishing the Y switch circuit, it is expressed as “Y switch circuit 30”. The same notation is applied to the precharge circuit, the memory cell, the connection transistor, the resistance change element, and the memory cell transistor.

  Each memory cell 32 included in the memory cell array 11 is selected by a word line WL and a bit line BL. The bit line BL used for selecting the memory cell 32 is hierarchized into a global bit line GBL and a local bit line LBL. For example, in FIG. 3, one of the local bit lines LBL0 to LBL7 is selected and connected to the global bit line GBL0.

  As described above, in the memory cell array 11, a plurality of global bit lines GBL are wired, and any one of the plurality of local bit lines LBL is selectively connected to each global bit line GBL.

  The Y switch circuit 30 is a switch circuit provided between the global bit line GBL and the plurality of local bit lines LBL. The Y switch circuit 30 functions as a switch that switches connection between the global bit line GBL and the plurality of local bit lines LBL. The Y switch circuit 30 is composed of, for example, an N-channel MOS transistor or the like, and receives a column selection signal YJ at its gate terminal (control electrode). For example, in FIG. 3, if the column selection signal YJ0 is in the active state and the column selection signals YJ1 to YJ7 are in the inactive state, the Y switch circuit 30-1 is turned on and the global bit line GBL0 and the local bit line LBL0 are connected. The In this way, each Y switch circuit 30 is turned on in response to the column selection signal YJ that switches connection of the plurality of local bit lines LBL to the global bit line GBL. The column selection signals YJ corresponding to the respective Y switch circuits 30 are independent selection signals.

  The precharge circuit 31 is a circuit connected to each of the plurality of local bit lines LBL. The precharge circuit 31 is a circuit that precharges the potential of the global bit line GBL and the local bit line LBL to the voltage VSL. The precharge circuit 31 is configured by, for example, an N-channel MOS transistor and receives a precharge signal YB at its gate terminal. Each precharge circuit 31 connects the global bit line GBL and the local bit line LBL by connecting the local bit line LBL and the common source line SL that supplies the voltage VSL in response to the activation of the precharge signal YB. Precharge to voltage VSL. The precharge signal YB is a signal that is activated when the column selection signal YJ is inactive (when the Y switch circuit 30 is not selected). That is, the precharge circuit 31 becomes conductive when any of the Y switch circuits 30 is not selected.

  In FIG. 3, the word line WL and the local bit line LBL are selected by various control signals generated by the row control circuit 14 and the column control circuit 15. Memory cells 32 are respectively provided between the word line WL and the plurality of local bit lines LBL. After the word line WL and the local bit line LBL are selected, the memory cell 32 located at the intersection is accessed. It becomes.

  The memory cell 32 includes a resistance change element 34 and a memory cell transistor 35. The first main electrode (one of the source terminal and the drain terminal) of the memory cell transistor 35 is connected to the resistance change element 34, the second main electrode (the other one of the source terminal and the drain terminal) is connected to the common source line SL, and the control electrode ( Gate terminals) are respectively connected to the word lines WL. As described above, the memory cells 32 are provided between the common source line SL and the plurality of local bit lines LBL, respectively, and are connected in series between the common source line SL and the plurality of local bit lines LBL. A resistance change element 34 and a memory cell transistor 35 are provided.

  When writing data in each memory cell 32, the word line WL corresponding to the memory cell 32 to which data is to be written is selected, so that the memory cell transistor 35 is turned on. Further, a write operation is performed by applying a write voltage between the common source line SL and the local bit line LBL and causing a current to flow through the resistance change element 34.

  More specifically, when data “0” is written in the memory cell 32, a low-potential voltage VRESET is applied to the global bit line GBL. On the other hand, when writing data “1” in the memory cell, a high-potential voltage VSET is applied to the global bit line GBL. Note that when data is written to the memory cell, the voltage applied to the global bit line GBL is switched by controlling the read / write amplifier 19. The read / write amplifier 19 receives the voltages VRESET and VSET, and changes the voltage supplied to the global bit line GBL corresponding to the data to be written.

  Further, the voltage VREAD is applied to the resistance change element 34, and the resistance state (low resistance state or high resistance state) of the resistance change element 34 is determined by the current flowing at that time, thereby reading data from the memory cell 32.

  The connecting transistor 33 is a transistor for mutually connecting channel portions formed in the body portion of the memory cell transistor 35 included in the adjacent memory cell 32. For example, the connection transistor 33-1 connects the channel portion in the body portion of the memory cell transistor 35-1 and the channel portion in the body portion of the memory cell transistor 35-2. As described above, the connection transistor 33 functions as a connection portion that connects channel portions formed in the body portion of the memory cell transistor 35 included in the adjacent memory cell 32.

  The range of the memory cells 32 to which the coupling transistor 33 is connected is limited to a plurality of memory cells 32 that can be selected by a specific global bit line GBL and a specific word line WL. In other words, among the plurality of memory cells 32, channel portions in the body portion of the memory cell transistor 35 included in the memory cell 32 sharing the global bit line GBL and the word line WL are connected to each other. For example, the memory cells 32-1 to 32-8 are connected to each other by the connecting transistors 33-1 to 33-7, but are not connected to other memory cells (for example, the memory cell 32-9). That is, among the plurality of memory cells 32, the channel portions in the body portion of the memory cell transistor included in the memory cell 32 that does not share the global bit line GBL and the word line WL are not connected to each other.

  The gate terminal of each connection transistor 33 is connected to the corresponding word line WL. Therefore, when the corresponding word line WL is activated, the connection transistor 33 becomes conductive. That is, when the corresponding word line WL is activated, a channel is formed in the body portion of the connection transistor 33. Further, when the word line WL is activated, a channel is also formed in the body portion of the memory cell transistor 35. Further, as will be described later, the body portion (silicon pillar) of the memory cell transistor 35 included in the plurality of memory cells 32 sharing the global bit line GBL and the word line WL is formed as one pillar. Therefore, the channel portions in the body portion of each memory cell transistor 35 connect memory cell transistors 35 adjacent to each other so that the channel portions are connected when the word line WL is in an active state. In FIG. 3, when the word line WL0 is activated, the connecting transistors 33-1 to 33-7 are turned on to connect the channel portions in the body portion of each memory cell transistor 35.

  In this way, each of the connection transistors 33 has a common word line WL connected to each gate, and a channel between one of the sources and drains of the two adjacent memory cell transistors 35 corresponding thereto. Configured to form. Therefore, one of the source and the drain in the two memory cell transistors 35 adjacent to each other is electrically connected to each other via the channel of the connection transistor 33 when the word line WL is in an active state, and the word line WL is in an inactive state. At this time, the connection transistor 33 becomes electrically independent depending on the fact that the channel is not formed. If the corresponding word line WL is in an inactive state, the connecting transistor 33 is not turned on, and the channel portion in the body portion of each memory cell transistor 35 in the memory cell 32 is not connected to each other. .

  Note that not only the bit lines BL but also the word lines WL may be hierarchized. In that case, the word line WL is hierarchized into a main word line and a sub word line, and the memory cell 32 is selected using a main word driver (not shown) or a sub word driver (not shown).

  FIG. 4 is a layout diagram in which the memory cells 32-1 to 32-8 shown in FIG. 3 and their peripheral circuit configurations are formed of so-called planar type transistors. In this configuration, the source, channel, and drain of each transistor are arranged so as not to overlap in a plane. In this way, the memory cell 32 can be configured using a planar type transistor.

  On the other hand, FIG. 5 is a structural diagram in which the above circuit configuration is formed by so-called vertical transistors, and is a diagram showing a cross section in the word line WL direction in the memory cells 32-1 to 32-8 shown in FIG. In this configuration, the source, channel (and body), and drain of each memory cell transistor 35 overlap in a plane and are arranged in a direction perpendicular to the semiconductor substrate. Further, the connection transistor 33 is formed so as to form a channel between one of the source and drain of two memory cell transistors 35 adjacent to each other, that is, like a planar type transistor. 4 and 5, the circuit symbols of the transistors are illustrated for easy understanding.

  Referring to FIG. 4, the N-type diffusion layer 102 forming the memory cell transistor 35 is electrically connected to one end of the variable resistance element 34 through the first contact 103. Furthermore, the other end of the resistance change element 34 is electrically connected to the local bit line LBL. The N-type diffusion layer 101 forming the memory cell transistor 35 is electrically connected to the common source line SL via the second contact 104. Further, the gate terminal of the memory cell transistor 35 is electrically connected to the corresponding word line WL. Note that a channel is formed in a region sandwiched between the N-type diffusion layers 101 and 102. Further, a connection transistor 33 is formed between nodes on the local bit line LBL side adjacent to each other of each memory cell transistor 35. Thus, the transistors in FIG. 4 are arranged in a plane.

  Referring to FIG. 5, each memory cell transistor is formed in a direction perpendicular to the semiconductor substrate, and a channel in the body portion of the memory cell transistor 35 is formed by a connecting transistor 33 formed between the N-type diffusion layers 102 as a part thereof. The parts are formed so as to be electrically connected to each other. That is, the N-type diffusion layer 101 is stacked on the substrate 105, and the silicon pillar 106 is formed as one pillar common to each memory cell transistor 35. A plurality of N-type diffusion layers 102 are formed on the silicon pillar 106 so as to correspond to the plurality of resistance change elements 34, respectively, and the silicon pillar 106 is formed so that the upper surface of the body portion is substantially flat. . As a result, the body portion is shared via the connection transistor 33 between the plurality of memory cell transistors 35 sharing the global bit line GBL and the word line WL. Further, gate electrodes (not shown) are arranged on both sides of the silicon pillar 106 with a predetermined interval (via a gate oxide film), and are electrically connected to the corresponding word line WL0. Although the formation difficulty in the process is high, the size of the semiconductor device can be reduced by forming in this way.

  Note that the channel portions in the body portion of the memory cell transistor 35 are connected to only the memory cell transistor 35 sharing the global bit line GBL and the word line WL, and one of the global bit line GBL and the word line WL is connected. The memory cell transistors 35 that do not share are not connected to each other. In other words, one of the source and drain of the memory cell transistors 35 arranged adjacent to each other (for example, the memory cell transistor 35 connected to the word line WL0) and another memory cell transistor 35 having a different word line WL connected thereto. One of the source and the drain of the memory cell transistor 35 (for example, the memory cell transistor 35 connected to a word line WL other than the word line WL0) is electrically independent regardless of which word line WL is activated.

  Next, a current sense amplifier included in the read / write amplifier 19 will be described.

  FIG. 1 is a diagram illustrating an example of an internal configuration of the current sense amplifier unit 36 included in the read / write amplifier 19. Referring to FIG. 1, the current sense amplifier 36 includes P-channel MOS transistors P01 and P02, a first reference current generator 201, a second reference current generator 202, an amplifier 203, and a switch 204. And comprising.

  The current sense amplifier unit 36 is connected to the global bit line GBL and the local bit line LBL via the transfer gate 37. Further, in the amplifier unit 203, the current sense amplifier unit 36 compares and amplifies the reference-side potential and the memory cell 32-side potential, and outputs them as read data to the read / write bus RWBS.

  The current sense amplifier unit 36 receives the control signal DETECT. The control signal DETECT is a control signal for switching connection between the switch 204 and a plurality of switches (switches SW1 to SW7 in FIG. 7) included in the amplifier unit 203.

  The source terminals of the P-channel MOS transistors P01 and P02 are connected to a power supply line that supplies the voltage VREAD, and the gate terminals of the P-channel MOS transistors P01 and P02 are connected in common. The drain terminal of the P-channel MOS transistor P02 is connected to the first reference current generator 201. The drain terminal of the P-channel MOS transistor P01 is connected to the second reference current generator 202 via the switch 204 or to the memory cell 32 via the transfer gate 37 and the Y switch circuit 30. The gate terminals of P-channel MOS transistors P01 and P02 are connected in common and connected to the drain terminal of P-channel MOS transistor P02. A current mirror circuit is formed by the P-channel MOS transistors P01 and P02, and a memory cell current is supplied from the P-channel MOS transistor P01 to the memory cell 32.

  The transfer gate 37, the Y switch circuit 30, and the switch 204 are circuits that switch between connecting the current mirror circuit and the second reference current generation unit 202, or connecting the current mirror circuit and the memory cell 32. Function.

  In the following description, a connection node between the P-channel MOS transistor P01 and the switch 204 is a node A1, and a connection node between the P-channel MOS transistor P02 and the first reference current generator 201 is a node A2. In addition, the potential at each node is described using the name of the node. For example, the potential of the node A1 is expressed as VA1. Further, the potential at the input end of the amplifier unit 203 on the memory cell 32 side (input end connected to the node A1) is Vsout, and the reference side input end of the amplifier unit 203 (input end connected to the node A2). ) Is expressed as Vref. Furthermore, during a detection operation (DETECT operation) described later, the potential at the input end on the memory cell 32 side of the amplifier unit 203 is Vsout (d), the potential at the input end on the reference side of the amplifier unit 203 is Vref (d), Respectively. Furthermore, the potential at the input end on the memory cell 32 side of the amplifier unit 203 in the sense operation to be described later is expressed as Vsout (s), and the potential at the input end on the reference side of the amplifier unit 203 is expressed as Vref (s). .

  The first reference current generator 201 and the second reference current generator 202 are configured to generate a reference current Iref having substantially the same current value. FIG. 6 is a diagram illustrating an example of a circuit configuration of the first reference current generator 201. The first reference current generator 201 includes an amplifier 301, a resistor 302, and N-channel MOS transistors N01 and N02. Note that the circuit configuration of the second reference current generation unit 202 does not differ from the circuit configuration of the first reference current generation unit 201, and thus description thereof is omitted.

  The first reference current generator 201 generates the reference current Iref in response to the activation of the control signal CONT. The amplifier 301 receives the clamp voltage VCLMP and the potential VA3 at the node A3 (a connection node between the N-channel MOS transistor N01 and the resistor 302), and makes the potential VA3 substantially the same as the potential of the clamp voltage VCLMP. That is, the amplifier 301 and the N-channel MOS transistor N01 form a clamp circuit, and this clamp circuit is a circuit that holds the potential VA3 of the node A3, which is a connection node between the resistor 302 and the clamp circuit, at a predetermined potential. .

  N-channel MOS transistor N02 receives control signal CONT at its gate terminal, and generates reference current Iref in response to activation of control signal CONT (transition to H level). More specifically, the reference current Iref having a current value obtained by dividing the potential VA3 at the node A3 by the resistance value of the resistor 302 is generated.

  Since the configurations of the first reference current generation unit 201 and the second reference current generation unit 202 are the same, the current of the reference current Iref generated by each reference current generation unit is supplied by supplying the same clamp voltage VCLMP to each. The values substantially match. Referring to FIG. 1, when the switch 204 is conductive and the transfer gate 37 is non-conductive, the reference current Iref generated by each reference current generator has the same current value, so that the thresholds of the P-channel MOS transistors P01 and P02 are the same. If the characteristics such as voltage are the same, the potential Vsout and the potential Vref are equal.

  However, if there is a characteristic difference between the P-channel MOS transistors P01 and P02, a potential difference (offset voltage) is generated between the potential Vsout and the potential Vref. More specifically, when the threshold voltage of the P-channel MOS transistor P01 is higher than the threshold voltage of the P-channel MOS transistor P02, the potential Vsaout is lower than the potential Vref (the potential Vref is used as a reference). As a negative offset voltage). On the other hand, when the threshold voltage of the P-channel MOS transistor P01 is lower than the threshold voltage of the P-channel MOS transistor P02, the potential Vsout becomes higher than the potential Vref (a positive offset with respect to the potential Vref). Voltage is generated).

  Next, the amplifier unit 203 will be described.

  In the amplifier unit 203, the potential Vref at the node A2 (connection node between the current mirror circuit and the first reference current generation unit 201) is input to the first input terminal, and the node A1 (current mirror) is input to the second input terminal. This is an amplifier circuit to which a potential Vsaout at a circuit and a connection node such as the switch 204 is input (see FIG. 1).

  FIG. 7 is a diagram illustrating an example of a circuit configuration of the amplifier unit 203. Referring to FIG. 7, the amplifier unit 203 includes capacitors C1 and C2, switches SW1 to SW7, P-channel MOS transistors P03 and P04, N-channel MOS transistors N03 to N05, a latch circuit 401, and switch switching. Circuit 402.

  One end of the capacitor C1 is connected to the above-mentioned first input terminal, and the other end is connected to the gate terminal (control terminal) of the N-channel MOS transistor N04. Similarly, one end of the capacitor C2 is connected to the above-mentioned second input end, and the other end is connected to the gate terminal of the N-channel MOS transistor N05. The P-channel MOS transistors P03 and P04 have gate terminals connected in common, and supply current to the N-channel MOS transistors N04 and N05, respectively.

  The switch SW1 is connected between one end of the capacitor C1 and the drain terminal (main terminal) of the N-channel MOS transistor N04. Similarly, the switch SW2 is connected between one end of the capacitor C2 and the drain terminal of the N-channel MOS transistor N05. The switch SW3 is connected between the drain terminals of the P-channel MOS transistors P03 and P04. The switch SW4 is connected between the N channel type MOS transistor N04 and the P channel type MOS transistor P03. Similarly, the switch SW5 is connected between the N-channel MOS transistor N05 and the P-channel MOS transistor P04. The switch SW 6 is connected between the power supply line that supplies the power supply VDD to the latch circuit 401 and the latch circuit 401. The switch SW7 is connected between the power supply line that grounds the latch circuit 401 and the latch circuit 401.

  The latch circuit 401 includes flip-flop connected P-channel MOS transistors P05 and P06, and N-channel MOS transistors N06 and N07. The latch circuit includes an inversion local amplifier line LAN including a connection node between the N-channel MOS transistor N04 and the P-channel MOS transistor P03, and a non-connection including a connection node between the N-channel MOS transistor N05 and the P-channel MOS transistor P04. It is connected between the inverted local amplifier line LAP. When the latch circuit 401 is activated, the potential difference between the non-inverting local amplifier line LAP and the inverting local amplifier line LAN is latched.

  The switch switching circuit 402 is means for switching between conduction and non-conduction of the switches SW1 to SW7 in accordance with the active state of the control signal DETECT. Specific control of the switches SW1 to SW7 by the switch switching circuit 402 will be described later. In FIG. 7, the switch switching circuit 402 and the connection lines of the switches SW1 to SW7 are not shown.

  Referring to FIG. 7, when the control signal OFFCHK is set to H level, the P-channel MOS transistors P03 and P04 and the N-channel MOS transistor N03 are turned on, and the amplifier unit 203 is activated. The control signal OFFCHKB is a signal obtained by inverting the control signal OFFCHK by an inverter circuit (not shown).

  The amplifier unit 203 receives the control signal DETECT. When the control signal DETECT is activated, the amplifier unit 203 detects a characteristic difference between the P-channel MOS transistors P01 and P02 and performs an operation of holding the characteristic difference inside.

  On the other hand, when the control signal DETECT is inactive, the amplifier unit 203 compares and amplifies the potential difference between the non-inverted local amplifier line LAP and the inverted local amplifier line LAN, and outputs the comparison result to the read / write bus RWBS. Perform the action.

  Next, the operation of the amplifier unit 203 will be described.

  First, the operation (DETECT operation) of the amplifier unit 203 when the control signal DETECT is in the active state will be described.

  When the control signal DETECT is activated, the switch switching circuit 402 turns on the switches SW1 to SW5 and turns off the switches SW6 and SW7. When the switches SW6 and SW7 are turned off, power is not supplied to the latch circuit 401, and the latch circuit 401 is inactivated. When the control signal DETECT transitions to the active state, the switches SW1 to SW5 are turned on, so that the connection node A4 between the capacitor C1 and the N-channel MOS transistor N04, and the connection node A5 between the capacitor C2 and the N-channel MOS transistor N05 Both are charged. Subsequently, the switch switching circuit 402 makes the switches SW4 and SW5 non-conductive, so that the N-channel MOS transistors N04 and N05 are in a so-called diode connection, and are stepped down to a potential depending on the threshold voltage Vt. Subsequently, the switch switching circuit 402 turns off the switches SW1 and SW2 and turns on the switches SW4 and SW5. As a result, the connection nodes A4 and A5 of the N-channel MOS transistors N04 and N05 hold the potential depending on the threshold voltage Vt of the N-channel MOS transistors N04 and N05 (N-channel MOS transistors N04 and N05). The offset amount of the threshold voltage is retained).

  On the other hand, if there is a characteristic difference between the P-channel MOS transistors P01 and P02 shown in FIG. 1, the offset voltage is generated as described above. At that time, together with the held potentials of the nodes A4 and A5, the offset voltage between the potential Vsout (d) and the potential Vref (d) is retained as the difference between the retained charges of the capacitors C1 and C2. More specifically, the potential difference between the electrodes in the capacitor C1 is Vsaout (d) −VA4. Further, the potential difference between the electrodes in the capacitor C2 is Vref (d) −VA5. In the following description, the potential difference between the electrodes in the capacitor C1 is expressed as VC1 (VC1 = Vsaout (d) −VA4), and the potential difference between the electrodes in the capacitor C2 is expressed as VC2 (VC2 = Vref (d) −VA5). To do. By using the potential differences VC1 and VC2 as offset voltages, it is possible to perform a sensing operation in which the offsets of the N-channel transistors N04 and N05 are canceled and the offsets of the P-channel MOS transistors P01 and P02 are also canceled. .

  Next, an operation (sense operation) of the amplifier unit 203 when the control signal DETECT is in an inactive state will be described.

  When a significant potential difference occurs between the potential VA4 of the node A4 and the potential VA5 of the node A5, the amplifier unit 203 causes a difference in the current value of the current flowing through the N-channel MOS transistors N04 and N05. A potential difference is generated between the non-inverting local amplifier line LAP and the inverting local amplifier line LAN at the input end of the latch circuit. When the control signal DETECT is activated, the switch switching circuit 402 turns off the switches SW1 to SW5 and turns on the switches SW6 and SW7. When the switches SW6 and SW7 are turned on, power is supplied to the latch circuit 401, and the latch circuit 401 is activated. The activated latch circuit 401 amplifies / latches the potential difference at the input terminal between the non-inverted local amplifier line LAP and the inverted local amplifier line LAN, and outputs it to the read / write bus RWBS as read data.

  Further, if the control signal DETECT is in an inactive state, the switches SW1 and SW2 are non-conductive, so that there is no path through which charges held in the capacitors C1 and C2 flow out in the DETECT operation. Therefore, the offset held by the capacitors C1 and C2 is a potential difference between the potential of the non-inverted local amplifier line LAP determined according to the potential Vref (s) and the potential of the inverted local amplifier line LAN determined according to the potential Vsout (s). The voltage is reflected.

  Next, the operation of the semiconductor device 10 will be described. Here, an operation at the time of reading data will be described.

  Referring to FIG. 1, when reading data from the memory cell 32, the command decode circuit 21 activates the control signal DETECT. When the control signal DETECT is activated, a switching circuit including the transfer gate 37, the Y switch circuit 30, and the switch 204 connects the current mirror circuit and the second reference current generator 202. That is, when the control signal DETECT is activated, the switch 204 included in the current sense amplifier unit 36 becomes conductive. At this time, since the first reference current generator 201 and the second reference current generator 202 are configured to generate the reference current Iref having the same current value, the P-channel MOS transistors P01 and P02 If there is no characteristic difference between the potential Vref (d) and the potential Vsout (d), they match.

  However, since a characteristic difference usually exists between the P-channel MOS transistors P01 and P02, a potential difference (offset voltage) is generated between the potential Vref (d) and the potential Vsout (d). Become. Further, as described above, the amplifier unit 203 holds potentials depending on the threshold voltages Vt of the N-channel MOS transistors N04 and N05 at the connection nodes A4 and A5, respectively (VA4 and VA5). The offset of both paths is canceled by the potential difference Vsaout (d) −VA4 held in the capacitor C1 and the potential difference Vref (d) −VA5 held in the capacitor C2.

  Next, the command decode circuit 21 deactivates the control signal DETECT after a predetermined time has elapsed since the activation of the control signal DETECT. At that time, the column control circuit 15 conducts the transfer gate 37 and the Y switch circuit 30 corresponding to the memory cell 32 to be accessed. When the control signal DETECT is deactivated, the switch 204 becomes non-conductive. Further, since the transfer gate 37 and the Y switch circuit 30 are turned on, the memory cell 32 to be accessed via the local bit line LBL and the global bit line GBL has a current including a P-channel MOS transistor P01. Connected to mirror circuit. That is, the switching circuit including the transfer gate 37, the Y switch circuit 30, and the switch 204 connects the current mirror circuit and the memory cell 32 in response to the deactivation of the control signal DETECT.

  By connecting the memory cell 32 to the current mirror circuit, a memory cell current flows through the resistance change element 34, and the potential Vsout (s) is changed according to the resistance state (high resistance state, low resistance state) of the resistance change element 34. Change. At this time, since the control signal DETECT is inactive, the amplifier unit 203 compares and amplifies the potential difference between the non-inverted local amplifier line LAP and the inverted local amplifier line LAN while taking the offset voltage into account.

  For example, consider a case where the P-channel MOS transistor P01 is inferior in current supply capability (threshold voltage is higher) than the P-channel MOS transistor P02. In this case, if the offset voltage is not taken into account, there is a possibility that the potential change element 34 is determined to be in the low resistance state because the potential Vsout (s) is lowered even though the resistance change element 34 is in the high resistance state. is there. That is, erroneous determination of data read from the memory cell 32 may occur.

  When the current supply capability of the P-channel MOS transistor P01 is low, a negative offset voltage (reference to the potential Vref) is generated between the potential Vsaout and the potential Vref. This negative offset voltage is held as the difference between the charges held in the capacitors C1 and C2, and is reflected in the potential difference between the non-inverting local amplifier line LAP and the inverting local amplifier line LAN during the sensing operation. More specifically, since the offset voltage is a negative value, the amplifier unit 203 operates to raise the potential Vsout (s). Alternatively, the amplifier unit 203 reduces the potential Vref (s) when determining the potential Vsout (s), and determines the resistance state of the resistance change element 34 of the memory cell 32. As a result, the potential Vsout (s) that should decrease due to the current supply capability of the P-channel MOS transistor P01 being inferior to the current supply capability of the P-channel MOS transistor P02 is increased, or Vref (s) is lowered, and the resistance change element 34 is correctly determined to be in the high resistance state. Thus, the current sense amplifier unit 36 holds the offset voltage in the capacitors C1 and C2, and compensates for the low current supply capability of the P-channel MOS transistor P01 by taking the offset voltage into account during the sensing operation. Yes.

  When the current supply capability of the P-channel MOS transistor P01 is higher than that of the P-channel MOS transistor P02, a positive offset voltage is generated between the potential Vsaout and the potential Vref. In this case, since the offset voltage is a positive value, the amplifier unit 203 operates to lower the potential Vsout (s). Alternatively, the potential Vref (s) when determining the potential Vsout (s) is raised, and the resistance state of the resistance change element 34 of the memory cell 32 is determined.

  As described above, the amplifier unit 203 holds the offset voltage between the potential Vsout and the potential Vref when the second reference current generation unit 202 and the current mirror circuit are connected (detect operation). In addition, when the current mirror circuit and the memory cell 32 are connected (during a sensing operation), the amplifier unit 203 differentially amplifies the potential difference between the potential Vsout and the potential Vref while reflecting the offset voltage.

  Here, the read / write amplifier 19 and its peripheral circuits shown in FIGS. 1 and 6 can be realized by the circuit configuration shown in FIG. In FIG. 8, the same components as those in FIGS. 1 and 6 are represented by the same reference numerals, and the description thereof is omitted. Referring to FIG. 8, the switch 204 can be taken into the second reference current generator 202a.

  As described above, the current sense amplifier unit 36 according to the first embodiment uses the offset voltage generated due to the characteristic difference between the P-channel MOS transistors P01 and P02 and between the N-channel MOS transistors N04 and N05. The DETECT operation is performed to hold the difference between the held charges of the capacitors C1 and C2. Thereafter, the current sense amplifier unit 36 compares and amplifies the potential difference between the non-inverted local amplifier line LAP and the inverted local amplifier line LAN while taking into account the offset voltage held in the capacitors C1 and C2 when performing data determination. To do. As a result, erroneous determination of data due to the characteristic difference between the P-channel MOS transistors P01 and P02 is prevented. That is, data reading by the current sense amplifier can be performed with high accuracy.

[Second Embodiment]
Next, a second embodiment will be described in detail with reference to the drawings.

  FIG. 9 is a diagram illustrating an example of a partial circuit configuration of the read / write amplifier 19 included in the semiconductor device 10a according to the second embodiment. 9, the same components as those in FIG. 8 are denoted by the same reference numerals, and the description thereof is omitted. Note that the semiconductor device 10 and the semiconductor device 10a are not different from each other in the overall configuration, the memory cell array, and the like, and thus description of the semiconductor device 10a corresponding to FIGS. 1 to 5 and FIG. 7 is omitted. The difference between the semiconductor device 10 and the semiconductor device 10a is that the internal configuration of each reference current generating unit is different and a regulator 403 is provided.

  The first reference current generator 211 included in the semiconductor device 10a divides the resistor 302 used for generating the reference current Iref into two resistors 302a and 302b. Note that the sum of the resistance value of the resistor 302 a and the resistance value of the resistor 302 b is equal to the resistance value of the resistor 302. That is, the resistor included in the first reference current generator 211 includes the resistor 302a and the resistor 302b. Therefore, the first reference current generator 211 can also generate the reference current Iref described in the first embodiment. A connection node between the resistors 302 a and 302 b is connected to the input terminal of the regulator 403. The regulator 403 inputs the potential of the connection node between the resistors 302 a and 302 b as the potential VCLPR, converts the potential into a potential VCLP, and supplies it to the second reference current generator 212. That is, the regulator 403 is means for generating the potential VCLP from the potential VCLPR.

  The resistance value of the resistor 302c included in the second reference current generator 212 is substantially the same as the resistance value of the resistor 302a. The potential at one end of the resistor 302c is maintained at the potential VCLP by the regulator 403. That is, the potential VCLP generated by the regulator 403 is supplied to one end of the resistor 302c. At that time, if the potential VCLPR and the potential VCLP are equal, the resistance value of the resistor 302c can be regarded as the resistance value of the resistor 302. That is, the second reference current generator 212 can also generate the reference current Iref described in the first embodiment. Furthermore, since the potential VCLP can be changed (adjusted) by the regulator 403, the apparent resistance value of the resistor 302c can be finely adjusted.

  As described above, in the semiconductor device 10a according to the second embodiment, the resistance value of the resistor 302c included in the first reference current generator 211 can be reduced by using the regulator 403. Therefore, even when the resistance value of the resistor 302 is large, the resistance value of the resistor 302c used for the first reference current generating unit 211 can be reduced, so that the mounting area of the first reference current generating unit 211 can be reduced. In addition, the semiconductor device 10a according to the second embodiment can read data with a current sense amplifier with high accuracy, like the semiconductor device 10 according to the first embodiment.

[Third Embodiment]
Next, a third embodiment will be described in detail with reference to the drawings.

  FIG. 10 is a diagram illustrating an example of a circuit configuration of the amplifier unit 203a included in the semiconductor device 10b according to the third embodiment. 10, the same components as those in FIG. 7 are denoted by the same reference numerals, and the description thereof is omitted. The semiconductor device 10 and the semiconductor device 10b are not different from each other in the overall configuration, the memory cell array, and the like, and thus description of the semiconductor device 10b corresponding to FIGS. 1 to 5 is omitted. The difference between the semiconductor device 10 and the semiconductor device 10b is that the amplifier unit 203a includes an N-channel MOS transistor N08, and the control regarding ON / OFF of the N-channel MOS transistors N03 and N08 is different.

  N-channel MOS transistor N08 is connected between N-channel MOS transistors N04 and N05 and a power supply line to which potential VCLMP2 is supplied. The potential VCLMP2 is higher than the potential VSS, and is generated by the internal power generation circuit 22. The gate terminal of the N-channel MOS transistor N03 receives the control signal OFFCHK1, and the gate terminal of the N-channel MOS transistor N08 receives the control signal OFFCHK2. The control signal OFFCHKB is generated using a negative OR circuit (not shown) or the like so that either the control signal OFFCHK1 or OFFCHK2 becomes L level when it is at H level.

  The command decode circuit 21 sets the control signal OFFCHK1 to the L level and the control signal OFFCHK2 to the H level during the period in which the control signal DETECT for reading data from the memory cell 32 is activated. Thereafter, the command decode circuit 21 sets the control signal OFFCHK1 to the H level and the control signal OFFCHK2 to the L level in synchronization with the deactivation of the control signal DETECT.

  Under such control by the command decode circuit 21, a characteristic difference between the transistors is detected, and during the DETEC operation in which the characteristic difference is held inside, the N-channel MOS transistor N08 is turned on, and the potential VA4 of the node A4 and The potential VA5 of the node A5 is pushed up by the potential VCLMP2. Thereafter, with the potentials VA4 and VA5 being pushed up, the potential difference between the non-inverted local amplifier line LAP and the inverted local amplifier line LAN described in the first embodiment is compared and amplified, and the comparison result is read / written. A sense operation for outputting to the bus RWBS is performed.

  By appropriately selecting the level of the potential VCLMP2, the potentials VA4 and VA5 can be set to the optimum operating point of the amplifier unit 203a during the sensing operation following the DETECT operation. Similarly to the semiconductor device 10 according to the first embodiment, the semiconductor device 10b according to the third embodiment can read data with a current sense amplifier with high accuracy.

  The disclosure of the cited patent document is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) within the scope of the claims of the present invention, Selection is possible. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea. In particular, with respect to the numerical ranges described in this document, any numerical value or small range included in the range should be construed as being specifically described even if there is no specific description.

10, 10a, 10b Semiconductor device 11 Memory cell array 12 Address input circuit 13 Address latch circuit 14 Row control circuit 15 Column control circuit 16 Clock input circuit 17 Timing generator 18 Input / output circuit 19 Read / write amplifier (RWAMP)
20 Command input circuit 21 Command decode circuit 22 Internal power supply generation circuit 30, 30-1 to 30-8 Y switch circuit 31, 31-1 to 31-8 Precharge circuit 32, 32-1 to 32-11 Memory cell 33, 33-1 to 33-8, connection transistor 34, 34-1 to 34-8, resistance change element 35, 35-1 to 35-8, memory cell transistor 36, current sense amplifier 37, transfer gate (TG)
101, 102 N-type diffusion layer 103 First contact 104 Second contact 105 Substrate 106 Silicon pillars 201, 211 First reference current generators 202, 202a, 212 Second reference current generators 203, 203a Amplifier 204, SW1 To SW7 switch 301 amplifier 302, 302a to 302c resistor 401 latch circuit 402 switch switching circuit 403 regulator C1, C2 capacitors P01 to P06 P-channel MOS transistors N01 to N08 N-channel MOS transistors

Claims (10)

First and second reference current generators for generating a reference current;
A current mirror circuit connected to the first reference current generator for generating a memory cell current;
A switching circuit for connecting the current mirror circuit and the second reference current generator, or for connecting the current mirror circuit and a memory cell;
A potential at the first connection node of the current mirror circuit and the first reference current generator is input to a first input terminal, and a second of the current mirror circuit and the switching circuit is input to a second input terminal. An amplifier unit to which the potential at the connection node of
With
The amplifier unit holds an offset voltage generated between the first and second connection nodes when the second reference current generation unit and the current mirror circuit are connected, and the current mirror circuit and the current mirror circuit A semiconductor device that differentially amplifies a potential difference between the first and second connection nodes while reflecting the offset voltage when a memory cell is connected.   The semiconductor device according to claim 1, wherein the amplifier section includes a first capacitor connected to the first input terminal, and a second capacitor connected to the second input terminal. The amplifier section is
A first transistor having a control terminal connected to the first capacitor;
A second transistor having a control terminal connected to the second capacitor;
A third transistor for supplying current to the first transistor;
A fourth transistor connected to a control terminal of the third transistor and supplying a current to the second transistor;
A first switch circuit connected between the first capacitor and a main terminal of the first transistor;
A second switch circuit connected between the second capacitor and a main terminal of the second transistor;
A third switch circuit connected between the main terminals of the third and fourth transistors;
A fourth switch circuit connected between the first transistor and the third transistor;
A fifth switch circuit connected between the second transistor and the fourth transistor;
A semiconductor device according to claim 2. The amplifier section is
A latch circuit connected between a connection node of the first transistor and the third transistor, and a connection node of the second transistor and the fourth transistor;
A sixth switch circuit connected between a power supply line for supplying power to the latch circuit and the latch circuit;
A seventh switch circuit connected between the power supply line for grounding the latch circuit and the latch circuit;
The semiconductor device according to claim 3, further comprising: A control circuit that activates a control signal when reading data from the memory cell, and deactivates the control signal after a predetermined period of time;
The switching circuit connects the current mirror circuit and the second reference current generator according to activation of the control signal, and connects the current mirror circuit and the memory according to deactivation of the control signal. Connect the cells,
The first to fifth switch circuits are turned on in response to the activation of the control signal, and then the third to fifth switch circuits are turned off, and then the fourth and fifth switch circuits are turned on. The semiconductor device of Claim 3 or 4 which conducts.   6. The semiconductor device according to claim 5, wherein the sixth and seventh switch circuits are turned off in response to the activation of the control signal, and are turned on in response to the deactivation of the control signal. The first and second reference current generators are
Resistance,
7. A clamp circuit that is connected to one end of the resistor and holds a potential of a node connected to the one end of the resistor at a predetermined potential. 8. Semiconductor device. The resistor included in the first reference current generating unit includes a first resistor and a second resistor,
The resistor included in the second reference current generation unit is a third resistor having the same resistance value as the first resistor,
The second resistor is generated at one end of the third resistor opposite to the side connected to the clamp circuit according to the first potential of the connection node between the first resistor and the second resistor. The semiconductor device according to claim 7, wherein a potential is supplied.   The semiconductor device according to claim 8, further comprising a regulator that generates the second potential from the first potential.   10. The semiconductor according to claim 3, further comprising a fifth transistor connected between the first and second transistors and a power supply line to which a higher potential than a ground potential is supplied. apparatus.

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