JP2014239209A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can achieve good yield.SOLUTION: A semiconductor device comprises: a pair of first magnetization fixed layers FF1 arranged apart from each other in a plane direction; a magnetization free layer FR1 which overlaps a part of each of the pair of first magnetization fixed layers FF1 in planar view and which is electrically connected with the pair of first magnetization fixed layers FF1; a non-magnetized layer TB1 arranged on the magnetization free layer FR1; and a second magnetization fixed layer RF1 arranged on the non-magnetized layer TB1. The magnetization free layer FR1, the non-magnetized layer TB1 and the second magnetization fixed layer RF1 have the same planar shape.

Description

  The present invention relates to a semiconductor device and is a technology applicable to a semiconductor device having a magnetic random access memory, for example.

  Magnetic random access memory (Magnetic Random Access Memory (MRAM)) is a high-speed and non-volatile memory, and is expected to contribute to lower power consumption of semiconductor devices. Examples of the technology related to the magnetic random access memory include those described in Patent Documents 1 and 2.

Patent Documents 1 and 2 describe magnetic random access memories that perform magnetization reversal using a current-induced domain wall motion phenomenon.
Among these, the technique described in Patent Document 1 includes a first magnetization fixed region and a second magnetization fixed region having magnetizations fixed in antiparallel directions, and a magnetization free region bonded thereto. The present invention relates to a magnetoresistive effect element including a first ferromagnetic layer. Specifically, for the first magnetization fixed region and the magnetization free region, one upper surface is formed at a position higher than the other upper surface, and one lower surface is formed at a position lower than the other lower surface. Yes.
In Patent Document 1, a magnetoresistive effect element includes a second ferromagnetic layer provided to face the first ferromagnetic layer, and a second ferromagnetic layer provided between the second ferromagnetic layer and the magnetization free region. 1 nonmagnetic layer.

JP 2009-252909 A International Publication No. 2009/001706 Pamphlet

Patent Document 1 describes a magnetoresistive effect element in which a second ferromagnetic layer and a nonmagnetic layer smaller than the magnetization free region are provided on the magnetization free region. However, in such a configuration, there is a concern that deposits generated from the magnetization free region adhere to the side walls of the nonmagnetic layer and remain when the second ferromagnetic layer and the nonmagnetic layer are processed into desired shapes. Is done. In this case, a short circuit may occur at the magnetic tunnel junction.
Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a magnetization free layer electrically connected to a pair of first magnetization fixed layers, and a nonmagnetic layer and a second magnetization fixed layer provided on the magnetization free layer are simultaneously desired to each other. Process into shape.

  According to the one embodiment, it is possible to provide a semiconductor device capable of realizing a good yield.

It is sectional drawing which shows the magnetoresistive memory based on 1st Embodiment. It is a top view which shows the magnetoresistive memory shown in FIG. It is sectional drawing which shows the semiconductor device which has a magnetoresistive memory shown in FIG. It is sectional drawing which shows the modification of the magnetoresistive memory which concerns on 1st Embodiment. It is a figure which shows the principle of operation of the magnetoresistive memory shown in FIG. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the magnetoresistive memory based on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows the magnetoresistive memory based on 3rd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. It is a figure which shows the magnetoresistive memory based on 4th Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 4th Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 4th Embodiment. It is a figure which shows the magnetoresistive memory based on 5th Embodiment. It is sectional drawing which shows the modification of the manufacturing process shown in FIG. It is sectional drawing which shows the magnetoresistive memory based on 6th Embodiment. It is a top view which shows the magnetoresistive memory shown in FIG. It is sectional drawing which shows the semiconductor device which has a magnetoresistive memory shown in FIG. FIG. 22 is a cross-sectional view showing a modification of the magnetoresistive memory shown in FIG. 21. It is a schematic diagram for demonstrating the graph shown to FIG. 26 and FIG. 26 is a graph showing the relationship between the length L of the magnetization fixed layer shown in FIG. 25 and the leakage magnetic field from the magnetization fixed layer at point A. FIG. It is a graph which shows the relationship between the distance d from the magnetization fixed layer shown in FIG. 25 to the point A, and the leakage magnetic field from the magnetization fixed layer in the point A. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 6th Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 6th Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 6th Embodiment. It is sectional drawing which shows the magnetoresistive memory based on 7th Embodiment. It is sectional drawing which shows the magnetoresistive memory based on 8th Embodiment. It is sectional drawing which shows the magnetoresistive memory based on 9th Embodiment. FIG. 34 is a cross-sectional view showing a modification of the magnetoresistive memory shown in FIG. 33. FIG. 22 is a cross-sectional view showing a modification of the magnetoresistive memory shown in FIG. 21.

  Hereinafter, embodiments will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a cross-sectional view showing the magnetoresistive memory MR1 according to the first embodiment. FIG. 2 is a plan view showing the magnetoresistive memory MR1 shown in FIG. FIG. 3 is a cross-sectional view showing a semiconductor device SD1 having the magnetoresistive memory MR1 shown in FIG. FIG. 4 is a cross-sectional view showing a modification of the magnetoresistive memory MR1 according to the first embodiment.

  The semiconductor device SD1 according to this embodiment includes a magnetoresistive memory MR1. The magnetoresistive memory MR1 includes a pair of first magnetization fixed layers FF1, a magnetization free layer FR1, a nonmagnetic layer TB1, and a second magnetization fixed layer RF1. The pair of first magnetization fixed layers FF1 are provided to be separated from each other in the planar direction. The magnetization free layer FR1 overlaps a part of each of the pair of first magnetization fixed layers FF1 in a plan view and is electrically connected to the pair of first magnetization fixed layers FF1. The nonmagnetic layer TB1 is provided on the magnetization free layer FR1. The second magnetization fixed layer RF1 is provided on the nonmagnetic layer TB1. Further, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 have the same planar shape. FIGS. 1 and 4 illustrate examples of the configuration of the magnetoresistive memory MR1 that constitutes the semiconductor device SD1.

  In the present embodiment, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 have the same planar shape. As a result, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 can be simultaneously processed into a desired shape. In this case, even if the deposit generated from the magnetic material layer to be the magnetization free layer FR1 adheres to the side wall of the nonmagnetic layer TB1, it can be removed together with the processing of the magnetization free layer FR1. For this reason, it can suppress that the deposit produced from the magnetic material layer used as the magnetization free layer FR1 remains on the side wall of the nonmagnetic layer TB1, and can suppress the occurrence of a short circuit in the magnetic tunnel junction TJ1. Thus, according to the present embodiment, it is possible to provide a semiconductor device capable of realizing a good yield.

  Hereinafter, the configuration of the semiconductor device SD1 and the method for manufacturing the semiconductor device SD1 according to the present embodiment will be described in detail.

First, the configuration of the semiconductor device SD1 according to this embodiment will be described.
The semiconductor device SD1 includes a magnetoresistive memory MR1 that is an MRAM (Magnetic Random Access Memory). For example, a plurality of magnetoresistive memories MR1 are provided in the semiconductor device SD1. FIG. 3 shows an example of a semiconductor device SD1 having a memory area having the magnetoresistive memory MR1 and a logic area different from the memory area.

A semiconductor device SD1 according to this embodiment includes, for example, a semiconductor substrate SB1 and a transistor TR1 provided on the semiconductor substrate SB1.
The semiconductor substrate SB1 is not particularly limited, but is, for example, a silicon substrate. On the semiconductor substrate SB1, for example, an element isolation film EI1 that electrically isolates the transistor TR1 from other elements is formed. On the semiconductor substrate SB1, an etching stopper film ES2 is formed so as to cover the transistor TR1, for example. The transistor TR1 includes, for example, a gate insulating film GI1 provided over the semiconductor substrate SB1, a gate electrode GE1 provided over the gate insulating film GI1, and a source / drain region DR1 formed across the gate electrode GE1. I have.

The semiconductor device SD1 includes, for example, a multilayer wiring layer provided on the semiconductor substrate SB1. The magnetoresistive memory MR1 is formed, for example, in a multilayer wiring layer. In this case, the magnetoresistive memory MR1 can be formed, for example, in an arbitrary wiring layer in the multilayer wiring layer.
In the example shown in FIG. 3, an interlayer insulating film II1 is provided on the semiconductor substrate SB1. In the interlayer insulating film II1, a contact plug CP1 connected to the source / drain region DR1 is embedded. On the interlayer insulating film II1, the interlayer insulating film II2 in which the wiring IC1 is embedded, the interlayer insulating film II3 in which the wiring IC2 is embedded, the interlayer insulating film II4 in which the wiring IC3 is embedded, and the interlayer insulating film in which the wiring IC4 is embedded An interlayer insulating film II6 in which II5 and wiring IC5 are embedded is formed in this order. Each wiring layer is constituted by each interlayer insulating film and wiring embedded therein. A plurality of wiring layers may be further formed on the interlayer insulating film II6.

  The magnetoresistive memory MR1 includes a pair of first magnetization fixed layers FF1, a magnetization free layer FR1 electrically connected thereto, a nonmagnetic layer TB1 provided on the magnetization free layer FR1, and a nonmagnetic layer TB1. And a second magnetization fixed layer RF1. In this case, the magnetoresistive memory MR1 has a magnetic tunnel junction TJ1 constituted by the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 that are stacked on each other.

The pair of first magnetization fixed layers FF1 includes a first magnetization fixed layer FF11 and a first magnetization fixed layer FF12. The first magnetization fixed layer FF11 and the first magnetization fixed layer FF12 are provided apart from each other in the plane direction parallel to the plane of the semiconductor substrate SB1.
Further, the pair of first magnetization fixed layers FF1 have magnetizations fixed in antiparallel directions. In the present embodiment, the first magnetization fixed layer FF11 has a magnetization fixed in a first direction perpendicular to the plane of the semiconductor substrate SB1, for example. The first magnetization fixed layer FF12 has a magnetization fixed in a second direction opposite to the first direction, for example. Here, the first direction refers to either the upward direction or the downward direction as viewed from the magnetoresistive memory MR1.

The first magnetization fixed layer FF1 is made of a ferromagnetic material exhibiting perpendicular magnetic anisotropy. The ferromagnetic material constituting the first magnetization fixed layer FF1 includes, for example, one or both of Fe and Co, and can be composed of an alloy with Pt or Pd or a laminated film with Pt or Pd.
The shape of the first magnetization fixed layer FF1 is not particularly limited. For example, the first magnetization fixed layer FF1 may have a columnar shape or a tapered shape having the same top and bottom areas.

In the present embodiment, the first magnetization fixed layer FF1 is formed, for example, in the insulating film IF1. The insulating film IF1 is made of, for example, SiO ₂ or SiN. In the example shown in FIG. 3, the insulating film IF1 constitutes at least a part of the interlayer insulating film II5, for example.
FIG. 3 illustrates a case where the pair of first magnetization fixed layers FF1 are provided so as to be electrically connected to different wiring IC3 via contact vias CV1 embedded in the insulating film IF3. Yes. At this time, the pair of first magnetization fixed layers FF1 are electrically connected to the source / drain regions DR1 of the different transistors TR1 through, for example, the wiring IC3. As another example, the magnetoresistive memory MR1 may be formed so that the first magnetization fixed layer FF1 and the etching stopper film ES1 are connected to the wiring IC5 in place of the wiring IC4 in the logic region.

The magnetization free layer FR1 is electrically connected to the first magnetization fixed layer FF11 and the first magnetization fixed layer FF12 constituting the pair of first magnetization fixed layers FF1. At this time, the first magnetization fixed layer FF1 and the second magnetization fixed layer RF1 are connected to each other via the magnetization free layer FR1. The magnetization free layer FR1 may be in direct contact with the first magnetization fixed layer FF1, or may be electrically connected to the first magnetization fixed layer FF1 through another conductive layer. In the example shown in FIG. 1, the magnetization free layer FR1 is electrically connected to the first magnetization fixed layer FF1 through, for example, an etching stopper film ES1.
The magnetization free layer FR1 has reversible magnetization. The magnetoresistive memory MR1 is written by inverting the magnetization of the magnetization free layer FR1. That is, the magnetization free layer FR1 functions as a data storage layer of the magnetic tunnel junction TJ1. In the present embodiment, for example, the magnetization of the magnetization free layer FR1 becomes either the first direction or the second direction by reversal.

In the present embodiment, the magnetization free layer FR1 is provided so as to overlap only a part of each of the pair of first magnetization fixed layers FF1 in a plan view and not to overlap other parts. In this case, since it is not necessary to etch the first magnetization fixed layer FF1 together with the magnetization free layer FR1, the etching time can be shortened compared to the sixth embodiment described later. Therefore, it is possible to suppress an increase in resistance value due to oxygen in the etchant and occurrence of resistance variation due to this.
In the magnetoresistive memory MR1 according to the present embodiment, a portion of the magnetization free layer FR1 that overlaps with the first magnetization fixed layer FF1 and its periphery receive a magnetic field generated from the first magnetization fixed layer FF1, for example, and the magnetization direction is fixed and the magnetization is fixed. It becomes a fixed area. Further, a portion of the magnetization free layer FR1 other than the magnetization fixed region becomes, for example, a magnetization free region having reversible magnetization.

In order to improve the performance of the magnetoresistive memory MR1, it is required to increase the magnetoresistance ratio (MR ratio). In order to increase the MR ratio, it is preferable to improve the ratio of the magnetization free region in the portion of the magnetization free layer FR1 that constitutes the magnetic tunnel junction TJ1.
In the present embodiment, the magnetization free layer FR1 is provided so as to overlap a part of each of the pair of first magnetization fixed layers FF1. In this case, the ratio of the magnetization free region in the magnetization free layer FR1 can be improved as compared with the case where all of the first magnetization fixed layer FF1 overlaps with the magnetization free layer FR1. That is, the MR ratio can be increased. Therefore, the magnetic tunnel junction TJ1 having an excellent MR ratio can be realized.

In the present embodiment, the magnetization free layer FR1 is provided in an upper layer than the first magnetization fixed layer FF1. In the example shown in FIG. 1, the magnetization free layer FR1 is provided on the first magnetization fixed layer FF1 and the insulating film IF1 so as to cover a part of each.
Further, as shown in FIG. 2, the magnetization free layer FR1 is provided, for example, such that one end overlaps the first magnetization fixed layer FF11 and the other end overlaps the first magnetization fixed layer FF12. At this time, portions other than both ends of the magnetization free layer FR1 overlap with, for example, a region sandwiched between the pair of first magnetization fixed layers FF1.

The magnetization free layer FR1 is made of a ferromagnetic material exhibiting perpendicular magnetic anisotropy. The ferromagnetic material constituting the magnetization free layer FR1 includes, for example, one or more selected from the group consisting of Fe, Co, and Ni. The ferromagnetic material may further include one or more selected from the group consisting of Pt, Pd, Au, Ag, and Cu.
In one example of the present embodiment, the magnetization free layer FR1 includes, for example, a CoFeB film, an alternating laminated film of Co and Ni, an alternating laminated film of Co and Pt, an alternating laminated film of Co and Pd, an alternating laminated film of CoFe and Ni, and CoFe And Pt, and CoFe and Pd.

  A nonmagnetic layer TB1 is provided on the magnetization free layer FR1. The nonmagnetic layer TB1 has a function as a tunnel barrier in the magnetic tunnel junction TJ1.

  The nonmagnetic layer TB1 is made of a nonmagnetic material. Examples of the nonmagnetic material constituting the nonmagnetic layer TB1 include those made of an insulator, a semiconductor, or a metal. In the present embodiment, it is particularly preferable to use a metal oxide such as MgO or AlO as a material constituting the nonmagnetic layer TB1.

A second magnetization fixed layer RF1 is provided on the nonmagnetic layer TB1. The second magnetization fixed layer RF1 has a magnetization fixed in a direction parallel to the magnetization of one of the pair of first magnetization fixed layers FF1. That is, the second magnetization fixed layer RF1 has magnetization fixed in either the first direction or the second direction.
The second magnetization fixed layer RF1 is provided on the magnetization free layer FR1, which is a data storage layer, via the nonmagnetic layer TB1. That is, the second magnetization fixed layer RF1 functions as a reference layer.

  The second magnetization fixed layer RF1 is made of a ferromagnetic material exhibiting perpendicular magnetic anisotropy. The ferromagnetic material forming the second magnetization fixed layer RF1 can be formed of, for example, a material used for the first magnetization fixed layer FF1, Fe, Co, or an alloy containing Tb in FeCo. The MR ratio can be increased by inserting a ferromagnetic film of Fe, CoFe, or CoFeB between the nonmagnetic layer TB1 and the first magnetization fixed layer FF1.

  The magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 have the same planar shape. In this case, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 can be simultaneously processed by etching. At this time, the deposit generated from the magnetic material layer that becomes the magnetization free layer FR1 adheres to the sidewall of the nonmagnetic layer TB1, but the sidewall deposit can be removed during the overetching of the magnetization free layer FR1. Further, by forming the etching stopper layer ES1 under the magnetization free layer FR1, it is possible to prevent the first magnetization fixed layer FF1 from being etched due to overetching of the magnetization free layer FR1. Therefore, a semiconductor device with excellent yield is realized. Further, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 can be processed using, for example, one mask. For this reason, it is possible to reduce the number of lithography processes and to reduce the manufacturing cost. Note that the same planar shape means that the planar shape caused by processing conditions such as etching selectivity of each layer when the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are processed simultaneously. A deviation is allowed.

  In the present embodiment, the side surfaces of the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 form, for example, the same surface. Even in this case, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 can be simultaneously processed by etching. For this reason, it is possible to reduce the manufacturing cost while realizing a semiconductor device having an excellent yield. The surface constituted by the side surfaces of the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 may be a flat surface or a curved surface. Note that the formation of the same surface allows the occurrence of unevenness due to processing conditions such as etching selectivity of each layer when the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are processed simultaneously. Is. When the planar shapes of the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are rectangular, one surface of each layer facing in the same direction constitutes one plane.

In the example shown in FIG. 1, the semiconductor device SD1 in the present embodiment includes an etching stopper film ES1 provided so as to cover the first magnetization fixed layer FF1, for example. Accordingly, when the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are processed by etching, the first magnetization fixed layer FF1 can be prevented from being etched.
When the etching stopper film ES1 is provided, the magnetization free layer FR1 is electrically connected to the first magnetization fixed layer FF1 through the etching stopper film ES1. In the example shown in FIG. 1, the magnetization free layer FR1 is provided on the etching stopper film ES1.

The etching stopper film ES1 is made of, for example, Ti or Ta, or a nitride thereof. Thereby, in etching using methanol, a high selection ratio with respect to the magnetization free layer FR1 can be realized. Therefore, when the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are processed by etching, the first magnetization fixed layer FF1 can be more reliably suppressed from being etched.
The film thickness of the etching stopper film ES1 is not particularly limited, and can be appropriately selected according to the required characteristics of the magnetoresistive memory MR1, but is, for example, 10 nm or more and 40 nm or less.

  The etching stopper film ES1 is provided so as to include the first magnetization fixed layer FF1 inside, for example, in plan view. In this case, as shown in FIG. 2, the etching stopper film ES1 is provided so that the outline of the etching stopper film ES1 is located outside the first magnetization fixed layer FF1 in plan view. Thereby, when the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are processed by etching, the first magnetization fixed layer FF1 can be more reliably suppressed from being etched.

  In the example shown in FIG. 1, the etching stopper film ES1 is provided so as to cover both the pair of first magnetization fixed layers FF1, for example. That is, one etching stopper film ES1 covering the pair of first magnetization fixed layers FF1 is provided on the first magnetization fixed layer FF1 and the insulating film IF1. In this case, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are provided on the one etching stopper film ES1. For this reason, it is possible to avoid the occurrence of steps in the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 due to the formation of the etching stopper film ES1.

FIG. 4 is a cross-sectional view showing a modification of the magnetoresistive memory MR1 shown in FIG.
In the example shown in FIG. 4, the magnetoresistive memory MR1 does not have the etching stopper film ES1. That is, the magnetization free layer FR1 is electrically connected to the first magnetization fixed layer FF1 without passing through the etching stopper film ES1. As a result, the manufacturing cost of the semiconductor device can be reduced.
In the example shown in FIG. 4, the ferromagnetic material constituting the first magnetization fixed layer FF1 includes, for example, Ti or Ta, or a nitride thereof in addition to the materials exemplified in the magnetoresistive memory MR1 shown in FIG. it can. Thereby, in the etching using methanol, the first magnetization fixed layer FF1 having a high etching selection ratio with respect to the magnetization free layer FR1 can be realized. For this reason, when the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are processed by etching, the first magnetization fixed layer FF1 can be prevented from being etched.

FIG. 5 is a diagram showing an operation principle of the magnetoresistive memory MR1 shown in FIG. In the figure, a one-dot chain line arrow indicates a current flow, and a white arrow indicates a magnetization direction.
In the magnetoresistive memory MR1 according to the present embodiment, data “0” or “1” is written using current-induced domain wall motion. That is, data “0” or “1” is written by moving the domain wall MW1 generated in the magnetization free layer FR1 to reverse the magnetization direction in the magnetization free region in the magnetization free layer FR1. The domain wall MW1 moves in the direction opposite to the direction of the current flowing through the magnetization free layer FR1. For this reason, the domain wall MW1 moves to the first magnetization fixed layer FF11 side by flowing a current from the first magnetization fixed layer FF11 to the first magnetization fixed layer FF12. Further, when a current is passed from the first magnetization fixed layer FF12 to the first magnetization fixed layer FF11, the domain wall MW1 moves to the first magnetization fixed layer FF12 side.

FIG. 5 shows the operation principle when the film thickness of the etching stopper film ES1 is 20 nm. FIG. 5 illustrates a case where the first magnetization fixed layer FF11 has an upward magnetization, and the first magnetization fixed layer FF12 has a downward magnetization.
Hereinafter, the write operation of the magnetoresistive memory MR1 shown in FIG. 5 will be described.

In the magnetoresistive memory MR1 shown in FIG. 5, the etching stopper film ES1 has a thickness of 20 nm. In this case, the magnetization fixed region overlapping the first magnetization fixed layer FF11 in the magnetization free layer FR1 has a magnetization fixed in a direction parallel to the magnetization of the first magnetization fixed layer FF11. In addition, the magnetization fixed region overlapping the first magnetization fixed layer FF12 in the magnetization free layer FR1 has magnetization fixed in a direction parallel to the magnetization of the first magnetization fixed layer FF12. That is, in the magnetization free layer FR1, the magnetization fixed region overlapping with the first magnetization fixed layer FF11 has upward magnetization, and the magnetization fixed region overlapping with the first magnetization fixed layer FF12 has downward magnetization.
In the example of the magnetoresistive memory MR1 shown in FIG. 5, as shown in FIG. 5A, a write current is passed from the first magnetization fixed layer FF11 to the first magnetization fixed layer FF12, and the domain wall MW1 is moved to the first magnetization fixed layer FF11 side. Is moved downward in the magnetization free region in the magnetization free layer FR1. As a result, the magnetization direction of the entire magnetization free layer FR1 is downward. On the other hand, as shown in FIG. 5B, a write current is passed from the first magnetization fixed layer FF12 to the first magnetization fixed layer FF11 and the domain wall MW1 is moved to the first magnetization fixed layer FF12 side, whereby the magnetization free layer. The magnetization in the magnetization free region in FR1 is upward. As a result, the magnetization direction of the entire magnetization free layer FR1 is upward. In the magnetoresistive memory MR1 shown in FIG. 5, the write operation is performed in this way.

The read operation of the magnetoresistive memory MR1 is performed by flowing a read current in a direction penetrating the magnetic tunnel junction TJ1. Thereby, the resistance value of the magnetic tunnel junction TJ1 is detected, and data “0” or “1” corresponding to the resistance value is read out.
When the magnetization direction in the magnetization free region in the magnetization free layer FR1 is antiparallel to the magnetization direction of the second magnetization fixed layer RF1, the resistance value of the magnetic tunnel junction TJ1 becomes relatively large. On the other hand, when the magnetization direction in the magnetization free region in the magnetization free layer FR1 is the same as the magnetization direction of the second magnetization fixed layer RF1, the resistance value of the magnetic tunnel junction TJ1 becomes relatively small. These resistance values are respectively associated with data “0” or “1”.

Next, a method for manufacturing the semiconductor device SD1 according to this embodiment will be described. 6 to 8 and 20 are cross-sectional views illustrating a method for manufacturing the semiconductor device SD1 according to the first embodiment.
The manufacturing method of the semiconductor device SD1 according to this embodiment is performed as follows, for example. First, a pair of first magnetization fixed layers FF1 separated from each other in the planar direction is formed. Next, the first layer FL1 serving as the magnetization free layer FR1 is formed so as to cover the pair of first magnetization fixed layers FF1. Next, the second layer SL1 to be the nonmagnetic layer TB1 is formed on the first layer FL1. Next, a third layer TL1 to be the second magnetization fixed layer RF1 is formed on the second layer SL1. Next, the first layer FL1, the second layer SL1, and the third layer TL1 are simultaneously patterned by etching, and a magnetization free layer FR1, a nonmagnetic layer TB1, and a part of each of the pair of first magnetization fixed layers FF1, The second magnetization fixed layer RF1 is formed. FIGS. 6 to 8 and FIG. 20 illustrate an example of a method for manufacturing such a semiconductor device SD1.
Hereinafter, a method for manufacturing the semiconductor device SD1 according to the present embodiment will be described in detail.

  First, the interlayer insulating film II4 in which the wiring IC3 is embedded is formed over the semiconductor substrate SB1 provided with the transistor TR1. Note that the interlayer insulating film II4 is provided on the semiconductor substrate SB1 through the respective wiring layers respectively constituted by the interlayer insulating film II2 and the interlayer insulating film II3, for example. The wiring in each wiring layer is formed using, for example, a damascene process. Next, the insulating film IF3 in which the contact via CV1 is embedded is formed on the interlayer insulating film II4. 6 to 8, the contact via CV1 is omitted. The same applies to FIGS. 10 to 11, 13 to 15, and 17 to 18 described later.

Next, a pair of first magnetization fixed layers FF1 separated from each other in the planar direction is formed. The pair of first magnetization fixed layers FF1 is formed as follows, for example.
First, as shown in FIG. 6A, the magnetic material layer MM1 is formed on the insulating film IF3. The magnetic material layer MM1 is constituted by, for example, those exemplified above as the material constituting the first magnetization fixed layer FF1. Next, as shown in FIG. 6B, the magnetic material layer MM1 is patterned by etching to form a first magnetization fixed layer FF11. Next, as shown in FIG. 6C, the magnetic material layer MM2 is formed on the insulating film IF3 so as to cover the first magnetization fixed layer FF11. The magnetic material layer MM2 is constituted by, for example, those exemplified above as the material constituting the first magnetization fixed layer FF1. Next, as shown in FIG. 7A, the magnetic material layer MM2 is patterned by etching to form a first magnetization fixed layer FF12. As a result, a pair of first magnetization fixed layers FF1 is formed. Patterning of the magnetic material layer MM1 and the magnetic material layer MM2 can be performed using a resist mask or a hard mask such as SiO ₂ processed with the resist mask, respectively.

  Next, as shown in FIG. 7B, the insulating film IF1 is formed on the insulating film IF3 so as to cover the pair of first magnetization fixed layers FF1. Next, the insulating film IF1 is planarized by CMP (Chemical Mechanical Polishing). Next, as shown in FIG. 7C, the entire surface of the insulating film IF1 is etched back to expose the upper surfaces of the pair of first magnetization fixed layers FF1. In some cases, the upper surfaces of the pair of first magnetization fixed layers FF1 may be exposed only by CMP without using the entire surface etch back.

Next, an etching stopper film ES1 that covers the first magnetization fixed layer FF1 is formed. The etching stopper film ES1 can function as an etching stopper when patterning a first layer FL1, a second layer SL1, and a third layer TL1 described later by etching. In the present embodiment, for example, one etching stopper film ES1 that covers both the pair of first magnetization fixed layers FF1 is formed.
The etching stopper film ES1 is formed as follows, for example. First, as shown in FIG. 8A, the conductive layer CL1 is formed on the insulating film IF1 and the pair of first magnetization fixed layers FF1. The conductive layer CL1 is configured by, for example, those exemplified above as a material constituting the etching stopper film ES1. Next, as shown in FIG. 8B, the conductive layer CL1 is patterned by etching to form an etching stopper film ES1. The patterning of the conductive layer CL1 can be performed using a resist mask or a hard mask such as SiO ₂ processed with the resist mask.

Next, the first layer FL1 serving as the magnetization free layer FR1 is formed so as to cover the pair of first magnetization fixed layers FF1. The first layer FL1 is constituted by, for example, those exemplified above as materials constituting the magnetization free layer FR1. In the present embodiment, the first layer FL1 is formed on the etching stopper film ES1 and the insulating film IF1 so as to cover the pair of first magnetization fixed layers FF1. Next, the second layer SL1 to be the nonmagnetic layer TB1 is formed on the first layer FL1. The second layer SL1 is constituted by, for example, those exemplified above as a material constituting the nonmagnetic layer TB1. Next, a third layer TL1 to be the second magnetization fixed layer RF1 is formed on the second layer SL1. The third layer TL1 is configured by, for example, those exemplified above as a material constituting the second magnetization fixed layer RF1.
As a result, the structure shown in FIG. 8C is obtained.

20 is a cross-sectional view showing a modification of the manufacturing process shown in FIG.
In the method for manufacturing the semiconductor device SD1 according to this embodiment, as illustrated in FIG. 20, the etching stopper film ES1 need not be formed. In this case, the first layer FL1 is provided on the first magnetization fixed layer FF1 and the insulating film IF1 without using the etching stopper film ES1. In the example shown in FIG. 20, the material exemplified in the magnetoresistive memory MR1 shown in FIG. 4 can be used as the ferromagnetic material constituting the first magnetization fixed layer FF1.

Next, the first layer FL1, the second layer SL1, and the third layer TL1 are simultaneously patterned by etching. That is, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are processed into desired shapes. As a result, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 that overlap each part of the pair of first magnetization fixed layers FF1 are formed. The patterning of the first layer FL1, the second layer SL1, and the third layer TL1 can be performed using a resist mask or a hard mask such as SiO ₂ processed with the resist mask. The first layer FL1, the second layer SL1, and the third layer TL1 are etched by dry etching using, for example, methanol as an etchant.
Thereby, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 having the same planar shape are formed. At this time, the side surfaces of the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 form the same surface.

In the present embodiment, the first layer FL1, the second layer SL1, and the third layer TL1 are simultaneously patterned by etching in this way. In this case, the deposit generated from the first layer FL1 adheres to the side wall of the nonmagnetic layer TB1, and this side wall deposit can be removed during overetching of the first layer FL1. Therefore, it is possible to suppress a short circuit from occurring in the magnetic tunnel junction TJ1. In addition, by forming the etching stopper layer ES1 under the first layer FL1, it is possible to suppress the first magnetization fixed layer FF1 from being etched due to overetching of the first layer FL1.
As a result, the magnetoresistive memory MR1 is formed.

Next, after forming the insulating film IF2 that embeds the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1, this is etched back to expose the second magnetization fixed layer RF1. Thereby, an interlayer insulating film II5 constituted by the insulating film IF1 and the insulating film IF2 is formed. Next, a wiring IC4 is formed in the interlayer insulating film II5. The wiring IC 4 can be formed using a damascene process, for example.
Thereafter, a plurality of wiring layers are formed on the interlayer insulating film II5. In the present embodiment, for example, the semiconductor device SD1 is formed in this way.

Next, effects according to the present embodiment will be described. In the present embodiment, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 have the same planar shape. As a result, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 can be simultaneously processed into a desired shape. In this case, the deposit generated from the magnetic material layer that becomes the magnetization free layer FR1 adheres to the sidewall of the nonmagnetic layer TB1, and this sidewall deposit can be removed during the overetching of the magnetization free layer FR1. For this reason, it can suppress that the deposit produced from the magnetic material layer used as the magnetization free layer FR1 remains on the side wall of the nonmagnetic layer TB1, and can suppress the occurrence of a short circuit in the magnetic tunnel junction TJ1. Further, by forming the etching stopper layer ES1 under the magnetization free layer FR1, it is possible to prevent the first magnetization fixed layer FF1 from being etched due to overetching of the magnetization free layer FR1. Thus, according to the present embodiment, it is possible to provide a semiconductor device capable of realizing a good yield.

(Second Embodiment)
FIG. 9 shows a magnetoresistive memory MR2 according to the second embodiment. FIG. 9A is a sectional view showing a sectional structure, and FIG. 9B is a plan view showing a planar structure.
The magnetoresistive memory MR2 according to the present embodiment is the same as the magnetoresistive memory MR1 according to the first embodiment except for the configuration of the etching stopper film ES1. Hereinafter, the configuration of the magnetoresistive memory MR2 according to the present embodiment will be described in detail.

As shown in FIGS. 9A and 9B, the magnetoresistive memory MR2 is provided so as to cover different first magnetization fixed layers FF1, and includes a pair of etching stopper films ES1 separated from each other. Have. Here, the etching stopper film FE1 covering the first magnetization fixed layer FF11 and the etching stopper film SE1 covering the first magnetization fixed layer FF12 constitute a pair of etching stopper films ES1.
According to this embodiment, the pair of first magnetization fixed layers FF1 are respectively covered with the etching stopper film FE1 and the etching stopper film SE1 that are separated from each other. For this reason, it is possible to avoid the current that flows in the magnetization free layer FR1 during the write operation to the magnetoresistive memory MR2 being shunted to the etching stopper film ES1. Thereby, the value of the current flowing through the magnetization free layer FR1 during the write operation can be increased. Accordingly, the total write current can be reduced.

  In the example shown in FIG. 9, the etching stopper film FE1 is provided so as to include the first magnetization fixed layer FF11 on the inner side in a plan view. Further, the etching stopper film SE1 is provided so as to include the first magnetization fixed layer FF12 inside in a plan view. In this case, as shown in FIG. 9B, the etching stopper film ES1 is provided so that the outline of the etching stopper film ES1 is located outside the first magnetization fixed layer FF1 in plan view. Thereby, when the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are processed by etching, the first magnetization fixed layer FF1 can be more reliably suppressed from being etched.

In the present embodiment, the semiconductor device SD1 includes an insulating film IF1 including, for example, an insulating film IF11 in which the first magnetization fixed layer FF1 is embedded and an insulating film IF12 in which an etching stopper film ES1 is embedded. In this case, the magnetization free layer FR1 is provided on the etching stopper film ES1 and the insulating film IF12.
A step generated when the etching stopper film ES1 is formed in a region located between the pair of first magnetization fixed layers FF1 is eliminated by embedding the insulating film IF12 and planarizing it by CMP or the like. In this case, the magnetization free layer FR1 can be formed on a flat surface constituted by the etching stopper film ES1 and the insulating film IF12. Therefore, it is possible to avoid the occurrence of a step in the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 due to the formation of the etching stopper film ES1.
The insulating film IF11 and the insulating film IF12 can be configured by, for example, the materials exemplified in the first embodiment as materials constituting the insulating film IF1.

Next, a method for manufacturing the semiconductor device SD1 according to this embodiment will be described. 10 and 11 are cross-sectional views illustrating a method for manufacturing the semiconductor device SD1 according to the second embodiment.
First, the insulating film IF3 is formed. The insulating film IF3 is formed on the semiconductor substrate SB1 using, for example, the same method as in the first embodiment. Next, a pair of first magnetization fixed layers FF1 separated from each other in the planar direction is formed. The first magnetization fixed layer FF1 can be formed, for example, by the same method as in the first embodiment. Next, the insulating film IF11 is formed on the insulating film IF3 so as to cover the first magnetization fixed layer FF1, and is planarized. Next, the entire surface of the insulating film IF11 is etched back or CMP to expose the first magnetization fixed layer FF1.

Next, an etching stopper film ES1 that covers the first magnetization fixed layer FF1 is formed.
The etching stopper film ES1 is formed as follows, for example. First, as shown in FIG. 10A, a conductive layer CL1 that covers the pair of first magnetization fixed layers FF1 is formed. The conductive layer CL1 is formed on the first magnetization fixed layer FF1 and the insulating film IF11. In addition, the conductive layer CL1 is constituted by, for example, the material exemplified in the first embodiment as a material constituting the etching stopper film ES1. Next, as shown in FIG. 10B, the conductive layer CL1 is patterned by etching. As a result, a pair of etching stopper films ES1 that cover the first magnetization fixed layers FF1 different from each other and are separated from each other are formed. The patterning of the conductive layer CL1 can be performed using a resist mask or a hard mask such as SiO ₂ processed with the resist mask.

Next, as shown in FIG. 10C, an insulating film IF12 is formed on the etching stopper film ES1 and the insulating film IF11 so as to cover the pair of etching stopper films ES1. Next, the insulating film IF12 is planarized by CMP.
Next, as shown in FIG. 11A, the entire surface of the insulating film IF12 is etched back or CMP to expose the upper surfaces of the pair of etching stopper films ES1.

  Next, as shown in FIG. 11B, the first layer FL1, the second layer SL1, and the third layer are formed on the etching stopper film ES1 and the insulating film IF12 so as to cover the pair of first magnetization fixed layers FF1. TL1 is formed in order. Next, the first layer FL1, the second layer SL1, and the third layer TL1 are simultaneously patterned by etching. That is, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are processed into desired shapes. As a result, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 that overlap each part of the pair of first magnetization fixed layers FF1 are formed. The etching process can be performed in the same manner as in the first embodiment.

  Thereafter, each wiring layer is formed as in the first embodiment. In the present embodiment, for example, the semiconductor device SD1 is formed in this way.

  Also in this embodiment, the same effect as the first embodiment can be obtained.

(Third embodiment)
FIG. 12 shows a magnetoresistive memory MR3 according to the third embodiment. FIG. 12A is a sectional view showing a sectional structure, and FIG. 12B is a plan view showing a planar structure.
The magnetoresistive memory MR3 according to the present embodiment is the same as the magnetoresistive memory MR1 according to the first embodiment except for the configuration of the etching stopper film ES1. Hereinafter, the configuration of the magnetoresistive memory MR3 according to the present embodiment will be described in detail.

As shown in FIGS. 12A and 12B, the magnetoresistive memory MR3 has a pair of etching stopper films ES1 provided so as to cover different first magnetization fixed layers FF1 and spaced apart from each other. Here, the etching stopper film FE1 covering the first magnetization fixed layer FF11 and the etching stopper film SE1 covering the first magnetization fixed layer FF12 constitute a pair of etching stopper films ES1.
According to this embodiment, the pair of first magnetization fixed layers FF1 are respectively covered with the etching stopper film FE1 and the etching stopper film SE1 that are separated from each other. For this reason, it is possible to avoid the current flowing through the magnetization free layer FR1 during the write operation of the magnetoresistive memory MR3 from being shunted into the etching stopper film ES1. Thereby, the value of the current flowing through the magnetization free layer FR1 during the write operation can be increased. Therefore, it is possible to improve the operational reliability of the magnetoresistive memory.

  In the example shown in FIG. 12, the etching stopper film FE1 is provided so as to have the same shape as the first magnetization fixed layer FF11 in plan view. In this case, the etching stopper film ES1 and the first magnetization fixed layer FF1 can be patterned using one mask. For this reason, the number of lithography processes can be reduced as compared with the first embodiment. Therefore, it is possible to reduce the manufacturing cost of the semiconductor device.

  The etching stopper film ES1 and the first magnetization fixed layer FF1 are embedded in, for example, the insulating film IF1. In this case, the step generated when the etching stopper film ES1 is formed in the region located between the pair of first magnetization fixed layers FF1 is eliminated by embedding the insulating film IF1 and flattening by CMP or the like. Therefore, the magnetization free layer FR1 can be formed on a flat surface constituted by the etching stopper film ES1 and the insulating film IF1. Therefore, it is possible to avoid the occurrence of a step in the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 due to the formation of the etching stopper film ES1.

Next, a method for manufacturing the semiconductor device SD1 according to this embodiment will be described. 13 to 15 are cross-sectional views illustrating a method for manufacturing the semiconductor device SD1 according to the third embodiment.
First, the insulating film IF3 is formed. The insulating film IF3 is formed on the semiconductor substrate SB1 using, for example, the same method as in the first embodiment.

Next, a pair of first magnetization fixed layers FF1 separated from each other in the planar direction is formed. The process of forming 1st magnetization fixed layer FF1 is performed as follows, for example.
First, as shown in FIG. 13A, a magnetic material layer MM1 and a conductive layer CL1 are sequentially stacked on the insulating film IF3. Next, as shown in FIG. 13B, by etching the magnetic material layer MM1 and the conductive layer CL1, the first magnetization fixed layer FF11 which is one of the pair of first magnetization fixed layers FF1, and the etching stopper And a film FE1. The magnetic material layer MM1 and the conductive layer CL1 are etched using, for example, one resist mask or a hard mask such as SiO ₂ processed with the resist mask. In the present embodiment, for example, after the conductive layer CL1 is patterned by the first etching, the magnetic material layer MM1 can be patterned by the second etching using an etchant different from the first etching.
Next, as illustrated in FIG. 13C, the magnetic material layer MM2 and the conductive layer CL2 are sequentially stacked so as to cover the first magnetization fixed layer FF11 which is one of the pair of first magnetization fixed layers FF1. Next, as shown in FIG. 14A, by etching the magnetic material layer MM2 and the conductive layer CL2, the first magnetization fixed layer FF12 which is the other of the pair of first magnetization fixed layers FF1, and the etching stopper A film SE1 is formed. The magnetic material layer MM2 and the conductive layer CL2 are etched using, for example, one resist mask or a hard mask such as SiO ₂ processed with the resist mask. In the present embodiment, for example, after the conductive layer CL2 is patterned by the third etching, the magnetic material layer MM2 can be patterned by the fourth etching using an etchant different from the third etching.
As a result, a pair of first magnetization fixed layers FF1 is formed.

  Next, as illustrated in FIG. 14B, the insulating film IF1 is formed on the insulating film IF3 so as to cover the pair of first magnetization fixed layers FF1. Next, the insulating film IF1 is planarized by CMP. Next, as shown in FIG. 15A, the entire surface of the insulating film IF1 is etched back or CMP to expose the upper surfaces of the pair of etching stopper films ES1 from the insulating film IF1.

  Next, as shown in FIG. 15B, the first layer FL1, the second layer SL1, and the third layer TL1 are formed on the etching stopper film ES1 and the insulating film IF1 so as to cover the pair of first magnetization fixed layers FF1. Are formed in order. Next, the first layer FL1, the second layer SL1, and the third layer TL1 are simultaneously patterned by etching. That is, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are processed into desired shapes. As a result, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 that overlap each part of the pair of first magnetization fixed layers FF1 are formed. The etching process can be performed in the same manner as in the first embodiment.

  Thereafter, each wiring layer is formed as in the first embodiment. In the present embodiment, for example, the semiconductor device SD1 is formed in this way.

  Also in this embodiment, the same effect as the first embodiment can be obtained.

(Fourth embodiment)
FIG. 16 is a diagram showing a magnetoresistive memory MR4 according to the fourth embodiment. FIG. 16A is a sectional view showing a sectional structure, and FIG. 16B is a plan view showing a planar structure.
The magnetoresistive memory MR4 according to the present embodiment is the same as the magnetoresistive memory MR3 according to the third embodiment except for the configuration of the etching stopper film ES1. Hereinafter, the configuration of the magnetoresistive memory MR4 according to the present embodiment will be described in detail.

  As shown in FIG. 16A, the etching stopper film ES1 is provided so as to cover the upper surface and the side surface of the first magnetization fixed layer FF1. Thereby, when the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are processed by etching, the first magnetization fixed layer FF1 can be reliably prevented from being etched.

Next, a method for manufacturing the semiconductor device SD1 according to this embodiment will be described. 17 and 18 are cross-sectional views illustrating a method for manufacturing the semiconductor device SD1 according to the fourth embodiment.
First, the steps up to the step of forming the first magnetization fixed layer FF1 and the etching stopper film ES1 are performed by the same method as in the third embodiment.

Next, as shown in FIG. 17A, a conductive layer CL3 is formed so as to cover the upper surface and side surfaces of the first magnetization fixed layer FF1. The conductive layer CL3 is constituted by, for example, the material exemplified in the first embodiment as a material constituting the etching stopper film ES1. In the present embodiment, the conductive layer CL3 is formed on the etching stopper film ES1 and the insulating film IF3 so as to cover the etching stopper film ES1 and the first magnetization fixed layer FF1, for example.
Next, as shown in FIG. 17B, the entire surface of the conductive layer CL3 is etched back so that only the portions covering the upper surface and side surfaces of the first magnetization fixed layer FF1 remain.

  Next, as shown in FIG. 17C, the insulating film IF1 is formed on the insulating film IF3 so as to cover the pair of first magnetization fixed layers FF1. Next, the insulating film IF1 is planarized by CMP. Next, as shown in FIG. 18A, the entire surface of the insulating film IF1 is etched back or CMP to expose the upper surfaces of the pair of etching stopper films ES1 from the insulating film IF1.

  Next, as shown in FIG. 18B, the first layer FL1, the second layer SL1, and the third layer TL1 are sequentially formed on the etching stopper film ES1 and the insulating film IF1 so as to cover the pair of first magnetization fixed layers FF1. Form. Next, the first layer FL1, the second layer SL1, and the third layer TL1 are simultaneously patterned by etching. That is, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are processed into desired shapes. As a result, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 that overlap each part of the pair of first magnetization fixed layers FF1 are formed. The etching process can be performed as in the third embodiment.

  Thereafter, each wiring layer is formed as in the third embodiment. In the present embodiment, for example, the semiconductor device SD1 is formed in this way.

  Also in this embodiment, the same effect as the first embodiment can be obtained.

(Fifth embodiment)
FIG. 19 is a diagram showing a magnetoresistive memory MR5 according to the fifth embodiment. FIG. 19A is a sectional view showing a sectional structure, and FIG. 19B is a plan view showing a planar structure.
In the magnetoresistive memory MR5 according to this embodiment, the first magnetization fixed layer FF1 has a tapered shape. Except for this point, the magnetoresistive memory MR5 according to the present embodiment has the same configuration as the magnetoresistive memory MR4 according to the fourth embodiment.
The shape of the first magnetization fixed layer FF1 can be controlled by adjusting the etching conditions when the first magnetization fixed layer FF1 is processed by etching.

In the method for manufacturing the semiconductor device SD1 according to the fourth embodiment, deposits of a magnetic material generated during processing of the first magnetization fixed layer FF1 may remain on the sidewalls of the first magnetization fixed layer FF1. This deposit is not removed by etching back the conductive layer CL3, and remains on the side wall of the first magnetization fixed layer FF1. In this case, when the protrusion that is formed of the deposit remaining on the side wall of the first magnetization fixed layer FF1 and protrudes above the etching stopper film ES1 exposes the upper surface of the etching stopper film ES1 from the insulating film IF1. There are concerns about the occurrence. In this case, there is a possibility that a step is generated in the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 formed on the first magnetization fixed layer FF1.
According to the present embodiment, the first magnetization fixed layer FF1 has a tapered shape. In this case, the first magnetization fixed layer FF1 can be processed by etching, and deposits attached to the side walls of the first magnetization fixed layer FF1 can be removed. For this reason, it is possible to suppress the deposit of the magnetic material from remaining in the first magnetization fixed layer FF1. Therefore, it is possible to suppress the occurrence of steps in the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1.

  Also in this embodiment, the same effect as the fourth embodiment can be obtained.

(Sixth embodiment)
FIG. 21 is a sectional view showing a magnetoresistive memory MR6 according to the sixth embodiment. FIG. 22 is a plan view showing the magnetoresistive memory MR6 shown in FIG.

  The semiconductor device SD1 according to this embodiment includes a magnetoresistive memory MR6. The magnetoresistive memory MR6 includes a pair of etching stopper films ES3, a pair of first magnetization fixed layers FF1, a magnetization free layer FR1, a nonmagnetic layer TB1, and a second magnetization fixed layer RF1. The pair of etching stopper films ES3 are provided apart from each other in the planar direction. The pair of first magnetization fixed layers FF1 are provided on different etching stopper films ES3. The magnetization free layer FR1 overlaps the entire pair of first magnetization fixed layers FF1 in a plan view and is electrically connected to the pair of first magnetization fixed layers FF1. The nonmagnetic layer TB1 is provided on the magnetization free layer FR1. The second magnetization fixed layer RF1 is provided on the nonmagnetic layer TB1. The side surfaces of the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 form the same surface. In plan view, a part of the outline of the first magnetization fixed layer FF1 overlaps the outline of the magnetization free layer FR1, and is located inside the etching stopper film ES3. FIG. 21 shows an example of a magnetoresistive memory MR6 constituting such a semiconductor device SD1.

  In the present embodiment, the side surfaces of the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 form the same surface. In this case, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 can be simultaneously processed into a desired shape. For this reason, similarly to the first embodiment, it is possible to suppress the deposits generated from the magnetic material layer serving as the magnetization free layer FR1 from remaining on the side walls of the nonmagnetic layer TB1, and to cause a short circuit in the magnetic tunnel junction TJ1. Can be suppressed.

On the other hand, in the magnetoresistive memory MR1 according to the first embodiment, the etching stopper film ES1 may be required to be a thin film. However, in such a case, there is a concern that the etching stopper film ES1 that protects the first magnetization fixed layer FF1 disappears when the magnetization free layer FR1 is processed. In this case, a part of the first magnetization fixed layer FF1 is etched together with the processing of the magnetization free layer FR1, and deposits are generated, which may adhere to and remain on the sidewall of the nonmagnetic layer TB1.
In the present embodiment, the first magnetization fixed layer FF1 is entirely covered with the magnetization free layer FR1, and a part of the outline overlaps the outline of the magnetization free layer FR1. Such a structure simultaneously processes the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1, and selects a portion of the first magnetization fixed layer FF1 that is not covered by the magnetization free layer FR1. It can be realized by removing them automatically. According to the present embodiment, by performing such a process, the deposit of the magnetic material layer that becomes the first magnetization fixed layer FF1 on the side wall of the nonmagnetic layer TB1 when the magnetization free layer FR1 is processed as described above. Even if adhering, the deposit can be removed together with the selective removal of the first magnetization fixed layer FF1. Therefore, the occurrence of a short circuit at the magnetic tunnel junction TJ1 can be more reliably suppressed.

Further, according to the present embodiment, a part of the outline of the first magnetization fixed layer FF1 that overlaps the outline of the magnetization free layer FR1 is located inside the etching stopper film ES3 in plan view. That is, the etching stopper film ES3 has a portion that is not covered by the first magnetization fixed layer FF1 and the magnetization free layer FR1. In this case, constituent members such as plugs which are lower than the magnetoresistive memory MR6 and are located around the magnetoresistive memory MR6 can be protected by the etching stopper film ES3.
As described above, according to the present embodiment, it is possible to provide a semiconductor device capable of realizing a better yield.

  Hereinafter, the configuration of the magnetoresistive memory MR6 according to the present embodiment and the configuration of the semiconductor device SD1 including the magnetoresistive memory MR6 will be described in detail.

  The semiconductor device SD1 according to the present embodiment can have the same configuration as the semiconductor device SD1 according to the first embodiment, for example, except that the magnetoresistive memory MR6 is provided. The semiconductor device SD1 has a plurality of magnetoresistive memories MR6, for example.

  FIG. 23 is a sectional view showing a semiconductor device SD1 having the magnetoresistive memory MR6 shown in FIG. FIG. 23 illustrates a case where the magnetoresistive memory MR6 is formed in a multilayer wiring layer constituting the semiconductor device SD1. In this case, the magnetoresistive memory MR6 can be formed, for example, in an arbitrary wiring layer in the multilayer wiring layer. In the example shown in FIG. 23, the magnetoresistive memory MR6 is formed in a wiring layer including the interlayer insulating film II5 and the wiring IC4. As the semiconductor substrate SB1, the transistor TR1, and the multilayer wiring layer constituting the semiconductor device SD1, for example, those exemplified in the first embodiment can be adopted.

  The magnetoresistive memory MR6 includes a pair of etching stopper films ES3 that are provided apart from each other in the planar direction. The etching stopper film ES3 has a function of protecting constituent members such as plugs located below the magnetoresistive memory MR6 when the first magnetization fixed layer FF1 is etched. Thereby, the reliability of the semiconductor device SD1 having the magnetoresistive memory MR6 can be further improved.

  FIG. 21 illustrates the case where the etching stopper film ES3 is provided so as to cover the entire contact via CV1 located under the etching stopper film ES3. In this case, the etching stopper film ES3 is provided so as to be electrically connected to the contact via CV1. Thus, the contact via CV1 for supplying current to the magnetoresistive memory MR6 can be protected by the etching stopper film ES3. As the contact via CV1, for example, the one exemplified in the first embodiment can be adopted.

  The etching stopper film ES3 is made of, for example, Ti or Ta, or a nitride thereof. Thereby, for example, in etching using methanol, a high selection ratio can be realized with respect to the first magnetization fixed layer FF1.

The thickness of the etching stopper film ES3 can be appropriately selected according to the required characteristics of the magnetoresistive memory MR6, and is, for example, not less than 10 nm and not more than 40 nm. As a result, it is possible to improve the electrical characteristics of the magnetoresistive memory MR6 while sufficiently exhibiting the function as a protective film.
The shape of the etching stopper film ES3 is not particularly limited. In the example shown in FIG. 22, the etching stopper film ES3 is provided so that at least the upper surface of the etching stopper film ES3 has a rectangular shape. The etching stopper film ES3 may have a tapered shape whose width increases from the upper end toward the lower end.

The magnetoresistive memory MR6 includes a pair of first magnetization fixed layers FF1 provided on different etching stopper films ES3. FIG. 21 illustrates the case where the first magnetization fixed layer FF1 is electrically connected to the contact via CV1 via the etching stopper film ES3.
The pair of first magnetization fixed layers FF1 includes a first magnetization fixed layer FF11 and a first magnetization fixed layer FF12. The pair of first magnetization fixed layers FF1 have magnetizations fixed in antiparallel directions to each other. In the present embodiment, the first magnetization fixed layer FF11 has a magnetization fixed in a first direction perpendicular to the plane of the semiconductor substrate SB1, for example. The first magnetization fixed layer FF12 has a magnetization fixed in a second direction opposite to the first direction, for example.

  The first magnetization fixed layer FF1 is made of a ferromagnetic material exhibiting perpendicular magnetic anisotropy. As such a ferromagnetic material, for example, the ferromagnetic material constituting the first magnetization fixed layer FF1 in the first embodiment can be adopted. The shape of the first magnetization fixed layer FF1 is not particularly limited. In the example shown in FIG. 22, the first magnetization fixed layer FF1 is provided so that at least the upper surface of the first magnetization fixed layer FF1 has a rectangular shape.

  The magnetoresistive memory MR6 can include, for example, a cap layer CA1. The cap layer CA1 is provided on the first magnetization fixed layer FF1. Thereby, in the formation process of the magnetoresistive memory MR6, it is possible to reliably suppress the upper surface of the first magnetization fixed layer FF1 from being damaged by etching or the like. The cap layer CA1 is provided below the magnetization free layer FR1 described later, and is entirely covered with the magnetization free layer FR1.

  In the present embodiment, for example, a pair of cap layers CA1 provided on different first magnetization fixed layers FF1 and spaced apart from each other in the planar direction are provided. In this case, it is possible to avoid the current flowing in the magnetization free layer FR1 during the write operation to the magnetoresistive memory MR6 from being shunted to the cap layer CA1. Thereby, the value of the current flowing through the magnetization free layer FR1 during the write operation can be increased. Accordingly, the total write current can be reduced.

  The cap layer CA1 is formed of a conductive material. Thereby, the magnetization free layer FR1 can be electrically connected to the first magnetization fixed layer FF1 via the cap layer CA1. The conductive material constituting the cap layer CA1 can include, for example, Ta, Ti, Ru, or Pt. This makes it possible to exhibit a particularly excellent function as a protective film for protecting the upper surface of the first magnetization fixed layer FF1.

  The thickness of the cap layer CA1 is not particularly limited, but can be, for example, 1 nm or more and 15 nm or less. This makes it easy to control the magnitude of the leakage magnetic field generated from the first magnetization fixed layer FF1 to the magnetization free layer FR1 to an appropriate value for improving the operation performance of the magnetoresistive memory MR6. Further, the cap layer CA1 can sufficiently function as a protective film for protecting the upper surface of the first magnetization fixed layer FF1.

  The shape of the cap layer CA1 is not particularly limited. In the present embodiment, for example, the cap layer CA1 can be provided so that at least the upper surface of the cap layer CA1 has a rectangular shape. In the method for manufacturing the semiconductor device SD1 according to the present embodiment, which will be described later, for example, an etching process is performed on the cap layer CA1 before and after the step of forming the magnetic tunnel junction TJ1. These etching processes are all performed on the cap layer CA1 and the first magnetization fixed layer FF1. Therefore, in the present embodiment, the cap layer CA1 and the first magnetization fixed layer FF1 can be provided such that the respective side surfaces form the same surface. Note that the formation of the same surface allows generation of irregularities due to processing conditions such as etching selectivity of each layer when the cap layer CA1 and the first magnetization fixed layer FF1 are etched simultaneously. In this embodiment, when the planar shape of the cap layer CA1 and the first magnetization fixed layer FF1 is a rectangle, one surface of the cap layer CA1 and one surface of the first magnetization fixed layer FF1 adjacent to the one surface in the vertical direction Will constitute one plane.

  The magnetoresistive memory MR6 may not include the cap layer CA1. In this case, the first magnetization fixed layer FF1 is in contact with the magnetization free layer FR1. Thereby, the connection reliability between the first magnetization fixed layer FF1 and the magnetization free layer FR1 can be improved, and the leakage magnetic field generated from the first magnetization fixed layer FF1 to the magnetization free layer FR1 can be increased.

  In the present embodiment, the interval between the first magnetization fixed layer FF1 and the magnetization free layer FR1 is preferably 15 nm or less in the stacking direction of the first magnetization fixed layer FF1 and the magnetization free layer FR1. Thereby, the leakage magnetic field generated from the first magnetization fixed layer FF1 to the magnetization free layer FR1 can be effectively increased, which can contribute to the improvement of the operation performance of the magnetoresistive memory MR6. The lower limit value of the distance between the first magnetization fixed layer FF1 and the magnetization free layer FR1 in the stacking direction is not particularly limited, and can be set to, for example, 0 nm.

The magnetoresistive memory MR6 includes a magnetization free layer FR1 that is electrically connected to the first magnetization fixed layer FF1. In the present embodiment, the magnetization free layer FR1 is provided so as to overlap the entire pair of first magnetization fixed layers FF1 in plan view. That is, the magnetization free layer FR1 is provided so as to cover the entire first magnetization fixed layer FF11 and the first magnetization fixed layer FF12.
When the cap layer CA1 is provided on the first magnetization fixed layer FF1, the magnetization free layer FR1 is provided on the cap layer CA1 so as to overlap the entire cap layer CA1 in plan view. In this case, the magnetization free layer FR1 is electrically connected to the first magnetization fixed layer FF1 via the cap layer CA1.

  The magnetoresistive memory MR6 includes a nonmagnetic layer TB1 provided on the magnetization free layer FR1 and a second magnetization fixed layer RF1 provided on the nonmagnetic layer TB1. As a result, the magnetoresistive memory MR6 has the magnetic tunnel junction TJ1 constituted by the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 that are stacked together. As the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1, for example, those exemplified in the first embodiment can be adopted.

  The side surfaces of the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 form the same surface. Such a structure can be realized by simultaneously processing the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 by etching. According to the present embodiment, by performing such a process, it is possible to realize a semiconductor device excellent in yield as described above. The surface constituted by the side surfaces of the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 may be a flat surface or a curved surface. Note that the formation of the same surface allows the occurrence of unevenness due to processing conditions such as etching selectivity of each layer when the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are processed simultaneously. Is. When the planar shapes of the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are rectangular, one surface of each layer facing in the same direction constitutes one plane.

  Moreover, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 have, for example, the same planar shape. Such a structure can be realized by simultaneously processing the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 by etching. According to the present embodiment, by performing such a process, it is possible to realize a semiconductor device excellent in yield as described above. Note that the same planar shape means that the planar shape caused by processing conditions such as etching selectivity of each layer when the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are processed simultaneously. A deviation is allowed.

In the present embodiment, a part of the outline of the first magnetization fixed layer FF1 overlaps the outline of the magnetization free layer FR1 in plan view. Such a structure selectively processes a portion of the first magnetization fixed layer FF1 that is not covered by the magnetization free layer FR1 along with the processing of the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1. It can be realized by removing. According to the present embodiment, by performing such a process, it is possible to more reliably suppress the occurrence of a short circuit in the magnetic tunnel junction TJ1 as described above.
In the present embodiment, for example, when the outline of the lower surface of the magnetization free layer FR1 and the outline of the lower surface of the first magnetization fixed layer FF1 are observed, a part of the outline of the first magnetization fixed layer FF1 is magnetized. It is possible to adopt an aspect that overlaps the outline of the free layer FR1 in plan view.

  In the present embodiment, a part of the outline of the first magnetization fixed layer FF1 that overlaps the outline of the magnetization free layer FR1 is located inside the etching stopper film ES3 in plan view. That is, the etching stopper film ES3 has a portion that is not covered by the first magnetization fixed layer FF1 and the magnetization free layer FR1. As a result, as described above, components such as plugs located around the magnetoresistive memory MR6 can be protected by the etching stopper film ES3.

  FIG. 21 illustrates a case where the entire contact via CV1 is formed under a portion of the etching stopper film ES3 that is not covered with the magnetization free layer FR1. The arrangement of the contact via CV1 is not limited to this. For example, a part of the contact via CV1 may overlap with the magnetization free layer FR1 in a plan view. In this case, it is possible to reduce the size of the magnetoresistive memory MR6.

FIG. 22 illustrates a case where the planar shape of the first magnetization fixed layer FF1 is a rectangle. In this case, the pair of first magnetization fixed layers FF1 has, for example, three sides excluding one side facing the other first magnetization fixed layer FF1 in the outline of one first magnetization fixed layer FF1 in a plan view. It is provided so as to overlap with the outline of the magnetization free layer FR1. At this time, the one side facing the other first magnetization fixed layer FF12 of the outline of one first magnetization fixed layer FF1 is located inside the magnetization free layer FR1 in a plan view, and the one side of the magnetization free layer FR1 It will not overlap with the outline. Further, of the outline of one first magnetization fixed layer FF1, the three sides excluding the one side facing the other first magnetization fixed layer FF1 are located inside the etching stopper film ES3 in plan view. Become.
In the example shown in FIG. 22, the first magnetization is such that three sides of the outline of the first magnetization fixed layer FF11 except for one side facing the first magnetization fixed layer FF12 overlap with the outline of the magnetization free layer FR1. A fixed layer FF11 is provided. In addition, the first magnetization fixed layer FF12 is provided so that three sides of the outer shape line of the first magnetization fixed layer FF12 excluding one side facing the first magnetization fixed layer FF11 overlap with the outer shape line of the magnetization free layer FR1. It has been.

In the present embodiment, a part of the side surface of the first magnetization fixed layer FF1 is continuous with, for example, the side surface of the magnetization free layer FR1. Such a structure selectively processes a portion of the first magnetization fixed layer FF1 that is not covered by the magnetization free layer FR1 along with the processing of the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1. It can be realized by removing. According to the present embodiment, by performing such a process, it is possible to more reliably suppress the occurrence of a short circuit in the magnetic tunnel junction TJ1 as described above. When the cap layer CA1 is provided between the first magnetization fixed layer FF1 and the magnetization free layer FR1, a part of the side surface of the first magnetization fixed layer FF1, a part of the side surface of the cap layer CA1, and the magnetization The side surfaces of the free layer FR1 are provided so as to be continuous with each other.
Note that a part of the side surface of the first magnetization fixed layer FF1 is continuous with the side surface of the magnetization free layer FR1 means that a part of the side surface of the first magnetization fixed layer FF1 and the side surface of the magnetization free layer FR1. This refers to the case where there are no discontinuous steps between them. On the other hand, when the first magnetization fixed layer FF1 is etched together with the magnetization free layer FR1, the occurrence of unevenness due to processing conditions such as etching selectivity of each layer can be allowed.

  In the present embodiment, a part of the side surface of the first magnetization fixed layer FF1 that is continuous with the side surface of the magnetization free layer FR1 is located inside the etching stopper film ES3 in plan view. That is, the etching stopper film ES3 has a portion that is not covered by the first magnetization fixed layer FF1 and the magnetization free layer FR1. Thereby, constituent members such as plugs that are lower than the magnetoresistive memory MR6 and are located around the magnetoresistive memory MR6 can be protected by the etching stopper film ES3.

In the example shown in FIG. 22, the planar shape of the first magnetization fixed layer FF1 is a rectangle. In this case, in the pair of first magnetization fixed layers FF1, for example, three of the side surfaces of one first magnetization fixed layer FF1 excluding one surface facing the other first magnetization fixed layer FF1 are side surfaces of the magnetization free layer FR1. It is provided to be continuous. At this time, one of the side surfaces of the first magnetization fixed layer FF1 facing the other first magnetization fixed layer FF12 is located inside the magnetization free layer FR1 in a plan view, and the side surface of the magnetization free layer FR1 Will not be continuous. In addition, among the side surfaces of one first magnetization fixed layer FF1, the three surfaces other than the one surface facing the other first magnetization fixed layer FF1 are located inside the etching stopper film ES3 in plan view.
In the example shown in FIG. 22, the first magnetization pinned layer is such that three of the side surfaces of the first magnetization pinned layer FF11 excluding one surface facing the first magnetization pinned layer FF12 are continuous with the side surface of the magnetization free layer FR1. A layer FF11 is provided. In addition, the first magnetization fixed layer FF12 is provided such that three of the side surfaces of the first magnetization fixed layer FF12 excluding one surface facing the first magnetization fixed layer FF11 are continuous with the side surface of the magnetization free layer FR1. Yes.

  In the present embodiment, a part of the side surface of the first magnetization fixed layer FF1 that is continuous with the side surface of the magnetization free layer FR1 can be formed, for example, perpendicular to the plane of the semiconductor substrate SB1. As a result, it is possible to more reliably suppress deposits generated by etching the first magnetization fixed layer FF1 from remaining on the sidewalls of the nonmagnetic layer. In such a structure, for example, the conditions for selectively removing the first magnetization fixed layer FF1 by etching together with the processing of the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 are appropriately selected. It can be realized by performing dry etching.

FIG. 24 is a sectional view showing a modification of the magnetoresistive memory MR6 shown in FIG.
As shown in FIG. 24, the etching stopper film ES3 is formed on one surface where the first magnetization fixed layer FF1 is provided from one region covered by the magnetization free layer FR1 to another region not covered by the magnetization free layer FR1. You may have level | step difference DL1 which becomes low toward. In this case, when the first magnetization fixed layer FF1 is etched, the overetching can be sufficiently performed, so that it is possible to reliably suppress the deposit from remaining on the sidewall of the nonmagnetic layer TB1. The height of the step DL1 is not particularly limited, but can be, for example, 1 nm or more and 10 nm or less. As will be described later, when the first magnetization fixed layer FF1 is selectively removed by etching, the step DL1 removes the upper portion of the etching stopper film ES3 that is not covered by the magnetization free layer FR1. Can be realized.

FIG. 35 is a cross-sectional view showing a modified example of the magnetoresistive memory MR6 shown in FIG. 21, and an example different from FIG. 24 is shown.
As shown in FIG. 35, the pair of first magnetization fixed layers FF1 may be inclined so that the side surfaces facing each other are close to each other from the upper end toward the lower end. At this time, for example, the pair of etching stopper films ES3 are also provided so that the respective side surfaces facing each other are inclined so as to approach each other from the upper end toward the lower end. Further, for example, the pair of cap layers CA1 are also provided so that the respective side surfaces facing each other are inclined so as to approach each other from the upper end toward the lower end. In such a structure, in the manufacturing method of the semiconductor device SD1 described later, after the stacked body LM1 is formed in a tapered shape whose width decreases from the lower end toward the upper end, the first magnetization fixed layer FF1 and the cap layer CA1 This can be realized by selectively removing the portion not covered by the magnetization free layer FR1 together with the processing of the magnetization free layer FR1.

  The magnetoresistive memory MR6 according to the present embodiment can perform a write operation and a read operation in the same manner as the magnetoresistive memory MR1 according to the first embodiment.

  FIG. 25 is a schematic diagram for explaining the graphs shown in FIGS. 26 and 27. In FIG. 25, a rectangular parallelepiped magnetization fixed layer having a length L, a width of 120 nm, and a height of 12 nm is shown. This magnetization fixed layer is uniformly magnetized in the direction indicated by the white arrow in FIG. A point A in FIG. 25 indicates a point separated from the center of the upper surface of the magnetization fixed layer by a distance d in the thickness direction of the magnetization fixed layer. Here, the leakage magnetic field from the magnetization fixed layer at point A was obtained by calculation.

  FIG. 26 is a graph showing the relationship between the length L of the magnetization fixed layer shown in FIG. 25 and the leakage magnetic field from the magnetization fixed layer at point A. FIG. 26 shows the dependence on the length L of the leakage magnetic field when the distance d is fixed at 6 nm or 21 nm. Comparing the case where the distance d is 6 nm and the case where the distance d is 21 nm, the length L is about the same when the length L is 120 mm or more, but a significant difference may occur when the length L is 80 nm or less. I understand. In particular, when the length L is 30 nm, the leakage magnetic field when the distance d is 6 nm is about 2.5 times that when the distance d is 21 nm.

  Based on such a calculation result, in order to increase the leakage magnetic field from the first magnetization fixed layer FF1 in the magnetization free layer FR1, while reducing the interval between the magnetization free layer FR1 and the first magnetization fixed layer FF1, It can be seen that it is important to appropriately reduce the length L of the first magnetization fixed layer FF1. The distance between the magnetization free layer FR1 and the first magnetization fixed layer FF1 can be reduced, for example, by reducing the thickness of the cap layer CA1. In other words, even when the leakage magnetic field needs to be increased, an increase in the leakage magnetic field can be realized by appropriately reducing the length L of the first magnetization fixed layer FF1 while thinning the cap layer CA1. Therefore, the film thickness of the first magnetization fixed layer FF1 can be reduced. Therefore, it is possible to reduce the amount of expensive metal material used for forming the first magnetization fixed layer FF1 and to reduce the manufacturing cost.

In the present embodiment, the portion of the first magnetization fixed layer FF1 that is not covered by the magnetization free layer FR1 is selected along with the processing of the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1. Removed. For this reason, compared with 1st Embodiment, the length L of 1st magnetization fixed layer FF1 can be shortened. Based on the result shown in FIG. 26, it is possible to obtain a larger leakage magnetic field by shortening the length L as described above while keeping the distance d below a certain value. For this reason, according to the present embodiment, it is possible to contribute to the improvement of the operation performance of the magnetoresistive memory MR6.
The length L of the first magnetization fixed layer FF1 in the linear direction connecting the pair of first magnetization fixed layers FF1 is not particularly limited, but may be 5 nm to 300 nm, and may be 10 nm to 100 nm. Can be adopted as a more preferred embodiment.

  FIG. 27 is a graph showing the relationship between the distance d from the magnetization fixed layer to the point A shown in FIG. 25 and the leakage magnetic field from the magnetization fixed layer at the point A. FIG. 27 shows the dependence of the leakage magnetic field on the distance d when the length L is fixed at 30 nm or 280 nm. It can be seen that in the region where the distance d is 20 nm or less, the leakage magnetic field at the point A is larger when the length L is 30 nm than when the length L is 280 nm. Further, it is shown that the difference between the leakage magnetic field when the length L is 30 nm and the leakage magnetic field when the length L is 280 nm is larger as the distance d is shorter.

  Actually, the shape of the first magnetization fixed layer FF1 is various, but from the result shown in FIG. 27, the distance d between the first magnetization fixed layer FF1 and the magnetization free layer FR1 is preferably 15 nm or less. it is conceivable that. Thereby, even if the film thickness of the first magnetization fixed layer FF1 is thin, a sufficient leakage magnetic field can be obtained by adjusting the length L. Therefore, it is possible to reduce the amount of expensive metal material used for forming the first magnetization fixed layer FF1 and to reduce the manufacturing cost.

  In the present embodiment, the portion of the first magnetization fixed layer FF1 that is not covered by the magnetization free layer FR1 is selected along with the processing of the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1. Removed. That is, it is not necessary to form the etching stopper film ES1 having a large film thickness on the first magnetization fixed layer FF1. For this reason, as compared with the first embodiment, the distance d between the first magnetization fixed layer FF1 and the magnetization free layer FR1 can be sufficiently shortened. Based on the result shown in FIG. 27, it is possible to obtain a larger leakage magnetic field by shortening the distance d in this way. Therefore, according to the present embodiment, it is possible to contribute to the improvement of the operation performance of the magnetoresistive memory MR6.

28 to 30 are cross-sectional views illustrating the method for manufacturing the semiconductor device SD1 according to this embodiment.
The manufacturing method of the semiconductor device SD1 according to this embodiment is performed as follows, for example. First, the etching stopper film ES3 and the first magnetization fixed layer FF1 are sequentially stacked, and a pair of stacked bodies LM1 separated from each other in the planar direction is formed. Next, a first layer FL1 serving as the magnetization free layer FR1 is formed so as to cover the pair of stacked bodies LM1. Next, a second layer SL1 to be the nonmagnetic layer TB1 is formed on the first layer FL1. Next, a third layer TL1 to be the second magnetization fixed layer RF1 is formed on the second layer SL1. Next, the first layer FL1, the second layer SL1, and the third layer TL1 are simultaneously patterned by etching to form the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1, and the first magnetization fixed A portion of the layer FF1 that is not covered with the magnetization free layer FR1 is removed by etching. 28 to 30 exemplify methods for manufacturing such a semiconductor device SD1.
Hereinafter, a method for manufacturing the semiconductor device SD1 according to the present embodiment will be described in detail.

  First, the insulating layer IF3 in which the contact via CV1 is embedded is formed on the semiconductor substrate SB1 provided with the transistor TR1. Insulating layer IF3 is formed, for example, on a plurality of interlayer insulating films. Contact via CV1 is electrically connected to, for example, transistor TR1 through the wiring and via formed in these interlayer insulating films.

Next, the etching stopper film ES3 and the first magnetization fixed layer FF1 are sequentially stacked, and a pair of stacked bodies LM1 that are separated from each other in the planar direction is formed. This pair of laminated bodies LM1 is formed as follows, for example.
First, as shown in FIG. 28A, a stacked body LM11 in which an etching stopper film ES3, a first magnetization fixed layer FF11, and a cap layer CA1 are stacked in this order is formed. The stacked body LM11 is formed by sequentially stacking a conductor layer to be the etching stopper film ES3, a magnetic material layer to be the first magnetization fixed layer FF11, and a conductor layer to be the cap layer CA1, and then patterning them by etching. Can be obtained.
Next, as illustrated in FIG. 28B, a stacked body LM12 in which the etching stopper film ES3, the first magnetization fixed layer FF12, and the cap layer CA1 are sequentially stacked is formed. The stacked body LM12 is formed by sequentially stacking a conductive layer that becomes the etching stopper film ES3, a magnetic material layer that becomes the first magnetization fixed layer FF12, and a conductive layer that becomes the cap layer CA1 so as to cover the stacked body LM11. Thereafter, these are obtained by patterning by etching.
Thereby, a pair of laminated body LM1 will be obtained.

  In the present embodiment, as described above, for example, the stacked body LM1 in which the etching stopper film ES3, the first magnetization fixed layer FF1, and the cap layer CA1 are sequentially stacked can be formed. Thereby, for example, when the stacked body LM12 is processed or when an etch-back process is performed on an insulating layer IF1 described later, it is possible to suppress the surface of the first magnetization fixed layer FF1 from being damaged. In addition, it is possible to suppress the influence on the first magnetization fixed layer FF1 due to oxygen in the air and moisture in the interlayer insulating film during the process.

Next, as illustrated in FIG. 28C, the insulating layer IF1 is formed on the insulating layer IF3 so as to cover the pair of stacked bodies LM1. Next, the insulating film IF1 is planarized by CMP (Chemical Mechanical Polishing). Next, as shown in FIG. 29A, the entire surface of the insulating film IF1 is etched back to expose the upper surfaces of the pair of stacked bodies LM1. In some cases, the upper surfaces of the pair of stacked bodies LM1 are exposed only by CMP without using the entire surface etch back.
As shown in FIG. 29B, the cap layer CA1 may disappear by performing etch back or CMP on the insulating layer IF1. In this case, the upper surface of the stacked body LM1 is constituted by the first magnetization fixed layer FF1.

  Next, a first layer FL1 serving as the magnetization free layer FR1 is formed so as to cover the pair of stacked bodies LM1. Next, the second layer SL1 to be the nonmagnetic layer TB1 is formed on the first layer FL1. Next, a third layer TL1 to be the second magnetization fixed layer RF1 is formed on the second layer SL1. The first layer FL1, the second layer SL1, and the third layer TL1 can be formed, for example, in the same manner as the method exemplified in the first embodiment. As a result, the structure shown in FIG.

Next, the first layer FL1, the second layer SL1, and the third layer TL1 are simultaneously patterned by etching to form the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1, and the first magnetization A portion of the fixed layer FF1 that is not covered with the magnetization free layer FR1 is removed by etching. At this time, the same mask is used for the etching of the first layer FL1, the second layer SL1, and the third layer TL1 and the etching of the portion of the first magnetization fixed layer FF1 that is not covered by the magnetization free layer FR1. Done. Etching of the first layer FL1, the second layer SL1, the third layer TL1, and the first magnetization fixed layer FF1 can be performed using a resist mask or a hard mask such as SiO ₂ processed with the resist mask. Etching for the first layer FL1, the second layer SL1, the third layer TL1, and the first magnetization fixed layer FF1 is performed by dry etching using, for example, methanol as an etchant.
When the cap layer CA1 is provided on the first magnetization fixed layer FF1, the first layer FL1, the second layer SL1, and the third layer TL1 are patterned, and the first magnetization fixed layer FF1 and the cap layer CA1. Of these, the portion not covered with the magnetization free layer FR1 is removed by etching.
As a result, the magnetoresistive memory MR6 shown in FIG. 21 is formed.

  In the present embodiment, the etching stopper film ES3 is, for example, a protective film that protects the contact via CV1 located in the lower layer when the portion of the first magnetization fixed layer FF1 that is not covered by the magnetization free layer FR1 is removed by etching. Function as. For this reason, the step of removing the portion of the first magnetization fixed layer FF1 that is not covered by the magnetization free layer FR1 by etching depends on the condition that the portion of the etching stopper film ES3 that is not covered by the magnetization free layer FR1 remains. It can be carried out.

  In FIG. 30B, after the first layer FL1, the second layer SL1, and the third layer TL1 are patterned, a portion of the first magnetization fixed layer FF1 that is not covered by the magnetization free layer FR1 The structure is shown before is removed by etching. In the present embodiment, for example, after the first layer FL1, the second layer SL1, and the third layer TL1 are patterned to obtain the structure shown in FIG. 30B, the first magnetization is fixed through another process. An etching process can be performed on a portion of the layer FF1 that is not covered with the magnetization free layer FR1. On the other hand, simultaneously with the patterning of the first layer FL1, the second layer SL1, and the third layer TL1, a portion of the first magnetization fixed layer FF1 that is not covered by the magnetization free layer FR1 can be etched.

  In the present embodiment, the step of removing the portion of the first magnetization fixed layer FF1 that is not covered by the magnetization free layer FR1 by etching is performed by removing the upper portion of the portion of the etching stopper film ES3 that is not covered by the magnetization free layer FR1. Done to remove. In this case, after the above process, the lower portion of the portion of the etching stopper film ES3 that is not covered by the magnetization free layer FR1 remains on the insulating layer IF3. In this case, when the first magnetization fixed layer FF1 is etched, sufficient over-etching can be performed, so that it is possible to more reliably suppress deposits from remaining on the side walls of the nonmagnetic layer TB1.

  Thereafter, a plurality of wiring layers can be formed on the magnetoresistive memory MR6 by, for example, the same method as in the first embodiment. In the present embodiment, for example, the semiconductor device SD1 is formed in this way.

(Seventh embodiment)
FIG. 31 is a cross-sectional view showing a magnetoresistive memory MR7 according to the seventh embodiment.
In the magnetoresistive memory MR7 according to the present embodiment, one cap layer CA1 is provided so as to cover the entire pair of first magnetization fixed layers FF1. Except for this point, the magnetoresistive memory MR7 is the same as the magnetoresistive memory MR6 according to the sixth embodiment.
Such a structure includes, for example, a pair of stacked bodies LM1 formed of the etching stopper film ES3 and the first magnetization fixed layer FF1 in the method for manufacturing the semiconductor device SD1 exemplified in the sixth embodiment, and the stacked body LM1. After forming the insulating layer IF1 to be embedded, it can be realized by forming one cap layer CA1 so as to cover the entire pair of stacked bodies LM1.

  In the present embodiment, as shown in FIG. 31, for example, the cap layer CA1, the magnetization free layer FR1, the nonmagnetic layer TB1, and the second magnetization fixed layer RF1 have the same planar shape. These can be formed.

  Also in this embodiment, the same effect as that of the sixth embodiment can be obtained.

(Eighth embodiment)
FIG. 32 is a sectional view showing a magnetoresistive memory MR8 according to the eighth embodiment.
In the magnetoresistive memory MR8 according to the present embodiment, a pair of cap layers CA1 located on different first magnetization fixed layers FF1 are provided. In plan view, a part of the outline of each cap layer CA1 that does not overlap with the outline of the magnetization free layer FR1 does not overlap with the first magnetization fixed layer FF1. That is, the part of the outline of each cap layer CA1 that does not overlap with the outline of the magnetization free layer FR1 is located outside the first magnetization fixed layer FF1 in plan view. Except for this point, the magnetoresistive memory MR8 is the same as the magnetoresistive memory MR6 according to the sixth embodiment.
Such a structure includes, for example, a pair of stacked bodies LM1 formed of the etching stopper film ES3 and the first magnetization fixed layer FF1 in the method for manufacturing the semiconductor device SD1 exemplified in the sixth embodiment, and the stacked body LM1. After forming the insulating layer IF1 to be embedded, it can be realized by forming a cap layer CA1 larger than the stacked body LM1 on each stacked body LM1.

  Also in this embodiment, the same effect as that of the sixth embodiment can be obtained.

(Ninth embodiment)
FIG. 33 is a cross-sectional view showing a magnetoresistive memory MR9 according to the ninth embodiment.
In the magnetoresistive memory MR9 according to the present embodiment, the cap layer CA1 is covered with the magnetization free layer FR1 on the first magnetization fixed layer FF1 and among the side surfaces of the first magnetization fixed layer FF1 and the etching stopper film ES3. And provided on the part. In the example shown in FIG. 33, the cap layer CA1 is provided on each side surface of the pair of first magnetization fixed layers FF1 facing each other and on each side surface of the pair of etching stopper films ES3 facing each other. . Except for this point, the magnetoresistive memory MR9 is the same as the magnetoresistive memory MR6 according to the sixth embodiment.
Such a structure is obtained by, for example, forming a pair of stacked bodies LM1 including the etching stopper film ES3 and the first magnetization fixed layer FF1 in the method for manufacturing the semiconductor device SD1 exemplified in the sixth embodiment, and then stacking This can be realized by forming the cap layer CA1 on the upper surface and the side surface of the body LM1.

FIG. 34 is a sectional view showing a modification of the magnetoresistive memory MR9 shown in FIG.
As shown in FIG. 34, the pair of first magnetization fixed layers FF1 may be inclined such that the side surfaces facing each other are close to each other from the upper end toward the lower end. Further, the pair of etching stopper films ES3 may be inclined such that the side surfaces facing each other are close to each other from the upper end toward the lower end. Such a structure can be realized by appropriately adjusting the etching conditions and the like when processing the first magnetization fixed layer FF1 and the etching stopper film ES1.

  Also in this embodiment, the same effect as that of the sixth embodiment can be obtained.

In addition, according to the said embodiment, the following invention is disclosed.
(Appendix 1)
A pair of etching stopper layers provided apart from each other in the planar direction; and
A pair of first magnetization fixed layers provided on the different etching stopper layers;
A magnetization free layer that overlaps the entire pair of first magnetization fixed layers in a plan view and is electrically connected to the pair of first magnetization fixed layers;
A nonmagnetic layer provided on the magnetization free layer;
A second magnetization pinned layer provided on the nonmagnetic layer;
With
The magnetization free layer, the nonmagnetic layer, and the second magnetization fixed layer have the same planar shape.
A semiconductor device in plan view, wherein a part of the outline of the first magnetization fixed layer overlaps with the outline of the magnetization free layer and is located inside the etching stopper layer.
(Appendix 2)
A pair of etching stopper layers provided apart from each other in the planar direction; and
A pair of first magnetization fixed layers provided on the different etching stopper layers;
A magnetization free layer that overlaps the entire pair of first magnetization fixed layers in a plan view and is electrically connected to the pair of first magnetization fixed layers;
A nonmagnetic layer provided on the magnetization free layer;
A second magnetization pinned layer provided on the nonmagnetic layer;
With
The side surfaces of the magnetization free layer, the nonmagnetic layer, and the second magnetization fixed layer form the same surface,
A part of the side surface of the first magnetization fixed layer is continuous with the side surface of the magnetization free layer and is located inside the etching stopper film in a plan view.
(Appendix 3)
Forming a pair of first magnetization fixed layers spaced apart from each other in a plane direction;
Forming a first layer to be a magnetization free layer so as to cover the pair of first magnetization fixed layers;
Forming a second layer to be a nonmagnetic layer on the first layer;
Forming a third layer to be a second magnetization fixed layer on the second layer;
The first layer, the second layer, and the third layer are simultaneously patterned by etching, so that the magnetization free layer, the nonmagnetic layer, and the first layer that overlap with a part of each of the pair of first magnetization fixed layers Forming a two-magnetization pinned layer;
A method for manufacturing a semiconductor device comprising:
(Appendix 4)
In the method for manufacturing a semiconductor device according to attachment 3,
A semiconductor device further comprising a step of forming an etching stopper film covering the first magnetization fixed layer after the step of forming the first magnetization fixed layer and before the step of forming the first layer. Production method.
(Appendix 5)
In the method for manufacturing a semiconductor device according to attachment 4,
The step of forming the etching stopper film includes:
Forming a conductive layer covering the pair of first magnetization fixed layers;
Patterning the conductive layer to form a pair of the etching stopper films covering the different first magnetization fixed layers and spaced apart from each other;
A method of manufacturing a semiconductor device including:
(Appendix 6)
In the method for manufacturing a semiconductor device according to attachment 3,
The step of forming the first magnetization fixed layer includes:
Laminating a first magnetic material layer and a first conductive layer in order;
Etching one of the first magnetic material layer and the first conductive layer to form one of the pair of first magnetization fixed layers;
Laminating a second magnetic material layer and a second conductive layer in order so as to cover the one of the pair of first magnetization fixed layers;
Etching the second magnetic material layer and the second conductive layer to form the other of the pair of first magnetization fixed layers;
A method of manufacturing a semiconductor device including:
(Appendix 7)
In the method for manufacturing a semiconductor device according to attachment 6,
After the step of forming the first magnetization fixed layer and before the step of forming the first layer,
Forming a third conductive layer covering an upper surface and a side surface of the first magnetization fixed layer;
Etching back the third conductive layer;
A method for manufacturing a semiconductor device further comprising:
(Appendix 8)
Forming a pair of stacked bodies in which an etching stopper film and a first magnetization fixed layer are sequentially stacked and spaced apart from each other in a plane direction;
Forming a first layer to be a magnetization free layer so as to cover the pair of stacked bodies;
Forming a second layer to be a nonmagnetic layer on the first layer;
Forming a third layer to be a second magnetization fixed layer on the second layer;
The first layer, the second layer, and the third layer are simultaneously patterned by etching to form the magnetization free layer, the nonmagnetic layer, and the second magnetization fixed layer, and the first magnetization fixed layer A step of removing a portion not covered by the magnetization free layer by etching,
A method for manufacturing a semiconductor device comprising:
(Appendix 9)
In the method for manufacturing a semiconductor device according to attachment 8,
The step of removing the portion of the first magnetization fixed layer that is not covered by the magnetization free layer by etching is such that the upper portion of the portion of the etching stopper film that is not covered by the magnetization free layer is removed. A method for manufacturing a semiconductor device.
(Appendix 10)
In the method for manufacturing a semiconductor device according to attachment 8,
The stacked body is a semiconductor device in which the etching stopper film, the first magnetization fixed layer, and a cap layer are sequentially stacked.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

SD1 Semiconductor device MR1, MR2, MR3, MR4, MR5, MR6, MR7, MR8, MR9 Magnetoresistive memory TJ1 Magnetic tunnel junction FF1, FF11, FF12 First magnetization fixed layer RF1 Second magnetization fixed layer TB1 Nonmagnetic layer FR1 Magnetization free Layer ES1, ES2, ES3, FE1, SE1 Etching stopper film MW1 Domain wall MM1, MM2 Magnetic material layer FL1 First layer SL1 Second layer TL1 Third layer CL1, CL2, CL3 Conductive layers IF1, IF11, IF12, IF2, IF3 Insulation Film II1, II2, II3, II4, II5, II6 Interlayer insulating film SB1 Semiconductor substrate TR1 Transistor GE1 Gate electrode GI1 Gate insulating film DR1 Source / drain region EI1 Element isolation film CP1 Contact plug IC1, IC2, IC3, IC4, IC5 Wiring CV Contact via CA1 capping layer DL1 step LM1, LM11, LM12 laminate

Claims (19)

A pair of first magnetization fixed layers provided to be spaced apart from each other in a plane direction;
A magnetization free layer that overlaps a part of each of the pair of first magnetization fixed layers in a plan view and is electrically connected to the pair of first magnetization fixed layers;
A nonmagnetic layer provided on the magnetization free layer;
A second magnetization pinned layer provided on the nonmagnetic layer;
With
The said magnetization free layer, the said nonmagnetic layer, and the said 2nd magnetization fixed layer are semiconductor devices which have mutually the same planar shape. The semiconductor device according to claim 1,
An etching stopper film provided to cover the first magnetization fixed layer;
The semiconductor device wherein the magnetization free layer is electrically connected to the first magnetization fixed layer via the etching stopper film. The semiconductor device according to claim 2,
The etching stopper film is a semiconductor device including the first magnetization fixed layer inside in a plan view. The semiconductor device according to claim 2,
The etching stopper film is a semiconductor device made of Ti, Ta, or a nitride thereof. The semiconductor device according to claim 2,
The etching stopper film is a semiconductor device that covers both of the pair of first magnetization fixed layers. The semiconductor device according to claim 2,
A semiconductor device comprising a pair of the etching stopper films provided so as to cover the first magnetization fixed layers different from each other and spaced apart from each other. The semiconductor device according to claim 6.
The etching stopper film is a semiconductor device that covers an upper surface and a side surface of the first magnetization fixed layer. The semiconductor device according to claim 7,
The first magnetization fixed layer is a semiconductor device provided in a tapered shape. The semiconductor device according to claim 6.
An insulating film having the etching stopper film embedded therein;
The magnetization free layer is a semiconductor device provided on the etching stopper film and the insulating film. A pair of first magnetization fixed layers provided to be spaced apart from each other in a plane direction;
A magnetization free layer that overlaps a part of each of the pair of first magnetization fixed layers in a plan view and is electrically connected to the pair of first magnetization fixed layers;
A nonmagnetic layer provided on the magnetization free layer;
A second magnetization pinned layer provided on the nonmagnetic layer;
With
Side surfaces of the magnetization free layer, the nonmagnetic layer, and the second magnetization fixed layer are the same surface. A pair of etching stopper layers provided apart from each other in the planar direction; and
A pair of first magnetization fixed layers provided on the different etching stopper layers;
A magnetization free layer that overlaps the entire pair of first magnetization fixed layers in a plan view and is electrically connected to the pair of first magnetization fixed layers;
A nonmagnetic layer provided on the magnetization free layer;
A second magnetization pinned layer provided on the nonmagnetic layer;
With
The side surfaces of the magnetization free layer, the nonmagnetic layer, and the second magnetization fixed layer form the same surface,
A semiconductor device in plan view, wherein a part of the outline of the first magnetization fixed layer overlaps with the outline of the magnetization free layer and is located inside the etching stopper layer. The semiconductor device according to claim 11,
A semiconductor device comprising a cap layer which is provided on the first magnetization fixed layer and under the magnetization free layer, and is entirely covered with the magnetization free layer. The semiconductor device according to claim 12,
A semiconductor device comprising a pair of cap layers provided on different first magnetization fixed layers and spaced apart from each other in a planar direction. The semiconductor device according to claim 11,
The semiconductor device in which the first magnetization fixed layer is in contact with the magnetization free layer. The semiconductor device according to claim 11,
A semiconductor device, wherein an interval between the first magnetization fixed layer and the magnetization free layer is 15 nm or less in a stacking direction of the first magnetization fixed layer and the magnetization free layer. The semiconductor device according to claim 11,
The etching stopper layer has a step which is lowered from one region covered by the magnetization free layer to another region not covered by the magnetization free layer on one surface where the first magnetization fixed layer is provided. A semiconductor device. The semiconductor device according to claim 11,
A semiconductor device comprising a plug that is entirely covered with the etching stopper layer and connected to the etching stopper layer. The semiconductor device according to claim 11,
The etching stopper layer is a semiconductor device made of Ti, Ta, or a nitride thereof. The semiconductor device according to claim 11,
The cap layer is a semiconductor device made of Ta, Ti, Ru, or Pt.

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