JP2014236422A5 - - Google Patents

Claims (19)

A photoelectric conversion unit that generates a signal charge corresponding to the amount of incident light, a storage unit that stores the signal charge generated in the photoelectric conversion unit, and an output that outputs a voltage corresponding to the signal charge stored in the storage unit and a circuit, a pixel portion which the input node and is electrically connected between the photoelectric conversion unit and the accumulation unit and the output circuit is arrayed two-dimensionally,
The discharges the signal charges accumulated in the accumulation unit, exhaust Dego, resetting the accumulation unit the signal charges accumulated in the accumulation section obtained at the time elapsed charge accumulation period, and after the acquisition of the signal charge are those lines sequentially performing charge storage read operation to retrieve the reset level of the accumulating product portion and,
Before the discharge of each row, performs the蓄perform preliminary discharge to perform discharge of preliminary charge from a product unit, and the n-th (n is a natural number) the discharge and (n + 1) th row of the preliminary discharge at the same time the Is,
For each column of the pixel unit, the feedback control circuit for feedback control is provided so as to accumulate unit becomes the reference potential, the solid-state image, characterized in that it performs the feedback control when the discharge element.   The solid-state imaging device according to claim 1, wherein the feedback control is performed at the time of resetting. The pixel portion includes a row selection circuit connected between the output circuit and a signal line from which the signal charge and a reset level are output.
3. The solid-state imaging device according to claim 1, wherein the row selection circuit is turned on during the discharge and is turned off during the preliminary discharge.   4. The solid-state imaging device according to claim 1, wherein the discharge of the n-th row and the reset of a row other than the n-th row are performed at different timings.   5. The solid-state imaging device according to claim 1, wherein the feedback control circuit includes a voltage source for supplying a reference voltage and an inverting amplifier to which the voltage source is connected. For each row, prior to the reset even after the discharge, the claims 1 performs a read pre-reset performing discharge of preliminary charge from accumulation of 5 to any one of claims solid-state imaging device .   The solid-state imaging device according to claim 6, wherein the reset of the nth row and the read preliminary reset of the (n + 1) th row are performed simultaneously. The pixel portion includes a row selection circuit connected between the output circuit and a signal line from which the signal charge and a reset level are output.
8. The solid-state imaging device according to claim 6, wherein the row selection circuit is turned on during the resetting and is turned off during the read preliminary resetting.   The signal charge is acquired before the read preliminary reset of the nth row, and the reset level of the nth row is acquired after the reset of the (n + 1) th row. Solid-state image sensor.   10. The solid-state imaging device according to claim 6, wherein the accumulation unit in the n-th row is in a floating state in which the storage unit is electrically floated at the time of the ejection and the reset of the (n + 1) -th row. A preliminary discharge shift register that outputs a pulse signal for performing the preliminary discharge;
A discharge shift register that outputs a pulse signal for performing the discharge;
A signal level acquisition / reading preliminary discharge shift register that outputs a pulse signal for acquiring the signal charge and performing the reading preliminary reset, and
A read reset shift register that outputs a pulse signal for performing the reset;
The solid-state imaging device according to claim 6, further comprising: a reset level acquisition shift register that outputs a pulse signal for acquiring the reset level.   The solid-state imaging device according to claim 6, wherein at least three correlated double sampling processing circuits are provided for each signal line from which the signal charge and the reset level are output. The pixel unit includes a first electrode partitioned in pixel units and a second electrode provided to face the pixel electrode with the photoelectric conversion unit interposed therebetween,
13. The solid-state imaging device according to claim 1, wherein the second electrode is a common electrode for all the pixel portions.   The solid-state imaging device according to claim 1, wherein the photoelectric conversion unit includes an organic photoelectric conversion film.   The solid-state imaging device according to claim 14, wherein the organic photoelectric conversion film is common to all the pixel portions.   The solid-state imaging device according to claim 1, wherein a signal charge from the photoelectric conversion unit is a hole.   The solid-state imaging device according to claim 1, wherein the signal charge from the photoelectric conversion unit is an electron. The solid-state imaging device according to any one of claims 1-17, wherein a protective circuit in the accumulation portion.   An imaging apparatus comprising the solid-state imaging device according to claim 1.