JP2014236041A - Semiconductor device and layout method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a layout method capable of wiring layout that satisfies a maximum wiring interval condition even if a wiring interval is narrow.SOLUTION: In a layout method for a semiconductor device, a wiring layout containing a plurality of wiring patterns is generated so as to satisfy a routing pitch condition that is preset for a first direction, a first incompatible point that violates the routing pitch condition is detected from the wiring layout, a wiring layout that has been corrected by providing a deviation correction pattern so as to satisfy the routing pitch condition is generated at the first incompatible point, there is detected from the corrected wiring layout a second square incompatible point in which a distance between two wiring patterns adjoining each other in the first direction is larger than a first maximum tolerable value and a distance between two wiring patterns adjoining each other in a second direction orthogonal to the first direction is larger than a second maximum tolerable value, and an extension wiring pattern that satisfies the routing pitch condition is provided at the second incompatible point so that a distance between two wiring patterns adjoining each other in the second direction is equal to or less than the second maximum tolerable value.

Description

  The present invention relates to a semiconductor device, and more particularly to a layout method thereof.

  As a layout method of a semiconductor device, a method of adopting multilayer wiring and performing wiring layout based on a line-and-space with a predetermined pitch for each wiring layer is known (for example, see Patent Document 1).

  Further, as a method for solving various problems that occur when the wiring interval is wide, a technique of arranging a dummy called a fill metal between wirings is known (for example, see Patent Document 2).

JP 2012-109460 A JP 2003-37111 A

  With the miniaturization of the semiconductor device, the width of the internal wiring is also reduced. Here, there is a problem that a narrow wiring is likely to collapse when formed alone. For this reason, a wiring layout based on a line and space pattern in which a plurality of wirings are arranged in parallel at intervals of a predetermined value or less is used.

  However, in an actual circuit, the length of each wiring is determined according to its use, and thus is not constant. That is, the wirings adjacent to each other are not necessarily adjacent over the entire length. For this reason, an area in which the wiring interval cannot be made equal to or less than a predetermined position (hereinafter referred to as a vacant area) always occurs. Therefore, in the related technology, a dummy called a fill metal that is electrically independent from the wiring is arranged in the empty area.

  However, the minimum value (minimum area standard) of the area occupied by the fill metal is determined. That is, the fill metal cannot be arranged in an empty area whose occupied area is smaller than the minimum area standard. This means that the smaller the wiring width and the wiring interval, the higher the possibility that the empty area where the fill metal cannot be arranged increases. The narrower the wiring width, the higher the risk of collapse, but it is impossible to manually correct it, and the existence of free space where fill metal can not be placed is expected to become a bigger problem in the future .

  A layout method of a semiconductor device by a computer-aided design system according to an embodiment of the present invention generates a wiring layout including a plurality of wiring patterns so as to satisfy a predetermined routing pitch condition in the first direction, and the wiring A first nonconforming portion that violates the routing pitch condition is detected from the layout, and a corrected wiring layout is generated by providing a misalignment correction pattern so as to satisfy the routing pitch condition at the first nonconforming portion, and the corrected From the wiring layout, the distance between the two wiring patterns adjacent to each other in the first direction is larger than the first maximum allowable value and the distance between the two wiring patterns adjacent to the second direction orthogonal to the first direction is the second. A rectangular second nonconforming portion that is larger than the maximum allowable value is detected, and the second nonconforming portion is detected in the second direction. As the distance between the two wiring patterns adjacent becomes less than the second maximum permissible value, providing the routing pitch satisfying extension wiring pattern, characterized in that.

  A semiconductor device according to another embodiment of the present invention includes a first wiring and a second wiring in a first wiring layer, and each of the first wiring and the second wiring is at least connected to a via. One contact region, and the distance from the end of the first wiring to the nearest contact region is different from the distance from the end of the second wiring to the nearest contact region. A featured semiconductor device.

  As a first nonconforming part of the wiring layout, a part that violates the routing pitch condition set for the first direction is detected, and after providing a deviation correction pattern for correcting it, as a second nonconforming part of the corrected wiring layout By detecting an area exceeding the first and second maximum allowable values in the first direction and the second direction orthogonal to the first direction and providing an extended correction pattern that satisfies the routing pitch condition in the area, the dummy fill metal is provided. In this case, the empty area that cannot be filled in can be corrected to a state that satisfies the maximum wiring interval condition.

It is a figure which shows an example of a wiring matrix table. It is a figure which shows an example of the line and space pattern which has the wiring width and wiring space | interval in the point P1 of FIG. It is a figure which shows an example of the line and space pattern which has the wiring width and wiring space | interval in the point P2 of FIG. It is a figure which shows an example of the line and space pattern which has the wiring width and wiring space | interval in the point P3 of FIG. It is a figure which shows an example of the wiring layout with the area | region which cannot arrange | position a dummy fill metal. It is a figure which shows the other example of the wiring layout with the area | region which cannot arrange | position a dummy fill metal. It is a figure which shows another example of the wiring layout with the area | region which cannot arrange | position a dummy fill metal. It is a flowchart for demonstrating the layout method which concerns on the 1st Embodiment of this invention. FIG. 7 is a diagram for explaining the isolated wiring correction dummy wiring step (ST105) in FIG. 6 and showing an example of a wiring layout having a vacant area. FIG. 8 is a diagram illustrating an example of a state in which a correction pattern is inserted and arranged in the wiring layout of FIG. 7. FIG. 8 is a diagram illustrating another example of a state in which a correction pattern is inserted and arranged in the wiring layout of FIG. 7. It is a figure for demonstrating edge length. FIG. 10 is a diagram for explaining a process of generating the wiring layout of FIG. 9 from the wiring layout of FIG. 7 and showing a complementary pattern. FIG. 10 is a diagram for explaining a process of generating the wiring layout of FIG. 9 from the wiring layout of FIG. FIG. 10 is a diagram for explaining a process of generating the wiring layout of FIG. 9 from the wiring layout of FIG. 7 and showing a deviation correction pattern. FIG. 10 is a diagram for explaining a process of generating the wiring layout of FIG. 9 from the wiring layout of FIG. 7 and showing an edge longer than the basic wiring width. FIG. 10 is a diagram for explaining a process of generating the wiring layout of FIG. 9 from the wiring layout of FIG. 7 and showing a part of the extension correction pattern. FIG. 10 is a diagram for explaining a process of generating the wiring layout of FIG. 9 from the wiring layout of FIG. 7 and showing the remaining part of the extension correction pattern. FIG. 10 is a diagram for explaining a process of generating the wiring layout of FIG. 9 from the wiring layout of FIG. 7 and showing a recessed region formed by an extension correction pattern. FIG. 10 is a diagram for explaining a process of generating the wiring layout of FIG. 9 from the wiring layout of FIG. 7 and showing a shape correction pattern. It is a figure which shows an example of the wiring layout by which the extension correction pattern was inserted and arrange | positioned. It is a figure which shows the other example of the wiring layout by which the extension correction pattern was inserted and arrange | positioned. It is a figure which shows the other example of the wiring layout by which the extension correction pattern was inserted and arrange | positioned. It is a figure which shows another example of the wiring layout by which the extension correction pattern was inserted and arrange | positioned. It is a figure which shows an example of the wiring layout by which the deviation correction pattern was inserted and arrange | positioned. It is a figure which shows an example of the wiring layout by which the deviation correction pattern and the extension correction pattern were inserted and arranged. It is a figure which shows an example of the wiring layout by which the extension correction pattern and the shape correction pattern were inserted and arranged. It is a figure which shows the other example of the wiring layout by which the extension correction pattern and the shape correction pattern were inserted and arrange | positioned.

  Before describing the embodiment of the present invention, first, the relationship between the wiring width W and the wiring interval S will be described in order to facilitate understanding of the present invention. Here, it is assumed that a plurality of wirings are line and space patterns arranged in parallel at a predetermined pitch. Such a line-and-space-based wiring is used in, for example, a random logic area of a semiconductor device that forms a desired circuit by being multilayered. The random logic area corresponds to a peripheral circuit in a DRAM (Dynamic Random Access Memory) device, for example.

  FIG. 1 is an example of a wiring matrix table (wiring reference) showing the relationship between the wiring width W and the allowable wiring interval S.

  As shown in FIG. 1, as the wiring width W becomes smaller (W1c> W1b> W1a> W1> W2> W3), the minimum wiring interval minS can be reduced (minS1c> minS1b> minS1a> minS1> minS2> minS3). . This can reduce the area occupied by the wiring and contribute to miniaturization of the semiconductor device.

  On the other hand, as the wiring width W decreases, the maximum wiring interval maxS needs to be reduced (maxS1 (no restriction)> maxS2> maxS3). This is because if the wiring width W is reduced, it becomes difficult or impossible to isolate the wiring during lithography, but if there are other wirings in the vicinity, the collapse is prevented or suppressed. That is, as the wiring width W is smaller, it is necessary to arrange other wiring closer.

  FIG. 2A is a diagram showing a part of an example of a wiring layout based on a line-and-space pattern of wiring pitch T1 = W1 + minS1 designed by adopting wiring width W1 and wiring interval minS1 at point P1 in FIG. In the following description, the direction in which the wiring pitch is defined (vertical direction in the figure) is referred to as the first direction, and the direction in which the wiring extends (direction perpendicular to the first direction, horizontal direction in the figure) is the second direction. Call it.

  In FIG. 2A, the wiring 210a located at the center in the first direction is electrically connected to another wiring layer (not shown) via the via 220a. Therefore, the wiring 210a is shorter in the second direction than the wirings 211a and 212a located on both sides in the first direction. As a result, a vacant area 230a having a wiring interval S1 exists between the wiring 211a and the wiring 212a. As described above, when the wiring width W is greater than or equal to W1, the maximum wiring interval maxS is not limited. That is, regardless of the value of the wiring interval S1, the wirings 211a and 212a can be isolated, and the problem of collapse due to the wide wiring interval does not occur.

  FIG. 2B is a diagram showing a part of an example of a wiring layout based on a line and space pattern of wiring pitch T2 = W2 + minS2 designed by adopting wiring width W2 and wiring interval minS2 at point P2 in FIG.

  In FIG. 2B, the wiring 210b located at the center in the first direction is electrically connected to another wiring layer (not shown) via the via 220b. Therefore, the wiring 210b is shorter in the second direction than the wirings 211b and 212b located on both sides in the first direction. As a result, a vacant area 230b having a wiring interval S2 exists between the wiring 211b and the wiring 212b. Here, the point P2 in FIG. 1 is a point determined so that S2 ≦ max2S. Accordingly, the distance S2 between the wirings 211b and 212b located on both sides of the wiring 210b is equal to or less than the maximum wiring interval max2S, and the problem of collapse due to the wide wiring interval between these wirings 211b and 212b can be avoided. Even in the case where there is a vacant area with a wiring interval exceeding the maximum wiring interval maxS2 in an area not shown, the wiring pitch T2 is a relatively large value, so that the vacant area is formed using the fill metal method. There is a high possibility of placing dummy fill metal. Therefore, even in this case, the problem of the collapse of the wiring due to the wide wiring interval hardly occurs.

  FIG. 2C is a diagram showing an example of a wiring layout based on the line and space pattern of the wiring bit T3 = W3 + minS3 designed by adopting the wiring width W3 and the wiring interval minS3 at the point P3 in FIG.

  In FIG. 2C, the wiring 210c located at the center in the vertical direction is electrically connected to another wiring layer (not shown) via the via 220c. Therefore, the wiring 210c is shorter in the second direction than the wirings 211c and 212c located on both sides in the first direction. As a result, a vacant area 230c having a wiring interval S3 exists between the wiring 211c and the wiring 212c. In this case, since S3> max3S, the wirings 211c and 212c located on both sides of the wiring 210c include a portion where the distance to the wiring adjacent to a part thereof exceeds the maximum wiring interval maz3S. Therefore, these wirings 211c and 212c may collapse. There is a possibility that the problem of collapse can be solved by disposing dummy fill metal by the fill metal method in the empty area 230c. However, in order to arrange the dummy fill metal in the empty area by the fill metal method, the minimum area standard must be satisfied. In the case of FIG. 2C, since the wiring pitch T3 is small, the vacant area must be considerably long in the second direction. Therefore, there are many cases where the dummy fill metal cannot be arranged without satisfying the minimum area standard of the fill metal method.

  For example, in the wiring layout shown in FIG. 3, the dummy fill metal 310 can be arranged in many empty areas. However, since the empty area 320 does not satisfy the minimum area criterion, no dummy fill metal is disposed.

  Here, it is assumed that the minimum area reference of wiring required for disposing the dummy fill metal is minArea. Further, it is assumed that the wiring interval in the empty area 320 is S4 (= W + 2 · minS) exceeding the maximum wiring interval maxS. In this case, if the length L1 of the empty area 320 is not L1 ≧ minArea / W + (minS · 2), a dummy fill metal by the fill metal method cannot be arranged there.

  In the example of FIG. 3, the adjacent wiring interval in the empty area 321 and the like is equal to S4 and larger than the maximum wiring interval maxS. However, in the empty area 321 and the like, the distance L2 between the wiring 331 and the dummy fill metal 311 (or other wiring) adjacent in the second direction is not more than a predetermined value (for example, the maximum wiring interval maxS). For this reason, in the empty area 321 and the like, it can be considered that the pattern (wiring and dummy fill metal or wiring) is continuous in the second direction. Therefore, there is no problem of wiring collapse around the empty area 321 or the like.

  Further, as an example in which the dummy fill metal cannot be arranged, there is a wiring layout as shown in FIG.

  In the wiring layout of FIG. 4, sub-wirings 430 for forming double vias 420 are connected to some end portions of the main wiring 410 extending in the second direction.

  The interval S5 between the sub-wirings 430 is determined by the wiring pitch T4 of another wiring layer (not shown) to which the double via 420 is connected. For this reason, the wiring interval S5 is larger than the maximum wiring interval maxS corresponding to the wiring width W in this wiring layer. Further, like the empty region 440, the wiring interval S6 between the sub wiring 430 and the main wiring 410 may exceed the maximum wiring interval maxS. However, if the area of the empty area 441 formed between these sub-wirings and the area of the empty area 440 formed between the sub-wiring 430 and the main wiring 410 is smaller than the minimum area standard for arranging the dummy fill metal. In the empty areas 440 and 441, dummy fill metal cannot be arranged. Therefore, the sub-wiring 430 and the peripheral wiring 410 around it may be collapsed.

  Furthermore, as another example in which the dummy fill metal cannot be arranged, there is a wiring layout as shown in FIG.

  Usually, wiring layout design is performed using an automatic wiring tool (computer-aided design system). In this case, the wiring is arranged so as to pass on the routing grid 510 determined by a preset routing pitch T5. However, like the wirings 521 and 522 shown in FIG. 5, there may be wirings that are arranged so as to deviate or deviate from the routing grid 510 depending on the surrounding conditions. Among the empty areas formed around such wirings, A: those in which the width (wiring interval) required for arranging the dummy fill metal by the fill metal method is insufficient (empty areas 531 and 532). ) And B: those that do not satisfy the minimum area standard for fill metal (empty regions 533 and 534).

  According to the present invention, a displacement correction pattern and / or a wiring for correcting a displacement of a wiring pattern in empty areas (320, 440-441, 531-534) where a dummy fill metal by the metal fill method as described above cannot be arranged. At least one of the above problems is solved by adding an extension correction pattern for extending the pattern.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 6 is a flowchart showing an overall flow of the layout method of the semiconductor device by the computer-aided design system according to the first embodiment of the present invention. The layout method according to the present embodiment includes an isolated wiring correction dummy generation step (ST105). Other steps are the same as the related layout method.

  Referring to FIG. 6, first, in step ST101, a floor plan is created.

  Next, in step ST102, according to the floor plan, automatic arrangement of elements and automatic wiring for connecting elements are performed, and a wiring layout is created.

  Next, in step ST103, it is verified whether or not there is an error in the wiring. If an error is detected as a result of the verification (Yes), the process returns to step ST102 again, and automatic element placement and automatic wiring are performed again. On the other hand, if no error is detected as a result of the verification (No), the process proceeds to step ST104.

  In step ST104, dummy fill metal insertion placement is performed on the obtained wiring layout by the dummy metal fill method.

  Subsequently, in step ST105, an isolated wiring correction dummy pattern is generated. That is, the correction pattern is inserted and arranged in an empty area where the dummy fill metal cannot be arranged.

  In step ST105, first, a position where the wiring is shifted from the routing grid is detected, and a shift correction pattern for correcting it is generated (step ST201).

  Then, the minimum area standard violation point where the dummy fill metal cannot be arranged is detected, and an extension correction pattern for extending the surrounding wiring is generated (step ST202).

  Further, if necessary, a complicated pattern shape portion is detected and a shape correction pattern is generated (step ST203).

  Thereafter, in step ST106, the presence / absence of a free area is verified. If a free area remains (Yes), the process returns to step ST104. If no free area remains (No), the process ends. .

  Thereafter, a semiconductor device manufacturing process including a wiring forming process using the obtained wiring layout is performed to obtain a semiconductor device. The manufacturing method of the semiconductor device is not different from the related method. In each wiring layer of the multilayer wiring included in the obtained semiconductor device, the wiring is different from the related semiconductor device in a portion corresponding to the deviation correction pattern, the extension correction pattern, and the shape correction pattern.

  Specifically, the distance from the edge of the wiring corresponding to the deviation correction pattern and / or the extension correction pattern to the nearest via (or the contact region to which the via is connected) when there is no such correction pattern. The distance is longer than the distance from the edge of the wiring to the nearest via (or contact region to which the via is connected). Further, in the wiring portion corresponding to the extension correction pattern, the wiring width and wiring interval of the main wiring are maintained.

  Next, step ST105 will be described in more detail with reference to FIGS.

  FIG. 7 is a diagram illustrating an example of a wiring layout after step ST104 is completed. In this example, there are a plurality of empty areas 710 to 716 where the dummy fill metal by the dummy metal fill method could not be arranged. FIG. 8 is a diagram illustrating an example of a wiring pattern after step ST105 is completed. In the wiring layout shown in FIG. 8, several correction patterns are added to the wiring pattern of FIG. FIG. 9 is a diagram illustrating an example in which processing different from that in FIG. 8 is performed in step ST105.

  Referring to FIG. 7, the routing grid 720 is indicated by a dotted line. The routing grid 720 is arranged at a first interval (wiring pitch T) in the first direction (the vertical direction in the figure). The first interval defines the wiring pitch T. The routing grid 720 is repeatedly arranged at a second interval in a second direction (left-right direction in the drawing) orthogonal to the first direction. The second interval is significantly narrower than the first interval.

  In the wiring layout of FIG. 7, a plurality of main wirings 730 formed so as to extend in the left-right direction in the drawing along the routing grid 720 and sub wirings arranged so as to partially overlap the plurality of main wirings 730. included. The sub wiring includes a connection wiring 741 that electrically connects the first wirings 730 and via wirings 742 to 744 that realize double vias. Many of the sub-wirings (741 to 743) are formed along the second direction, but some are formed along the first direction (744). Further, the wiring layout of FIG. 7 includes a plurality of dummy fill metals 750. An upper via 760 connected to the wiring included in the upper wiring layer or a lower via 770 connected to the wiring included in the lower wiring layer is provided at a position away from the end of each wiring by a predetermined distance. .

  The reason why the empty areas 710 to 716 remain in the wiring layout of FIG. 7 is that A: the pattern is shifted from the routing grid (insufficient wiring interval), and B: the minimum area condition by the fill metal method cannot be satisfied. And in both these A and B cases. In order to deal with these causes, as described with reference to FIG. 6, first, a deviation correction pattern for correcting the pattern shifted from the routing grid 720 is generated (step ST201), and then the minimum area criterion is not satisfied. An extension correction pattern (step ST202) for extending the wiring at the location is generated.

  Referring to FIG. 8, with respect to the sub-wirings 742 to 744 that are shifted from the routing grid 720, the shift correction patterns 811 that have edges that cross the routing grid 720 and coincide with the extended lines of the edges of the main wiring 730. 814 is connected. The deviation correction patterns 811 to 813 extend upward from the corresponding sub wirings 742 to 744, respectively. The deviation correction pattern 814 extends downward from the corresponding sub wiring 744.

  In the empty areas 710 to 713 remaining after the misalignment correction patterns 811 to 814 are inserted and arranged, extended correction patterns 821 to 826 extending from both sides of the areas toward the center are provided. In other words, each of the extension correction patterns 821 to 826 is connected between two wirings located on both sides of the empty areas 710 to 713. These extension correction patterns 821 to 826 are inserted and arranged on the routing grid 720 so as to satisfy the routing pitch condition. In other words, the extension correction patterns 821 to 826 are arranged so as to maintain the same wiring width W and wiring interval minS as the main wiring 730. Further, each of the extension correction patterns 821 to 826 is divided into two at the center. This is to keep the two wires located on both sides of the extension correction patterns 821 to 826 electrically separated.

  Note that the contact region to which the upper layer via 760 and the lower layer via 770 are connected is usually provided at a predetermined distance from the end of the corresponding wiring. However, in the places where the deviation correction patterns 811 and 812 and the extension correction patterns 821 to 824 are provided, the distance from the end of the wiring to the nearest contact region (via) is longer than a predetermined distance.

  As described above, according to the present embodiment, it is possible to realize a wiring layout without a fear of collapse using a narrow wiring.

  Now, as described above, the wiring layout of FIG. 8 can avoid the possibility of wiring collapse. However, there are cases where relatively small irregularities are formed in the wiring pattern by providing the correction pattern as in the empty areas 712 and 713. Such small irregularities are not desirable in the manufacturing process.

  Therefore, in the wiring layout shown in FIG. 9, the formation of such small irregularities is avoided as much as possible. Specifically, when the extension correction pattern is provided, the edge lengths of two wirings to be connected to the extension pattern are compared, and the extension correction pattern is connected to the shorter one. Note that the edge length is the length of the straight line portion along the first direction at the end of the wiring in the second direction, as indicated by an arrow in FIG.

  Referring again to FIG. 9, in the empty area 710, the edge lengths of the two wirings are both equal to the wiring width W. Therefore, as in the case of FIG. 8, the extension correction pattern 821 is connected to each of the two wirings. In the empty area 713, the edge lengths of the two wires are sufficiently longer than the wire width W, and can be regarded as being equal to each other. Therefore, as in the case of FIG. 8, the extension correction patterns 825 and 826 are connected to the two wires, respectively. On the other hand, in the empty areas 711 and 712, one of the edge lengths of the two wirings to be connected is equal to the wiring width W, and the other is significantly longer than the wiring width W. In this case, the extension correction patterns 827, 828, and 829 are connected to the wiring having the shorter edge length. Thereby, the shape of the wiring pattern in the empty area 712 can be simplified. That is, it is possible to avoid the formation of small irregularities by providing the extension correction pattern.

  With respect to the empty area 713, the above method cannot simplify the shape of the wiring pattern. Therefore, a shape correction pattern 910 is further added to fill the pattern-shaped recess (recessed area). Thereby, the shape of the wiring pattern in the empty area 713 can be simplified.

  Next, a specific procedure (steps ST201 to ST203) for obtaining the wiring layout of FIG. 9 from the wiring layout of FIG. 7 will be described with reference to FIGS. The following processing is data processing and does not handle actual wiring or the like. The following processing is distinguished from main wiring and sub wiring, but vias and fill metal are handled in the same manner as main wiring.

  First, as shown in FIG. 11, a complementary pattern 1110 is added to the wiring layout of FIG.

  For example, the complementary pattern 1110 is created as follows.

  First, a line-and-space reference pattern according to the same routing grid as the routing grid used in the wiring layout of FIG. 7 is created. Further, a reverse (Not) pattern of the wiring layout of FIG. 7 is created. When a logical product (AND) of the obtained reference pattern and inverted pattern is obtained, a complementary pattern is obtained. If the logical sum (OR) of the obtained complementary pattern and the wiring layout of FIG. 7 is obtained, the wiring layout shown in FIG. 11 is obtained.

  Next, as shown in FIG. 12, in the wiring layout of FIG. 11, basic interval violation places (first nonconforming places, rectangular areas) 1121 to 1124 are detected in the first direction. In other words, a location that violates the routing pitch condition, that is, a location where the wiring interval deviates from the routing pitch T is detected. This is equivalent to detecting a location where the edge of the second wiring and the edge of the complementary pattern do not match in the vertical direction in the figure.

  Next, as shown in FIG. 13, the deviation correction patterns 811 to 814 are arranged so as to eliminate the violations of the detected basic interval violation points 1121 to 1124, and the edges of the corresponding complementary patterns 1110 on the far side are arranged. Enlarge to match In other words, the shift correction patterns 811 to 814 are far away when one of the edges in the first direction is connected to the corresponding wiring and the other edge extends the main wiring adjacent to the first direction in the second direction. It is arranged so as to coincide with the side edge.

  As described above, pattern data regarding the deviation correction patterns 811 to 814 is obtained.

  Next, the obtained deviation correction pattern is inserted and arranged in the wiring layout of FIG. The deviation correction pattern is treated as one piece with each connected sub-wiring. Then, the obtained wiring layout is complemented with the complement pattern using the same method as described above. The wiring layout thus obtained is as shown in FIG.

  Next, among the wiring edges that are in contact with the complementary pattern 1410, the wiring edges 1421-1428 whose edge length is longer than the basic wiring width W are detected. Then, the wiring (including the misalignment correction pattern portion) having the detected wiring edges 1421-1428 is enlarged in the left-right direction by the basic wiring interval (for example, equal to minS). Thereby, a wiring layout as shown in FIG. 15 is obtained.

  Next, in the wiring layout of FIG. 15, complementary patterns 1410-1 to 1410-3 having one end in contact with the enlarged wiring and the other end in contact with the first wiring are extracted. Then, the data representing the extracted complementary patterns 1410-1 to 1410-3 is held as data representing the first extension correction pattern.

  Next, the wiring layout of FIG. 14 is prepared again, and as shown in FIG. 16, the complementary patterns 1410 related to the complementary patterns 1410-1 to 1410-3 are handled as wiring. Then, the center of the second direction is detected for each of the remaining complementary patterns 1410, and a region 1610 having a width equal to the basic wiring width is defined. A complementary pattern portion 1620 excluding the defined region 1610 is extracted, and pattern data representing the extracted portion is held as data representing the second extended correction pattern.

  When the logical sum (OR) of the first extension correction pattern and the second extension correction pattern obtained as described above and the wiring layout of FIG. 7 is obtained, a wiring layout pattern as shown in FIG. 17 is obtained.

  In this way, a rectangular area in which the inter-wiring distance is longer than the wiring interval minS (first allowable value) in the first direction and the inter-wiring distance is longer than the basic wiring width (second allowable value) in the second direction is detected. The first and second extended wiring patterns can be provided therewith the distance between the wirings in the second direction being equal to or smaller than the basic wiring width and satisfying the routing pitch.

  Next, an edge 1710 having an edge length equal to or smaller than a threshold value is detected from the wiring layout shown in FIG. An edge having an edge length equal to or smaller than a threshold value is an edge that may form a recessed area. Note that the edge having a length equal to or shorter than the threshold length is formed by the second extended wiring pattern.

  Then, a rectangular area formed by the detected edge 1710 and the edge of the wiring that follows is detected. When the extracted rectangular area is not surrounded by three edges, that is, when there is no other edge facing the edge 1710 detected with the area interposed therebetween, the area is excluded. Then, as shown in FIG. 18, pattern data representing the shape correction pattern 910 corresponding to the extracted rectangular area is generated.

  The wiring layout of FIG. 9 is completed by obtaining the logical product (OR) of the wiring layout data shown in FIG. 7 for all the correction pattern data obtained as described above.

  FIG. 19 to FIG. 26 are diagrams showing examples of the arrangement of correction patterns. FIGS. 19 to 22 show examples in which only the extension correction pattern is inserted and arranged without any sub-wiring disposition. FIG. 23 shows an example in which only the displacement correction pattern is inserted and arranged. FIG. 24 shows an example in which both the deviation correction pattern and the extension correction pattern are inserted and arranged. 25 and 26 show an example in which an extension correction pattern and a shape correction pattern are inserted and arranged.

  Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the above-described embodiments, and various modifications and changes can be made.

210a to 212a, 210b to 212b, 210c to 212c Wiring 220a, 220b, 220c Via 230a, 230b, 230c Empty area 310, 311 Dummy fill metal 320, 321 Empty area 331 Wiring 410 Main wiring 420 Double via 430 Sub wiring 440, 441 Empty Area 510 Routing grid 521, 522 Wiring 531, 532, 533, 534 Free area 710-716 Empty area 720 Routing grid 730 Main wiring 741 Connection wiring 742-744 Via wiring 750 Dummy fill metal 760 Upper layer via 770 Lower layer via 811 814 Misalignment correction pattern 821-829 Extension correction pattern 910 Shape correction pattern 1110 Complement pattern 1121-1124 Non-compliance with basic interval 1410,14 10-1 to 1410-3 Complementary pattern 1421 to 1428 Wiring edge 1610 Region 1620 Part of complementary pattern 1710 Edge

Claims (11)

Generating a wiring layout including a plurality of wiring patterns so as to satisfy a predetermined routing pitch condition with respect to the first direction;
Detecting a first nonconforming portion that violates the routing pitch condition from the wiring layout,
Providing a corrected wiring layout by providing a deviation correction pattern so as to satisfy the routing pitch condition at the first nonconforming location,
From the modified wiring layout, the distance between two wiring patterns adjacent to each other in the first direction is larger than the first maximum allowable value and between two wiring patterns adjacent to each other in the second direction orthogonal to the first direction. Detecting a rectangular second nonconformity where the distance is greater than the second maximum permissible value;
An extended wiring pattern that satisfies the routing pitch condition is provided at the second nonconforming location so that a distance between the two wiring patterns adjacent in the second direction is equal to or less than the second maximum allowable value;
A semiconductor device layout method using a computer-aided design system.   2. The semiconductor device layout method according to claim 1, wherein the extended wiring pattern is connected to at least one of the two wiring patterns adjacent in the second direction.   3. The semiconductor device layout method according to claim 2, wherein the extended wiring pattern is connected to each of the two wiring patterns adjacent to each other in the second direction. The extended wiring pattern is
When the edge lengths along the first direction of the two wiring patterns adjacent to each other in the second direction are equal to each other, they are connected to both of the second wiring patterns,
When the edge lengths along the first direction of the two wiring patterns adjacent in the second direction are different from each other, they are connected to one of the wiring patterns adjacent in the second direction.
A layout method of a semiconductor device by a computer-aided design system according to claim 2.   The extended wiring pattern is connected to the shorter one of the edge lengths along the first direction of the two wiring patterns adjacent to each other in the second direction. A layout method of a semiconductor device by the computer-aided design system according to claim 4.   When the length of the extended wiring pattern is equal to or less than a preset threshold value and a recessed area is formed around the extended wiring pattern by providing the extended wiring pattern, a shape correction pattern for filling the recessed area is provided. A semiconductor device layout method using a computer-aided design system according to claim 1.   The misalignment correction pattern is provided so that an edge in the first direction coincides with an edge on a far side when a wiring pattern laid in the first direction is extended in the second direction. A layout method of a semiconductor device by the computer-aided design system according to claim 1. After generating the wiring layout and before detecting the first nonconforming portion, detecting a third nonconforming portion where a distance between wiring patterns adjacent in the first direction is greater than the first maximum allowable value,
8. The dummy fill metal pattern independent from the plurality of wiring patterns is provided when the third nonconforming portion satisfies a preset minimum area criterion. 9. Layout method of semiconductor device by computer-aided design system. The first wiring layer includes a first wiring and a second wiring,
Each of the first wiring and the second wiring includes at least one contact region connected to a via,
2. A semiconductor device according to claim 1, wherein a distance from an end portion of the first wiring to the nearest contact region is different from a distance from the end portion of the second wiring to the nearest contact region.   The said 1st wiring and the said 2nd wiring are provided along the 2nd direction orthogonal to the said 1st direction so that the routing pitch conditions preset regarding the 1st direction may be satisfy | filled. 9. The semiconductor device according to 9.   In the first wiring layer, the distance between the first wiring and another wiring adjacent in the second direction is different from the distance between the second wiring and another wiring adjacent in the second direction. The semiconductor device according to claim 9, wherein the semiconductor devices are equal to each other.

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