JP2014230058A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve lower cost and lower power consumption.SOLUTION: A differential output circuit (10, 10A to 10E) includes a first transistor (MN1) which is provided between a second node (ND2) to which sink current flows out and a first node (ND1) and to which one differential input signal is supplied, and a second transistor (MN2) which is provided between a third node (ND3) and the second node and to which the other differential input signal is supplied. The differential output circuit also includes a third transistor (MP1) which is provided between a fourth node (ND4) into which source current flows and the first node and in which an input electrode is connected to the third node, and a fourth transistor (MP2) which is provided between the third node and the fourth node, and in which the input electrode is connected to the first node. The differential output circuit further includes a first voltage generating circuit (103) which generates voltage between the first node and a first output terminal according to input current, and a second voltage generating circuit (104) which generates voltage between the third node and a second output terminal according to input current.

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device including a differential output circuit that outputs a differential signal.

  Electronic devices such as home appliances and portable terminals are equipped with a plurality of semiconductor devices (IC chips), and various functions (characteristics) specific to electronic circuits are realized by exchanging various signals (data) between the semiconductor devices. The Many semiconductor devices include an interface circuit for transmitting or receiving a signal (data), and communicate with the outside through the interface circuit.

  In recent years, the communication speed in communication between semiconductor devices has been increased. As a high-speed digital interface for performing high-speed communication, small signal output such as LVDS (Low Voltage Differential Signaling), MIPI (Mobile Industry Processor Interface), and RSDS (Reduced Swing Differential Signaling) are known. Among them, LVDS is widely used for an interface between a liquid crystal display and a control IC, an interface between an LDD (Laser Diode Driver) control IC and a digital signal processing IC in an optical disk device, and the like.

  The small signal differential output type interface circuit receives a signal (data) from an internal core circuit (a data processing circuit such as a CPU) for realizing a specific function of the semiconductor device, and outputs the signal to an external terminal. In many cases, the signal level of the signal output from the internal core circuit operating at a low power supply voltage is less than the signal level of the signal to be output from the interface circuit. A differential signal is generated based on the received signal. For example, in many interface circuits that support LVDS, a signal output from an internal core circuit that operates at a core power supply voltage (for example, 1.2 V) is level-shifted to a power supply voltage level (for example, 3.3 V). A differential signal (for example, 1.05 V to 1.4 V) is generated based on the received signal. Therefore, as a circuit block constituting the interface circuit, a level shift circuit that level-shifts an input signal, a differential output circuit that generates a differential signal based on the level-shifted signal, and a common voltage of the differential signal And a common feedback circuit (CMFB: Common Mode Feedback) for controlling.

  For example, Patent Document 1 discloses a conventional level shift circuit, and Patent Documents 2 and 3 disclose conventional techniques for a differential output circuit. Patent Document 4 discloses a differential output circuit having a level shift function.

JP-A-4-268818 Special table 2012-510208 gazette JP 2007-329550 A US Patent Application Publication No. 2009/0167369 A1

  2. Description of the Related Art In recent years, there has been a demand for lower cost and lower power consumption of semiconductor devices mounted on the market in response to demands for lower prices and lower power consumption of electronic devices in the market. In order to realize low cost and low power consumption of semiconductor devices, it is important to reduce not only the core part of the signal processing circuit and memory circuit in the semiconductor device, but also the above-mentioned interface circuit in a small scale and low power consumption. It is.

  The inventor of the present application generates a differential signal from two output terminals of a level shift circuit as shown in the cited reference 1 in order to realize a reduction in size and a reduction in power consumption of a small signal differential output type interface circuit. We examined the configuration to do. However, according to the study of the present inventor, in the case of a small signal differential output system such as LVDS, the amplitude of the differential signal output from the level shift circuit as the differential output circuit is determined by the power supply / ground of the level shift circuit. Since the voltage is lower than the inter-voltage, there is a problem that the transistor on the power supply side of the level shift circuit cannot be completely turned off and a desired differential signal cannot be obtained.

  Further, according to the study of the present inventor, even if a differential output circuit such as that disclosed in Patent Document 4 is adopted as a small signal differential output type interface circuit, for example, the circuit can be reduced in size and consumption can be reduced. It cannot be said that a sufficient effect can be expected for electric power generation. In the configuration of Patent Document 4, a low breakdown voltage N-channel transistor is used as an input stage transistor that receives an input signal having a low signal level in order to realize high-speed operation of the circuit. A circuit is required to protect against damage. Specifically, as shown in FIG. 2 (FIG. 2) of the same document, a protective transistor connected in series to the drain side of the transistor in the input stage to reduce the voltage applied to the transistor, In addition to a current source circuit for supplying a bias current to the protection transistor, a circuit for supplying a bias voltage to the protection transistor is required. For this reason, even if the level shift circuit is reduced by the differential output circuit of Patent Document 4, reduction of the circuit scale and power consumption of the interface circuit as a whole is limited.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  An outline of representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, the semiconductor device includes a differential output circuit for generating a differential signal according to a voltage difference between two input signals, and a common feedback circuit. The differential output circuit is provided between the first node and the second node from which the sink current adjusted according to the control from the common feedback circuit flows, and one of the two input signals is applied to the input electrode. An N-channel first transistor to be supplied; and an N-channel second transistor provided between the third node and the second node, to which the other of the two input signals is supplied to the input electrode. Including. The differential output circuit is further provided between the fourth node and the first node into which the source current adjusted according to the control from the common feedback circuit flows, and the input electrode is connected to the third node. A channel-type third transistor; and a P-channel type fourth transistor provided between the third node and the fourth node and having an input electrode connected to the first node. The differential output circuit is further connected between the first node and the first output terminal, generates a voltage at both ends based on the supplied current, a third node, and a second output terminal. And a second voltage generation circuit that generates a voltage at both ends based on the supplied current.

  The effects obtained by the representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, according to this semiconductor device, cost reduction and power consumption can be reduced.

FIG. 1 is a diagram illustrating a semiconductor device including a differential output circuit according to an embodiment of the present application. FIG. 2 is a diagram illustrating a semiconductor device including an interface circuit including the differential output circuit according to the first embodiment. FIG. 3 is a diagram illustrating an internal configuration of the voltage control unit 11. FIG. 4 is a diagram illustrating the internal configuration of the differential output circuit 10 and the common feedback circuit 13. FIG. 5 is a diagram illustrating a current path in the differential output circuit when a high level voltage is output from the output terminal OUTP1 and a low level voltage is output from the output terminal OUTN1. FIG. 6 is a diagram illustrating a current path in the differential output circuit when a low level voltage is output from the output terminal OUTP1 and a high level voltage is output from the output terminal OUTN1. FIG. 7 is a diagram illustrating a differential output circuit according to the second embodiment. FIG. 8 is a diagram illustrating a differential output circuit according to the third embodiment. FIG. 9 is a diagram illustrating another differential output circuit according to the third embodiment. FIG. 10 is a diagram illustrating a differential output circuit according to the fourth embodiment. FIG. 11 is a diagram illustrating another differential output circuit according to the fourth embodiment. FIG. 12 is a diagram illustrating a differential output circuit according to the fifth embodiment. FIG. 13 is a diagram illustrating another differential output circuit according to the fifth embodiment. FIG. 14 is a diagram illustrating a differential output circuit according to the sixth embodiment. FIG. 15 is a diagram illustrating another differential output circuit according to the sixth embodiment. FIG. 16 is a diagram illustrating a system example to which an interface circuit including a differential output circuit according to the third embodiment is applied.

1. First, an outline of a typical embodiment disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] (A differential output circuit in which a resistor is connected between the output terminal and the output node of the level shift circuit)
As shown in FIG. 1, the semiconductor device (100) according to the representative embodiment of the present application generates a differential signal (VP, VN) according to a voltage difference between two input signals (INP, INN). A differential output circuit (10) for outputting the differential signal, and a first output terminal (OUTP) and a second output terminal (OUTN) for outputting the differential signal to the outside. The semiconductor device further controls the differential output circuit so that a common voltage (VCM) of a differential signal output from the first output terminal and the second output terminal matches a reference value (VREF). It has a common feedback circuit. The differential output circuit is provided between a first node (ND1) and a second node (ND2), and an N-channel first transistor (MN1) in which one of the two input signals is supplied to an input electrode. And an N-channel second transistor (MN2) provided between the third node (ND3) and the second node, and supplied with the other of the two input signals to the input electrode. The differential output circuit is further provided between the first node and the fourth node (ND4), and a P-channel third transistor (MP1) having an input electrode connected to the third node; A P-channel fourth transistor (MP2) provided between a third node and the fourth node and having an input electrode connected to the first node. The differential output circuit is further provided between the second node and a ground node (GND) to which a ground voltage is supplied, and a sink current (a current amount is adjusted according to control from the common feedback circuit). (102) includes a sink current source circuit for draining (ISN) from the second node to the ground node. The differential output circuit is further provided between the fourth node and a power supply node (VDD) to which a power supply voltage is supplied, and a source current (current amount is adjusted according to control from the common feedback circuit). A source current source circuit (101) for causing ISP to flow from the power supply node to the fourth node. The differential output circuit is further connected between the first node and the first output terminal, and generates a voltage at both ends based on the supplied current, and the first output circuit (103). A second voltage generation circuit (104) connected between the three nodes and the second output terminal and generating a voltage at both ends based on the supplied current;

  According to this, even when the differential signal having an amplitude smaller than the voltage between the power source and the ground of the differential output circuit is output from the first output terminal and the second output terminal, the third transistor and the fourth transistor. Can be controlled so as to be reliably turned on and off. For example, when outputting a differential signal in which the voltage of the first output terminal is high level and the voltage of the second output terminal is low level, the first node supplied to the input electrode of the fourth transistor by the first voltage generation circuit Can be made higher than the voltage at the first output terminal. This makes it easier for the fourth transistor to turn off than when the input electrode of the fourth transistor is directly controlled by the voltage at the first output terminal. For example, the fourth transistor can be reliably turned off by setting the voltage of the first voltage generation circuit so that the voltage of the first node does not exceed the threshold value of the fourth transistor. On the other hand, when outputting a differential signal in which the voltage at the first output terminal is low level and the voltage at the second output terminal is high level, the second voltage generation circuit supplies the third signal supplied to the input electrode of the third transistor. The voltage of the node can be made higher than the voltage of the second output terminal. This makes it easier for the third transistor to turn off than when the input electrode of the third transistor is directly controlled by the voltage of the second output terminal. For example, the third transistor can be reliably turned off by setting the voltage of the second voltage generation circuit so that the voltage of the third node does not exceed the threshold of the third transistor.

  Thus, a differential output circuit capable of generating a differential signal having an amplitude larger than that of the input signal can be realized without providing a level shift circuit separately as in the prior art. Furthermore, since a high-breakdown-voltage transistor can be adopted as the first and second transistors of the differential input stage, a circuit for protecting the differential input stage transistor from overvoltage as shown in Patent Document 4 is provided. It becomes unnecessary, the circuit scale can be reduced, and the current consumption can be reduced. Therefore, according to the present semiconductor device, the chip area of the semiconductor device can be reduced as compared with the prior art, and the current consumption of the semiconductor device can be reduced.

[2] (Voltage generation circuit: resistance)
In the semiconductor device according to item 1, the first voltage generation circuit includes a first resistor (R1, R1X) connected between the first node and the first output terminal, and the second voltage generation circuit includes: , Second resistors (R2, R2X) connected between the third node and the second output terminal.

  According to this, the magnitude of the voltage (voltage generated between the third node and the second output terminal) generated between the first node and the first output terminal is set to the first resistance (second resistance). ) And the current value flowing through it. Thereby, the generated voltage can be set easily and accurately.

[3] (Variable resistance)
In the semiconductor device according to Item 2, resistance values of the first resistor (R1X) and the second resistor (R2X) can be adjusted.

  According to this, it becomes easy to adjust the magnitude of the voltage to be generated according to the process variation of the semiconductor device, the temperature fluctuation, and the like.

[4] (Voltage generation circuit: transistor)
In the semiconductor device according to item 1, the first voltage generation circuit is connected between the first node and the first output terminal so that a voltage generated at both ends of the supplied current has linearity. Includes a fifth transistor (MN3, MP3) biased at the same time. The second voltage generation circuit is connected between the third node and the second output terminal, and is a sixth transistor biased so that a voltage generated at both ends has a linearity with respect to a supplied current. (MN4, MP4).

  According to this, it becomes easy to generate a voltage between the first node and the first output terminal (between the third node and the second output terminal). Further, the magnitude of the voltage to be generated can be determined by the value of the current flowing through the fifth transistor (sixth transistor).

[5] (Generate bias voltage of voltage generating transistor based on common voltage)
In the semiconductor device according to Item 4, the common voltage is supplied to input electrodes of the fifth transistor and the sixth transistor.

  According to this, it becomes easy to bias the fifth and sixth transistors so that the voltage generated at both ends has a linearity with respect to the supplied current.

[6] (Common voltage is generated by a resistor circuit)
The semiconductor device according to Item 5 further includes a third resistor (RP1 to RPn) and a fourth resistor (RN1 to RNn) connected in series between the first output terminal and the second output terminal. The fifth transistor and the sixth transistor are supplied with voltages of nodes (VCM, VCM_1 to VCM_n) to which the third resistor and the fourth resistor are connected in common to their input electrodes. In the common feedback circuit, a voltage at a node to which the third resistor and the fourth resistor are connected in common is set as the common voltage.

  According to this, the common voltage can be easily generated. Further, it is not necessary to separately prepare a circuit for generating the bias voltages of the fifth and sixth transistors, and an increase in chip area can be suppressed.

[7] (Voltage generating transistor: NMOS)
In the semiconductor device according to any one of Items 4 to 6, the fifth transistor and the sixth transistor are N-channel MOS transistors.

[8] (Voltage generating transistor: PMOS)
In the semiconductor device according to any one of Items 4 to 6, the fifth transistor and the sixth transistor are P-channel MOS transistors.

[9] (Differential input stage with inverter configuration)
The semiconductor device according to any one of Items 1 to 8, wherein the semiconductor device is connected in series between the first node and the third transistor, and is supplied with one of the two input signals to an input electrode. A transistor (MP5), a P-channel eighth transistor (MP6) connected in series between the third node and the fourth transistor, and having the other of the two input signals supplied to an input electrode; It has further.

  According to this, since the through current flowing through the third transistor and the first transistor and the through current flowing through the fourth transistor and the second transistor can be reduced, the first node and the third node can be reduced. Can be stabilized more quickly, and the response speed of the differential output circuit can be increased.

[10] (Semiconductor device having an output interface including a differential output circuit in which a resistor is connected between the output terminal and the output node of the level shift circuit)
A semiconductor device (100) according to a representative embodiment of the present application includes an internal circuit (2), a first output terminal (OUTP1 to OUTPn) and a second output terminal (OUTN1) for outputting a differential signal to the outside. ˜OUTNn) as a set and a plurality of differential output terminal pairs. The semiconductor device further generates differential signals (VP1, VN1 to VPn, VNn) corresponding to the plurality of digital signals (SGNL1 to SGNLn) supplied from the internal circuit, and supplies the differential signals to the corresponding differential output terminal pairs. It has an interface circuit (1) for outputting. The interface circuit is provided corresponding to each digital signal supplied from the internal circuit, generates a differential signal according to a voltage difference between two input signals generated according to the input digital signal, A plurality of differential output circuits (10_1 to 10_n) for outputting to the corresponding differential output terminal pairs. The interface circuit further includes a common feedback circuit (13_1 to 13_n) that controls the differential output circuit so that a common voltage of a differential signal output from each of the differential output terminal pairs matches a reference value. And having. The differential output circuit is provided between a first node (ND1) and a second node (ND2), and an N-channel first transistor (MN1) in which one of the two input signals is supplied to an input electrode. And an N-channel second transistor (MN2) provided between the third node (ND3) and the second node, and supplied with the other of the two input signals to the input electrode. The differential output circuit is further provided between the first node and the fourth node (ND4), and a P-channel third transistor (MP3) having an input electrode connected to the third node; A P-channel fourth transistor (MP4) provided between the second node and the fourth node and having an input electrode connected to the first node. The differential output circuit is further provided between the second node and a ground node (GND) to which a ground voltage is supplied, and a sink current whose current amount is adjusted according to control from the common feedback circuit A sink current source circuit (102) for flowing (ISN) from the second node to the ground node; The differential output circuit is provided between the fourth node and a power supply node (VDD) to which a power supply voltage is supplied, and a source current (ISP) whose amount of current is adjusted according to control from the common feedback circuit. ) From the power supply node to the fourth node. The differential output circuit is further connected between the first node and the first output terminal, and generates a voltage at both ends based on the supplied current; and A second voltage generation circuit (104) connected between a third node and the second output terminal and generating a voltage at both ends based on the supplied current;

  According to this, as in item 1, the circuit scale of the interface circuit can be reduced compared to the conventional case, and the current consumption of the interface circuit can be reduced. As a result, the semiconductor device can be reduced in size and power consumption can be reduced.

[11] (Differential input stage 2 of inverter configuration)
In the semiconductor device of Item 10, a P-channel transistor (MP5) connected in series between the first node and the third transistor, and supplied with one of the two input signals to an input electrode, A P-channel transistor (MP6) connected in series between the third node and the fourth transistor and having the other of the two input signals supplied to the input electrode;

  According to this, similarly to the item 9, the response speed of the differential output circuit can be increased.

[12] (Voltage generation circuit: resistor 2)
In the semiconductor device according to Item 10 or 11, the first voltage generation circuit includes a first resistor (R1, R1X) connected between the first node and the first output terminal, and the second voltage generation circuit The circuit includes a second resistor (R2, R2X) connected between the third node and the second output terminal.

  According to this, the magnitude of the voltage (voltage generated between the third node and the second output terminal) generated between the first node and the first output terminal is set to the first resistance (second resistance). ) And the current value flowing through it. Thereby, the generated voltage can be set easily and accurately.

[13] (Voltage generation circuit: transistor 2)
In the semiconductor device according to Item 10 or 11, the first voltage generation circuit is connected between the first node and the first output terminal, and the voltage generated at both ends with respect to the supplied current has linearity. A fifth transistor (MN3, MP3) biased to have is included. The second voltage generation circuit is connected between the third node and the second output terminal, and is a sixth transistor biased so that a voltage generated at both ends has a linearity with respect to a supplied current. (MN4, MP4).

  According to this, it becomes easy to generate a voltage between the first node and the first output terminal (between the third node and the second output terminal). The magnitude of the voltage to be generated can be determined by the value of the current flowing through the fifth transistor (sixth transistor).

2. Details of Embodiments Embodiments will be further described in detail.

<< Embodiment 1 >>
FIG. 2 is a diagram illustrating a semiconductor device including an interface circuit including the differential output circuit according to the first embodiment.

  The electronic circuit 200 shown in the figure includes, for example, a plurality of semiconductor devices (IC chips) mounted on a wiring board and various electronic components, and these components exchange various signals with each other. One system for realizing a desired function is configured. In the drawing, two semiconductor devices 100 and 110 are shown as some components constituting the electronic circuit 200.

  The semiconductor device 100 and the semiconductor device 110 are connected through, for example, a wiring pattern formed on a wiring board, and high-speed data communication is enabled. For example, data generated by signal processing of the semiconductor device 100 is output to a wiring pattern on the wiring board, and the semiconductor device 110 receives the data via the wiring pattern. The semiconductor device 110 performs various signal processing based on the received data. Communication from the semiconductor device 100 to the semiconductor device 110 is realized by a small signal differential output method. Although not particularly limited, the semiconductor device 100 and the semiconductor device 101 can communicate with each other by LVDS.

  The semiconductor device 100 shown in the figure is not particularly limited, but is formed on a single semiconductor substrate (semiconductor chip) such as single crystal silicon by a known CMOS (Complementary Metal Oxide Semiconductor) integrated circuit manufacturing technique. The semiconductor device 100 includes an internal circuit 2, a plurality of differential output terminal pairs each including two output terminals for outputting differential signals to the outside, and a plurality of digital signals supplied from the internal circuit 2. And an interface circuit 1 that outputs a corresponding differential signal to a corresponding differential output terminal pair. In the figure, typically, output terminals OUTP1 to OUTPn (n is an integer of 2 or more) and output terminals OUTN1 to OUTNn are shown as external terminals included in the semiconductor device 100, but external terminals other than these are shown. A terminal may be provided.

  The internal circuit 2 performs signal processing for realizing functions unique to the semiconductor device 100. The internal circuit 2 includes, for example, a program processing device in which a CPU executes processing according to a program stored in a memory, a digital signal processing circuit configured by dedicated hardware logic, and the like. A part of the data generated by the signal processing by the internal circuit 2 is supplied to the interface circuit 1 as digital signals SGNL <b> 1 to SGNLn and is output to the semiconductor device 110 via the interface circuit 1.

  The interface circuit 1 includes a plurality of differential output circuits (DFSO) 10_1 to 10_n, a voltage controller (VCM_CNT) 11, and a plurality of logic circuits (INV) 14_1 to 14_n.

  The logic circuits 14_1 to 14_n are provided corresponding to the respective digital signals SGNL1 to SGNLn, and two differential input signals (inverted from each other) from the single-ended digital signals SGNL1 to SGNLn supplied from the internal circuit 2. Digital signal). The logic circuit 14_1 includes, for example, an inverter circuit, and generates a signal INP1 having the same phase as the digital signal SGNL1 and a signal INN1 having the opposite phase. The logic circuits 14_2 to 14_n are similar, and generate differential input signals INP2, INN2 to INPn and INNn, respectively. Although not particularly limited, for example, the digital signals SGNL1 to SGNLn have a high level of 1.2V and a low level of 0V, and the differential input signals INP1, INN1 to INPn and INNn have a high level of 1.2V, Low level is 0V. In the figure, the case where the logic circuits 14_1 to 14_n are provided in the interface circuit 1 is illustrated. However, if the differential signals are input to the differential output circuits 10_1 to 10_n, the above configuration is used. It is not limited. For example, the internal circuit 2 may output a differential signal instead of a single end signal, and supply the differential signal to each of the differential output circuits 10_1 to 10_n. In this case, the logic circuits 14_1 to 14_n may be deleted.

  The differential output circuits 10_1 to 10_n (generally referred to as the differential output circuit 10) are fully differential output circuits, and are provided for each differential input signal supplied from the logic circuits 14_1 to 14_n. Correspondingly provided. For example, the differential output circuit 10_1 operates by supplying power from a power supply voltage VDD (for example, 3.3V) and a ground voltage (0V), and corresponds to the potential difference between the input signal INP1 and the input signal INN1 supplied from the logic circuit 14_1. Differential signals VP1 and VN1 are generated. The differential signal VP1 is output to the output terminal OUTP1, and the differential signal VN1 is output to the output terminal OUTN1. The output terminals OUTP1 and OUTN1 are electrically connected to the input interface circuit 10X_1 of the semiconductor device 110. The input interface circuit 10X_1 includes, for example, a positive input terminal IXP1 connected to the output terminal OUTP1, a negative input terminal IXN1 connected to the output terminal OUTN1, and a positive input terminal IXP1 and a negative input terminal INX1. And a load resistor Ro_1 connected to. The input interface circuit 10X_1 outputs a signal corresponding to the potential difference generated at both ends of the load resistor Ro_1 to the internal circuit 111 at the subsequent stage. Although not particularly limited, as specific numerical examples, the output high level voltage of the differential signals VP1 and VN1 is 1.4V, the output low level voltage is 1.05V, and the common voltage of the differential signals VP1 and VN1 is 1. It is 225V (amplitude 0.35V), and the resistance Ro_1 is 100Ω.

  Note that the differential output circuits 10_2 to 10_n are connected to the input interface circuits 10X_2 to 10X_n of the semiconductor device 110, respectively, similarly to the differential output circuit 10_1. The circuit configuration of the differential output circuits 10_2 to 10_n is similar to that of the differential output circuit 10_1, and the circuit configuration of the input interface circuits 10X_2 to 10X_n is similar to that of the input interface circuit 10X_1.

  The voltage control unit 11 controls the signal levels of the differential signals VP1, VN1 to VPn, and VNn output from the respective differential output circuits 10_1 to 10_n.

  FIG. 3 illustrates an internal configuration of the voltage control unit 11.

  As shown in the figure, the voltage control unit 11 includes a resistor circuit 12_1 to 12_n (generally referred to as a resistor circuit 12) and a common feedback circuit 13_1 to 13_n (generally referred to as a common feedback circuit 13). Notation.) The resistance circuits 12_1 to 12_n generate a common voltage for differential signals. For example, the resistance circuit 12_1 includes resistors RP1 and RN1 connected in series between the output terminal OUTP1 and the output terminal OUTN1. The resistors RP1 and RN1 have the same resistance value, for example, and the voltage of the node VCM_1 to which the resistor RP1 and the resistor RN1 are connected is output as the common voltage of the differential signals VP1 and VN1. The same applies to the resistor circuits 12_2 to 12_n.

  The common feedback circuit 13 controls the differential output circuit so that the common voltage of the differential signal output from the differential output terminal pair matches the reference value. For example, the common feedback circuit 13_1 generates the control voltages VGP_1 and VGN_1 so that the voltage of the node VCM_1 in the resistor circuit 12_1 matches the reference voltage VREF, thereby causing the differential signal VP1 output from the differential output circuit 10_1. , Control the signal level of VN1.

  FIG. 4 is a diagram illustrating the internal configuration of the differential output circuit 10 and the common feedback circuit 13. In the figure, only the common feedback circuit 13_1 and the differential output circuit 10_1 and their peripheral circuit blocks and output terminals are typically shown, and other functional units are not shown. Note that since the differential output circuits 10_1 to 10_n have the same circuit configuration, the differential output circuit 10_1 is typically described, and detailed descriptions of the other differential output circuits 10_2 to 10_n are omitted. Reference sign VDD represents not only the power supply voltage but also a node to which the power supply voltage is supplied, and reference sign GND represents not only the ground voltage but also a node to which the ground voltage is supplied. .

  As shown in the figure, the common feedback circuit 13_1 forms a differential pair with the constant current source I1 that outputs a constant current, the transistor MP8 to which the voltage VCM_1 is supplied to the input electrode, and the transistor MP8. And a transistor MP7 to which a reference voltage VREF is supplied. For example, the transistors MP7 and MP8 are P-channel MOS transistors. The output terminal of the constant current source I1 is commonly connected to the source electrodes of the transistors MP7 and MP8. Further, the common feedback circuit 13_1 includes a transistor MN6 connected in series with the transistor MP8 and a transistor MN5 connected in series with the transistor MP7. For example, the transistors MN5 and MN6 are N-channel MOS transistors. The source electrodes of the transistors MN5 and MN6 are connected to a ground node GND to which a ground voltage is supplied. The gate electrode and the drain electrode of the transistor MN5 are commonly connected to the drain electrode of the transistor MP7. The gate electrode and the drain electrode of the transistor MN6 are commonly connected to the drain electrode of the transistor MP8. Although details will be described later, the transistor MN6 forms a current mirror circuit together with the transistor MNTL that forms the sink current source circuit 102 in the differential output circuit 10_1. The gate voltage of the transistor MN6 becomes the control voltage VGN_1.

  The common feedback circuit 13_1 further includes transistors MN7 and MP9 constituting a current mirror folding circuit. For example, the transistor MN7 is an N channel type MOS transistor, and the transistor MP9 is a P channel type MOS transistor. The transistor MN7 forms a current mirror circuit by sharing the gate-source voltage with the transistor MN5. Transistor MP9 has its drain electrode and gate electrode commonly connected to the drain electrode of transistor MN7, and its source electrode connected to power supply node VDD. Although details will be described later, the transistor MP9 forms a current mirror circuit together with the transistor MPTL that forms the source current source circuit 101 in the differential output circuit 10_1. The gate voltage of the transistor MP9 becomes the control voltage VGP_1.

  By configuring the common feedback circuit 13_1 as described above, the control voltages VGP_1 and VGN_1 are generated so that the voltage of the node VCM_1 in the resistor circuit 12_1 matches the reference voltage VREF.

  As shown in FIG. 4, the differential output circuit 10_1 includes a differential circuit including transistors MN1, MN2, MP1, and MP2, a source current source circuit 101, a sink current source circuit 102, and voltage generation circuits 103 and 104. It is comprised including. Although not particularly limited, the transistors MN1, MN2, MP1, and MP2 are MOS transistors (eg, 3.3V withstand voltage) having a higher withstand voltage than the MOS transistors (eg, 1.2V withstand voltage) constituting the internal circuit 2.

  Specifically, the transistor MN1 is provided between the node ND1 and the node ND2, and the input signal INN1 is supplied to the input electrode. The transistor MN2 is provided between the node ND3 and the node ND2, and the input signal INP1 is supplied to the input electrode. The transistor MP1 is provided between the node ND1 and the node ND4, and the input electrode is connected to the node ND3. The transistor MP2 is provided between the node ND3 and the node ND4, and the input electrode is connected to the node ND1. For example, the transistors MN1 and MN2 are N-channel MOS transistors, and the transistors MP1 and MP2 are P-channel MOS transistors.

  The sink current source circuit 102 is provided between the node ND2 and the ground node GND, and causes the sink current ISN whose current amount is adjusted according to control from the common feedback circuit 13_1 to flow from the node ND2 to the ground node GND. The sink current source circuit 102 includes, for example, a transistor MNTL that is connected between the node ND2 and the ground node GND, and the control voltage VGN_1 is supplied to the input electrode. The transistor MNTL is, for example, an N channel type MOS transistor. As described above, the transistor MNTL forms a current mirror circuit together with the transistor MN6 of the common feedback circuit 13_1. That is, the current flowing through the transistor MNTL is adjusted by changing the control voltage VGN_1 according to the current flowing through the transistor MN6 in the common feedback circuit 13_1.

  The source current source circuit 101 is provided between the node ND4 and the power supply node VDD, and flows the source current ISP whose amount of current is adjusted according to control from the common feedback circuit 13_1 from the power supply node VDD to the node ND4. The source current source circuit 101 includes, for example, a transistor MPTL that is connected between the power supply node VDD and the node ND4 and is supplied with the control voltage VGP_1 at the input electrode. The transistor MPTL is, for example, a P channel type MOS transistor. As described above, the transistor MPTL forms a current mirror circuit together with the transistor MP9 of the common feedback circuit 13_1. That is, the current flowing through the transistor MPTL is adjusted by changing the control voltage VGP_1 according to the current flowing through the transistor MN5 in the common feedback circuit 13_1.

  The voltage generation circuit 103 is connected between the node ND1 and the output terminal OUTP1, and generates a voltage at both ends based on the supplied current. The voltage generating element 104 is connected between the node ND3 and the output terminal OUTN1, and generates a voltage at both ends based on the supplied current. For example, the voltage generation circuit 103 includes a resistor R1 connected between the node ND1 and the output terminal OUTP1, and the voltage generation circuit 104 includes a resistor R2 connected between the node ND3 and the output terminal OUTN1. It is comprised including. Thereby, the voltage generated by the voltage generation circuits 103 and 104 can be set easily and accurately.

  By configuring the differential output circuit 10_1 as described above, the differential signals VP1 and VN1 having a larger amplitude than the input signals INN1 and INP1 can be generated without separately providing a level shift circuit as in the prior art. it can. Hereinafter, this will be described in detail with reference to FIGS.

  5 and 6, the high level voltage of the input signals INP1 and INN1 is 1.2V, the low level voltage is 0V, and the high level voltages of the differential signals VP1 and VN1 are 1.4V and low level. Is set to 1.05V. Further, the load resistance Ro_1 is set to 100Ω, the current flowing from the differential output circuit 10_1 to the load resistance Ro_1 via the output terminals OUTP1 and OUTN1 is set to 3.5 mA, the power supply voltage VDD is set to 3.3V, and the ground voltage is set to 0V. . These numerical values are merely examples, and are not limited. The resistors RP1 and RN1 have sufficiently larger resistance values than the load resistor Ro_1, and the current flowing through the resistors RP1 and RP2 can be ignored.

  FIG. 5 is a diagram illustrating a current path in the differential output circuit when a high level voltage is output from the output terminal OUTP1 and a low level voltage is output from the output terminal OUTN1.

  As shown in the figure, when a low level (0V) signal INN1 is input to the input electrode INB and a high level (1.2V) signal INP1 is input to the input electrode INT, the transistor MN1 is turned off. The transistor MN2 is turned on. As a result, the transistor MP1 is turned on, and current flows from the transistor MPTL to the node ND1 via the transistor MP1, whereby the voltage of the node ND1 rises and the state of the transistor MP2 changes in the off direction. The current flowing into the node ND1 flows into the ground node GND via the resistor R1, the output terminal OUTP1, the load resistor Ro_1, the output terminal OUTN1, the resistor R2, the node ND3, the transistor MN2, and the transistor MNTL. As a result, a high level voltage VP1 is generated at the output terminal OUTP1, and a low level voltage VN1 is generated at the output terminal OUTN1. Specifically, the source current ISP and the sink current ISN are controlled by the common feedback circuit 13_1 so that the intermediate voltage (common voltage) of the differential signals (voltages VP1 and VN1) is 1.225V. Control is performed so that VP1 is at a high level (1.4V) and the voltage VN1 is at a low level (1.05V).

  At this time, a voltage is generated at both ends of the resistor R1 constituting the voltage generation circuit 103, so that the voltage of the node ND1 becomes higher than that of the output terminal OUTP1. As a result, the transistor MP2 can be easily turned off as compared with the configuration in which the transistor MP2 is driven by the voltage of the output terminal OUTP1 without providing the resistor R1. This will be specifically described below.

  For example, assume that a circuit configuration in which the node ND1 and the output terminal OUTP1 are short-circuited without providing the voltage generation circuit 103 is employed as the differential output circuit. In this case, the transistor MP2 is driven by the voltage VP1 of the output terminal OUTP1. However, since the voltage range of the voltage VP1 is set to 1.05V to 1.4V by the LVDS standard, the gate voltage of the transistor MP2 rises only to 1.4V at the maximum. On the other hand, the source voltage of the transistor MP2 rises to near the power supply voltage VDD (3.3 V). As a result, the transistor MP2 cannot be completely turned off, and a desired differential signal cannot be generated. On the other hand, according to the differential output circuit 10_1, the gate voltage of the transistor MP2 (the voltage of the node ND1) is higher than the voltage of the output terminal OUTP1 by the resistor R1, so that the transistor MP2 can be easily turned off. Here, if the resistance value of the resistor R1 is determined so that the gate-source voltage of the transistor MP2 is smaller than the threshold voltage, the transistor MP2 can be turned off. For example, when the transistor MP2 has a characteristic of being turned off when a gate voltage of 1.75 V or higher is applied, the resistance R1 is set to 100Ω, for example. As a result, a voltage drop of 0.35 V occurs due to the current (3.5 mA) flowing through the resistor R1, so that a voltage (1.75 V) higher than the voltage (1.4V) of the output terminal OUTP1 is applied to the transistor MP2. Applied to the gate electrode, the transistor MP2 can be turned off.

  FIG. 6 is a diagram illustrating a current path in the differential output circuit when a low level voltage is output from the output terminal OUTP1 and a high level voltage is output from the output terminal OUTN1.

  As shown in the figure, when a low level (0V) signal INP1 is input to the input electrode INT and a high level (1.2V) signal INN1 is input to the input electrode INB, the transistor MN2 is turned off. The transistor MN1 is turned on. As a result, the transistor MP2 is turned on, and current flows from the transistor MPTL to the node ND3 via the transistor MP2. As a result, the voltage of the node ND3 rises, and the state of the transistor MP1 changes in the off direction. The current that flows into the node ND3 flows into the ground node via the resistor R2, the output terminal OUTN1, the load resistor Ro_1, the output terminal OUTP1, the resistor R1, the node ND1, the transistor MN1, and the transistor MNTL. As a result, a high level (1.4V) voltage VN1 is generated at the output terminal OUTN1, and a low level (1.05V) voltage VP1 is generated at the output terminal OUTP1. Specifically, the source current ISP and the sink current ISN are controlled by the common feedback circuit 13_1 so that the intermediate voltage (common voltage) of the differential signals (voltages VP1 and VN1) is 1.225V. Control is performed so that VN1 is at a high level (1.4V) and voltage VP1 is at a low level (1.05V).

  At this time, a voltage is generated at both ends of the resistor R2 constituting the voltage generation circuit 104, so that the voltage of the node ND3 becomes higher than that of the output terminal OUTN1. Thus, as in the case of generating a differential signal in which the voltage VP1 is at a high level and the voltage VN1 is at a low level, the transistor MP1 is driven by the voltage at the output terminal OUTN1 without providing the resistor R2. This makes it easier to turn off the transistor MP1. Here, when the resistance value of the resistor R2 is determined so that the gate-source voltage of the transistor MP1 becomes smaller than the threshold voltage, the transistor MP1 can be turned off. For example, when the transistor MP1 has a characteristic of being turned off when a gate voltage of 1.75 V or higher is applied, the resistance R2 is set to 100Ω, for example. As a result, a voltage drop of 0.35 V occurs due to the current (3.5 mA) flowing through the resistor R2, so that a voltage (1.75 V) higher than the voltage (1.4V) of the output terminal OUTN1 is applied to the transistor MP1. Applied to the gate electrode, the transistor MP1 can be turned off.

  As described above, according to the differential output circuit 10, the difference in amplitude (for example, 1.05 V to 1.4 V) smaller than the voltage (for example, 0 to 3.3 V) between the power source and the ground of the differential output circuit 10. Even when the dynamic signal is output from the output terminal, the on / off control of the transistors MP1 and MP2 can be reliably performed. Thus, a differential output circuit capable of generating a differential signal having an amplitude larger than that of the input signal can be realized without providing a level shift circuit separately as in the prior art. Further, since a high-breakdown-voltage transistor can be employed as the differential input stage transistors MN1 and MN2, a circuit for protecting the differential input stage transistor from overvoltage as shown in Patent Document 4 is not required. The circuit scale can be reduced and the current consumption can be reduced. Therefore, according to the differential output circuit 10 according to the present embodiment, it is possible to reduce the chip area of the semiconductor device and reduce the current consumption of the semiconductor device as compared with the conventional case.

<< Embodiment 2 >>
FIG. 7 illustrates a differential output circuit according to the second embodiment.

  The differential output circuit 10A shown in the figure is different from the differential output circuit 10 according to the first embodiment in that variable resistors R1X and RX2 are used instead of the resistors R1 and R2 constituting the voltage generating circuits 103 and 104. Is different. In the figure, the same components as those of the differential output circuit 10 are denoted by the same reference numerals, and detailed description thereof is omitted.

  According to the differential output circuit 10A, it is easy to adjust the magnitude of the voltage generated by the voltage generation circuits 103 and 104 in accordance with the manufacturing variation of the semiconductor device 100, temperature fluctuation, and the like. As a result, the transistors MP1 and MP2 can be accurately controlled on and off regardless of manufacturing variations and temperature fluctuations.

<< Embodiment 3 >>
FIG. 8 illustrates a differential output circuit according to the third embodiment.

  The differential output circuit 10B shown in the figure is different from the differential output circuit 10 according to the first embodiment in having an input stage having an inverter configuration. In the figure, the same components as those of the differential output circuit 10 are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in the figure, the differential output circuit 10B includes a transistor MP5 connected in series between the transistor MN1 and the transistor MP1, and a transistor MP6 connected in series between the transistor MN2 and the transistor MP2. Also have. Specifically, the transistor MP5 is connected between the node ND5 and the node ND1 to which the drain electrode of the transistor MP1 is connected, and the input electrode is shared with the transistor MN1. The transistor MP6 is connected in series between the node ND6 and the node ND3 to which the drain electrode of the transistor MP2 is connected, and the input electrode is shared with the transistor MN2. The transistors MP5 and MP6 are, for example, P channel type MOS transistors.

  According to this, the through current flowing between the power source and the ground via the transistor MP1 and the transistor MN1 generated when the logic level of the signal supplied to the input electrodes INT and INB of the differential input stage is switched, and the transistor MP2 and A through current flowing between the power source and the ground via the transistor MP6 can be reduced. As a result, the potential of the node ND1 and the potential of the node ND3 are stabilized more quickly, so that the response speed of the differential output circuit can be increased.

  Further, as in the above-described second embodiment, variable resistors may be used as the voltage generation circuits 103 and 104 in the differential output circuit 10B_1. For example, as shown in FIG. 9, a variable resistor R1X is used as the voltage generation circuit 103, and a variable resistor R2X is used as the voltage generation circuit 104. According to this, similarly to the differential output circuit 10A according to the second embodiment, the magnitude of the voltage generated by the voltage generation circuits 103 and 104 is adjusted in accordance with the manufacturing variation of the semiconductor device 100, temperature fluctuation, and the like. It becomes easy.

  As described above, according to the differential output circuit 10B according to the third embodiment, similarly to the differential output circuit 10 according to the first embodiment, the chip area of the semiconductor device can be reduced and the current consumption of the semiconductor device can be reduced. Can be reduced. Furthermore, the response performance of the interface circuit 1 can be improved.

<< Embodiment 4 >>
FIG. 10 illustrates a differential output circuit according to the fourth embodiment.

  The differential output circuit 10C shown in the figure is different from the differential output circuit 10 according to the first embodiment in that a transistor is used instead of the resistors constituting the voltage generation circuits 103 and 104. In the figure, the same components as those of the differential output circuit 10 are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in the figure, the voltage generation circuit 103 includes a transistor MN3 connected between the node ND1 and the output terminal OUTP1. Similarly, the voltage generation circuit 104 includes a transistor MN4 connected between the node ND3 and the output terminal OUTN1. The transistors MN3 and MN4 are, for example, N channel type MOS transistors.

  The transistors MN3 and MN4 are biased so that the voltage generated at both ends is linear with respect to the supplied current. Specifically, the transistors MN3 and MN4 operate in a tripolar region (non-saturated region) having a linear characteristic in which a voltage is generated between the drain and the source in proportion to the current flowing between the drain and the source. A bias voltage VBIAS is supplied to the gate electrode.

  According to this, it becomes easy to generate a voltage between the node ND1 and the output terminal OUTP1, and to generate a voltage between the node ND3 and the output terminal OUTN1. The magnitude of the voltage to be generated can be determined by the current flowing through the transistors MN3 and MN4.

  The means for generating the bias voltage VBIAS is not particularly limited. For example, it may be generated based on a bandgap reference voltage, similarly to an internal reference voltage such as the reference voltage VREF, or may be supplied from the outside.

  Further, a P-channel MOS transistor can be used as a transistor constituting the voltage generation circuits 103 and 104. For example, as shown in FIG. 11, a transistor MP3 is used as the voltage generation circuit 103, and a transistor MP4 is used as the voltage generation circuit 104. Similarly to the transistors MN3 and MN4 described above, the bias voltage VBAIS is supplied to the transistors MP3 and MP4 so that the voltage generated between the source and the drain has linearity with respect to the current flowing through the transistors MP3 and MP4. This makes it easy to generate a voltage between the node ND1 and the output terminal OUTP1, and between the node ND3 and the output terminal OUTN1, similarly to the transistors MN3 and MN4. , And can be determined by the current flowing through the transistors MP3 and MP4.

  As described above, according to the differential output circuit 10C according to the fourth embodiment, the chip area of the semiconductor device can be reduced and the current consumption of the semiconductor device can be reduced as in the differential output circuit 10 according to the first embodiment. Can be reduced.

<< Embodiment 5 >>
FIG. 12 illustrates a differential output circuit according to the fifth embodiment.

  The differential output circuit 10D shown in the figure is different from the differential output circuit 10C according to the fourth embodiment in that it includes an input stage having an inverter configuration. In the figure, the same components as those of the differential output circuit 10C are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in the figure, the differential output circuit 10D is connected in series between the node ND1 and the transistor MP1 as in the differential output circuit 10B according to the third embodiment, and the input electrode is connected to the transistor MN1. A common transistor MP5 and a transistor MP6 connected in series between the node ND3 and the transistor MP2 and having an input electrode common to the transistor MN2 are provided.

  According to this, similarly to the differential output circuit 10B, the potential of the node ND1 and the potential of the node ND3 are stabilized more quickly, so that the response speed of the differential output circuit can be increased.

  Further, similarly to the differential output circuit 10C according to the fourth embodiment, a P-channel MOS transistor can be used as a transistor constituting the voltage generation circuits 103 and 104. For example, as shown in FIG. 13, a transistor MP3 is used as the voltage generation circuit 103, and a transistor MP4 is used as the voltage generation circuit 104. Thereby, the same effect as that of the N-channel transistors MN3 and MN4 can be expected.

  As described above, according to the differential output circuit 10D according to the fifth embodiment, similarly to the differential output circuit 10 according to the first embodiment, the chip area of the semiconductor device can be reduced, and the current consumption of the semiconductor device can be reduced. Can be reduced. Furthermore, the response performance of the interface circuit 1 can be improved.

<< Embodiment 6 >>
FIG. 14 illustrates a differential output circuit according to the sixth embodiment.

  The differential output circuit 10E shown in the figure is different from the differential output circuit 10C according to the fourth embodiment in that the bias voltages of the transistors MN3 and MN4 are obtained from the resistor circuit 12. In the figure, the same components as those of the differential output circuit 10C are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in the figure, the transistors MN3 and MN4 are supplied with the common voltages of the differential signals VP1 and VN1 as bias voltages. Specifically, the voltage of the node VCM_1 to which the resistors RP1 and RN1 in the resistor circuit 12_1 are connected in common is supplied to the gate electrodes of the transistors MN3 and MN4.

  This makes it easy to bias the transistors MN3 and MN4 so as to operate in the tripolar region. Further, it is not necessary to separately prepare a circuit for generating a bias voltage, and an increase in chip area can be suppressed.

  As shown in FIG. 15, when the voltage generation circuits 103 and 104 are configured by P-channel type transistors MP3 and MP4, resistors RP1 and RP2 are connected in common as bias voltages of the transistors MP3 and MP4. The voltage of the node VCM_1 can be supplied. Thereby, the same effect as in the case of the N-channel type transistors MN3 and MN4 can be expected.

  As described above, according to the differential output circuit 10E according to the sixth embodiment, the current consumption of the semiconductor device can be reduced as in the differential output circuit 10 according to the first embodiment. In addition, since it is not necessary to separately prepare a circuit for generating the bias voltage of the transistors constituting the voltage generation circuits 103 and 104, the chip area of the semiconductor device can be further reduced.

  Note that the input stage of the differential output circuit 10E may have an inverter configuration (a configuration in which MP5 and MP6 are inserted) similarly to the differential output circuit 10D. According to this, the response speed of the differential output circuit can be increased.

<< Embodiment 7 >>
FIG. 16 shows a system example to which an interface circuit including the differential output circuit of the present application is applied.

  In the figure, as an example of a system to which an interface circuit including a differential output circuit according to the present application is applied, an optical disc apparatus 120 capable of writing data to the optical disc 121 is illustrated. The optical disc 121 is not particularly limited, and is, for example, a BD (Blu-ray Disc; registered trademark; the same applies hereinafter), a DVD, or the like.

  The optical disc apparatus 120 includes a spindle motor 122 that rotationally drives a removable optical disc 121, an optical pickup 123, an LDD control IC (LDD_CNT) 110A, and a digital signal processing IC 100A.

  The spindle motor 122 rotates the optical disc 121 at a predetermined number of rotations by being controlled by a motor control signal supplied from a motor control circuit (not shown), for example. The optical pickup 123 irradiates the optical disc 121 with laser light under the control of the LDD control IC 110A, and generates an electrical signal based on the amount of reflected light.

  The digital signal processing IC 100A includes a data processing unit 2A and an interface circuit 1A. The data processing unit 2A performs various signal processes for writing data to the optical disc 121. The digital signal processing IC 100A and the LDD control IC 110A can communicate with each other by a small signal differential output system such as LVDS. For example, when writing data to the optical disc 121, data generated by signal processing of the data processing unit 2A is supplied to the LDD control IC 110A via the interface circuit 1A. In the figure, as the interface circuit 1A, an output interface portion for outputting data is shown, and an input interface portion for inputting data is not shown.

  As the output interface portion of the interface circuit 1A, the interface circuit 1 including any of the differential output circuits 10, 10A to 10E according to the first to sixth embodiments can be applied. In the figure, a case where the interface circuit 1 including the differential output circuits 10B_1 to 10B_n according to the third embodiment is applied is exemplarily illustrated. Although not shown, an interface circuit including any one of the differential output circuits 10, 10A to 10E can be applied as a data output side interface circuit in the LDD control IC 110A.

  Thus, by applying a small-scale and low power consumption interface circuit to the digital signal processing IC 100A and the LDD control IC 110A, it is possible to reduce the cost and power consumption of the entire system (the optical disk device 120). .

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the case where the differential output circuits 10 and 10A to 10E according to the first to sixth embodiments are applied to an interface circuit corresponding to LVDS is exemplified, but the voltage is lower than the voltage between the power supply and the ground of the differential output circuit. Any system that outputs a differential signal having an amplitude can be applied to another small-signal differential output system interface circuit. For example, in addition to MIPI and RSDS, the present invention can be applied to an interface circuit corresponding to miniLVDS (mini-low voltage differential signaling), PPDS (Point to Point Differential Signaling), and the like.

100, 110 Semiconductor device 200 Electronic circuit 1 Interface circuit 2, 111 Internal circuit 10X_1 to 10X_n Input interface circuit OUTP1, OUTN1 to OUTPn, OUTNn Output terminal (differential output terminal pair)
IXP1, IXN1 to IXPn, IXNn Input terminals Ro_1 to Ro_n Load resistance 10_1 to 10_n Differential output circuit SGNL1 to SGNLn Digital signal INP1, INN1 to INPn, INNNn Differential input signal 11 Voltage controller 12_1 to 12_n Resistance circuit 13_1 to 13_n Common Feedback circuit 14_1 to 14_n Logic circuit VP1, VN1 to VPn, VNn Differential signal RN1 to RNn, RP1 to RPn Resistor VCM, VCM_1 to VCM_n Node and common voltage VREF Reference voltage VGP_1 to VGP_n, VGN_1 to VGN_n, VGP voltage, VGN 101 source current source circuit 102 sink current source circuit 103, 104 voltage generation circuit R1, R2 resistance RX1, RX2 variable resistance ISP source current ISN thin Current MPTL, MNTL, MN1~MN7, MP1~MP9 transistor I1 constant current source VDD power supply voltage, the power supply node GND a ground voltage, a ground node 10A~10E differential output circuit VBIAS bias voltage 110A LDD control IC110A
100A Digital signal processing IC
10B_1 to 10B_n Differential output circuit 120 Optical disc device 121 Optical disc 122 Spindle motor 123 Optical pickup

Claims (13)

A differential output circuit for generating a differential signal according to a voltage difference between two input signals;
A first output terminal and a second output terminal for outputting the differential signal to the outside;
A common feedback circuit that controls the differential output circuit so that a common voltage of a differential signal output from the first output terminal and the second output terminal matches a reference value;
The differential output circuit is:
An N-channel first transistor provided between a first node and a second node and having one of the two input signals supplied to an input electrode;
An N-channel second transistor provided between a third node and the second node, the other of the two input signals being supplied to an input electrode;
A P-channel third transistor provided between the first node and the fourth node and having an input electrode connected to the third node;
A P-channel fourth transistor provided between the third node and the fourth node and having an input electrode connected to the first node;
A sink provided between the second node and a ground node to which a ground voltage is supplied, and sinks a sink current whose amount of current is adjusted according to control from the common feedback circuit from the second node to the ground node. A current source circuit;
A source current, which is provided between the fourth node and a power supply node to which a power supply voltage is supplied and whose current amount is adjusted according to control from the common feedback circuit, flows from the power supply node to the fourth node. A source current source circuit;
A first voltage generating circuit connected between the first node and the first output terminal and generating a voltage at both ends based on a supplied current;
A semiconductor device comprising: a second voltage generation circuit connected between the third node and the second output terminal and generating a voltage at both ends based on the supplied current. The first voltage generation circuit includes a first resistor connected between the first node and the first output terminal;
The semiconductor device according to claim 1, wherein the second voltage generation circuit includes a second resistor connected between the third node and the second output terminal.   The semiconductor device according to claim 2, wherein resistance values of the first resistor and the second resistor are adjustable. The first voltage generation circuit is connected between the first node and the first output terminal, and is a fifth transistor biased so that a voltage generated at both ends has a linearity with respect to a supplied current. Including
The second voltage generation circuit is connected between the third node and the second output terminal, and is a sixth transistor biased so that a voltage generated at both ends has a linearity with respect to a supplied current. The semiconductor device according to claim 1, comprising:   The semiconductor device according to claim 4, wherein the common voltage is supplied to input electrodes of the fifth transistor and the sixth transistor. A third resistor and a fourth resistor connected in series between the first output terminal and the second output terminal;
The fifth transistor and the sixth transistor are supplied with voltages of nodes at which the third resistor and the fourth resistor are connected in common to their input electrodes,
The semiconductor device according to claim 5, wherein the common feedback circuit uses a voltage at a node to which the third resistor and the fourth resistor are connected in common as the common voltage.   The semiconductor device according to claim 6, wherein the fifth transistor and the sixth transistor are N-channel MOS transistors.   The semiconductor device according to claim 6, wherein the fifth transistor and the sixth transistor are P-channel MOS transistors. A P-channel seventh transistor which is connected in series between the first node and the third transistor and is supplied with one of the two input signals to an input electrode;
3. The P-channel eighth transistor connected in series between the third node and the fourth transistor and having the other of the two input signals supplied to an input electrode. Semiconductor device. Internal circuitry,
A plurality of differential output terminal pairs each including a first output terminal and a second output terminal for outputting a differential signal to the outside;
An interface circuit that generates a differential signal corresponding to a plurality of digital signals supplied from the internal circuit and outputs the differential signal to the corresponding differential output terminal pair;
The interface circuit is
Provided corresponding to each digital signal supplied from the internal circuit, generates a differential signal according to a voltage difference between two input signals generated according to the input digital signal, and corresponding the differential A plurality of differential output circuits that output to the output terminal pair;
A common feedback circuit that controls the differential output circuit such that a common voltage of a differential signal output from each differential output terminal pair matches a reference value,
The differential output circuit is:
An N-channel first transistor provided between a first node and a second node and having one of the two input signals supplied to an input electrode;
An N-channel second transistor provided between a third node and the second node, the other of the two input signals being supplied to an input electrode;
A P-channel third transistor provided between the first node and the fourth node and having an input electrode connected to the third node;
A P-channel fourth transistor provided between the third node and the fourth node and having an input electrode connected to the first node;
A sink provided between the second node and a ground node to which a ground voltage is supplied, and sinks a sink current whose amount of current is adjusted according to control from the common feedback circuit from the second node to the ground node. A current source circuit;
A source current, which is provided between the fourth node and a power supply node to which a power supply voltage is supplied and whose current amount is adjusted according to control from the common feedback circuit, flows from the power supply node to the fourth node. A source current source circuit;
A first voltage generating circuit connected between the first node and the first output terminal and generating a voltage at both ends based on a supplied current;
A semiconductor device comprising: a second voltage generation circuit connected between the third node and the second output terminal and generating a voltage at both ends based on the supplied current. A P-channel transistor connected in series between the first node and the third transistor, and having one of the two input signals supplied to an input electrode;
11. The semiconductor device according to claim 10, further comprising a P-channel transistor connected in series between the third node and the fourth transistor and having the other of the two input signals supplied to an input electrode. . The first voltage generation circuit includes a first resistor connected between the first node and the first output terminal;
The semiconductor device according to claim 11, wherein the second voltage generation circuit includes a second resistor connected between the third node and the second output terminal. The first voltage generation circuit is connected between the first node and the first output terminal, and is a fifth transistor biased so that a voltage generated at both ends has a linearity with respect to a supplied current. Including
The second voltage generation circuit is connected between the third node and the second output terminal, and is a sixth transistor biased so that a voltage generated at both ends has a linearity with respect to a supplied current. The semiconductor device according to claim 11, comprising:

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