JP2014229333A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a short-circuit failure between adjacent word lines.SOLUTION: A semiconductor device includes: a plurality of memory cells MC arranged side by side in the X direction; a plurality of word lines SWL each of which is arranged side by side in the X direction so as to sandwich the plurality of memory cells and extends in the Y direction; and a row decoder 20 that controls the plurality of word lines SWL. When accessing a memory cell MC1, the row decoder 20 sets the potentials of word lines SWL1 and SWL2, which sandwich the memory cell MC1, from a non-selection level to a selection level; and when accessing a memory cell MC2 adjacent to the memory cell MC1, sets the potentials of word lines SWL2 and SWL3, which sandwich the memory cell MC2, from the non-selection level to the selection level. According to this invention, adjacent memory cells share a word line and thereby, a short-circuit failure of the word line can be prevented.

Description

  The present invention relates to a semiconductor device, and more particularly to a type of semiconductor device in which two adjacent memory cells share one word line.

  In recent years, in a semiconductor device such as a DRAM (Dynamic Random Access Memory), a transistor having a vertical structure is sometimes used for the purpose of reducing the chip area (see Patent Document 1). Unlike a general planar transistor, a transistor having a vertical structure has a channel region extending perpendicularly to the main surface of a silicon substrate, and the periphery of the channel region is covered with a gate electrode. doing. Therefore, since the source region, the drain region, and the gate electrode can be arranged on substantially the same plane on the silicon substrate, the occupied area can be reduced as compared with the planar type transistor.

JP 2009-152585 A

  However, when transistors having a vertical structure are arranged in high density in an array, it is difficult to insulate and isolate adjacent word lines, resulting in a short circuit failure. Such a problem is not limited to a semiconductor device using a transistor having a vertical structure, but commonly occurs in a semiconductor device in which insulation isolation between adjacent word lines is difficult.

  The semiconductor device according to the present invention includes a plurality of memory cells arranged side by side in a first direction and a plurality of memory cells arranged side by side in the first direction so as to sandwich the plurality of memory cells. A plurality of word lines extending in a second direction intersecting with the control circuit, and a control circuit for controlling the plurality of word lines, wherein the control circuit is a first memory cell of the plurality of memory cells. Of the plurality of word lines, the potentials of the first and second word lines sandwiching the first memory cell are changed from the non-selection level to the selection level, and the second adjacent to the first memory cell is accessed. When the memory cell is accessed, the potential of the second word line and the third word line sandwiching the second memory cell is changed from the unselected level to the selected level.

  According to the present invention, since adjacent memory cells share a word line, it is possible to prevent a short-circuit failure of the word line.

1 is a block diagram showing a configuration of a semiconductor device 10 according to a preferred embodiment of the present invention. 2 is a schematic diagram for explaining a basic configuration of a memory cell array 11. FIG. 2 is a schematic diagram for explaining a structure of a memory cell array 11 according to an example in which word lines and bit lines are hierarchized. FIG. It is a figure for demonstrating the address allocation of row address Radd. 2 is a circuit diagram for explaining a circuit configuration of a memory cell array 11. FIG. 6A and 6B are diagrams for explaining the device structure of the memory cell array 11 shown in FIG. 5, where FIG. 6A is a cross-sectional view taken along the X direction (extending direction of the local bit line LBL), and FIG. A cross-sectional view in the case of cutting in the extending direction of the sub word line SWL is shown. 3 is a block diagram showing a configuration of a main part of a row decoder 20. FIG. 3 is a circuit diagram of an FX generation circuit 51. FIG. It is a truth table of the FX generation circuit 51. 3 is a circuit diagram of a row predecoder 52. FIG. It is a truth table of the row predecoder 52. 3 is a circuit diagram showing a configuration of a main part of a main word driver 56. FIG. 1 is a schematic diagram for explaining a structure of a memory cell array 11 according to a first embodiment of the present invention. 1 is a schematic diagram for explaining a structure of a memory cell array 11 according to a first embodiment of the present invention. (A) is a circuit diagram of the sub word driver SWDA0, and (b) is a circuit diagram of the sub word driver SWDMAX. 3 is a circuit diagram showing a part of the memory cell array 11 in more detail. FIG. 4 is a timing chart for explaining the operation of the semiconductor device 10. FIG. FIG. 6 is a schematic diagram for explaining a structure of a memory cell array 11 according to a second embodiment of the present invention. It is a block diagram which shows the structure of the principal part of the row decoder 20a. 3 is a circuit diagram of an FX generation circuit 61. FIG. It is a truth table of the FX generation circuit 61. 6 is a circuit diagram of an additional FX control circuit 67. FIG. It is a truth table of the additional FX control circuit 67. (A) is a circuit diagram of the gate circuits G1 to G7, (b) is a circuit diagram of the gate circuit G0 (O), (c) is a circuit diagram of the gate circuit G0 (E), (d) Is a circuit of the gate circuit G512. FIG. 10 is a schematic diagram for explaining the structure of a memory cell array 11 according to a third embodiment of the present invention. It is a block diagram which shows the structure of the principal part of the row decoder 20b. 3 is a circuit diagram of an FX generation circuit 71. FIG. 3 is a circuit diagram of an FX driver 77. FIG. It is a truth table of the FX driver 77. FIG. 4 is a circuit diagram of a row predecoder 72, where (a) shows a circuit portion that generates predecode signals R3A0-3, and (b) shows a circuit portion that generates predecode signals R3B0-3. (A) is a circuit diagram of the gate circuits G0a, G1a, G2 to G7, (b) is a circuit diagram of the gate circuit G0, and (c) is a circuit of the gate circuit G1. FIG. 10 is a circuit diagram showing a part of a memory cell array 11 in more detail in the third embodiment. FIG. 10 is a timing diagram for explaining the operation of the semiconductor device 10 according to the third embodiment. It is a block diagram which shows the structure of the principal part of the semiconductor device by the 4th Embodiment of this invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing a configuration of a semiconductor device 10 according to a preferred embodiment of the present invention.

  The semiconductor device 10 according to the present embodiment is a ReRAM (Resistive RAM), and has an interface conforming to the NAND flash memory in order to ensure compatibility with the NAND flash memory. However, the application target of the present invention is not limited to ReRAM, and can be applied to other types of resistance change memory devices such as PCRAM (Phase Change RAM) and STTRAM (Spin Transfer Torque RAM). It is also possible to apply to a memory device other than the resistance change type memory device. In addition, it is not essential for the semiconductor device according to the present invention to employ the NAND flash memory interface.

  As shown in FIG. 1, the semiconductor device 10 according to the present embodiment includes a memory cell array 11. The memory cell array 11 may be divided into a plurality of banks. A bank is a unit capable of executing commands individually, and basically non-exclusive operations are possible between banks.

  As described above, since the semiconductor device 10 according to the present embodiment has the NAND flash memory interface, as shown in FIG. 1, the chip enable signal CEB, the command latch enable signal CLE, the address latch enable signal ALE, the write A command detector 12 to which an enable signal WEB, a read enable signal REB and a write protect signal WPB are input, and an I / O control circuit 13 for inputting / outputting command / address data I / O0 to I / O7 are provided. A signal ending with B means a low active signal.

  The command detector 12 analyzes the content of the command by decoding the input signal, and controls the I / O control circuit 13 and the control logic circuit 14 based on the result. Specifically, when the command content analyzed by the command detector 12 indicates that it is a command input period, the command (I / O0 to I / O7) input to the I / O control circuit 13 Is latched in the command register 15 and supplied to the control logic circuit 14. The control logic circuit 14 controls the array control circuit 16 and the status register 17 on the basis of the command input via the command detector 12 and the command register 15 and also controls the transistor T, whereby the ready / busy signal RY / BY is generated.

  On the other hand, when the contents of the command analyzed by the command detector 12 indicate that it is an address input period, the addresses (I / O0 to I / O7) input to the I / O control circuit 13 are address registers. 18 is latched. Of the addresses latched in the address register 18, the row address Radd is supplied to the row decoder 20 via the row address buffer 19, and the column address Cadd is supplied to the column decoder 22 via the column address buffer 21.

  The row decoder 20 is a circuit that performs row access to the memory cell array 11, and the column decoder 22 is a circuit that performs column access to the memory cell array 11. In addition to the column decoder 22, a sense amplifier circuit 23, a write buffer circuit 24, a verify determination circuit 25, and a data register 26 are used for column access to the memory cell array 11. In the read operation, read data read from the memory cell array 11 to the data register 26 is output to the outside via the I / O control circuit 13, and in the write operation, the I / O control circuit is externally supplied. The write data input via 13 is written into the memory cell array 11 via the data register 26.

  FIG. 2 is a schematic diagram for explaining the basic configuration of the memory cell array 11.

  As shown in FIG. 2, in the memory cell array 11, a plurality of word lines WL and a plurality of bit lines BL intersect, and memory cells MC are arranged at the intersections. A plurality of memory cells MC selected by one word line WL constitute a so-called “page”, and read / write operations are performed in units of pages. Although not particularly limited, the capacity of one page is, for example, 512 bytes. Some pages constitute one “block”, and the erase operation is performed in units of blocks.

  In the example shown in FIG. 2, the word line WL extends over the entire width of the memory cell array 11 in the Y direction, and the bit line BL extends over the entire width of the memory cell array 11 in the X direction. When such a configuration is adopted, the parasitic capacitance of the word line WL and the bit line BL increases, and the access speed may be reduced. Therefore, in practice, it is preferable to reduce the number of memory cells MC connected to one word line WL and one bit line BL by hierarchizing the word lines WL and bit lines BL.

  FIG. 3 is a schematic diagram for explaining the structure of the memory cell array 11 according to an example in which word lines and bit lines are hierarchized.

  In the example shown in FIG. 3, the word lines are hierarchized into upper main word lines MWL and lower sub word lines SWL, and bit lines are hierarchized into upper global bit lines GBL and lower local bit lines LBL. ing. Memory cell MC is arranged at the intersection of sub-word line SWL and local bit line LBL.

  Although details will be described later, a sub word driver SWD is interposed between the main word line MWL and the lower sub word line SWL. Depending on the combination of the main word signal and the sub word selection signal, one or two or more Sub-word line SWL is activated. Further, the hierarchical switch SEL is interposed between the global bit line GBL and the lower local bit line LBL, and one lower local bit line LBL is connected to one global bit line GBL.

  In the example shown in FIG. 3, several blocks constitute one “mat”. Although details will be described later, the mat is selected using the upper bits of the row address Radd. In the present embodiment, the hierarchical switch SEL is provided in units of mats. Therefore, the selection of the hierarchical switch SEL is performed based on the mat address MA composed of the upper bits of the row address Radd.

  FIG. 4 is a diagram for explaining the address assignment of the row address Radd.

  As shown in FIG. 4, in this embodiment, the row address Radd has a 12-bit configuration including bits Radd0 to Radd11. Among these, 3 bits composed of bits Radd9 to 11 are mat addresses MA and are used for selection of the memory mat shown in FIG. In this embodiment, one memory cell array 11 is divided into eight memory mats MAT0 to MAT7, and one of them is selected based on the mat address MA.

  Further, 4 bits including the bits Radd5 to 8 are a block address BA, and are used for selecting a block in the selected memory mat. In this embodiment, one memory mat is divided into 16 blocks BLK0 to BLK15, and one of them is selected based on the block address BA.

  Furthermore, 5 bits including bits Radd0 to Radd4 are a page address PA, and are used for selecting a page in the selected block. In this embodiment, one block is divided into 32 pages, and one of them is selected based on the page address PA. Of the bits Radd0-4, the upper bits Radd3, 4 are used for generating a main word signal, and the lower bits Radd0-2 are used for generating a subword selection signal (FX).

  Next, the circuit configuration and device structure of the memory cell array 11 will be described in detail.

  FIG. 5 is a circuit diagram for explaining a circuit configuration of the memory cell array 11.

  The memory cell array 11 shown in FIG. 5 has a configuration in which two sub word lines SWL are assigned to one memory cell MC (MC0, MC1,...). The memory cell MC includes a variable resistance element R and a selection circuit TR connected in series between a corresponding local bit line LBL (LBL0, LBL1,...) And a source line SL, and the selection circuit TR is connected in parallel. It consists of two cell transistors TR1, TR2. The cell transistors TR1 and TR2 are N-channel MOS transistors, and their gate electrodes are respectively connected to two sub word lines SWL (SWL0, SWL1,...) Sandwiching the memory cell MC.

  For example, the memory cell MC0 shown in FIG. 5 is provided at a position sandwiched between the sub word lines SWL0 and SWL1, the gate electrode of one cell transistor TR1 is connected to the sub word line SWL0, and the gate electrode of the other cell transistor TR2 is It is connected to the sub word line SWL1. The memory cell MC1 adjacent to the memory cell MC0 has a configuration in which the gate electrode of one cell transistor TR1 is connected to the sub word line SWL1, and the gate electrode of the other cell transistor TR2 is connected to the sub word line SWL2. ing.

  Thus, each memory cell MC is selected by two sub word lines SWL sandwiching itself. Each sub word line SWL is shared by two memory cells MC located on both sides.

  6A and 6B are diagrams for explaining the device structure of the memory cell array 11 shown in FIG. 5, in which FIG. 6A is a cross-sectional view taken along the X direction (extending direction of the local bit line LBL), and FIG. Shows a cross-sectional view when cut in the Y direction (extending direction of the sub word line SWL).

  As shown in FIG. 6A, the selection circuit TR of the memory cell MC is configured by a vertical MOS transistor. The vertical MOS transistor includes a silicon pillar 31 extending perpendicularly to the main surface of the silicon substrate 30, source / drain regions 32 and 33 provided above and below the silicon pillar 31, and gate insulation. A gate electrode that covers the side surface of the silicon pillar 31 via the film 34, that is, a sub word line SWL is formed. With this configuration, when the two sub word lines SWL sandwiching the silicon pillar 31 are activated, channels are formed on both side surfaces of the silicon pillar 31.

  The upper source / drain region 32 is connected to the corresponding local bit line LBL via the variable resistance element R. 6A and 6B, the variable resistance element R is sandwiched between the upper electrode 41 and the lower electrode 42, and the upper electrode 41 is connected to the local bit line LBL via the bit line contact 43. The lower electrode 42 is connected to the source / drain region 32 via the cell contact 44.

  On the other hand, the lower source / drain region 33 is connected to a source line SL embedded in the silicon substrate 30. As shown in FIGS. 6A and 6B, the source line SL is shared by a large number of memory cells MC arranged in the X direction and the Y direction.

  The variable resistance element R decreases in resistance when a current flows in the forward direction, that is, when a current flows from the local bit line LBL side to the source line SL side, and when a current flows in the reverse direction, that is, the local bit line from the source line SL side. It has a characteristic of increasing resistance when a current is supplied to the line LBL side. A state in which the resistance of the variable resistance element R is reduced is called a “set state”, for example, a logical value “1” is assigned. Conversely, the state in which the variable resistance element R has increased in resistance is called a “reset state” and is assigned a logical value “0”, for example. The operation of changing the variable resistance element R from the reset state to the set state (0 → 1) is called “set write operation”, and the operation of changing the variable resistance element R from the set state to the reset state (1 → 0) is “ This is called “reset write operation”.

  As a material of the variable resistance element R capable of obtaining such characteristics, Al, Hf, Ni, Co, Ta, Zr, W, Ti, Cu, V, Zn, and Nb are used. Oxides or oxynitrides are mentioned. As an example, it is possible to employ a configuration in which a thin film of Hf oxide is used as the variable resistance element R and is sandwiched between an upper electrode 41 made of Ta and a lower electrode 42 made of TiN.

  The set write operation is performed by applying a high potential to the local bit line LBL and a low potential to the source line SL, and selecting two sub word lines SWL sandwiching the target memory cell MC. As a result, since a current flows in the variable resistance element R in the forward direction, the resistance of the variable resistance element R is reduced. On the other hand, the reset write operation is performed by applying a low potential to the local bit line LBL and a high potential to the source line SL and selecting two sub word lines SWL sandwiching the target memory cell MC. As a result, since a current flows through the variable resistance element R in the opposite direction, the resistance of the variable resistance element R is increased. Such a variable resistance element R is called a bipolar type because the direction of the current for changing the resistance is bidirectional, but the present invention is not limited to this, and the direction of the current for changing the resistance is the same direction (the magnitude of the current). It is also applicable to the unipolar type.

  Although not particularly limited, in this embodiment, the reset write operation is performed in units of blocks. This is to ensure compatibility with the NAND flash memory. The reset write operation performed in units of blocks is called “block erase” and is executed in response to a block erase command. Data writing to each page is performed by selectively erasing the memory cell MC to which “1” needs to be written after the data of all the memory cells MC is set to “0” by erasing the block. Complete by performing an action.

  On the other hand, reading (reading operation) of data written in the memory cell MC applies a high potential to the local bit line LBL and a low potential to the source line SL and sandwiches the target memory cell MC as in the set write operation. This is done by selecting two sub word lines SWL. However, in the read operation, the amount of current flowing through the memory cell MC is set to be sufficiently smaller than that during the set write operation so that the variable resistance element R of the memory cell MC to be read is not set write (low resistance). The

  Here, considering the case where the read operation is performed on the memory cell MC3 shown in FIG. 6A, the sub-word lines SWL3 and SWL4 are applied with the high potential applied to the local bit line LBL0 and the low potential applied to the source line SL. Is selected, the read current Ir may be passed through the memory cell MC3. However, when the sub word lines SWL3 and SWL4 are selected, a channel is partially formed in the adjacent memory cells MC2 and MC4, so that an unnecessary read current Ir ′ flows through these memory cells MC2 and MC4. . Such an unnecessary read current Ir ′ becomes noise for an originally required signal component. However, if the selection potential of the sub word line SWL is set to a certain level, a sufficient S / N ratio during the read operation should be ensured. Is possible.

  FIG. 7 is a block diagram showing a configuration of a main part of the row decoder 20.

  As shown in FIG. 7, the row decoder 20 includes an FX generation circuit 51, row predecoders 52 to 54, and a mat selection circuit 55. The FX generation circuit 51 is a circuit that receives the bits Radd0 to Radd2 of the row address Radd and generates subword selection signals FXA0 to FXA3 and FXB0 to 3 and a max signal MAX0 based on the received bits. The sub word selection signals FXA0 to FXA3 and FXB0 to FXB3 are supplied to a sub word driver described later, and the max signal MAX0 is supplied to the row predecoder 52.

  FIG. 8 is a circuit diagram of the FX generation circuit 51, and FIG. 9 is a truth table thereof.

  As shown in FIGS. 8 and 9, the FX generation circuit 51 activates any two bits of the subword selection signals FXA0 to FXA3 and FXB0 to 3 according to the values of the bits Radd0 to Radd2. For example, when the value of the bits Radd0 to 2 is “000b” which is the minimum value, the subword selection signals FXA0 and FXB0 are activated, and when the value of the bits Radd0 to 2 is “001b”, the subword selection signals FXB0 and FXA1 are activated. Is activated. When the values of the bits Radd0 to Radd2 are “111b” which is the maximum value, the subword selection signals FXA0 and FXB3 are activated and the max signal MAX0 is activated. As described above, the maximum signal MAX0 is supplied to the row predecoder 52.

  FIG. 10 is a circuit diagram of the row predecoder 52, and FIG. 11 is a truth table thereof.

  As shown in FIG. 10 and FIG. 11, the row predecoder 52 receives any two bits of the predecode signals R3A0-3, R3B0-3 and the max signal MAX1 according to the value of the bits Radd3, 4 and the max signal MAX0. Activate. Specifically, assuming that the value of the bits Radd3, 4 is j, the predecode signals R3Aj and R3Bj are activated when the max signal MAX0 is at the low level (= 0). On the other hand, when the max signal MAX0 is at the high level (= 1), the predecode signals R3Bj and R3A (j + 1) are activated. However, when the value of the bits Radd3, 4 is “11b” which is the maximum value and the max signal MAX0 is at the high level (= 1), the predecode signal R3B3 and the max signal MAX1 are activated. As shown in FIG. 7, the maximum signal MAX 1 is supplied to the row predecoder 53.

  The row predecoder 53 has a circuit configuration similar to that of the row predecoder 52 shown in FIG. 10, and predecode signals R5A0-3 and R5B0-3 according to the values of the bits Radd5, 6 and the maximum signal MAX1. And any two bits of the MAX signal MAX2 are activated. Specifically, assuming that the value of bits Radd5 and 6 is k, pre-decode signals R5Ak and R5Bk are activated when max signal MAX1 is at a low level (= 0). On the other hand, when the max signal MAX1 is at the high level (= 1), the predecode signals R5Bk and R5A (k + 1) are activated. However, when the value of the bits Radd5, 6 is “11b” which is the maximum value and the max signal MAX1 is at the high level (= 1), the predecode signal R5B3 and the max signal MAX2 are activated. As shown in FIG. 7, the maximum signal MAX 2 is supplied to the row predecoder 54.

  The row predecoder 54 also has a circuit configuration similar to that of the row predecoder 52 shown in FIG. 10, and predecode signals R7A0-3 and R7B0-3 according to the values of the bits Radd7, 8 and the maximum signal MAX2. And any two bits of the MAX signal MAX3 are activated. Specifically, assuming that the value of the bits Radd7, 8 is 1, when the max signal MAX2 is at a low level (= 0), the predecode signals R7Al, R7Bl are activated. On the other hand, when the max signal MAX2 is at the high level (= 1), the predecode signals R7B1 and R7A (l + 1) are activated. However, when the value of the bits Radd7, 8 is “11b” which is the maximum value and the maximum signal MAX2 is at the high level (= 1), the predecode signal R7B3 and the maximum signal MAX3 are activated. As shown in FIG. 7, the maximum signal MAX3 is supplied to the main word driver 56.

  The mat selection circuit 55 receives bits Radd9 to 11 (mat address MA) of the row address Radd, and activates one of the mat selection signals MAten0 to MAten7 based on the received bits.

  Output signals from the row predecoders 52 to 54 and the mat selection circuit 55 are supplied to the main word driver 56 shown in FIG. The main word driver 56 includes many driver circuits shown in FIG. 12, and predecode signals R3Aj, R3Bj (j = 0 to 3), R5Ak, R5Bk (k = 0 to 3), R7Al, R7Bl (l = 0 to 3) and two main word signals MWLpAm and MWLpBm (m = 0 to 63) are activated based on the mat selection signal MATemp (p = 0 to 7).

  FIGS. 13 and 14 are block diagrams showing the relationship between the sub word driver SWD and the sub word line SWL in the memory mat MAT0, and correspond to the first embodiment of the present invention.

  As shown in FIGS. 13 and 14, sub word drivers SWDA0 to 63, SWDB0 to 63, and SWDMAX are allocated to one memory mat. Among these, the sub word drivers SWDA0 to 63 and SWDMAX are arranged on one side (the lower side in FIGS. 13 and 14) when viewed from the memory mat, and the sub word drivers SWDB0 to 63 are arranged on the other side (when viewed from the memory mat). In FIG. 13 and FIG.

  The sub word drivers SWDA0 to SWDA63 are activated by the main word signals MWL0A0 to 63, respectively, and drive the corresponding subword lines SWL based on the subword selection signals FXA0 to FXA3. The sub-word lines SWL driven by the sub-word drivers SWDA0 to 63 have an even number at the end. Similarly, sub word drivers SWDB0 to SWDB63 are activated by main word signals MWL0B0 to 63, respectively, and drive corresponding subword lines SWL based on subword selection signals FXB0 to FXB3. Sub-word lines SWL driven by the sub-word drivers SWDB0 to SWDB are suffixed with odd numbers.

  On the other hand, the sub word driver SWDMAX is activated by the corresponding max signal MAX 40 and drives the last sub word line SWL 512 belonging to the memory mat MAT 0.

  As shown in FIGS. 13 and 14, memory cells MC are arranged between two adjacent sub-word lines SWL. Thereby, for example, when the memory cell MC0 is selected, the sub word lines SWL0 and SWL1 are activated, and when the memory cell MC511 is selected, the sub word lines SWL511 and SWL512 are activated. Thus, 513 sub word lines SWL are allocated to one memory mat, and only the last sub word line SWL 512 is activated by the sub word driver SWDMAX.

  FIG. 15A is a circuit diagram of the sub word driver SWDA0, and FIG. 15B is a circuit diagram of the sub word driver SWDMAX.

  As shown in FIG. 15A, in the sub word driver SWDA0, an AND gate circuit G0 in which the main word signal MWL0A0 is commonly input to one input node and the sub word selection signals FXA0 to FXA3 are respectively input to the other input node. , 2, 4 and 6. With this configuration, when the main word signal MWL0A0 is activated, one of the sub word lines SWL0, 2, 4, and 6 is selected based on the sub word selection signals FXA0 to FXA3.

  The sub word drivers SWDA1 to SWDA1 to 63 also have the same circuit configuration as the sub word driver SWDA0 shown in FIG. 15A except that the corresponding main word signals MWL0A1 to 63 are input instead of the main word signal MWL0A0. . For the sub word drivers SWDB0 to SWDB63, the corresponding main word signals MWL0B0 to 63 are input instead of the main word signal MWL0A0, and the subword selection signals FXB0 to FXB3 are input instead of the subword selection signals FXA0 to FXA3. Has the same circuit configuration as that of the sub-word driver SWDA0 shown in FIG.

As shown in FIG. 15B, the sub-word driver SWDMAX is composed of an AND gate circuit G512 in which the maximum signal MAX40 is input to one input node and the other input node is fixed to the active level. With such a configuration, when these signals are activated, the sub word line SWL 512 is selected.

  FIG. 16 is a circuit diagram showing a part of the memory cell array 11 in more detail, and shows a region where the sub word lines SWL0 to SWLn and the local bit lines LBL0 to LBLm intersect.

  As shown in FIG. 16, each of the sub word lines SWL0 to SWLn is driven by gate circuits G0 to Gn included in the sub word driver. As described above, the corresponding main word signals MWL0A0, MWL0B0... And the corresponding sub word selection signals FXA0 to FXA3, FXB0 to FXB3 are supplied to the gate circuits G0 to Gn. On the other hand, local bit lines LBL0 to LBLm are connected to corresponding global bit lines GBL0 to GBLm via hierarchical switches SEL, respectively.

  FIG. 16 shows several memory cells MC selected by the sub word lines SWL2 and SWL3. When the sub word lines SWL2 and SWL3 are selected, these memory cells MC are connected to the corresponding local bit lines LBL0 to LBLm, and further connected to the corresponding global bit lines GBL0 to GBLm via the hierarchical switch SEL. Will be. The global bit lines GBL0 to GBLm are connected to the sense amplifier circuit 23 and the write buffer circuit 24 shown in FIG. 1, thereby executing a read operation and a write operation for the memory cell MC.

  FIG. 17 is a timing chart for explaining the operation of the semiconductor device 10 according to the present embodiment.

  In the example shown in FIG. 17, a program command PROG and a row address Raddk are input from the outside. The row address Raddk is an address that designates the sub word line SWLk. The program command PROG is a command for performing a set write operation on an arbitrary memory cell MC constituting the page specified by the row address Radd. In this example, the program command PROG is a memory cell corresponding to the local bit line LBL0. An example is shown in which a set write operation is performed on MC and a set write operation is not performed on the memory cell MC corresponding to the local bit line LBL1. As shown in FIG. 17, the corresponding local bit line LBL is set to the high level for the memory cell MC that executes the set write operation, and the corresponding local bit is set for the memory cell MC that does not execute the set write operation. The line LBL may be set to a low level. During the set write operation, the source line SL is at a low level.

  In this embodiment, when the row address Raddk specifying the sub word line SWLk is input, the sub word line SWLk and the sub word line SWLk + 1 are activated. As a result, the cell transistor included in the memory cell MC (MCk) sandwiched between the two sub word lines SWLk and SWLk + 1 is turned on, and a set write current can be passed. This operation is the same not only during the set write operation but also during the reset write operation and the read operation. In either case, the two sub word lines SWLk and SWLk + 1 sandwiching the memory cell MC to be selected are activated. It will be.

  For example, when the value of the bits Radd0 to Radd8 of the row address Radd is “000000000000b” (k = 0), the main word signals MWL0A0 and MWL0B0 and the subword selection signals FXA0 and FXB0 are activated, so that the subword lines shown in FIG. SWL0 and SWL1 are driven to a high level, and the memory cell MC0 sandwiched between them is selected.

  On the other hand, when the value of the bits Radd0 to 8 of the row address Radd is “00000011b” (k = 7), the max signal MAX0 is activated, so that the values of the bits Radd3 and 4 are “00b”. However, the main word signals MWL0A1 and MWL0B0 are activated. As a result, the sub word lines SWL7 and SWL8 shown in FIG. 13 are driven to a high level, and the memory cell MC7 sandwiched between them is selected. As described above, when the memory cell MC located at the boundary of the sub word driver SWD is selected, the pair of the activated sub word drivers SWD is switched by the activation of the max signal MAX0.

  Further, when the values of the bits Radd0 to Radd8 of the row address Radd are “111111111b” (k = 511), the max signals MAX0 to MAX3 are activated. As a result, the main word signal MWL0B63 and the maximum signal MAX40 are activated, the sub word lines SWL511 and SWL512 shown in FIG. 14 are driven to a high level, and the memory cell MC511 sandwiched between them is selected. Thus, when the memory cell MC located at the end of the memory mat is selected, the sub word driver SWDMAX is used.

  As described above, in the semiconductor device 10 according to the present embodiment, since the two sub word lines SWL are allocated to the memory cell MC and the adjacent memory cells MC share the same sub word line SWL, the adjacent memory cells There is no need to arrange two sub word lines SWL to be insulated and separated between the MCs. As a result, the degree of integration on the chip can be increased, and the manufacturing yield can be increased.

  Next, a second embodiment of the present invention will be described.

  FIG. 18 is a schematic diagram for explaining the structure of the memory cell array 11 according to the second embodiment of the present invention.

  As shown in FIG. 18, in this embodiment, the main word signal MWLpi is commonly input to the sub word drivers SWDAi and SWDBi (i = 0 to 63). Further, subword selection signals FX0, 2, 4, 6, and 8 are commonly input to the subword driver SWDAi, and subword selection signals FX1, 3, 5, and 7 are commonly input to the subword driver SWDBi.

  FIG. 19 is a block diagram showing a configuration of a main part of the row decoder 20a used in the present embodiment.

  As shown in FIG. 19, the row decoder 20 a used in this embodiment includes an FX generation circuit 61, row predecoders 62 to 64, a mat selection circuit 65, a main word driver 66, and an additional FX control circuit 67. The FX generation circuit 61 is a circuit that receives the bits Radd0 to Radd2 of the row address Radd and generates subword selection signals FX0 to FX8 based on the received bits. Among these, the subword selection signals FX0 and FX8 are supplied to the additional FX control circuit 67.

  FIG. 20 is a circuit diagram of the FX generation circuit 61, and FIG. 21 is a truth table thereof.

  As shown in FIGS. 20 and 21, the FX generation circuit 61 activates any two bits of the subword selection signals FX0 to FX8 according to the values of the bits Radd0 to Radd2. For example, if the value of the bits Radd0 to Radd2 is r, the subword selection signals FXr and FX (r + 1) are activated. The sub word selection signals FX0 to FX8 are supplied to the sub word drivers SWDAi and SWDBi shown in FIG. Further, the sub-word selection signals FX0 and FX8 are also supplied to the additional FX control circuit 67.

  The row predecoders 62 to 64 are general 2-bit decoders, and activate any one bit of the 4-bit output signal based on a 2-bit input signal in a binary format. Similarly to the mat selection circuit 55 shown in FIG. 7, the mat selection circuit 65 receives the bits Radd9 to 11 (mat address MA) of the row address Radd, and activates one of the mat selection signals MAten0 to MAten7 based on this. Let

  The predecode signals R3 <0: 3>, R5 <0: 3>, R7 <0: 3> output from the row predecoders 62 to 64 and the mat selection signals MATEN0 to MATEN7 output from the mat selection circuit 65 are It is supplied to the main word driver 66. The main word driver 66 selects the main word signal MWLp <0:63> and predecode signals R3 <0: 3>, R5 <0: 3> when the activated mat selection signal is MATENp. , R7 <0: 3>, one of the main word signals MWLp <0:63> is activated.

  FIG. 22 is a circuit diagram of the additional FX control circuit 67, and FIG. 23 is a truth table thereof.

  The additional FX control circuit 67 is a circuit that generates the subword switching signals FXOB and FXEB based on the subword selection signals FX0 and FX8 and the bit Radd3 of the row address Radd. As shown in FIGS. 22 and 23, when the sub word selection signal FX0 or FX8 is activated, one of the sub word switching signals FXOB and FXEB is activated to a low level. Here, the sub word selection signal FX0 or FX8 is activated when the value of the bits Radd0 to 2 of the row address Radd is “000b” which is the minimum value or “111b” which is the maximum value. Then, the relationship between the logic of the sub word selection signals FX0 and FX8 and the logic of the sub word switching signals FXOB and FXEB is configured to be inverted by the bit Radd3 of the row address Radd.

  Returning to FIG. 18, in the present embodiment, the sub-word driver SWDAi (i = 0 to 63) includes the gate circuits G0, 2, 4, and 6, and the sub-word driver SWDBi (i = 0 to 63) includes the gate circuit G1. , 3, 5 and 7 are included. These gate circuits G0 to G7 are circuits for driving the sub word lines SWL0 to SWL7 in the sub word drivers SWDA0 and SWDB0, for example.

  Among these gate circuits G0 to G7, as for the gate circuits G1 to G7, as shown in FIG. 24A, the corresponding subword selection signals FX1 to FX7 and their inverted signals, and the corresponding main word signal MWLpi (p is matte). The address is one of 0 to 7, and i is a block address and is any one of 0 to 63), and the corresponding sub word lines SWL1 to 7 × (pi) are driven based on them.

  On the other hand, for the gate circuit G0 (O) included in the odd-numbered sub word drivers SWDA1, 3, 5,..., The sub word selection signals FX0 and FX8, the sub word switching signal FXOB, as shown in FIG. The corresponding main word signal MWLpi and the previous main word signal MWLp (i−1) are received, and the corresponding sub word line SWL0 × (pi) is driven based on these. For example, the gate circuit G0 (O) included in the sub word driver SWDA1 receives the sub word selection signals FX0 and FX8, the sub word switching signal FXOB, the corresponding main word signals MWLp0 and MWLp1, and based on these, the corresponding sub word line SWL8 is set. To drive.

  On the other hand, the gate circuits G0 (E) included in the even-numbered sub word drivers SWDA0, 2, 4... Correspond to the sub word selection signals FX0 and FX8, the sub word switching signal FXEB, as shown in FIG. The main word signal MWLpi and the main word signal MWLp (i−1) of the previous stage are received, and based on these, the corresponding sub word line SWL0 × (pi) is driven. For example, the gate circuit G0 (E) included in the sub word driver SWDA2 receives the sub word selection signals FX0 and FX8, the sub word switching signal FXEB, the corresponding main word signals MWLp1 and MWLp2, and based on these, the corresponding sub word line SWL16 is set. To drive.

  However, for the gate circuit G0 (E) included in the first sub-word driver SWDAp0, since the main word signal at the previous stage does not exist, the corresponding signal is fixed at the high level. The last sub word driver SWDAp63 includes a gate circuit G512 shown in FIG. The gate circuit G512 activates the last sub word line SWL512 when the value of the bits Radd0 to 8 of the row address Radd is “111111111b” which is the maximum value (k = 511).

  With this configuration, in this embodiment as well, as in the first embodiment described above, when a row address Raddk designating a certain sub word line SWLk is input, the sub word line SWLk and the sub word line SWLk + 1 can be activated. As a result, the cell transistor included in the memory cell MC (MCk) sandwiched between the two sub word lines SWLk and SWLk + 1 is turned on, and a read current and a write current can flow.

  In addition, in the present embodiment, since the same main word signal MWLpi can be input to the sub word driver SWDAi and the sub word driver SWDBi, it is possible to reduce the number of main word lines.

  Next, a third embodiment of the present invention will be described.

  FIG. 25 is a schematic view for explaining the structure of the memory cell array 11 according to the third embodiment of the present invention.

  As shown in FIG. 25, in this embodiment, subword selection signals FXA0 to FXA4 are input to the subword driver SWDAi, and subword selection signals FXB0 to FXB4 are input to the subword driver SWDBi. Further, not only the corresponding main word signal MWLpAi but also the previous main word signal MWLpA (i−1) are input to the gate circuit G0 included in the sub word driver SWDAi. Similarly, not only the corresponding main word signal MWLpBi but also the previous main word signal MWLpB (i−1) are input to the gate circuit G1 included in the sub word driver SWDBi.

  FIG. 26 is a block diagram showing a configuration of a main part of the row decoder 20b used in the present embodiment.

  As shown in FIG. 26, the row decoder 20b used in this embodiment includes an FX generation circuit 71, row predecoders 72 to 74, a mat selection circuit 75, a main word driver 76, and an FX driver 77. As shown in FIG. 27, the FX generation circuit 71 is a general decoding circuit that receives bits Radd0 to 2 of the row address Radd and activates any one of the subword selection signals FX0 to FX7. The subword selection signals FX0 to FX7 are input to the FX driver 77. The sub word selection signal FX0 is also input to the row predecoder 72.

  FIG. 28 is a circuit diagram of the FX driver 77, and FIG. 29 is a truth table thereof. In FIG. 29, “0” in the Radd 3-8 column means that the value of the bits Radd 3 to 8 of the row address Radd is “000000b”, and the Radd 3-8 column The notation “1” means that the values of the bits Radd 3 to 8 of the row address Radd are other than “000000b”.

As shown in FIG. 28, the FX driver 77 receives the subword selection signals FX0 to FX7, the bits Radd3 to 8 of the row address Radd and the corresponding mat selection signal MATemp (p = 0 to 7), and selects the subword based on them. Signals FXA0 to FXA4, FXB0 to FXB4 are generated. The level of the sub word selection signals FXA0 to FXA4, FXB0 to FXB4 is one of the selection level VWL, the non-selection level VKKS, and the reverse bias level VKK. The relationship between the selection level VWL, the non-selection level VKKS and the reverse bias level VKK is
VWL>VKKS> VKK
It is.

  The selection level VWL is a potential that turns on the transistors TR1 and TR2 included in the memory cell MC, that is, a potential that exceeds a threshold value. The non-selection level VKKS and the reverse bias level VKK are potentials that turn off the transistors TR1 and TR2. That is, the potential does not exceed the threshold value. In particular, since the reverse bias level VKK is lower than the non-selection level VKKS, for example, when the potential of the reverse bias level VKK is applied to the gate electrode of one transistor TR1, the gate electrode of the other transistor TR2 is selected. Even when the potential of the level VWL is applied, the channel formed in the transistor TR2 is canceled, and the on-state current is greatly reduced or hardly flows.

  Here, the gate circuit 77a shown in FIG. 28 is a circuit for selecting the subword selection signal FXB0 when the values of the bits Radd0 to Radd8 of the row address Radd are “000000000000b”. A gate circuit 77b shown in FIG. 28 is a circuit for selecting the subword selection signal FXB4 when the values of the bits Radd3 to 8 of the row address Radd are other than “000000b”.

  Of the subword selection signals FXA0 to FXA4 and FXB0 to FXB4 generated in this way, the subword selection signals FXA0 to FXA4 are supplied to the subword driver SWDAi shown in FIG. 25, and the subword selection signals FXB0 to FXB4 are shown in FIG. Is supplied to the sub word driver SWDBi.

  30 is a circuit diagram of the row predecoder 72. FIG. 30A shows a circuit portion that generates the predecode signals R3A0-3, and FIG. 30B shows a circuit portion that generates the predecode signals R3B0-3. .

  As shown in FIG. 30A, a circuit portion that generates the predecode signals R3A0 to R3A0-3 in the row predecoder 72 is a general 2-bit decoder, and is based on the bits Radd3 and 4 of the row address Radd. Any one bit of the bit predecode signals R3A0-3 is activated.

  On the other hand, in the row predecoder 72, the circuit portion for generating the predecode signals R3B0 to R3B0 is activated in addition to the general 2-bit decoder circuit configuration as shown in FIG. A logic gate circuit for switching .about.3 is added. Specifically, when the value of the bits Radd0 to 8 of the row address Radd is “000000000000b”, the value of the bits Radd0 to 8 of the row address Radd is achieved while performing the same function as the circuit portion of FIG. Is other than “000000000000b”, the predecode signals R3B0-3 to be activated are switched, and the previous predecode signal is activated.

  With this configuration, the row predecoder 72 activates any one bit of the predecode signals R3A0 to R3B0 and any one bit of the predecode signals R3B0 to R3 based on the bits Radd3 and 4 of the row address Radd.

  The other row predecoders 73 and 74 have the same circuit configuration as the row predecoder 72 shown in FIGS. Therefore, for row predecoder 73, one bit of predecode signals R5A0-3 and one bit of predecode signals R5B0-3 are activated based on bits Radd5, 6 of row address Radd. For predecoder 74, one bit of predecode signals R7A0-3 and one bit of predecode signals R7B0-3 are activated based on bits Radd7, 8 of row address Radd.

  Similarly to the mat selection circuit 55 shown in FIG. 7, the mat selection circuit 75 receives bits Radd9 to 11 (mat address MA) of the row address Radd, and activates one of the mat selection signals MAten0 to MAten7 based on this. Let

  These predecode signals output from the row predecoders 72 to 74 and the mat selection signals MATEN0 to MATEN7 output from the mat selection circuit 75 are supplied to the main word driver 76. The main word driver 76 has the same function as the main word driver 56 shown in FIG. 7, and therefore activates two main word signals.

  Returning to FIG. 25, also in this embodiment, the sub-word driver SWDAi (i = 1 to 63) includes the gate circuits G0, 2, 4, and 6, and the sub-word driver SWDBi (i = 1 to 63) includes the gate circuit G1. , 3, 5 and 7 are included. The top subword driver SWDA0 includes gate circuits G0a, 2, 4, and 6, and the top subword driver SWDB0 includes gate circuits G1a, 2, 4, and 6. These gate circuits G0 to G7, G0a, and G1a are circuits that drive the corresponding sub word lines SWL. For example, in the sub word drivers SWDA0 and SWDB0, the sub word lines SWL0 to SWL7 are driven by the gate circuits G0a, G1a, and G2 to G7, respectively. Is done.

  Among these gate circuits G0-G7, G0a, G1a, the gate circuits G0a, G1a, G2-G7 have the circuit configuration shown in FIG. As shown in FIG. 31 (a), the gate circuits G2 to G7 are inverters having the corresponding main word signal MWLpAi (or MWLpBi) as an input signal and the corresponding subword selection signals FXA0 to FXA0 to 3 (or FXB0 to 3) as power sources. Although it is a circuit, a transfer gate TG is used instead of a transistor that uses the sub word selection signals FXA0 to FXA3 (or FXB0 to FXB3) as a source. Accordingly, when the corresponding main word signal MWLpAi (or MWLpBi) is activated to a low level, the sub word line SWL is driven to the potential (VWL, VKKS, or VKK) of the sub word selection signals FXA0 to FXA3 (or FXB0 to FXB3). Is done.

  On the other hand, in the gate circuit G0, as shown in FIG. 31B, a transfer gate TG0 that receives the subword selection signal FXA0 and a transfer gate TG4 that receives the subword selection signal FXA4 are connected in parallel. The transfer gate TG0 is controlled by the main word signal MWLpA (i-1) in the previous stage, and the transfer gate TG4 is controlled by the corresponding main word signal MWLpAi.

  As for the gate circuit G1, as shown in FIG. 31 (c), transfer gates TG4a and TG4b receiving the sub word selection signal FXA4 are connected in parallel. The transfer gate TG4b is controlled by the main word signal MWLpB (i-1) in the previous stage, and the transfer gate TG4a is controlled by the corresponding main word signal MWLpBi.

  FIG. 32 is a circuit diagram showing a part of the memory cell array 11 in this embodiment in more detail.

  As shown in FIG. 32, the corresponding main word signal MWLpAi is supplied to the gate circuits G0, 2, 4, and 6, and the corresponding main word signal MWLpBi is supplied to the gate circuits G1, 3, 5, and 7. In addition, the previous main word signal MWLpA (i-1) is supplied to the gate circuit G0, and the previous main word signal MWLpB (i-1) is supplied to the gate circuit G1.

  Of the gate circuits G0, 2, 4, and 6, the gate circuits G2, 4, and 6 drive the corresponding sub word lines SWL based on the levels of the sub word selection signals FXA1 to FXA1. On the other hand, for the gate circuit G0, the corresponding sub word line SWL is driven based on the level of the sub word selection signal FXA0 or FXA4. Selection of the sub word selection signal FXA0 or FXA4 is performed by the activated main word signal MWLpAi or main word signal MWLpA (i-1).

  However, the sub-word selection signal FXA4 is not supplied to the gate circuit G0 included in the first-stage sub-word driver SWDA0 because the previous-stage main word signal does not exist. Although not shown, the last sub-word driver SWDA64 includes a circuit corresponding to FIG. 31A in which FXA0 to FXA3 are replaced with FXA4, and the value of the bits Radd0 to 8 of the row address Radd is the maximum value. In the case of “111111111b” (k = 511), the last sub-word line SWL512 is activated.

  Similarly, among the gate circuits G1, 3, 5, and 7, the gate circuits G3, 5, and 7 drive the corresponding sub word lines SWL based on the levels of the sub word selection signals FXB1 to FXB1. On the other hand, for the gate circuit G1, the corresponding sub word line SWL is driven based on the level of the sub word selection signal FXB0 or FXB4. The selection of the sub word selection signal FXB0 or FXB4 is performed by the activated main word signal MWLpBi or main word signal MWLpB (i-1).

  FIG. 33 is a timing chart for explaining the operation of the semiconductor device 10 according to the third embodiment.

  As shown in FIG. 33, in the present embodiment, when a program command PROG and a row address Raddk are input from the outside, the sub word line SWLk and the sub word line SWLk + 1 are driven to the selection level VWL, and the sub word line SWLk−1. The sub word line SWLk + 2 is driven to the reverse bias level VKK. Other sub word lines SWL (for example, SWLk-2) are driven to the non-selection level VKKS.

  As a result, the cell transistor included in the memory cell MC (MCk) sandwiched between the two sub word lines SWLk and SWLk + 1 is turned on, and a set write current can be passed. This operation is the same not only during the set write operation but also during the reset write operation and the read operation. In either case, the two sub word lines SWLk and SWLk + 1 sandwiching the memory cell MC to be selected are activated. It will be.

  Then, since the sub word line SWLk-1 and the sub word line SWLk + 2 located outside the sub word lines SWLk and SWLk + 1 are driven to the reverse bias level VKK, the memory cell MC (MCk-1) adjacent to the memory cell MC (MCk-1) is driven. , MCk + 1) can be cancelled. As an example, when the sub word lines SWL8 and SWL9 shown in FIG. 32 are driven to the selection level VWL by the gate circuits G0 and G1, respectively, the sub word lines SWL7 and SWL10 located outside the sub word lines SWL8 and SWL9 are reverse bias levels by the gate circuits G7 and G2, respectively. Driven to VKK.

  As described with reference to FIG. 6A, for example, when the sub word lines SWL3 and SWL4 are driven to the selection level VWL, channels are formed not only in the corresponding memory cell MC3 but also in the adjacent memory cells MC2 and MC4. This may cause unnecessary current (for example, current Ir ′) to flow. However, in this embodiment, since the sub word lines SWL2 and SWL5 are driven to the reverse bias level VKK, the adjacent memory cells MC2 and MC4 The channel that is formed is canceled. As a result, unnecessary current (for example, current Ir ′) is reduced, thereby improving the S / N ratio during the read operation and preventing erroneous writing during the write operation.

  Next, a fourth embodiment of the present invention will be described.

  FIG. 34 is a block diagram showing the configuration of the main part of the semiconductor device according to the fourth embodiment of the present invention.

  In the semiconductor device according to the present embodiment, in response to the 9-bit row address Radd0-8, any two of the 513 word lines WL0-WL512 are driven to the selection level VWL, and the other two are reverse bias levels. Drive to VKK. First, the 9-bit row addresses Radd0 to Radd8 are input to the decoder 80, whereby one of the 512-bit decode signals DEC0 to DEC511 is activated. The decode signal DECj (j = 0 to 511) is supplied to the enable node EN of the word drivers WDj and WDj + 1, whereby the corresponding word lines WLj and WLj + 1 are driven to the selection level VWL.

  Further, the decode signal DECj (j = 0 to 511) is also supplied to the negative nodes NEG of the word drivers WDj−1 and WDj + 2, thereby driving the corresponding word lines WLj−1 and WLj + 2 to the reverse bias level VKK. . However, when the first decode signal DEC0 is activated, the dummy word line DWL0 is driven to the reverse bias level VKK by the dummy word driver DWD0 corresponding to the word driver WDj-1. When the last decode signal DEC511 is activated, the dummy word line DWL1 is driven to the reverse bias level VKK by the dummy word driver DWD1 corresponding to the word driver WDj + 2.

  With this configuration, the two adjacent word lines WLj and WLj + 1 are driven to the selection level VWL regardless of the values of the row addresses Radd0 to Radd8, and the other two word lines adjacent to them are driven. WLj−1 (or dummy word line DWL0) and WLj + 2 (or dummy word line DWL1) are driven to the reverse bias level VKK. This makes it possible to obtain the same effect as that of the third embodiment described above with a simple configuration.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Memory cell array 12 Command detector 13 Control circuit 14 Control logic circuit 15 Command register 16 Array control circuit 17 Status register 18 Address register 19 Row address buffer 20, 20a, 20b Row decoder 21 Column address buffer 22 Column decoder 23 Sense amplifier Circuit 24 Write buffer circuit 25 Verify determination circuit 26 Data register 30 Silicon substrate 31 Silicon pillar 32, 33 Source / drain region 34 Gate insulating film 41 Upper electrode 42 Lower electrode 43 Bit line contact 44 Cell contact 51, 61, 71 FX generation circuit 52 to 54, 62 to 64, 72 to 74 Row predecoders 55, 65, 75 Mat selection circuits 56, 66, 76 Main word Driver 67 Additional FX control circuit 77 FX driver 77a, 77b Gate circuit 80 Decoder BL Bit line BLK Block DWD0, DWD1 Dummy word driver DWL0, DWL1 Dummy word line GBL Global bit line LBL Local bit line MAT Memory mat MC Memory cell MWL Main word Line R Variable resistance element SEL Hierarchical switch SL Source line SWD Sub word driver SWL Sub word line T Transistor TG Transfer gate TR Select circuit TR1, TR2 Cell transistor WD Word driver WL Word line

Claims (8)

A plurality of memory cells arranged side by side in a first direction;
A plurality of word lines arranged in the first direction so as to sandwich the plurality of memory cells, respectively, and extending in a second direction intersecting the first direction;
A control circuit for controlling the plurality of word lines,
The control circuit sets the potentials of the first and second word lines sandwiching the first memory cell out of the plurality of word lines when the first memory cell of the plurality of memory cells is accessed. The potential of the second word line and the third word line sandwiching the second memory cell when the second memory cell adjacent to the first memory cell is accessed is changed from the selection level to the selection level. A semiconductor device, wherein the selection level is changed from a non-selection level.   The control circuit controls the third memory cell when accessing the third memory cell on the opposite side to the second memory cell adjacent to the first memory cell among the plurality of memory cells. 2. The semiconductor device according to claim 1, wherein the potential of the first word line and the fourth word line sandwiched between the non-selection level and the selection level is set. Each of the plurality of memory cells includes a selection circuit and a storage element connected in series,
The selection circuit includes first and second cell transistors connected in parallel,
The control electrode of the first cell transistor is connected to one of two word lines sandwiching the memory cell,
3. The semiconductor device according to claim 2, wherein a control electrode of the second cell transistor is connected to the other of the two word lines.   4. The semiconductor device according to claim 3, wherein each of the first and second cell transistors is a MOS transistor having a vertical structure.   The semiconductor device according to claim 4, wherein the memory element is a variable resistance element.   6. The semiconductor device according to claim 5, wherein the selection level is a potential exceeding a threshold value of the MOS transistor, and the non-selection level is a potential not exceeding a threshold value of the MOS transistor.   7. The semiconductor device according to claim 6, wherein the control circuit changes the potential of the third and fourth word lines from the non-selection level to a reverse bias level when accessing the first memory cell. apparatus.   The semiconductor device according to claim 7, wherein the non-selection level is a potential between the reverse bias level and the selection level.

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