JP2014225564A - Management method used for semiconductor manufacturing apparatus and manufacturing method of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a management method used for a semiconductor manufacturing apparatus which can estimate the occurrence of defect with high accuracy.SOLUTION: A management method used for a semiconductor manufacturing apparatus isolates the defects into area-based defect and random defect. The area-based defect is determined by using a plurality of wafers. On each of the plurality of wafers, a plurality of semiconductor chips are formed. A defect-prone area where a defective semiconductor chip frequently occurs is extracted from the wafer and estimated as the area-based defect by using the plurality of wafers. On the other hand, the random defect is determined by wafer unit. From each of the plurality of wafers, the wafer where a defective semiconductor chip frequently occurs in an area other than the defect-prone area is extracted. The defective semiconductor chip in the extracted wafer is estimated to occur due to the random defect.

Description

  The present invention relates to a management method used in a semiconductor manufacturing apparatus and a manufacturing method of a semiconductor integrated circuit device (hereinafter also referred to as a semiconductor device). In particular, the semiconductor device is manufactured based on an analysis of a failure (defect) occurring in the semiconductor device. The present invention relates to a management method for managing a semiconductor manufacturing apparatus used in the process and a method for manufacturing a semiconductor integrated circuit device.

  In recent years, with the miniaturization and higher functionality of semiconductor devices, it has become difficult to quickly increase and stabilize the manufacturing yield of new semiconductor devices when starting the manufacture of new semiconductor devices. Yes. One of the causes is that a semiconductor device is provided with a memory (storage circuit) having a relatively high degree of integration, and defects occurring in the memory portion are diversified. In addition, the frequency of occurrence of defects in the memory is increased.

  The types of defects that occur in the memory part include a short circuit of wiring, disconnection, and / or non-conductivity of interlayer contacts due to the entry of foreign matters in a processing step when manufacturing a semiconductor device, and a film is formed on a wafer. There is a pattern shape defect due to in-wafer variation in film thickness at the time of film formation. In addition, there are defects due to variations in characteristics of transistors manufactured through processing steps and / or variations in response speed in a circuit constituted by the transistors.

  When manufacturing a new semiconductor device, it is desirable to quickly achieve a high manufacturing yield and stabilize it from the start of manufacturing. To that end, with respect to defects such as those described above, the status of occurrence is monitored and analyzed for each wafer, a process step corresponding to the cause of the defect occurrence is estimated, and a manufacturing apparatus related to the process step corresponding to the cause (for example, It is important to narrow down manufacturing conditions in a CVD apparatus, an etching apparatus, etc.) and / or a manufacturing apparatus. Also, in order to quickly increase the manufacturing yield from the start of manufacturing, it is desirable to prioritize the countermeasures for each defect content and implement the countermeasures efficiently.

  In order to quantify the processing process that causes each wafer, an electrical test is performed on the memory, and the determination result of the quality is arranged, and an array pattern of fail bits in the memory (referred to as a fail bit mode). ) Is done. Patent Document 1 discloses a technique for calculating the defect density for each process using the defect rate for each fail bit mode obtained as described above and the result of the defect sensitivity simulation using the design layout.

  Patent Document 2 discloses a technique for visualizing the distribution of fail bits on a wafer and improving the efficiency of defect analysis. Patent Document 3 discloses a technique for recognizing a region where a fail bit is generated and performing defect sensitivity simulation for each region.

  In this Patent Document 3, it is shown that a wafer is divided into a plurality of concentric circles, a concentric circle area where the number of fail bits is large is called a characteristic defect area, and other areas are called foreign substance defects and classified. Has been. Further, it is shown that when fail bits are generated in adjacent areas, they are classified as cluster defects.

US Pat. No. 6,701,477 JP 11-87454 A JP 2011-187836 A

  In Patent Document 1, only the defect is the target of the defect sensitivity simulation. Therefore, when a defect system defect and a characteristic system (electrical characteristic system) defect coexist on the same wafer, there is a problem that the estimation accuracy such as the defect density for each process is deteriorated. It is desirable to efficiently classify characteristic system defects and defect system defects that are mixedly distributed on the wafer.

  In Patent Document 2, it is shown that the fail bit distribution in a plurality of wafers is visualized and compared. However, it has not yet been recognized as a region where defects are distributed.

  In Patent Document 3, attention is paid to defects in a single wafer. When fail bits are distributed concentrically in a single wafer, or when there is a dense area in a single wafer, the fail bit generation region is recognized. However, for example, when the manufacturing yield is improved to some extent, the frequency of occurrence of fail bits decreases. In this case, it is feared that it is difficult to recognize the fail bit generation area only by targeting a single wafer. For this reason, there is a concern that the accuracy of recognizing the fail bit occurrence region is lowered. As a result, there is a concern that the estimation accuracy of the defect density by process using the defect sensitivity simulation is lowered. In addition, when the fail bit distribution is not concentric or clustered, the fail bit recognition also decreases.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  In a management method used in a semiconductor manufacturing apparatus, a defect is divided into an area defect and a random defect. A regional defect is recognized using a plurality of wafers. A plurality of semiconductor chips are formed on each of the plurality of wafers. Using a plurality of wafers, a frequently occurring region where defective semiconductor chips are frequently generated is extracted, and is estimated to be a region defect. On the other hand, the failure of randomness is recognized on a wafer basis. From each of the plurality of wafers, a wafer in which defective semiconductor chips are frequently generated is extracted in an area excluding the frequent occurrence area. It is presumed that defective semiconductor chips in the extracted wafer are generated due to random defects. It is possible to accurately estimate the occurrence of a defect by distinguishing between a region defect and a random defect. In addition, since the regional defect is statistically estimated using a plurality of wafers, it is possible to reliably recognize the occurrence of the defect.

  Based on the recognized regionality failure and randomness failure, the processing steps applied to the wafer in time series are reviewed. The review is performed, for example, as a change in manufacturing conditions used in the processing steps. For example, it is possible to promptly improve the manufacturing yield from the start of manufacturing when manufacturing a new semiconductor device by quickly eliminating the region defect by changing the manufacturing conditions. In other words, it is possible to provide a semiconductor manufacturing method with a high yield from the start of manufacturing.

  In one embodiment, the determination of a failure is made based on the result of an electrical test on a memory formed on a semiconductor chip. As a result, both the defect system defect and the characteristic system (electrical characteristic system) defect are recognized as defects.

  In one embodiment, the region defect and the random defect are displayed as positions on the wafer. This makes it possible to facilitate analysis.

  Furthermore, according to one embodiment, the defect density for each process is estimated using defect sensitivity simulation for each of the regional defects (multiple areas) and random defects. Thereby, effective information is provided by failure analysis.

  According to one embodiment, it is possible to provide a management method used in a semiconductor manufacturing apparatus that can accurately estimate the occurrence of a defect.

It is a block diagram which shows the structure of the semiconductor manufacturing apparatus concerning one embodiment, a management system, and a failure analysis system. It is a conceptual diagram for demonstrating the concept of the superposition | stacking of the defect chip | tip in a some wafer. It is a histogram figure for demonstrating the concept which extracts a defect frequent occurrence area | region when a defective chip | tip is piled up. It is a histogram figure for demonstrating the concept which extracts the wafer with many defective chips outside a defect frequent occurrence area | region. It is a flowchart figure which shows the process which extracts a defect frequent occurrence area | region and an out-of-area defect frequent occurrence wafer. It is a figure which shows an example of the screen output of an analysis result. It is a figure which shows an example of the screen output of an analysis result. It is the block diagram which showed the monitoring method of the defect occurrence condition of the semiconductor manufacturing line concerning one Embodiment. It is the block diagram which showed the effect confirmation method of the countermeasure against the defect in the semiconductor manufacturing line concerning one embodiment. It is a schematic diagram which shows an example of generation | occurrence | production of a defect. It is a schematic diagram which shows an example of generation | occurrence | production of a defect. It is a schematic diagram which shows an example of generation | occurrence | production of a defect. It is a schematic diagram which shows an example of generation | occurrence | production of a defect.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
<Overall configuration>
FIG. 1 is a block diagram showing configurations of the semiconductor manufacturing apparatus 12, the management system 11, and the failure analysis system 2. In the figure, reference numeral 10 denotes a semiconductor manufacturing line, which includes a semiconductor manufacturing apparatus 12 and a management system 11 that manages the semiconductor manufacturing apparatus 12. The semiconductor manufacturing apparatus 12 is shown by one block in the figure, but a plurality of semiconductor manufacturing apparatuses that apply a plurality of processes in time series to each of a plurality of wafers (semiconductor wafers). Contains. The semiconductor manufacturing apparatus 12 includes, for example, a CVD apparatus, a sputtering apparatus, an etching apparatus, and the like that put a wafer in a chamber and form a film on the wafer. Each of these manufacturing apparatuses performs time-series processing (processing process) on each of the plurality of wafers to form a plurality of semiconductor chips on the wafer.

  The defect analysis system 2 transmits and receives information to and from the semiconductor manufacturing line 10 (the management system 11 and the semiconductor manufacturing apparatus 12). Further, the layout information 26 relating to the layout of the semiconductor device to be manufactured is received, and the analysis result is displayed and / or the management system 11 is instructed as will be described later. This failure analysis system 2 has a manufacturing history database 31 (in the figure, a manufacturing history DB) 31. Information related to semiconductor manufacturing is supplied from the semiconductor manufacturing line 10 and stored in the manufacturing history database 31. The Information related to semiconductor manufacturing includes manufacturing condition designation information 20, device state monitoring information 21, in-line inspection results 22, electrical test results 23, fail bit analysis results 24, and various defect analysis results 25. Collected in the manufacturing history database 31.

  In this embodiment, a semiconductor chip to be manufactured is provided with a memory. In other words, the case of manufacturing a semiconductor chip with a built-in memory will be described below. The fail bit analysis result 24 described above is obtained by an electrical test (test) for a memory portion built in the semiconductor chip. Therefore, the fail bit analysis result 24 is a part of information of the electrical test result 23 and can be understood as the electrical test result. However, in order to facilitate later explanation, in this embodiment, separation is performed. It is described as.

  The memory includes a plurality of memory elements arranged in a matrix, a plurality of word lines arranged in each row of the matrix, and a plurality of bit lines arranged in each column of the matrix. doing. Each of the plurality of memory elements arranged in a matrix is connected to a corresponding word line and bit line. By selecting a word line from a plurality of word lines, the memory element connected to the selected word line is selected, and the memory element is connected to the memory element via the bit line connected to the selected memory element. Data is written or read. Although not particularly limited, a fail bit analysis result is formed when a defect occurs in the memory portion. The fail bit represents a failure of the memory element. In this specification, the fail bit is simply referred to as F. B. The fail bit analysis result 24 is simply F.D. B. Sometimes referred to as data.

  As described above, F.I. B. The data is information relating to good or bad electrical operation of the memory portion mounted on the semiconductor device. F.F. B. The data also includes position information relating to the positions of the memory elements that were particularly defective, plotted in virtual coordinates according to the arrangement in the actual semiconductor device. By having information on the position (arrangement) in this way, when only one bit is defective even though the surrounding area is a good bit memory element, a single bit (hereinafter referred to as SB) is used. It can be assumed that it is defective. A plurality of memory elements arranged in a line in the word line direction are F.D. B. In this case, it can be estimated that the word line (hereinafter referred to as WL) is defective. In addition, a plurality of memory elements arranged in the bit line direction are F.D. B. In this case, it can be inferred that the bit line (hereinafter referred to as BL) is defective. If it guesses and classifies like this, S.I. B. In the case of a defect, the W.V. L. If defective, W. L. B. L. If it is defective, B. L. It can be determined that there is a problem in the layer that generates In this way, S.I. B. Bad, W. L. Bad, B. L. F. Like bad. B. A classification of F. B. This is called a mode.

  Further, layout information 26 for a photomask used for manufacturing a semiconductor device is supplied to a CAA (Critical Area Analysis) simulation tool 27. The CAA simulation tool 27 is described in, for example, Patent Document 3 and Japanese Patent Application Laid-Open No. 2010-73992. Therefore, although not described in detail here, a plurality of foreign objects are virtually dropped randomly on the layout. The processing unit calculates a critical area for each process fail bit mode (FB mode). Information on the calculated result, that is, information on critical areas for each process fail bit mode is stored in a critical area database (DB) 32.

  In FIG. 1, reference numeral 30 denotes a failure analysis unit. The defect analysis unit 30 includes a layer-specific foreign matter defect rate calculation unit 41, a defect frequent occurrence region extraction unit 40, an out-of-region defect frequent wafer extraction unit 42, a defect cause investigation unit 43, and setting information 44.

  The information stored in the critical area DB 32 is read by the layer-specific foreign material defect rate calculation unit 41. Based on the read information, the layer-specific foreign material defect rate calculation unit 41 calculates the foreign material defect rate for each layer using the techniques described in Patent Document 3 and Japanese Patent Application Laid-Open No. 2010-73992.

  The calculation result in the foreign matter defect rate calculation unit 41 for each layer and the F.F. stored in the manufacturing history DB 31. B. Data is supplied to the defective frequent occurrence area extraction unit 40. The defective frequent occurrence area extraction unit 40 calculates the F.F. B. Using the data, an area where defects frequently occur in the wafer is extracted. In addition, the calculation result in the layer-specific foreign matter defect rate calculation unit 41 and the F.V. B. The data and the result of extraction by the defect frequent occurrence area extraction unit 40 are supplied to the out-of-area defect frequent wafer extraction part 42. The out-of-area defect frequent wafer extraction unit 42 uses these pieces of supplied information, and defects frequently occur in areas outside the areas where defects are frequently occurring (areas extracted by the defect frequent area extraction unit 40). The wafers that are present. The setting information 44 is a unit that supplies setting information to the frequent defect region extraction unit 40, out-of-region defect frequent wafer extraction unit 42, and defect cause investigation unit 43. Regarding the defect frequent area extraction unit 40, the out-of-area defect frequent wafer extraction part 42, and the setting information 44, the contents of the process will be described later.

  The information obtained by the layer-specific foreign matter defect rate calculation unit 41, the defect frequent region extraction unit 40, and the out-of-region defect frequent wafer extraction unit 42 is, for example, layer-specific defect density and / or defect frequent occurrence in a region where defects frequently occur. The defect density for each layer outside the region is used for defect analysis. That is, the obtained information is supplied to the input / output unit 45, and the defect density by layer in the region where defects frequently occur and / or the defect density by layer outside the region where defects occur frequently are output and output by the input / output unit 45. / Or displayed. Of course, the analysis results regarding these densities may be output and displayed from the input / output unit 45. Using the output / display from the input / output unit 45, for example, the production line can be monitored, the effect of countermeasures against defects can be confirmed, and the like. It is also possible to control the production line by supplying information from the input / output unit 45 to the management system 11.

  The defect cause investigation unit 43 includes manufacturing condition designation information 20, device state monitoring information 21, in-line inspection results 22, electrical test results 23, fail bit analysis results 24, various defect analysis results 25, and layer-specific foreign substance defect rate calculation unit 41. Information obtained by the defect frequent area extraction unit 40 and the out-of-area defect frequent wafer extraction part 42 are supplied. The defect cause investigating unit 43 performs various analyzes using the supplied information and performs cause analysis. The result of the cause analysis in the defect cause investigation unit 43 is output / displayed in the input / output unit 45.

<Faulty area extraction unit 40 and out-of-area defect occurrence wafer extraction unit 42>
Next, the concept of processing in the defect frequent area extraction unit 40 and the out-of-area defect frequent wafer extraction part 42 will be described.

<< Extraction of defective areas >>
First, extraction of defective frequent occurrence areas will be described. FIG. 2 is a conceptual diagram showing a concept of superposition of defective chips on a wafer.

  In the figure, reference numerals 201, 206, and 207 denote wafers. A defective semiconductor chip is generated on each of the wafers 201, 206, and 207. In the figure, the positions where defective semiconductor chips are generated on the wafer are indicated by the symbols ●. For example, in the wafer 201, defective semiconductor chips are generated at two positions. Of these two locations, one defective semiconductor chip is shown as 202. Similarly, it is shown that a defective semiconductor chip is generated at one location on the wafer 206 and a defective semiconductor chip is generated at two locations on the wafer 207.

  In the figure, reference numeral 203 denotes one virtual wafer. Symbols ● are attached to positions on the virtual wafer 203 corresponding to positions (locations) where defective semiconductor chips are generated in the wafers 201, 206, and 207, respectively. That is, the position of the defective semiconductor chip in each of the wafers 201, 206, and 207 is transferred to the virtual wafer 203, and each position is reflected in the virtual wafer 203. In other words, the wafers 201, 206, and 207 are superimposed on the virtual wafer 203, and the positions of the defective semiconductor chips in each are plotted on the virtual wafer 203. In the figure, an example of the position plotted on the virtual wafer 203 is shown as 204. In the example illustrated in FIG. 2, a region 205 surrounded by a broken line is extracted as a defective frequent occurrence region in the virtual wafer 203.

  As a method for selecting wafers to be overlapped, for example, there is a method for overlapping all the wafers constituting one lot. In addition, as a selection method, a predetermined number of wafers are extracted from each of a plurality of lots manufactured during one day or each of a plurality of lots manufactured during several days, and are overlapped. It may be. In any case, each of the plurality of wafers to be overlaid on the virtual wafer 203 is a wafer that has been manufactured and has been confirmed to have a defective semiconductor chip in the presence / absence of a defect.

  Hereinafter, when simply referred to as an area, it means a defective frequent occurrence area 205. In addition, when simply referring to the area, it means the inside of the defective frequent occurrence area 205. Further, when simply described as “outside the area”, it means an area outside the defective frequent occurrence area 205.

  Next, a process of extracting a defective frequent occurrence region 205 by overlapping a plurality of wafers including defective semiconductor chips will be described with reference to FIG. In FIG. 3, the horizontal axis 301 represents the number N of stacked wafers and the number of defective semiconductor chips determined to be defective at the same position among the plurality of stacked wafers (or the number of wafers including the defective semiconductor chips). The number Pov (= P / N). Here, the defective semiconductor chip is the same F.D. B. Points that are judged as bad in the mode.

  For example, when 100 wafers are targeted, semiconductor chips at the same position between the wafers are S.D. B. If it is determined to be defective and the number is 10 (the number of wafers including the semiconductor chip determined to be defective), the ratio Pov is 1/10 (= 10/100). The maximum value of the ratio Pov shown on the horizontal axis 301 is that all the semiconductor chips at the same position have the same F.V. B. When the mode is determined to be defective, the value is 1. The ratio Pov is the position of the defective semiconductor chip in the virtual wafer (coordinates i, j), F.V. B. Calculate for each mode m. Since a plurality of wafers are overlaid on the virtual wafer, the position of the semiconductor chip on the virtual wafer corresponds to a corresponding position in each of the plurality of overlaid wafers.

  In FIG. 3, for convenience, subscripts i and j indicating the position of the defective semiconductor chip, B. The subscript m indicating the mode is omitted. In FIG. 3, the vertical axis 302 represents the occurrence frequency at each Pov value. That is, in FIG. 3, the frequency of occurrence of defects at the same position is represented by a histogram. In other words, the horizontal axis 301 (Pov) in FIG. 3 represents the defect rate in the wafer, and the vertical axis 302 represents the number of occurrences of the defect rate. Such a histogram is represented by F.R. B. Create for each mode. F. B. In the above example, the mode is S. B. Since there are three types including modes, in this embodiment, three types of histograms are created.

  In this embodiment, when the ratio Pov at which defects occur with respect to the number of stacked wafers exceeds, for example, 303 shown in FIG. The positions (locations) in the semiconductor chip having the ratio Pov exceeding the threshold value 303 are collected, and the collected area is defined as a defective frequent occurrence area 205. In FIG. 3, coordinates (subscripts) indicating the positions of defective semiconductor chips are omitted, but the positions of semiconductor chips having a ratio Pov exceeding the threshold value 303 can be grasped by referring to the subscripts. Can do.

  As described above, the threshold 303 is used as a reference, and classification is performed based on whether or not this reference is exceeded. Examples of classification are shown in FIGS. 10 and 11 show a virtual wafer 203, and the generation positions of defective semiconductor chips are plotted on the virtual wafer 203 with symbols ●. In FIG. 10, a defective semiconductor chip is generated. B. This shows a case where the ratio Pov of defective semiconductor chips occurring in the mode does not exceed the threshold value 303. That is, it shows a case where only a defect with a threshold value 303 or less has occurred.

  In contrast to FIG. 10, in FIG. 11, the positions of the semiconductor chips having the ratio Pov exceeding the threshold value 303 are plotted on the virtual wafer 203 with symbols ●. ● By collecting the positions of the semiconductor chips plotted with symbols, the positions of frequent defects that are close to each other are grouped to form a frequent defect area 205. In FIG. 11, positions of frequent failures that are not included in the frequent failure area 205 are also indicated by ● symbols. For comparison with FIG. 11, FIG. 10 also shows the defective frequent occurrence region 205 with a broken line. However, in the example of FIG. 10, there is a position of a semiconductor chip having a ratio Pov exceeding the threshold 303. Absent.

<< Extraction of out-of-range defective wafers >>
Next, extraction of a wafer having a large number of defective semiconductor chips (hereinafter referred to as an out-of-area defective chip number or an out-of-area defective semiconductor chip number) in an area outside the defective frequent occurrence area 205 (FIGS. 2 and 11) will be described. FIG. 4 is a conceptual diagram for explaining extraction of a wafer having a large number of out-of-region defective semiconductor chips.

  In FIG. 4, the horizontal axis 401 indicates the number of defective semiconductor chips that occur outside the region (the number of defective chips outside the defective region). The maximum value on the horizontal axis is the number obtained by subtracting the number of chips included in the defective frequent occurrence area 205 from the total number of chips formed on the wafer. The vertical axis 402 represents the occurrence frequency in the number of out-of-region defective chips. Here, the occurrence frequency means the number of wafers having the number of defective chips corresponding to the number of defective chips outside a certain area (excluding the number of defective chips included in the defective frequent occurrence area 205). In this embodiment, a threshold value for determining whether or not the wafer has a large number of out-of-region defective chips is shown as a threshold value 403 in FIG. Therefore, a wafer having an out-of-region defective chip number exceeding the threshold 403 is extracted as an out-of-region defective chip frequent wafer. It can be understood that FIG. 4 shows a histogram showing the occurrence frequency of out-of-area defective chips. Although it is not particularly limited, it is possible to easily grasp out-of-area defective chip frequent wafers from FIG. 4 by assigning the wafer identification number when registering it in the histogram of FIG. .

  In this way, the threshold value 403 can be used to classify whether the wafer is an out-of-region defective chip frequent wafer. Examples of wafers classified in this way are shown in FIGS. 12 and 13 show a virtual wafer 203, and the positions of defective semiconductor chips extracted by overlapping the wafers are plotted on the virtual wafer 203 with a symbol ●. In both FIG. 12 and FIG. 13, as described with reference to FIG. 3, the defective frequent occurrence region 205 is extracted and surrounded by a broken line. In FIG. 12, defective chips are also generated in the overlapped wafers in the region excluding the defective frequent occurrence region 205. For this reason, the symbol ● is also written on the virtual wafer 203 in an area excluding the defective frequent occurrence area 205 surrounded by a broken line. However, in the example of FIG. 12, the number of defective chips (• symbol) in the area excluding the defective frequent occurrence area 205 is equal to or less than the threshold value 403 that is a criterion for determining whether or not the wafer is a defective frequent defective chip wafer. Therefore, it is determined that this wafer is not an out-of-area defective chip frequent wafer. On the other hand, in FIG. 13, since the number of defective chips (● symbol) in the area excluding the defective frequent areas 205 exceeds the threshold value 403 that is a criterion for determining whether or not the wafers are frequent defective chips, out of the defective chips It is determined that the wafer is a multiple wafer and extracted.

  In FIGS. 12 and 13, the description has been given using the defective chips reflected in the virtual wafer 203, but the out-of-region defective chips are frequently generated using the manufactured wafers 201, 206, and 207 (FIG. 2) instead of the virtual wafer 203. It is possible to determine whether or not it is a wafer. In this case, the defective chips in the defective frequent occurrence area 205 are removed from the defective chips in each of the manufactured wafers 201, 206, and 207 and compared with the threshold value 403 described above.

<< Excessive defect extraction and out-of-area defect extraction processing >>
The above-described defect frequent region extraction and out-of-region defect frequent wafer extraction are performed in the defect frequent region extraction unit 40 and the out-of-region defect frequent wafer extraction unit 42 shown in FIG. FIG. 5 shows a processing flow for performing defect frequent area extraction and out-of-area defect frequent wafer extraction in these extraction units 40 and 42. Next, the processing will be described with reference to FIG. 5 showing this processing flow. In FIG. 5, on the right side, a delimiter is shown in order to distinguish between the processing steps executed by the defect frequent occurrence region extraction unit 40 and the processing steps executed by the out-of-region defect frequent occurrence wafer extraction unit 42. .

  First, in step 501, a wafer to be processed is selected. As described with reference to FIG. 2, the selection may be made for each lot, or by selecting one or a plurality of lots from a plurality of lots and selecting a plurality of lots collectively. Good.

  Step 502 includes chip superposition, F.F. B. This is a step of calculating a defect rate. The fail bit analysis result 24 is acquired from the manufacturing history database 31 shown in FIG. For each of a plurality of selected wafers, for each semiconductor chip disposed at the same position in each wafer, F.M. B. The defect rate Pov is calculated for each mode. Targeting the position (i, j) of the semiconductor chip on the wafer, the F.F. B. When the number of defective chips in mode m is N (i, j, m) and the number of stacked wafers is M (for example, the number of wafers included in one lot), the defect rate Pov (i, j, m) is Equation (1) is obtained. F. B. The number of defective chips in mode m can be acquired from the fail bit analysis result 24.

Pov (i, j, m) = N (i, j, m) / M (1)
Step 503 is a step of creating a histogram based on the obtained defect rate Pov (i, j, m). The histogram is F.D. B. Create for each mode. The threshold value 303 shown in FIG. B. Set for each mode. The threshold value is determined in advance and registered in the setting information 44 of FIG. The registered threshold value is acquired from the setting information 44 in step 503.

  In step 504, a comparison is made between the threshold value 303 and the defect rate Pov (i, j, m) at each position (i, j) of the plurality of semiconductor chips on the virtual wafer.

  Either F. B. In mode m, if there is a failure rate Pov (i, j, m) greater than threshold 303, failure frequent flag FFlag (i, j) is set to 1 (step 505). On the other hand, all F.I. B. In mode m, if the defect rate Pov (i, j, m) ≦ threshold 303, the failure frequent flag FFlag (i, j) is set to 0 (step 506). That is, a frequent failure flag FFlag (i, j) corresponding to the position (i, j) of the chip is provided, and the corresponding frequent failure flag FFlag (i, j) is set according to whether or not the position is frequent failure. Set. Next, in step 507, the sum of defective frequent occurrence flags FFlag (i, j) (the sum of set 1) is taken for the area where chips exist on the wafer, and the sum is set as Fcount.

  Using this total Fcount, in step 508, the chip position (i, j) in the defective frequent occurrence area 205 and the Pchip (i, j, m) of the defective mode (FB mode) m are calculated. Pchip (i, j, m) is obtained by equation (2).

Pchip (i, j, m) = N (i, j, m) / Fcount (2)
In FIG. 5, subscripts i, j, and m of Pchip are omitted for convenience.

  The obtained Pchip (i, j, m) is F.F. for each position of the semiconductor chip on the wafer. B. It represents the defective chip rate in the defective frequent occurrence region for each mode.

  In step 509, chips belonging to (included in) the defective frequent occurrence area are extracted. This can be done by listing the position (i, j) of the semiconductor chip on the wafer where the frequent failure flag FFlag (i, j) = 1. The defect frequent occurrence flag FFlag (i, j) B. Regardless of the type of mode m, if the defect rate Pov at the position (i, j) exceeds the threshold value 303, 1 is set, but from the position (i, j), a defect is detected. Since it is possible to determine the mode, F. B. It is also possible to list for each mode m.

  After listing up, for example, the defect frequent occurrence area may be determined visually, or a threshold value is set for the distance between defective chips, and if it falls within the defined threshold value, the defect constituting the defect frequent occurrence area You may determine with frequent occurrence.

  In step 510, the F.F. B. The defect rate Pwafer for each mode is calculated.

  For the semiconductor chip position (i, j) outside the frequent defect area, B. The sum of the number of defective semiconductor chips (i, j, m) generated in mode m is defined as Fout (m). Assuming that the number of all semiconductor chips formed on the wafer is T, the F.F. B. The defect rate Pwafer (m) for each mode is expressed by the following equation (3).

Pwafer (m) = Fout (m) / (T-Fcount) (3)
This defect rate Pwafer (m) is obtained for each wafer. F.F. B. Ask for each mode. In step 511, a histogram is created using Pwafer (m) obtained for each wafer. That is, the number of generated wafers having a certain defect rate Pwafer (m) is integrated for each occurrence, the frequency is obtained, and a histogram as shown in FIG. 4 is created. This histogram is shown in FIG. B. Created for each mode.

  In step 512, F.R. B. The threshold value 403 set for each mode is compared with the magnitude of Pwafer (m) in the histogram. If Pwafer (m)> threshold 403, the wafer is extracted as a wafer with frequent out-of-region defects (step 513), and the process ends. If Pwafer (m) ≦ threshold, the process is terminated as it is. The threshold value 403 used here is also determined in advance and stored in the setting information 44 (FIG. 1).

  Steps 501 to 509 described above are performed by the failure frequent occurrence region extraction unit 40 shown in FIG. 1, and steps 510 to 513 are executed by the out-of-region failure frequent occurrence wafer extraction unit 42 shown in FIG. . The above steps are achieved, for example, by executing a program by a computer.

<Example of analysis result output>
FIG. 6 shows an example of a result of performing failure analysis using the above-described failure frequent region extraction unit 40 and out-of-region failure frequent wafer extraction unit 42. Although not particularly limited, the input / output unit 45 shown in FIG. 1 is provided with a display device, and the image of FIG. 6 is displayed on the screen of the display device.

  The display device screen is roughly divided into three display fields. In the figure, the layer-specific defect density 601 in the defective frequent occurrence area 205 is displayed in the display field in the upper central area. Further, the defect density 602 by layer in the area outside the frequent defect area is displayed in the display column in the lower center area. The defect density 601 and 602 for each layer is represented by a bar graph shape in which the defect density is clearly specified for each layer and the defect densities for each layer are stacked. In FIG. 6, a legend 603 indicating how to display each layer is displayed in the display field in the lower right area.

  In the bar graph representing the defect density by layer (defect density by layer within area) 601 in the defective frequent occurrence area, the horizontal axis 604 indicates the lot_wafer number. For example, a lot_wafer number is composed of a lot number and a wafer number in the lot. Here, when extracting the defective frequent occurrence area 205, lot_wafer numbers of a plurality of superimposed wafers are arranged. On the other hand, the vertical axis 605 represents the defect density in the defective frequent occurrence region. That is, for the wafer specified by the lot_wafer number on the horizontal axis, the defect density of each layer in the defective frequent occurrence area is displayed in a stacked form.

  Similarly for the defect density by layer (defect density by layer outside area) 602 in the area outside the frequent defect area, the horizontal axis 606 indicates the lot_wafer number. On the other hand, the vertical axis 607 represents the defect density in a region outside the defective frequent occurrence region 205. That is, the defect density of each layer in the area outside the defective occurrence area is displayed in a piled-up form with respect to the wafer specified by the lot_wafer number on the horizontal axis.

  In this embodiment, when stacking the defect density of each layer (layer), the layers (layers) in the semiconductor wafer and the layers of defect density to be stacked are arranged in the same order. That is, the order of the stacked defect density layers is the same as the layer order from bottom to top in the wafer. In this embodiment, the rod_wafer number in the in-region layer-by-layer defect density 601 and the rod_wafer number in the out-of-region layer-by-region defect density 602 are arranged in the same order. This facilitates comparison and reference between the defect density in the region and the defect density outside the region for the wafers having the same lot_wafer number. In addition, it becomes easy to grasp the relationship between the layers formed on the wafer and the stacked defect density.

  The defect density for each layer described here can be obtained by the calculation by the layer-specific particle defect rate calculation unit 41 shown in FIG. The defect density for each layer obtained by this calculation is determined in the defect frequent occurrence area 205 extracted by the defect frequent occurrence area extraction unit 40 (FIG. 1) and the area excluding this defect frequent occurrence area 205 (area outside the defect frequent occurrence area). Further, it is obtained for each rod_wafer number displayed as shown in FIG. Thereby, the defect density for every layer can be calculated | required for every rod_wafer number with respect to each in the defect frequent occurrence area | region and the area | region outside it.

<Application example>
FIG. 8 is a block diagram showing a process for monitoring a defect occurrence state in a semiconductor manufacturing line. In the figure, reference numeral 801 denotes a wafer processing step for processing a semiconductor wafer, and reference numeral 802 denotes a probe test step 802 for performing a probe test on the semiconductor wafer after the wafer processing step 801 is completed. In FIG. 8, reference numeral 803 denotes a sorting / assembling process for sorting the supplied semiconductor wafers through the probe test process 802 and assembling the semiconductor devices.

  In the wafer processing step 801, various processes are performed on the semiconductor wafer by various manufacturing apparatuses included in the semiconductor manufacturing apparatus 12 of FIG. For example, as described with reference to FIG. 1, a film formation process using a CVD apparatus, an etching process using an etching apparatus, and the like are performed on a semiconductor wafer, and a plurality of semiconductor chips are formed on the semiconductor wafer. In this wafer processing step 801, a circuit including a memory portion is formed on the semiconductor chip according to the layout information.

  In the probe test step 802, a circuit formed on the wafer is tested, and the test result is stored in the manufacturing history database 31. A test is also performed on memory portions of a plurality of semiconductor chips formed on the wafer. In this test, the quality of the operation of the memory element in each memory portion is tested. B. The data is stored in the manufacturing history database 31 as the fail bit analysis result 24. In this case, F. of all memory portions in the total number of wafers. B. Although it is preferable if the data can be stored in the manufacturing history database 31, some wafers may be extracted and the results may be stored. F. stored. B. The fail bit analysis result 24, which is data, is supplied to the defective frequent region extracting unit 40 and the out-of-region defective frequent wafer extracting unit 42, and the processing described in FIG. 5 is performed.

  By performing the processing of FIG. 5, the display screen as described in FIG. 6 or the display screen of FIG. 7 described later is provided to the user. The semiconductor production line is monitored 804 by the user confirming these display screens. For example, by confirming the display contents shown in FIG. 6, it is possible to monitor the transition of the defect density by layer in the region and / or outside the region in the order of lot_wafer. In the confirmation, when the stack height of the defect density by layer within or outside the area suddenly increases, when it gradually increases, or when the stack height is high at regular intervals It can be estimated that an abnormality has occurred in the semiconductor manufacturing line 10 (FIG. 1).

  When the state change as illustrated above cannot be confirmed from the contents displayed in FIG. 6 and the like, it is estimated that no abnormality has occurred in the semiconductor manufacturing line 10 and is stored in the manufacturing history database 31 every day. . B. Monitoring of the production line is continued on the display screen (FIG. 6, etc.) displayed based on the data (displayed as “no problem” in FIG. 8).

  If the state change as illustrated above can be confirmed, it is estimated that there is a problem, and countermeasure 805 is performed. In the countermeasure 805, for example, the value and / or change of the defect density is observed for each layer. Thereby, for example, in a specific layer among a plurality of layers, the defect density suddenly increases, gradually increases, or shows a large value at a certain interval. If there is, it is found that the defect density has changed due to the layer, and countermeasures are taken.

  Further, in the process of monitoring 804, the wafer having the most characteristic change in defect density is found (extracted) using FIG. 6 and FIG. 7 described later, and the defect situation is physically analyzed for the found wafer. It is used as a wafer for this purpose. In this way, it is possible to significantly reduce the time and man-hours for selecting a wafer to be subjected to physical analysis and / or specifying an analysis location on the physical analysis target wafer, and speeding up the process of the countermeasure 805. Efficiency can be improved. In the process of the countermeasure 805, the history of the semiconductor manufacturing apparatus, the photomask, the chemicals used for manufacturing, etc. is examined centering on the corresponding layer using the result of physical analysis, etc., and the cause of the defect is searched.

  In FIG. 8, reference numeral 806 denotes a failure analysis unit. Although the failure analysis unit 30 is also shown in FIG. 1, the failure cause investigation unit 43 and the layer-specific foreign matter failure rate calculation unit 41 are omitted from the failure analysis unit 30 shown in FIG. Assigned to the failure analysis unit.

  According to the embodiment, the defects in the semiconductor wafer are classified into a regional defect concentrated in a specific area and a random defect. In particular, a regional defect is extracted as a position (semiconductor chip) where a plurality of semiconductor wafers are virtually overlapped and defects are frequently generated in the plurality of semiconductor wafers. Further, random defects are extracted in units of semiconductor wafers, except for regional defects. In this case, a semiconductor wafer having many random defects is extracted as an out-of-region defective wafer. In this way, by separating and grasping the region defect and the random defect, it becomes possible to examine and adopt measures suitable for each.

  Further, for example, it is possible to quickly improve the manufacturing yield from the initial stage of manufacturing by eliminating the domain defect at an early stage of new development. For example, since it is conceivable that the defect in the region depends on the manufacturing apparatus (manufacturing conditions), it is desirable to take measures against the manufacturing apparatus from the initial stage of manufacturing. With regard to random defects, it is possible to analyze the cause of the defect except for the area defect, and it is also possible to facilitate measures against the cause.

  It is also conceivable to extract the poor regionality based on a prediction that the occurrence thereof is, for example, a large number of concentric circles. However, it may fall into a predicted or unexpected state. On the other hand, in the embodiment, a plurality of semiconductor wafers are overlapped, and a regional defect is estimated based on the frequency of occurrence of a failure at the same position of the plurality of semiconductor wafers. In other words, it is possible to statistically extract a regional defect using a plurality of semiconductor wafers, to improve the accuracy of the extraction of the regional defect, and to improve the analysis accuracy. It is possible.

  In the embodiment, the failure is detected based on the fail bit. The distribution of fail bits varies and cannot be predicted in advance. However, regardless of the distribution of fail bits, it is possible to separate random defects and regional defects.

  Further, the defect rate for each process is estimated by dividing the defect into a region defect and a random defect. As a result, the accuracy of the estimation result can be improved. In the embodiment, after extracting the regional defect as a defective frequent occurrence region, a wafer having a large number of defective chips outside the frequent defective region is extracted, and each of the extracted frequent defective region and out-of-region defective frequent wafers is classified by process. It is possible to estimate and compare defect density and yield.

  In the early stage of the process start-up of semiconductor products, not only random defects but also defects with regional characteristics cannot be improved unless measures are taken. In the embodiment, since it is possible to grasp the distribution of regional defects and defects occurring there, it is possible to improve the yield quickly.

  Using the layout information, which is design information, and the fail bit test result, it is possible to infer the occurrence of defects in the process of forming a chip on a semiconductor wafer, the so-called previous process, and consign production to a third party. It is also useful in terms of management of the previous process.

(Embodiment 2)
In addition to the display screen (FIG. 6) described in the first embodiment, a display screen as shown in FIG. 7 is added. Of course, the display of the display screen shown in FIG. 6 may be stopped, and only the display screen shown in FIG. 7 may be provided. As will be described below, by providing the display screen shown in FIG. 7, it becomes possible to investigate the cause of defects of individual semiconductor wafers in more detail.

  FIG. 7 shows an example of a display screen displayed by the display device provided in the input / output unit 45 shown in FIG. The display screen shown in FIG. 7 is roughly divided into five display fields. That is, in FIG. 7, a display column for displaying the defect frequent occurrence region map 701 is provided in the upper left region, and a display column for displaying the stacked bar graph 717 of the defect density by layer is provided in the lower left region. ing. In FIG. 7, a display field for displaying lot_wafer number 716 is provided in the upper right area, and the area F.D. B. A display field for displaying the mode-specific map 702 is provided. B. A display field for displaying the mode-specific map 703 is provided.

  The defect frequent occurrence area map 701 displayed in the upper left area is obtained by mapping the semiconductor chip extracted as FFlag = 1 in step 509 in FIG. 5 onto a circle image indicating the shape of the wafer. . In this embodiment, a defective frequent occurrence region is surrounded by a broken line. The lot_wafer number 716 displayed in the upper right area is a number for specifying the lot to which the target semiconductor wafer belongs and the wafer in the lot.

  In the defect frequent occurrence area displayed in the display field below the display field for displaying the lot_wafer number 716. B. The mode-specific map 702 includes F.I. B. For each mode, the position of the defective semiconductor chip on the wafer is mapped and displayed. In the embodiment, F.I. B. Since there are three types of modes, three maps are displayed as F. B. It is displayed on the map 702 by mode. That is, in the defective frequent occurrence region, S.I. B. The position of the semiconductor chip that is defective in the mode in the wafer is mapped onto the wafer shape (circular). B. It is displayed as a map 705. Similarly, in the defective frequent occurrence region, W.W. L. The position of the semiconductor chip that is defective in the mode is W.W. L. Displayed as map 706; L. The position of the semiconductor chip that is defective in the mode is shown in FIG. L. It is displayed as a map 707. In these maps, a broken line is displayed so as to surround the defective frequent occurrence area.

  In-region F. B. F. Out of defective frequent occurrence area displayed in the display field on the lower side (lower right) of the area where the map 702 for each mode is displayed. B. In the map 703 for each mode, the F.F. B. The distribution of defective semiconductor chips by mode is S.D. B. Map 708, W.W. L. Map 709, B.I. L. Displayed as a map 710. Here, S.M. B. In the map 708, S.D. B. The position of the semiconductor chip that is defective in the mode is mapped on the wafer shape. Similarly, W.W. L. In the map 709, W.P. L. B. The position of the semiconductor chip that is defective in the mode is mapped. L. The map 710 includes B.I. L. The position of the semiconductor chip that is defective in the mode is mapped. These S.P. B. Map 708, W.W. L. Map 709 and B.I. L. Each of the maps 710 is not particularly limited, but a defective frequent occurrence region is surrounded by a broken line.

  In addition, out-of-region F.R. B. In the mode-specific map 703, if the wafer displayed in the map 703 corresponds to a wafer determined to have frequent out-of-region defects in the process 513 in FIG. A display field for displaying the frequent occurrence flag 704 is provided.

  In-region F. B. The semiconductor wafer displayed by the mode-specific map 702 and the out-of-region F.R. B. The semiconductor wafers displayed by the mode-specific map 703 are the same wafer, and the specification is specified by the number displayed in the lot_wafer number 716. For the same semiconductor wafer, F.D. B. Map by mode and F.F. B. Since the maps for each mode are displayed, it is desirable that the maps for each mode (705 to 707) and the maps for each mode (708 to 710) are arranged in the same manner from the viewpoint of easy viewing. As an example, as shown in FIG. 7, it arrange | positions up and down and makes the order the same.

  In the stacking bar graph 717 of defect density by layer displayed in the display field at the lower left of FIG. 7, the horizontal axis 711 is in the failure frequent occurrence region (region), the region outside the failure frequent occurrence region (outside region), the region -It is divided into three areas outside the area. The vertical axis 712 indicates the defect density. In the portion within the failure frequent occurrence region divided on the horizontal axis 711, the defect density for each layer is piled up for the layers in the failure frequent occurrence region, and a piled bar graph 713 is formed. Similarly, in the area outside the defective frequent occurrence area, the layer defect density of the layer in the area outside the frequent defective area is indicated by a stacked bar graph 714. In the region outside the region divided by the horizontal axis 711, the difference between the defect density for each layer in the defective frequent occurrence region and the defect density for each layer in the region outside the frequent frequent failure region is shown by a stacked bar graph 715. Yes. Regarding the difference between the defect density inside and outside the area, if the layer is a, the defect density in the area in the layer a is Da_out, and the defect density outside the area in the layer a is Da_in, the inside of the area related to the layer a Assuming that Da_d is a difference (defect density difference) outside the region, the following equations (4) and (5) are used.

When Da_out ≧ Da_in, Da_d = 0 Expression (4)
When Da_out <Da_in, Da_d = Da_in−Da_out (5)
The layer-by-layer defect density display 717 shown in FIG. 7 may be displayed in the form of a component ratio of the layer-by-layer defect density by standardizing a height obtained by stacking the defect densities in each section to 1.

  Further, in the stacked bar graphs shown in FIGS. 6 and 7, the different layers are indicated by hatching.

  In the display screen of FIG. 6, a plurality of wafers can be compared and considered. On the other hand, in FIG. 7, the appearance pattern of the defective semiconductor chip can be confirmed for one wafer. For example, an analysis wafer is selected using FIG. 6, and the display as shown in FIG. 7 is performed on the selected analysis wafer. This makes it possible to investigate the cause of the defect in more detail.

(Embodiment 3)
In addition to analyzing and monitoring the cause of defects, it is also possible to confirm the effect after taking measures against defects (defects).

  FIG. 9 is a block diagram showing processing for confirming the effect of defect countermeasures in the semiconductor manufacturing line 10 (FIG. 1). The embodiment shown in FIG. 8 is similar to the embodiment shown in FIG. Therefore, differences from FIG. 8 will be mainly described.

  As described with reference to FIG. 8, after the processing of the wafer processing step 801 is completed, the semiconductor wafer is sent to the sorting / assembly step 803 through the probe test step 802. In the probe test process, the operation of the memory element portion is tested for goodness. B. The data is stored in the manufacturing history database 31 as data. F. stored. B. The data is processed by the defect frequent area extraction unit 40 and the out-of-area defect frequent wafer extraction part 42 in accordance with the process shown in FIG. 5, and is provided to the user on the display screens as shown in FIGS.

  In FIG. 7, for each wafer, defective chips inside and outside the defective frequent occurrence area are F.D. B. Visualized for each mode. In addition, the defect density by layer inside and outside the region is also visualized. In the monitoring 804 in FIG. 8, when an abnormality (state change) is detected, a defect occurrence state is recorded based on FIG. 7 for the wafer in which the abnormality has occurred.

  A countermeasure 805 corresponding to the recorded defect occurrence state is performed on the wafer processing step 801. After the countermeasure 805 is performed, the probe test 802 is performed on the wafer processed in the wafer processing step 801, and the F.F. B. Data is acquired and the defect occurrence status based on FIG. 7 is confirmed. Whether the defect density for each layer has been reduced or the shape of the defective frequent occurrence region has changed before and after the countermeasure 805 has been performed in this way is performed in the step of effect confirmation 901. In the step of effect confirmation 901, if the defect density by layer is reduced or the defect occurrence area is reduced, it can be confirmed that the countermeasure is successful. On the other hand, if the defect density by layer is not reduced and the defect occurrence area is not reduced, the countermeasure is not effective, so it is found that it is necessary to plan and implement another countermeasure separately. To do.

  That is, it is possible to confirm the effects after implementing measures such as process changes and machining condition changes. For example, the defect rate for each layer before and after the countermeasure is compared in the step of effect confirmation 901. If the defect rate of the layer targeted for the countermeasure is reduced, it can be determined that the countermeasure is effective. If there is no change in the defect rate, it can be determined that the implemented countermeasure has no effect, and another countermeasure is taken. As another countermeasure, there are further changes in the process and further changes in the processing conditions. That is, the conditions in the manufacturing process used for manufacturing are changed. In other words, it can be grasped as a method for manufacturing a semiconductor integrated circuit device in which the manufacturing conditions used in the manufacturing process are changed.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention.

For example, the in-region layer defect density 601 and the out-of-region layer defect density 602 shown in FIG. 6 may be represented as an in-region layer defect rate 601 and an out-of-region layer defect rate 602, respectively. In this case, the defect densities 605 and 607 on the vertical axis indicate the defect rates 605 and 607, respectively.
Display screen (display graph). The defect rate is obtained from the above defect density. Similarly, the stacked bar graph 717 of the defect density by layer displayed in the lower left display column of FIG. 7 may be the stacked bar graph 717 of the defect rate by layer. In this case, the vertical axis 712 represents the failure rate.

24 Fail bit analysis result 31 Manufacturing history database 40 Defect occurrence area extraction unit 42 Out-of-area defect occurrence wafer extraction section 44 Setting information 45 Input / output unit

Claims (10)

A semiconductor in which the plurality of semiconductor chips are formed on each of the plurality of wafers by applying a plurality of processing steps in time series to each of the plurality of wafers on which the plurality of semiconductor chips are formed. A management method used in a manufacturing apparatus,
A multiple region extraction step of extracting a plurality of regions in a wafer in which defective semiconductor chips are frequently generated using the plurality of wafers;
An extraction step of extracting a region excluding the frequent occurrence region from each of the plurality of wafers;
Comprising
A management method used in a semiconductor manufacturing apparatus, wherein the occurrence of a defect in the plurality of processing steps is estimated based on the frequent occurrence region extracted in the frequent occurrence region extraction step and the region extracted in the extraction step. In the management method used for the semiconductor manufacturing apparatus according to claim 1,
The extraction step is used for a semiconductor manufacturing apparatus, comprising a wafer extraction step of extracting, from the plurality of wafers, a wafer in which the number of defective semiconductor chips in a region excluding the frequent occurrence region is greater than a first value. Management method. In the management method used for the semiconductor manufacturing apparatus according to claim 2,
Each of the plurality of semiconductor chips includes a region where a memory is formed,
The management method used in the semiconductor manufacturing apparatus includes a failure determination step of determining a memory failure in the plurality of semiconductor chips in each of the plurality of wafers,
A management method used in a semiconductor manufacturing apparatus, wherein when a defect in a memory is determined in the defect determination step, a semiconductor chip including the memory is determined as a defective semiconductor chip. In the management method used for the semiconductor manufacturing apparatus according to claim 3,
The management method used for a semiconductor manufacturing apparatus, wherein the semiconductor manufacturing apparatus forms the plurality of semiconductor chips on each of a larger number of wafers than the plurality of wafers by applying the plurality of processing steps. In the management method used for the semiconductor manufacturing apparatus according to claim 3,
The management method used for the semiconductor manufacturing apparatus is:
A management method used in a semiconductor manufacturing apparatus, comprising: a display step of displaying an image clearly showing the frequent occurrence region and an image specifying a wafer extracted in the wafer extraction step. In the management method used for the semiconductor manufacturing apparatus according to claim 3,
The management method used in the semiconductor manufacturing apparatus includes a calculation step of calculating a defect rate for each of the plurality of layers formed on each of the plurality of wafers,
Management used in a semiconductor manufacturing apparatus that estimates the occurrence of defects in the plurality of processing steps based on the defect rate for each layer in the frequent occurrence region and the failure rate for each layer in the region extracted by the extraction step Method. A manufacturing process of forming the plurality of semiconductor chips on each of the plurality of wafers by applying a plurality of processing steps in time series to each of the plurality of wafers on which the plurality of semiconductor chips are formed. ,
A multiple region extraction step of extracting a plurality of regions in a wafer in which defective semiconductor chips are frequently generated using the plurality of wafers;
An extraction step of extracting a region excluding the frequent occurrence region from each of the plurality of wafers;
Based on the multiple regions extracted by the multiple region extraction step and the regions extracted by the extraction step, the manufacturing process conditions used when forming the plurality of semiconductor chips on each of the plurality of wafers are changed. Change process to
A method for manufacturing a semiconductor integrated circuit device, comprising: In the manufacturing method of the semiconductor integrated circuit device according to claim 7,
In the semiconductor integrated circuit device, the extraction step includes a wafer extraction step of extracting, from the plurality of wafers, a wafer in which the number of defective semiconductor chips in a region excluding the frequent occurrence region is greater than a first value. Production method. The method of manufacturing a semiconductor integrated circuit device according to claim 8.
Each of the plurality of semiconductor chips includes a region where a memory is formed,
The manufacturing method of the semiconductor integrated circuit device includes a failure determination step of determining a memory failure in the plurality of semiconductor chips in each of the plurality of wafers,
A method of manufacturing a semiconductor integrated circuit device, wherein when a defect in a memory is determined in the defect determination step, a semiconductor chip including the memory is determined as a defective semiconductor chip. In the manufacturing method of the semiconductor integrated circuit device according to claim 9,
The manufacturing method of the semiconductor integrated circuit device includes a calculation step of calculating a defect rate for each of the plurality of layers formed on each of the plurality of wafers,
The changing step estimates the occurrence of defects in the plurality of processing steps based on the defect rate for each layer in the frequent occurrence region and the defect rate for each layer in the region extracted by the extraction step. A method for manufacturing a semiconductor integrated circuit device, wherein the conditions of the above are changed.

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