JP2014220438A - Multilayer ceramic substrate and manufacturing method therefor - Google Patents

Multilayer ceramic substrate and manufacturing method therefor Download PDF

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JP2014220438A
JP2014220438A JP2013099772A JP2013099772A JP2014220438A JP 2014220438 A JP2014220438 A JP 2014220438A JP 2013099772 A JP2013099772 A JP 2013099772A JP 2013099772 A JP2013099772 A JP 2013099772A JP 2014220438 A JP2014220438 A JP 2014220438A
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cavity
ceramic
insulating layer
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via conductors
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JP6118170B2 (en
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隆幸 宮路
Takayuki Miyaji
隆幸 宮路
貞浩 西村
Teiko Nishimura
貞浩 西村
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Niterra Co Ltd
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K3/46Manufacturing multilayer circuits

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Abstract

PROBLEM TO BE SOLVED: To provide a multilayer ceramic substrate having a plurality of continuous via conductors penetrating a plurality of ceramic layers coaxially in the thickness direction, and insulating only the continuous via conductors not requiring conduction, where the dimensions and shape of the substrate body are accurate, and to provide a manufacturing method capable of obtaining a multilayer ceramic substrate surely at a relatively low cost.SOLUTION: A multilayer ceramic substrate 1a includes a substrate body 2a laminating a plurality of ceramic layers 3-5, and a plurality of continuous via conductors 12 penetrating a plurality of adjacent ceramic layers 3-5 coaxially in the thickness direction in the substrate body 2a. At least one of the continuous via conductors 12 is insulated by a ceramic-based insulation layer 20 located between a plurality of ceramic layers 4, 5 adjacent in the continuous via conductors 12. Such an insulation layer 20 is located in a gap 13s within the wiring layer 13 formed between adjacent ceramic layers 4, 5, or in a gap 13g between a plurality of wiring layers 13.

Description

本発明は、複数のセラミック層を厚み方向に沿って同軸状に貫通する複数の連続ビア導体を有する多層セラミック基板およびその製造方法に関する。   The present invention relates to a multilayer ceramic substrate having a plurality of continuous via conductors that pass through a plurality of ceramic layers coaxially along the thickness direction and a method for manufacturing the same.

例えば、セラミック層を貫通するビア導体を有するセラミック基板の製造工程においては、表面および裏面の少なくとも一方に配線層が予め形成されたグリーンシートに対し、専用の金型に配設された複数本のポンチにより、複数のビアホールを所要の位置ごとに穿孔している。ところで、異なるパターンのビア導体を含むセラミック基板を製造するたびに、専用の金型を用意していると、金型コストおよび得られるセラミック基板のコストが上昇する、という問題点があった。
前記問題点を解決し、可及的にビアホール穿孔用の金型を共通化し、コストダウンを図り、保守管理を容易にするべく、共通化した金型における複数のポンチによりグリーンシートに複数のビアホールを穿孔し、該ビアホール内ごとに導体ペーストを充填して穴埋めした後、上下層の配線層同士の導通が不要となる位置ごとの導体ペーストを選択し、該導体ペーストの上下端の露出面を、グリーンシートの表面または裏面に形成する絶縁層により被覆して、非導通状態とする多層配線セラミック基板の製造方法が提案されている(例えば、特許文献1参照)。
For example, in a manufacturing process of a ceramic substrate having a via conductor that penetrates a ceramic layer, a plurality of wires disposed in a dedicated mold are disposed on a green sheet in which a wiring layer is previously formed on at least one of the front surface and the back surface. A plurality of via holes are drilled at required positions by punches. By the way, if a dedicated mold is prepared each time a ceramic substrate including via conductors with different patterns is manufactured, there is a problem that the mold cost and the cost of the obtained ceramic substrate increase.
In order to solve the above-mentioned problems and to make the via hole drilling die as common as possible, to reduce costs, and to facilitate maintenance management, a plurality of via holes are formed in the green sheet by a plurality of punches in the common die. After filling and filling the conductor paste in each via hole, select the conductor paste for each position where conduction between the upper and lower wiring layers is unnecessary, and expose the exposed surfaces at the upper and lower ends of the conductor paste. There has been proposed a method of manufacturing a multilayer wiring ceramic substrate that is coated with an insulating layer formed on the front surface or the back surface of a green sheet so as to be in a non-conductive state (see, for example, Patent Document 1).

前記多層配線セラミック基板の製造方法では、複数のビアホール内に充填された導体ペーストを有するグリーンシートの表面または裏面の少なくとも一方に、上下層の配線層同士の導通が不要となる位置の導体ペーストの露出面を覆い、且つかかる導通が必要となる位置ごとの導体ペーストの端面を露出させるように、上記グリーンシートの表面または裏面のほぼ全面に前記絶縁層を形成している。
しかし、上記のように、グリーンシートのほぼ全面にわたり絶縁層を形成した場合、得られる多層配線セラミック基板全体の厚みが増加し、薄肉化ないし小型化の要請に逆行すると共に、前記導通が必要な導体ペーストの露出する端面ごとに開口する多孔状の前記絶縁層を、上記グリーンシートの表面または裏面のほぼ全面に形成することは、その製造工程が煩雑化する、という問題点があった。
In the manufacturing method of the multilayer wiring ceramic substrate, the conductive paste at a position where conduction between the upper and lower wiring layers is not required on at least one of the front and back surfaces of the green sheet having the conductive paste filled in the plurality of via holes. The insulating layer is formed on almost the entire front surface or back surface of the green sheet so as to cover the exposed surface and expose the end surface of the conductive paste for each position where conduction is required.
However, as described above, when the insulating layer is formed over almost the entire surface of the green sheet, the thickness of the entire multilayer wiring ceramic substrate is increased, which is contrary to the demand for thinning or miniaturization, and the conduction is necessary. Forming the porous insulating layer that opens at every exposed end surface of the conductive paste on almost the entire surface of the green sheet has the problem that the manufacturing process becomes complicated.

特開2006−291463号公報(第1〜6頁、図1〜6)JP 2006-291463 A (pages 1 to 6, FIGS. 1 to 6)

本発明は、背景技術で説明した問題点を解決し、複数のセラミック層を厚み方向に沿って同軸状に貫通する連続ビア導体を複数個有し、導通が不要な連続ビア導体のみを絶縁し、且つ基板本体の寸法および形状が正確な多層セラミック基板、および該多層セラミック基板を比較的低コストにより確実に得られる製造方法を提供する、ことを課題とする。   The present invention solves the problems described in the background art, has a plurality of continuous via conductors that pass through a plurality of ceramic layers coaxially along the thickness direction, and insulates only the continuous via conductors that do not require conduction. It is another object of the present invention to provide a multilayer ceramic substrate in which the dimensions and shape of the substrate body are accurate, and a manufacturing method capable of reliably obtaining the multilayer ceramic substrate at a relatively low cost.

課題を解決するための手段および発明の効果Means for Solving the Problems and Effects of the Invention

本発明は、前記課題を解決するため、厚み方向に隣接するセラミック層ごとを貫通する単位ビア導体同士の接続部付近で且つ前記セラミック層間に位置する配線層内の隙間などに絶縁層を形成する、ことに着想して成されたものである。
即ち、本発明の多層セラミック基板(請求項1)は、複数のセラミック層が積層された基板本体と、該基板本体において、隣接する複数のセラミック層を厚み方向に沿って同軸状に貫通する複数の連続ビア導体と、を備えた多層セラミック基板であって、上記連続ビア導体の少なくとも1つは、該連続ビア導体において隣接する上記複数のセラミック層間に位置するセラミック系の絶縁層により絶縁されていると共に、かかる絶縁層は、隣接する上記セラミック層間に形成された配線層内の隙間、あるいは、複数の配線層同士間の間隙に位置している、ことを特徴とする。
In order to solve the above-mentioned problem, the present invention forms an insulating layer in the vicinity of the connecting portion between unit via conductors that penetrate through the ceramic layers adjacent in the thickness direction and in a gap in the wiring layer located between the ceramic layers. , It was conceived.
That is, the multilayer ceramic substrate of the present invention (Claim 1) includes a substrate main body on which a plurality of ceramic layers are laminated, and a plurality of adjacent ceramic layers penetrating coaxially along the thickness direction in the substrate main body. A plurality of continuous via conductors, wherein at least one of the continuous via conductors is insulated by a ceramic insulating layer located between the plurality of adjacent ceramic layers in the continuous via conductor. In addition, the insulating layer is characterized in that it is located in a gap in a wiring layer formed between adjacent ceramic layers or in a gap between a plurality of wiring layers.

これによれば、複数のセラミック層を同軸状に貫通する複数の前記連続ビア導体のうち、導通が不要な連続ビア導体は、該ビア導体が貫通する配線層内の隙間、あるいは隣接する複数(2以上)の配線層間の隙間に形成されたセラミック系の絶縁層によって、電気的に絶縁されている。しかも、上記絶縁層は、厚み方向で隣接する2層のセラミック層間に配設された配線層の内側に位置する隙間、あるいは同じセラミック層間に隣接する複数の配線層同士間の隙間に形成されている。そのため、共通の金型によって複数の連続ビア導体が複数のセラミック層の厚み方向に沿って形成され、これらのうち導通が不要な連続ビア導体は、前記絶縁層により絶縁されていると共に、該絶縁層は、前記何れかの隙間に形成されているので、基板本体の表面や裏面に凹みなどの悪影響が生じにくくされている。
従って、複数のセラミック層を厚み方向に沿って同軸状に貫通する連続ビア導体を複数個有し、導通が不要な連続ビア導体のみを絶縁していると共に、基板本体の寸法および形状が正確な多層セラミック基板となっている。
According to this, among the plurality of continuous via conductors that pass through the plurality of ceramic layers coaxially, a continuous via conductor that does not require conduction is a gap in the wiring layer through which the via conductor passes or a plurality of adjacent via conductors ( (2 or more) is electrically insulated by a ceramic insulating layer formed in a gap between wiring layers. Moreover, the insulating layer is formed in a gap located inside the wiring layer disposed between two ceramic layers adjacent in the thickness direction, or a gap between a plurality of wiring layers adjacent in the same ceramic layer. Yes. Therefore, a plurality of continuous via conductors are formed along the thickness direction of the plurality of ceramic layers by a common mold, and the continuous via conductors that do not require conduction among them are insulated by the insulating layer and the insulating layers. Since the layer is formed in any one of the gaps, it is difficult for adverse effects such as dents to occur on the front and back surfaces of the substrate body.
Therefore, a plurality of continuous via conductors that pass through a plurality of ceramic layers coaxially along the thickness direction are insulated, and only the continuous via conductors that do not require conduction are insulated, and the size and shape of the substrate body are accurate. It is a multilayer ceramic substrate.

尚、前記セラミックは、例えば、アルミナ、ムライト、窒化アルミニウムなどの高温焼成セラミックのほか、低温焼成セラミックの一種であるガラスーセラミックも含む。
また、前記絶縁層は、前記セラミックと同じか、該セラミックと第1成分が同じである同種のセラミック、あるいは、第1成分が異なる異種のセラミックであるほか、これらのセラミックを主成分として含有するものも含まれる。
更に、前記連続ビア導体が複数のセラミック層を同軸状に貫通するとは、隣接するセラミック層間において、個々の単位ビア導体の軸心がズレていたとしても、互いに接触し且つ電気的導通が可能であることを指す。
また、前記連続ビア導体、単位ビア導体、および配線層は、例えば、W、Mo、Cu、Agなどや、これらの何れかをベース(第1成分)とする合金からなる。
The ceramic includes, for example, glass ceramics which are a kind of low-temperature fired ceramics, in addition to high-temperature fired ceramics such as alumina, mullite, and aluminum nitride.
In addition, the insulating layer is the same ceramic as the ceramic, the same kind of ceramic having the same first component as the ceramic, or a different kind of ceramic having a different first component, and contains these ceramics as a main component. Also included.
Furthermore, the continuous via conductor penetrates a plurality of ceramic layers coaxially, even if the axis centers of individual unit via conductors are misaligned between adjacent ceramic layers, they can contact each other and be electrically conductive. It points to something.
The continuous via conductor, the unit via conductor, and the wiring layer are made of, for example, W, Mo, Cu, Ag, or the like, or an alloy based on any of these (first component).

更に、前記連続ビア導体には、複数のセラミック層に同軸状に形成された複数のスルーホールの内壁面に沿って形成された円筒形状の連続スルーホール導体を含み、該連続スルーホール導体は、外径および内径が同じか同等である複数の単位スルーホール導体を同軸状に接続したものである。
また、前記配線層内に位置する隙間は、平面視で、円形、長円形、楕円形、四角形以上の正多角形あるいは変形多角形を呈する。
更に、前記複数の配線層間とは、同じセラミック層間に位置し且つ互いに離れて隣接する複数(2つ)の配線層同士間の上記セラミック層間で、且つ平面視で近接する複数の配線層間に位置する帯状ないし異形状などを呈する領域である。
また、前記セラミック層と絶縁層とは、異なる組成のセラミックからなる場合は基より、同じセラミックからなる場合でも、密度などが相違しているので、前記基板本体の断面において両者を区別して視認することが可能である。
加えて、前記絶縁層は、平面視で絶縁すべき連続ビア導体の直径の少なくとも2倍、望ましくは3倍以上の直径、短径、あるいは一辺の長さなどを有している。
Furthermore, the continuous via conductor includes a cylindrical continuous through-hole conductor formed along the inner wall surface of the plurality of through-holes formed coaxially in the plurality of ceramic layers, and the continuous through-hole conductor includes: A plurality of unit through-hole conductors having the same or equivalent outer diameter and inner diameter are connected coaxially.
In addition, the gap located in the wiring layer exhibits a circle, an oval, an ellipse, a regular polygon that is greater than or equal to a square, or a deformed polygon in plan view.
Further, the plurality of wiring layers are positioned between the ceramic layers between a plurality of (two) wiring layers that are located adjacent to each other and located adjacent to each other in a plan view. This is a region exhibiting a strip shape or a different shape.
Further, since the ceramic layer and the insulating layer are made of ceramics having different compositions, the density of the ceramic layer and the insulating layer are different from each other even when the ceramic layer and the insulating layer are made of the same ceramic. It is possible.
In addition, the insulating layer has at least twice the diameter of the continuous via conductor to be insulated in a plan view, preferably three times the diameter, the short diameter, or the length of one side.

また、本発明には、前記基板本体は、該基板本体の表面の中央側に開口するキャビティを有し、隣接する複数の前記セラミック層は、該キャビティの底面と側面とを形成するものであり、前記絶縁層の周辺部の一部は、上記キャビティの側面と面一状であるか、あるいは該キャビティの底面側に延在し且つ当該キャビティ内に露出している、多層セラミック基板(請求項2)も含まれる。
これによれば、上記キャビティの底面と側面とを形成し且つ厚み方向で隣接する2層のセラミック層間であって、該セラミック層間で隣接する複数の配線層間の隙間に位置し、且つ少なくとも上記2層のセラミック層を厚み方向で同軸状に貫通する連続ビア導体の中間に、セラミック系の前記絶縁層が形成されている。しかも、該絶縁層におけるキャビティ側の周辺部、あるいは該周辺部の一部は、上記キャビティの側面と面一状(ほぼ面一)であるか、あるいは該キャビティの底面側に延在し且つ当該キャビティ内に露出している。従って、複数の連続ビア導体のうち、導通が不要な連続ビア導体を絶縁できると共に、製造時での積層工程およびこれに続く圧着工程において、キャビティを囲む上層側のグリーンシートがキャビティ側に傾いて倒れ込む事態が抑制されているので、所要の形状および寸法のキャビティを含む基板本体を有する多層セラミック基板とされている。
尚、前記面一状とは、前記周辺部の一部が前記キャビティの側面よりも該側面の奥側に100μm以下の範囲(例えば、数10μm程度)で位置していることも含んでいる。
In the present invention, the substrate body has a cavity that opens to the center of the surface of the substrate body, and the plurality of adjacent ceramic layers form the bottom surface and side surfaces of the cavity. A part of the peripheral portion of the insulating layer is flush with a side surface of the cavity, or extends to a bottom side of the cavity and is exposed in the cavity. 2) is also included.
According to this, between the two ceramic layers adjacent to each other in the thickness direction and forming the bottom surface and the side surface of the cavity, the gap is located between the plurality of adjacent wiring layers, and at least the 2 The ceramic insulating layer is formed in the middle of the continuous via conductor that passes through the ceramic layer coaxially in the thickness direction. Moreover, the peripheral portion of the insulating layer on the cavity side, or a part of the peripheral portion, is flush with the side surface of the cavity (almost flush), or extends to the bottom surface side of the cavity and It is exposed in the cavity. Therefore, among the plurality of continuous via conductors, the continuous via conductors that do not need to be electrically conductive can be insulated, and the green sheet on the upper layer side surrounding the cavity is inclined toward the cavity side in the laminating process and the subsequent crimping process at the time of manufacture. Since the situation of falling is suppressed, the multilayer ceramic substrate has a substrate body including a cavity having a required shape and size.
In addition, the said flat shape includes that a part of the peripheral portion is located in a range of 100 μm or less (for example, about several tens of μm) on the back side of the side surface of the cavity.

一方、本発明による多層セラミック基板の製造方法(請求項3)は、複数のセラミック層が積層された基板本体と、該基板本体において、隣接する複数のセラミック層を厚み方向に沿って同軸状に貫通する複数の連続ビア導体と、を備えた多層セラミック基板の製造方法であって、複数のセラミックグリーンシートに複数のビアホールを形成する工程と、該グリーンシートごとのビアホールに導電性ペーストを充填して未焼成の単位ビア導体を形成する工程と、上記グリーンシートの表面および裏面の少なくとも一方に導電性ペーストを印刷して、未焼成で内部に隙間を有する配線層、あるいは未焼成で隣接する複数の配線層を形成する工程と、少なくとも1つの上記グリーンシートの表面および裏面の少なくとも一方において、上記単位ビア導体の端面が露出する位置およびその周囲に、セラミック系の絶縁ペーストを配置して未焼成の絶縁層を形成する工程と、複数の上記グリーンシートを、該グリーンシートごとの上記単位ビア導体が軸方向に沿って同軸状に連続するように積層する工程と、を含み、上記絶縁層を形成する工程において、上記未焼成の絶縁層は、上記配線層内の隙間、あるいは上記複数の配線層同士間の間隙に形成される、ことを特徴とする。   On the other hand, a method for manufacturing a multilayer ceramic substrate according to the present invention (Claim 3) includes a substrate body in which a plurality of ceramic layers are laminated, and a plurality of adjacent ceramic layers in the substrate body coaxially along the thickness direction. A method of manufacturing a multilayer ceramic substrate having a plurality of continuous via conductors penetrating therethrough, the step of forming a plurality of via holes in a plurality of ceramic green sheets, and filling a via paste for each green sheet with a conductive paste A step of forming an unfired unit via conductor, and printing a conductive paste on at least one of the front and back surfaces of the green sheet, and a non-fired wiring layer having a gap inside, or a plurality of unfired adjacent layers Forming the wiring layer and at least one of the front and back surfaces of the at least one green sheet. Disposing a ceramic insulating paste around the position where the end face of the conductor is exposed to form a green insulating layer, and a plurality of the green sheets, and the unit via conductor for each green sheet Laminating so as to be concentrically continuous along a direction, and in the step of forming the insulating layer, the unfired insulating layer is a gap in the wiring layer or between the plurality of wiring layers. It is formed in a gap between them.

これによれば、共通の金型によって複数のグリーンシートを同軸状に貫通するように形成された複数の前記単位ビア導体のうち、導通が不要となる複数の単位ビア導体は、該複数の単位ビア導体が貫通する配線層内の隙間、あるいは隣接する複数(2以上)の配線層間の隙間に形成されたセラミック系の絶縁層により、電気的に絶縁される。しかも、上記絶縁層は、厚み方向で隣接する2層のグリーンシート間に配設された配線層の内側に位置する隙間、あるいは同じグリーンシート間で隣接する複数の配線層同士間の隙間に形成される。そのため、焼成後に得られる複数の連続ビア導体が、積層後における複数のセラミック層の厚み方向に沿って形成され、これらのうち、導通が不要となる連続ビア導体は、前記絶縁層により絶縁されると共に、該絶縁層は、前記何れかの隙間に形成されるので、積層後および焼成後の基板本体における表面や裏面に凹みなどが生じる事態を皆無にすることができる。
従って、比較的低コストによって、複数の連続ビアを含む基板本体の寸法および形状が正確な多層セラミック基板を確実に製造することが可能となる。
According to this, among the plurality of unit via conductors formed so as to pass through a plurality of green sheets coaxially by a common mold, the plurality of unit via conductors that do not require conduction are the plurality of unit via conductors. It is electrically insulated by a ceramic insulating layer formed in a gap in the wiring layer through which the via conductor penetrates or in a gap between a plurality of (two or more) adjacent wiring layers. Moreover, the insulating layer is formed in a gap located inside the wiring layer disposed between two green sheets adjacent in the thickness direction, or a gap between a plurality of adjacent wiring layers between the same green sheets. Is done. Therefore, a plurality of continuous via conductors obtained after firing are formed along the thickness direction of the plurality of ceramic layers after lamination, and among these, the continuous via conductors that do not require conduction are insulated by the insulating layer. At the same time, since the insulating layer is formed in any one of the gaps, it is possible to eliminate the occurrence of dents on the front and back surfaces of the substrate body after lamination and firing.
Accordingly, it is possible to reliably manufacture a multilayer ceramic substrate with a precise size and shape of the substrate body including a plurality of continuous vias at a relatively low cost.

尚、前記セラミックグリーンシートは、前記セラミックの粉末にバインダ樹脂や溶剤などを混合したセラミックスラリをシート状に成形したものである。
また、前記積層工程の後には、積層された複数のセラミックグリーンシートの積層体を前記連続ビア導体や配線層などと同時に焼成する工程と、その後に外部に露出する表・裏面端子の表面にメッキ層を被覆するメッキ工程とが行われる。
更に、前記製造方法には、前記複数のグリーンシートを平面視で縦横に隣接する複数の基板領域を併有する製品領域と、その外周側に位置する耳部とからなるものとした多数個取りの形態も含まれる。
The ceramic green sheet is obtained by molding a ceramic slurry in which a binder resin or a solvent is mixed with the ceramic powder into a sheet shape.
In addition, after the laminating step, a step of firing a laminated body of a plurality of laminated ceramic green sheets simultaneously with the continuous via conductor, wiring layer, etc., and then plating on the surface of the front and back terminals exposed to the outside And a plating step for coating the layer.
Further, the manufacturing method includes a plurality of green sheets each including a product region having a plurality of substrate regions adjacent to each other in the vertical and horizontal directions in plan view and an ear portion located on the outer peripheral side thereof. Forms are also included.

また、本発明には、前記複数のグリーンシートは、前記基板本体の表面の中央側に開口するキャビティの底面と、該キャビティの側面とを構成するものであり、上記複数のグリーンシート間に形成される前記未焼成の絶縁層の周辺部の一部は、前記積層工程において、上記キャビティの側面と面一状であるか、あるいは該キャビティの底面に延在し且つ当該キャビティ内に露出している、多層セラミック基板の製造方法(請求項4)も含まれる。
これによれば、上記キャビティの底面と側面とを形成し且つ厚み方向で隣接する2層のグリーンシート間であって、該グリーンシート間で隣接する複数の配線層間の隙間に位置し、且つ少なくとも上記2層のグリーンシートを厚み方向で同軸状に貫通する連続ビア導体の中間に、セラミック系の前記絶縁層が形成される。しかも、該絶縁層におけるキャビティ側の周辺部、あるいは該周辺部の一部は、上記キャビティの側面と面一状か、あるいは該キャビティの底面側に延在し且つ当該キャビティ内に露出している。従って、複数の連続ビア導体のうち、導通が不要な連続ビア導体を絶縁できると共に、前記積層工程とこれに続く圧着工程で、キャビティを囲む上層側のグリーンシートが当該キャビティ側に傾く事態(倒れ込み)が抑制されるので、所要の形状および寸法のキャビティを含む基板本体を有する多層セラミック基板を、比較的低コストで確実に製造することができる。
Further, in the present invention, the plurality of green sheets constitute a bottom surface of a cavity that opens to the center side of the surface of the substrate body and a side surface of the cavity, and are formed between the plurality of green sheets. In the laminating step, a part of the periphery of the unfired insulating layer is flush with the side surface of the cavity, or extends to the bottom surface of the cavity and is exposed in the cavity. And a method of manufacturing a multilayer ceramic substrate (claim 4).
According to this, between the two green sheets adjacent to each other in the thickness direction that form the bottom surface and the side surface of the cavity, the gap is located between the plurality of wiring layers adjacent between the green sheets, and at least The ceramic insulating layer is formed in the middle of the continuous via conductor that passes through the two green sheets coaxially in the thickness direction. In addition, the peripheral portion of the insulating layer on the cavity side or a part of the peripheral portion is flush with the side surface of the cavity, or extends to the bottom surface side of the cavity and is exposed in the cavity. . Therefore, among the plurality of continuous via conductors, continuous via conductors that do not need to be electrically conductive can be insulated, and in the stacking step and the subsequent crimping step, the upper layer side green sheet surrounding the cavity is inclined toward the cavity side (falling down) Therefore, a multilayer ceramic substrate having a substrate body including a cavity having a required shape and size can be reliably manufactured at a relatively low cost.

本発明による第1の多層セラミック基板を示す垂直断面図。1 is a vertical sectional view showing a first multilayer ceramic substrate according to the present invention. (A)は図1中のA−A線の矢視に沿った部分断面図、(B)は図1中のB−B線の矢視に沿った部分断面図、(C)は(B)の変形形態を示す断面図。(A) is a partial cross-sectional view taken along the line AA in FIG. 1, (B) is a partial cross-sectional view taken along the line BB in FIG. 1, and (C) is (B Sectional drawing which shows the deformation | transformation form of). 第1の多層セラミック基板を得るための一製造工程を示す概略断面図。The schematic sectional drawing which shows one manufacturing process for obtaining a 1st multilayer ceramic substrate. 図3に続く製造工程の概略を示す断面図。Sectional drawing which shows the outline of the manufacturing process following FIG. 図4に続く製造工程の概略を示す断面図。Sectional drawing which shows the outline of the manufacturing process following FIG. 図5に続く製造工程の概略を示す断面図。Sectional drawing which shows the outline of the manufacturing process following FIG. 図6に続く製造工程の概略を示す断面図。Sectional drawing which shows the outline of the manufacturing process following FIG. 図7に続く製造工程の概略を示す断面図。Sectional drawing which shows the outline of the manufacturing process following FIG. 本発明による第2の多層セラミック基板を示す垂直断面図。FIG. 3 is a vertical sectional view showing a second multilayer ceramic substrate according to the present invention. 図9中のX−X線の矢視に沿った水平断面図。FIG. 10 is a horizontal sectional view taken along the line XX in FIG. 9. 第2の多層セラミック基板を得るための一製造工程を示す概略断面図。The schematic sectional drawing which shows one manufacturing process for obtaining a 2nd multilayer ceramic substrate. 図11に続く製造工程の概略を示す断面図。Sectional drawing which shows the outline of the manufacturing process following FIG. 図12に続く製造工程の概略を示す断面図。Sectional drawing which shows the outline of the manufacturing process following FIG.

以下において、本発明を実施するための形態について説明する。
図1は、本発明による第1の多層セラミック基板1aを示す垂直断面図、図2(A)は、図1中のA−A線の矢視に沿った部分断面図、図2(B)は、図1中のB−B線の矢視に沿った部分断面図、図2(C)は、(B)の変形形態である。
第1の多層セラミック基板1aは、図1に示すように、複数のセラミック層3〜5が積層され且つ表面6および裏面7を有する基板本体2aと、該基板本体2aの表面6と裏面7との間を同軸状に貫通する複数の連続ビア導体12と、セラミック層4,5間に形成された所定のパターンを有する複数の配線層13とを備えている。更に、基板本体2aの表面6には、連続ビア導体12ごとの上端部に個別に接続された表面端子14が形成され、該基板本体2aの裏面7には、連続ビア導体12ごとの下端部に個別に接続された裏面端子15が形成されている。
尚、前記セラミック層3〜5は、例えば、アルミナを主成分とするセラミックからなる。また、前記連続ビア導体12、配線層13、表面および裏面端子14,15は、例えば、W、Mo、Cu、あるいはAgなどからなる。
Hereinafter, modes for carrying out the present invention will be described.
FIG. 1 is a vertical sectional view showing a first multilayer ceramic substrate 1a according to the present invention, FIG. 2A is a partial sectional view taken along the line AA in FIG. 1, and FIG. FIG. 2 is a partial cross-sectional view taken along the line B-B in FIG. 1, and FIG. 2C is a modified form of (B).
As shown in FIG. 1, the first multilayer ceramic substrate 1a includes a substrate body 2a in which a plurality of ceramic layers 3 to 5 are laminated and has a front surface 6 and a back surface 7, and a front surface 6 and a back surface 7 of the substrate body 2a. There are provided a plurality of continuous via conductors 12 that pass coaxially there between, and a plurality of wiring layers 13 having a predetermined pattern formed between the ceramic layers 4 and 5. Further, a front surface terminal 14 is formed on the front surface 6 of the substrate main body 2a and is individually connected to the upper end portion of each continuous via conductor 12. The back terminals 15 are individually connected to each other.
The ceramic layers 3 to 5 are made of, for example, a ceramic mainly composed of alumina. The continuous via conductor 12, the wiring layer 13, the front and back terminals 14 and 15 are made of, for example, W, Mo, Cu, or Ag.

図1に示すように、5個(複数)の前記連続ビア導体12は、セラミック層3〜5を厚み方向に沿って同軸状に貫通するように、前記基板本体2a内に形成されている。こられのうち、図1で左右の両端に位置する2個の連続ビア導体12は、セラミック層4,5間に形成された配線層13と接続されている。また、図1で中央に位置する連続ビア導体12は、基板本体2aを構成するセラミック層3〜5を単独で且つ直線状に貫通している。
更に、図1で左右から2番目ごとに位置する2個の連続ビア導体12は、第1の多層セラミック基板1aでは、導通が不要なものである。そのため、該2個の連続ビア導体12は、これらがセラミック層4,5間と交差するに位置ごとに形成されたセラミック系の絶縁層20によって絶縁されている。該絶縁層20も、セラミック層3〜5と同様のアルミナを主成分とするセラミックからなる。
As shown in FIG. 1, the five (plural) continuous via conductors 12 are formed in the substrate body 2 a so as to penetrate the ceramic layers 3 to 5 coaxially along the thickness direction. Among these, the two continuous via conductors 12 positioned at the left and right ends in FIG. 1 are connected to the wiring layer 13 formed between the ceramic layers 4 and 5. Moreover, the continuous via conductor 12 located in the center in FIG. 1 penetrates the ceramic layers 3 to 5 constituting the substrate body 2a independently and linearly.
Further, the two continuous via conductors 12 positioned every second from the left and right in FIG. 1 are unnecessary for the first multilayer ceramic substrate 1a. Therefore, the two continuous via conductors 12 are insulated by a ceramic insulating layer 20 formed at each position so as to intersect between the ceramic layers 4 and 5. The insulating layer 20 is also made of a ceramic mainly composed of alumina similar to the ceramic layers 3 to 5.

即ち、図1中のA−A線の矢視に沿った部分断面図の図2(A)に示すように、図1で左から2番目に位置する連続ビア導体12は、セラミック層4,5間に位置する前記配線層13内に開設された平面視が円形の隙間13s内に形成された絶縁層20によって絶縁されている。該絶縁層20の直径は、上記連続ビア導体12の直径の約3倍である。
一方、図1中のB−B線の矢視に沿った部分断面図の図2(B)に示すように、図1で右から2番目に位置する連続ビア導体12は、セラミック層4,5間において隣接する2つの配線層13間における隙間13g内に形成された絶縁層20によって絶縁されている。上記隙間13gは、図示のように、絶縁された連続ビア導体12における上下の端面付近では、該連続ビア導体12の直径の約3倍とした円形状の部分と、隣接する2つの配線層13間において、該配線層13同士の絶縁に必要な最小限の幅を有する帯状の部分とからなる。
尚、上記隙間13gに位置する絶縁層20は、図2(C)に示すように、当該隙間13g内において、隣接する2つの配線層13同士間で、且つ絶縁すべき連続ビア導体12の付近に位置する円形滋養の部分だけに形成しても良い。
That is, as shown in FIG. 2A, which is a partial sectional view taken along the line AA in FIG. 1, the continuous via conductor 12 located second from the left in FIG. The plan view opened in the wiring layer 13 located between the two is insulated by the insulating layer 20 formed in the circular gap 13s. The diameter of the insulating layer 20 is about three times the diameter of the continuous via conductor 12.
On the other hand, as shown in FIG. 2B, which is a partial cross-sectional view taken along the line BB in FIG. 1, the continuous via conductor 12 located second from the right in FIG. 5 is insulated by an insulating layer 20 formed in a gap 13g between two adjacent wiring layers 13. As shown in the figure, the gap 13g includes a circular portion that is approximately three times the diameter of the continuous via conductor 12 and two adjacent wiring layers 13 in the vicinity of the upper and lower end faces of the insulated continuous via conductor 12. In the meantime, it consists of a strip-shaped portion having a minimum width necessary for insulation between the wiring layers 13.
As shown in FIG. 2C, the insulating layer 20 located in the gap 13g is located between the adjacent two wiring layers 13 in the gap 13g and in the vicinity of the continuous via conductor 12 to be insulated. You may form only in the part of circular nourishment located in.

以上のような第1の多層セラミック基板1aによれば、複数のセラミック層3〜5を同軸状に貫通する複数の前記連続ビア導体12のうち、導通が不要な連続ビア導体12は、該ビア導体12が貫通する配線層13内の隙間13s、あるいは隣接する2つの配線層13間の隙間13gに形成された前記絶縁層20によって絶縁されている。しかも、上記絶縁層20は、厚み方向で隣接する2層のセラミック層4,5間に配設された配線層13内に位置する隙間13s、あるいは同じセラミック層4,5間で隣接する2つの配線層13間の隙間13gに形成されている。そのため、共通の金型によって複数の連続ビア導体12が複数のセラミック層3〜5の厚み方向に沿って形成され、これらのうち導通が不要な連続ビア導体12は、前記絶縁層20により絶縁されていると共に、該絶縁層20は、前記隙間13s,13gに形成されているので、基板本体2aの表面6や裏面7に凹みなどの悪影響が生じくくされている。
従って、複数のセラミック層3〜5を厚み方向に沿って同軸状に貫通する複数の連続ビア導体12を有し、導通が不要な連続ビア導体12のみが絶縁されており、基板本体の寸法および形状が正確な多層セラミック基板1aとされている。
According to the first multilayer ceramic substrate 1a as described above, among the plurality of continuous via conductors 12 that pass through the plurality of ceramic layers 3 to 5 coaxially, the continuous via conductor 12 that does not require conduction is the via. The conductor 12 is insulated by the insulating layer 20 formed in the gap 13s in the wiring layer 13 through which the conductor 12 passes or in the gap 13g between two adjacent wiring layers 13. In addition, the insulating layer 20 includes the gap 13 s located in the wiring layer 13 disposed between the two ceramic layers 4 and 5 adjacent in the thickness direction, or two adjacent adjacent ceramic layers 4 and 5. A gap 13g between the wiring layers 13 is formed. Therefore, a plurality of continuous via conductors 12 are formed along the thickness direction of the plurality of ceramic layers 3 to 5 by a common mold, and the continuous via conductors 12 that do not require conduction are insulated by the insulating layer 20. In addition, since the insulating layer 20 is formed in the gaps 13s and 13g, adverse effects such as dents are unlikely to occur on the front surface 6 and the back surface 7 of the substrate body 2a.
Therefore, the plurality of continuous via conductors 12 that pass through the plurality of ceramic layers 3 to 5 coaxially along the thickness direction are insulated, and only the continuous via conductor 12 that does not need to be electrically conductive is insulated. The multilayer ceramic substrate 1a is accurate in shape.

以下において、前記多層セラミック基板1aの製造方法について説明する。
予め、アルミナ粉末、バインダ樹脂、および溶剤などを適量ずつ配合し、得られたセラミックスラリをドクターブレード法によってシート状に成形することによって、図3に示すように、3枚のグリーンシートg3〜g5を用意した。
次に、図4に示すように、上記グリーンシートg3〜g5における所定の位置ごとに、図示しない複数のポンチを併有する打ち抜き用の金型によって、内径が共通する複数のビアホール12hを平面視でほぼ等間隔にして形成した。
次いで、上記グリーンシートg3〜g5におけるビアホール12h内ごとに、WあるいはMo粉末を含む導電性ペーストを充填することにより、図5に示すように、未焼成である複数の単位ビア導体12uを形成した。図示のように、かかる複数の単位ビア導体12uは、上記グリーンシートg3〜g5の厚み方向において、互いに同軸状となる位置ごとに形成された。
Below, the manufacturing method of the said multilayer ceramic substrate 1a is demonstrated.
By mixing an appropriate amount of alumina powder, binder resin, solvent, and the like in advance, the obtained ceramic slurry is formed into a sheet shape by the doctor blade method, thereby obtaining three green sheets g3 to g5 as shown in FIG. Prepared.
Next, as shown in FIG. 4, a plurality of via holes 12h having a common inner diameter are seen in a plan view by a punching die having a plurality of punches (not shown) at predetermined positions in the green sheets g3 to g5. They were formed at approximately equal intervals.
Next, each of the via holes 12h in the green sheets g3 to g5 is filled with a conductive paste containing W or Mo powder, thereby forming a plurality of unfired unit via conductors 12u as shown in FIG. . As shown in the drawing, the plurality of unit via conductors 12u are formed at positions that are coaxial with each other in the thickness direction of the green sheets g3 to g5.

更に、図5中で最下層に位置するグリーンシートg5の表面に、上記同様の導電性ペーストをスクリーン印刷することにより、図示のように、平面視が円形である隙間13sを内側に有する未焼成の配線層13と、隙間13gを挟んで隣接する未焼成で且つ2つの配線層13とを形成した。図5中で示すように、上記隙間13sの中心部には、グリーンシートg5に形成した1つの単位ビア導体12uの上端面が露出していた。また、上記隙間13g内における平面視が円形状の部分の中心部には、別の単位ビア導体12uの上端面が露出していた。
次に、図6に示すように、上記配線層13内に位置する隙間13s内と、隣接する2つの配線層13間に挟まれた上記隙間13g内とに対し、所定パターンを有するスクリーン(図示せず)およびスキージ29を用いて、アルミナ(セラミック)粉末を含む絶縁ペースト20pを充填することにより、それぞれ未焼成の絶縁層20を形成した。
Furthermore, the same conductive paste as described above is screen-printed on the surface of the green sheet g5 located at the lowermost layer in FIG. Wiring layer 13 and two unfired and two wiring layers 13 adjacent to each other with a gap 13g interposed therebetween. As shown in FIG. 5, the upper end surface of one unit via conductor 12u formed in the green sheet g5 was exposed at the center of the gap 13s. In addition, the upper end surface of another unit via conductor 12u was exposed at the center of the circular portion in plan view in the gap 13g.
Next, as shown in FIG. 6, a screen having a predetermined pattern is formed in the gap 13s located in the wiring layer 13 and in the gap 13g sandwiched between two adjacent wiring layers 13 (see FIG. 6). An unfired insulating layer 20 was formed by filling an insulating paste 20p containing alumina (ceramic) powder using a squeegee 29 and a squeegee 29, respectively.

次いで、前記複数の単位ビア導体12uが形成されたグリーンシートg3,g4と、上記同様の単位ビア導体12u、絶縁層20、および複数の前記配線層13が形成されたグリーンシート5を、グリーンシートg3〜g5ごとの単位ビア導体12uが、互いに軸方向に沿って接触するように積層し、更に圧着した。
その結果、図7に示すように、グリーンシートg3〜g5からなる未焼成の基板本体2aと、図7で中央に位置し且つグリーンシートg3〜g5間を同軸状に貫通する3個の単位ビア導体12uと、グリーンシートg4,g5間で且つ図7で左端または右端に位置する上下の各単位ビア導体12uに接続された3つの配線層13と、を含む未焼成の積層体24が得られた。該積層体24では、図7で左側の配線層13内の隙間13sに位置する絶縁層20より、図7で左から2番目に位置する上下の単位ビア導体12uが絶縁されていた。更に、図7で右側において隣接する2つの配線層13間の隙間13gに位置する絶縁層20より、図示7右から2番目に位置する上下の単位ビア導体12uが絶縁されていた。
Next, the green sheets g3 and g4 on which the plurality of unit via conductors 12u are formed, and the green sheet 5 on which the same unit via conductors 12u, the insulating layer 20, and the plurality of wiring layers 13 are formed as green sheets The unit via conductors 12u for each of g3 to g5 were laminated so as to be in contact with each other along the axial direction, and further pressed.
As a result, as shown in FIG. 7, an unfired substrate body 2a made of green sheets g3 to g5 and three unit vias that are located in the center in FIG. 7 and pass through the green sheets g3 to g5 coaxially. An unfired laminated body 24 including the conductor 12u and the three wiring layers 13 connected to the upper and lower unit via conductors 12u located between the green sheets g4 and g5 and located at the left end or the right end in FIG. 7 is obtained. It was. In the laminate 24, the upper and lower unit via conductors 12u located second from the left in FIG. 7 are insulated from the insulating layer 20 located in the gap 13s in the left wiring layer 13 in FIG. Further, the upper and lower unit via conductors 12u located second from the right in FIG. 7 are insulated from the insulating layer 20 located in the gap 13g between the two adjacent wiring layers 13 on the right side in FIG.

更に、図8に示すように、前記積層体24における基板本体2aの表面6に露出する単位ビア導体12uごとの上に、前記同様の導電性ペーストをスクリーン印刷して、未焼成である複数の表面端子14を形成すると共に、上記基板本体2aの裏面7に露出する単位ビア導体12uごとの上に、上記同様の導電性ペーストをスクリーン印刷して、未焼成である複数の裏面端子15を形成した。
そして、上記積層体24を脱脂および焼成した後、電解Niメッキ液および電解Auメッキ液に順次浸漬して、上記基板本体2aの外部に露出する各表面端子14および各裏面端子15の表面に、下地側のNiメッキ膜と表層側のAuメッキ膜とからなるメッキ層(図示せず)を被覆した。その結果、前記図1,図2(A),(B)で示した第1の多層セラミック基板1aが得られた。
尚、前記焼成工程では、グリーンシートg3〜g5がセラミック層3〜5に焼成され、同軸状に接触していた複数ずつの単位ビア導体12uは、複数の連続ビア導体12となり、その一部は、焼成された絶縁層22により絶縁されていた。
また、以上のような多層セラミック基板1aの製造方法は、多数個取りの形態によって行っても良い。
Furthermore, as shown in FIG. 8, the same conductive paste as described above is screen-printed on each unit via conductor 12u exposed on the surface 6 of the substrate body 2a in the laminate 24, and a plurality of unfired plural pastes The front surface terminals 14 are formed, and the same conductive paste as described above is screen-printed on each unit via conductor 12u exposed on the back surface 7 of the substrate body 2a to form a plurality of unfired back surface terminals 15. did.
Then, after degreasing and firing the laminate 24, it is sequentially immersed in an electrolytic Ni plating solution and an electrolytic Au plating solution, and on the surfaces of the front surface terminals 14 and the rear surface terminals 15 exposed to the outside of the substrate body 2a, A plating layer (not shown) composed of a Ni plating film on the base side and an Au plating film on the surface layer side was coated. As a result, the first multilayer ceramic substrate 1a shown in FIGS. 1, 2A and 2B was obtained.
In the firing step, the green sheets g3 to g5 are fired into the ceramic layers 3 to 5, and the plurality of unit via conductors 12u that have been in contact with each other in a coaxial manner become a plurality of continuous via conductors 12, and part of them Insulated by the fired insulating layer 22.
Moreover, you may perform the manufacturing method of the above multilayer ceramic substrates 1a with the form of many pieces.

以上のような第1の多層セラミック基板1aの製造方法によれば、共通の金型によって複数のグリーンシートg3〜g5を同軸状に貫通するように形成された複数の単位ビア導体12uのうち、導通が不要な複数の単位ビア導体12uは、該複数のビア導体12uが貫通する配線層13内の隙間13s、あるいは隣接する2つの配線層13間の隙間13gに形成された前記絶縁層20によって電気的に絶縁された。しかも、上記絶縁層20は、厚み方向で隣接するグリーンシートg4,g5間に配設された配線層13内に位置する隙間13s、およびグリーンシートg4,g5間に隣接する2つの配線層13間の隙間13gに形成された。そのため、同軸状である複数の連続ビア導体12が、積層後における複数のグリーンシートg3〜g5の厚み方向に沿って形成され、これらのうち、導通が不要な連続ビア導体12は、前記絶縁層20により絶縁され、該絶縁層20は、前記隙間13s,13gの一方に形成されたので、積層後および焼成後における基板本体2aの表面6や裏面7に凹みなどが生じる事態を皆無にすることができた。
従って、比較的低コストによって、複数の連続ビア導体12を含む基板本体2aの寸法および形状が正確な多層セラミック基板1aを確実に製造できた。
According to the manufacturing method of the first multilayer ceramic substrate 1a as described above, among the plurality of unit via conductors 12u formed so as to penetrate the plurality of green sheets g3 to g5 coaxially by a common mold, The plurality of unit via conductors 12u that do not require conduction are formed by the insulating layer 20 formed in the gap 13s in the wiring layer 13 through which the plurality of via conductors 12u pass or the gap 13g between two adjacent wiring layers 13. Electrically isolated. Moreover, the insulating layer 20 includes a gap 13s located in the wiring layer 13 disposed between the green sheets g4 and g5 adjacent in the thickness direction, and between the two wiring layers 13 adjacent between the green sheets g4 and g5. Formed in a gap 13g. Therefore, a plurality of continuous via conductors 12 that are coaxial are formed along the thickness direction of the plurality of green sheets g3 to g5 after lamination, and among these, the continuous via conductor 12 that does not require conduction is the insulating layer. 20 and the insulating layer 20 is formed in one of the gaps 13s and 13g, so that there is no occurrence of dents on the front surface 6 and the rear surface 7 of the substrate body 2a after lamination and after firing. I was able to.
Therefore, the multilayer ceramic substrate 1a in which the size and shape of the substrate body 2a including the plurality of continuous via conductors 12 are accurate can be reliably manufactured at a relatively low cost.

図9は、本発明による第2の多層セラミック基板1bを示す垂直断面図、図10は、図9中のX−X線の矢視に沿った水平断面図である。
上記多層セラミック基板1bは、図9,10に示すように、前記同様である複数のセラミック層8〜10を積層してなり表面6bおよび裏面7を有する基板本体2bと、該基板本体2bの表面6bにおける中央側に開口したキャビティ16と、該キャビティ16を囲む上記セラミック層8〜10を厚み方向に同軸状に貫通する複数の連続ビア導体12と、を備えている。上層および中層セラミック層8,9は、上記キャビティ16を内設するため、平面視で四角枠形状を呈し、該キャビティ16は、平面視がほぼ正方形でセラミック層10の表面の一部である底面17と、該底面17の四辺から垂直に立設した4つの側面18とを備えている。上記連続ビア導体12ごとの上・下端には、基板本体2bの表面6bに設けた表面端子14と、裏面7に設けた裏面端子15とが個別に接続されている。
FIG. 9 is a vertical sectional view showing a second multilayer ceramic substrate 1b according to the present invention, and FIG. 10 is a horizontal sectional view taken along line XX in FIG.
As shown in FIGS. 9 and 10, the multilayer ceramic substrate 1b includes a substrate body 2b having a front surface 6b and a back surface 7 formed by laminating a plurality of ceramic layers 8 to 10 similar to the above, and a surface of the substrate body 2b. The cavity 16 opened to the center side in 6b, and a plurality of continuous via conductors 12 that coaxially penetrate the ceramic layers 8 to 10 surrounding the cavity 16 in the thickness direction. The upper and middle ceramic layers 8 and 9 have a rectangular frame shape in plan view in order to provide the cavity 16, and the cavity 16 is a bottom surface that is substantially square in plan view and is a part of the surface of the ceramic layer 10. 17 and four side surfaces 18 erected vertically from the four sides of the bottom surface 17. A front surface terminal 14 provided on the front surface 6 b of the substrate body 2 b and a back surface terminal 15 provided on the back surface 7 are individually connected to the upper and lower ends of each continuous via conductor 12.

また、図9,10に示すように、キャビティ16の底面17と基板本体2bの裏面7との間には、複数のビア導体21が貫通しており、該ビア導体21ごとの上端部である上記キャビティ16の底面17には、同数の内部端子19が形成されている。該内部端子19上には、追って該キャビティ16内に実装される図示しない電子部品が搭載される。上記ビア導体21ごとの下端には、基板本体2bの裏面7に設けた裏面端子15が個別に接続されている。
更に、図9,10に示すように、中層のセラミック層9と下層のセラミック層10との間には、平面視が角形状である複数の配線層23が互いに離れて形成され、隣接する配線層23同士間に位置する平面視が角形状の隙間23gごとには、前記同様である複数の絶縁層22が個別に形成されている。
Also, as shown in FIGS. 9 and 10, a plurality of via conductors 21 penetrate between the bottom surface 17 of the cavity 16 and the back surface 7 of the substrate body 2 b, and are the upper ends of the via conductors 21. The same number of internal terminals 19 are formed on the bottom surface 17 of the cavity 16. On the internal terminal 19, an electronic component (not shown) to be mounted in the cavity 16 later is mounted. A back surface terminal 15 provided on the back surface 7 of the substrate body 2b is individually connected to the lower end of each via conductor 21.
Further, as shown in FIGS. 9 and 10, a plurality of wiring layers 23 having a square shape in plan view are formed apart from each other between the middle ceramic layer 9 and the lower ceramic layer 10. A plurality of insulating layers 22 similar to those described above are individually formed for each gap 23g having a square shape in plan view located between the layers 23.

図10において、四隅に位置する配線層23内には、円形の隙間23sが形成され、該隙間23sに配置された絶縁層22が、当該隙間23sの中心部に接する連続ビア導体12を絶縁している。また、図10において、四辺に位置する複数の配線層23の上・下面には、連続ビア導体12が個別に接続されている。
一方、図10において、四辺に位置する複数の配線層23同士の隙間23gごとには、角形状の絶縁層22が形成され、該絶縁層22により、上下の連続ビア導体12を絶縁している。かかる絶縁層22におけるキャビティ16側の周辺部22aは、図9,10に示すように、キャビティ16の側面18と面一であるか、あるいは該キャビティ16の底面17側に延在し、且つ該キャビティ16内に露出している。
尚、上記周辺部22aの一部は、キャビティ16側の辺の一部でも良い。また、該周辺部22aは、100μm以下の範囲内でキャビティ16の側面18よりも該側面18の奥側に僅かに下がって位置する面一状(ほぼ面一)であっても良い。
In FIG. 10, circular gaps 23s are formed in the wiring layers 23 located at the four corners, and the insulating layer 22 disposed in the gaps 23s insulates the continuous via conductors 12 in contact with the central part of the gaps 23s. ing. In FIG. 10, continuous via conductors 12 are individually connected to the upper and lower surfaces of a plurality of wiring layers 23 located on the four sides.
On the other hand, in FIG. 10, a rectangular insulating layer 22 is formed for each gap 23g between the plurality of wiring layers 23 located on the four sides, and the upper and lower continuous via conductors 12 are insulated by the insulating layer 22. . The peripheral portion 22a on the cavity 16 side in the insulating layer 22 is flush with the side surface 18 of the cavity 16 or extends to the bottom surface 17 side of the cavity 16 as shown in FIGS. The cavity 16 is exposed.
Note that a part of the peripheral portion 22a may be a part of the side on the cavity 16 side. Further, the peripheral portion 22a may be flush (substantially flush) positioned slightly below the side surface 18 of the cavity 16 within the range of 100 μm or less.

以上のような第2の多層セラミック基板1bによれば、前記キャビティ16の底面17と側面18とを形成し且つ厚み方向で隣接するセラミック層9,10間であり、且つ該セラミック層9,10間で隣接する複数の配線層23間の隙間23gに位置し、且つ複数のセラミック層8〜10を厚み方向で同軸状に貫通する複数の連続ビア導体12における何れかの中間に、前記絶縁層22が形成されている。しかも、該絶縁層22におけるキャビティ16側の周辺部22a、あるいは該周辺部22aの一部は、上記キャビティ16の側面18と面一であるか、該キャビティ16の底面17側に延在し且つ当該キャビティ16内に露出している。しかも、前記配線層23内の隙間23sに設けた絶縁層22によって、キャビティ16の開口部を囲む基板本体2bの表面6bにも、凹みなどが生じていない。
従って、複数の連続ビア導体12のうち、導通が不要な連続ビア導体12を絶縁できると共に、製造時での積層および圧着工程において、キャビティ16を囲む上層側のグリーンシートがキャビティ側に傾いて倒れ込む事態が抑制されているので、所要の形状および寸法のキャビティ16を含む基板本体2bを有する多層セラミック基板1bとされている。
According to the second multilayer ceramic substrate 1b as described above, the bottom surface 17 and the side surface 18 of the cavity 16 are formed and between the adjacent ceramic layers 9 and 10 in the thickness direction, and the ceramic layers 9 and 10 are formed. The insulating layer is located in the middle of any of the plurality of continuous via conductors 12 that are located in the gaps 23g between the plurality of adjacent wiring layers 23 and pass through the plurality of ceramic layers 8 to 10 coaxially in the thickness direction. 22 is formed. Moreover, the peripheral portion 22a on the cavity 16 side in the insulating layer 22 or a part of the peripheral portion 22a is flush with the side surface 18 of the cavity 16 or extends to the bottom surface 17 side of the cavity 16 and The cavity 16 is exposed. In addition, the insulating layer 22 provided in the gap 23 s in the wiring layer 23 does not cause a dent in the surface 6 b of the substrate body 2 b surrounding the opening of the cavity 16.
Therefore, among the plurality of continuous via conductors 12, the continuous via conductor 12 that does not need to be electrically conductive can be insulated, and the upper green sheet surrounding the cavity 16 tilts toward the cavity and falls down in the lamination and crimping process at the time of manufacture. Since the situation is suppressed, the multilayer ceramic substrate 1b has the substrate body 2b including the cavity 16 having a required shape and size.

以下において、前記多層セラミック基板1bの製造方法について説明する。
予め、前記同様の方法により、3枚のグリーンシートg8〜g10を用意した。これらのうち、上層側となるグリーンシートg8,g9の中央部に対し、断面角形のポンチと該断面と相似形の抜き孔を有するダイとによる打ち抜き加工を行った。その結果、図11に示すように、下層側の平坦なグリーンシート10のほかに、平面視が角形の貫通孔18hを有するグリーンシートg8,g9が得られた。
次に、図11中の右側に示すように、グリーンシートg8〜g10における所定の位置ごとに、前記同様の複数のポンチを併有する打ち抜き用の金型によって、複数のビアホール12hを形成した。次いで、図11中の左側に示すように、ビアホール12hごと内に、前記同様の導電性ペーストを充填して、未焼成の単位ビア導体12uを個別に形成した。
Hereinafter, a method for manufacturing the multilayer ceramic substrate 1b will be described.
Three green sheets g8 to g10 were prepared in advance by the same method as described above. Among these, punching with a punch having a square cross section and a die having a punch hole having a shape similar to that of the cross section was performed on the central portion of the green sheets g8 and g9 on the upper layer side. As a result, as shown in FIG. 11, in addition to the flat green sheet 10 on the lower layer side, green sheets g8 and g9 having square through holes 18h in plan view were obtained.
Next, as shown on the right side in FIG. 11, a plurality of via holes 12h were formed at predetermined positions in the green sheets g8 to g10 by a punching die having a plurality of punches similar to the above. Next, as shown on the left side in FIG. 11, each of the via holes 12h was filled with the same conductive paste as described above to form unfired unit via conductors 12u individually.

更に、下層側のグリーンシートg10における表面の周辺部に沿って、前記同様の導電性ペーストをスクリーン印刷することで、複数の配線層23を形成した後、図12に示すように、隣接する配線層23同士間の隙間23gごとに、前記同様の絶縁ペーストからなる未焼成の絶縁層22を上記同様にして印刷した。この際、該絶縁層22におけるグリーンシートg10の中心側と周辺側との幅w2は、中・上層側のグリーンシートg8,g9の幅w1よりも大きく形成された。
次に、前記複数の単位ビア導体12uが形成されたグリーンシートg8,g9と、上記同様の単位ビア導体12u、絶縁層22、および複数の前記配線層23が形成されたグリーンシート10を、グリーンシートg8〜g10ごとの単位ビア導体12uが、互いに軸方向に沿って接触するように積層し、更に圧着した。
Furthermore, after the plurality of wiring layers 23 are formed by screen printing the same conductive paste as described above along the periphery of the surface of the green sheet g10 on the lower layer side, as shown in FIG. For each gap 23g between the layers 23, an unfired insulating layer 22 made of the same insulating paste was printed in the same manner as described above. At this time, the width w2 between the center side and the peripheral side of the green sheet g10 in the insulating layer 22 was formed larger than the width w1 of the green sheets g8 and g9 on the middle and upper layers.
Next, the green sheets g8 and g9 on which the plurality of unit via conductors 12u are formed, and the green sheet 10 on which the same unit via conductors 12u, the insulating layer 22, and the plurality of wiring layers 23 are formed are green. The unit via conductors 12u for each of the sheets g8 to g10 were laminated so as to be in contact with each other along the axial direction, and further pressure-bonded.

その結果、図13に示すように、グリーンシートg8〜10が積層されてなり、表面6bおよび裏面7と該表面6bに開口するキャビティ16とを有する未焼成の基板本体2bと、前記キャビティ16の底面17と基板本体2bの裏面7との間を貫通する複数のビア導体21と、上記基板本体2bの周辺部を同軸状に貫通する未焼成で複数ずつで且つ複数組の単位ビア導体12uと、これらのうち、絶縁すべき単位ビア導体12u同士間で且つグリーンシートg9,g10間に形成された未焼成の絶縁層22と、を備えた未焼成の積層体26が得られた。
上記積層体26において、複数の配線層23のうち、一部の配線層23の上・下面には、単位ビア導体12uが同軸状に接続されており、残部の配線層23では、該配線層23内に位置する隙間23s内に形成された未焼成の絶縁層22によって、該絶縁層22の中心部における上・下面に同軸状に接する上下の単位ビア導体12uが絶縁されていた。
As a result, as shown in FIG. 13, green sheets g8 to 10 are laminated, an unfired substrate body 2b having a front surface 6b and a back surface 7 and a cavity 16 opened to the front surface 6b, A plurality of via conductors 21 penetrating between the bottom surface 17 and the back surface 7 of the substrate body 2b; a plurality of unfired and plural sets of unit via conductors 12u coaxially penetrating the peripheral portion of the substrate body 2b; Of these, an unfired laminated body 26 including unfired insulating layers 22 formed between the unit via conductors 12u to be insulated and between the green sheets g9 and g10 was obtained.
In the multilayer body 26, the unit via conductors 12 u are coaxially connected to the upper and lower surfaces of a part of the wiring layers 23 among the plurality of wiring layers 23. The upper and lower unit via conductors 12 u that are in coaxial contact with the upper and lower surfaces of the central portion of the insulating layer 22 are insulated by the unfired insulating layer 22 formed in the gap 23 s located in the inner space 23.

しかも、前記積層および圧着工程では、予め、前記絶縁層22の幅w2を上・中層のグリーンシートg8,g9の幅w1よりも大きく設定したので、キャビティ16を囲む上記グリーンシートg8,g9が当該キャビティ16側に傾く所謂「倒れ込み」現象を確実に防ぐこともできた。
更に、図13に示すように、前記ビア導体21の上・下端に内部端子19と裏面端子15とを個別に接続すると共に、同軸状である複数の単位ビア導体12uの上・下端ごとに、表面端子14と裏面端子15とを個別に接続した。
そして、上記積層体26を脱脂および焼成した後、電解Niメッキ液および電解Auメッキ液に順次浸漬して、上記基板本体2bの外部に露出する各表面端子14、各裏面端子15、および各内部端子19との表面に、下地側のNiメッキ膜と表層側のAuメッキ膜とからなるメッキ層(図示せず)を被覆した。その結果、前記図9,図10で示した第1の多層セラミック基板1bが得られた。
Moreover, since the width w2 of the insulating layer 22 is set in advance larger than the width w1 of the upper and middle green sheets g8 and g9, the green sheets g8 and g9 surrounding the cavity 16 It was also possible to reliably prevent the so-called “falling” phenomenon that leans toward the cavity 16 side.
Further, as shown in FIG. 13, the internal terminal 19 and the back terminal 15 are individually connected to the upper and lower ends of the via conductor 21, and each of the upper and lower ends of the plurality of unit via conductors 12 u that are coaxial, The front surface terminal 14 and the back surface terminal 15 were individually connected.
And after degreasing and baking the said laminated body 26, each surface terminal 14, each back surface terminal 15 exposed to the exterior of the said board | substrate main body 2b, each back surface terminal, and each inside are immersed in electrolytic Ni plating liquid and electrolytic Au plating liquid sequentially. The surface of the terminal 19 was covered with a plating layer (not shown) composed of a Ni plating film on the base side and an Au plating film on the surface layer side. As a result, the first multilayer ceramic substrate 1b shown in FIGS. 9 and 10 was obtained.

尚、前記焼成時でも、予め、前記絶縁層22の幅w2を上・中層のグリーンシートg8,g9の幅w1よりも大きく設定してあったので、焼成後の絶縁層22におけるキャビティ16側の周辺部22aは、該キャビティ16の底面17側に延在しているか、少なくとも当該キャビティ16の側面18と面一状であった。
また、前記焼成工程では、グリーンシートg8〜g10がセラミック層8〜10となると共に、同軸状に接触していた複数ずつの単位ビア導体12uは、複数の連続ビア導体12となり、その一部は、焼成された絶縁層22により絶縁されていた。
更に、以上のような多層セラミック基板1bの製造方法は、多数個取りの形態によって行っても良い。
Even during the firing, since the width w2 of the insulating layer 22 was previously set larger than the width w1 of the upper and middle green sheets g8 and g9, the insulating layer 22 on the cavity 16 side in the fired insulating layer 22 was previously set. The peripheral portion 22 a extends to the bottom surface 17 side of the cavity 16 or is at least flush with the side surface 18 of the cavity 16.
Further, in the firing step, the green sheets g8 to g10 become the ceramic layers 8 to 10, and the plurality of unit via conductors 12u that are in contact with each other coaxially become a plurality of continuous via conductors 12, and part of them Insulated by the fired insulating layer 22.
Furthermore, the manufacturing method of the multilayer ceramic substrate 1b as described above may be performed in a multi-cavity form.

以上のような第2の多層セラミック基板1bの製造方法によれば、前記キャビティ16の底面17と側面18とを形成し且つ厚み方向で隣接するグリーンシートg9,g10間で隣接する複数の配線層23同士間の隙間23gに位置し、且つのグリーンシートg8〜g10を厚み方向で同軸状に貫通する複数の単位ビア導体12uの中間に、前記絶縁層22を形成された。しかも、該絶縁層22におけるキャビティ16側の周辺部22a、あるいは該周辺部22aの一部は、上記キャビティ16の側面18と面一か、あるいは該キャビティ16の底面17側に延在し且つ当該キャビティ16内に露出した。しかも、前記配線層23内の隙間23sに設けた絶縁層22によって、キャビティ16の開口部を囲む基板本体2bの表面6bにも、凹みなどが生じなかった。
従って、複数の連続ビア導体12のうち、導通が不要な連続ビア導体12を絶縁できると共に、積層工程、圧着工程、および焼成工程で、キャビティ16を囲む上層側のグリーンシートg8,g9が当該キャビティ16側に傾く事態を抑制できたので、所要の形状および寸法のキャビティ16を含む基板本体2bを有する多層セラミック基板1bを、比較的低コストで確実に製造することができた。
According to the manufacturing method of the second multilayer ceramic substrate 1b as described above, a plurality of wiring layers which form the bottom surface 17 and the side surface 18 of the cavity 16 and are adjacent between the green sheets g9 and g10 adjacent in the thickness direction. The insulating layer 22 is formed in the middle of a plurality of unit via conductors 12u that are located in the gap 23g between the 23 and pass through the green sheets g8 to g10 coaxially in the thickness direction. Moreover, the peripheral portion 22a on the cavity 16 side in the insulating layer 22 or a part of the peripheral portion 22a is flush with the side surface 18 of the cavity 16 or extends to the bottom surface 17 side of the cavity 16 and It was exposed in the cavity 16. In addition, the insulating layer 22 provided in the gap 23 s in the wiring layer 23 did not cause dents on the surface 6 b of the substrate body 2 b surrounding the opening of the cavity 16.
Therefore, among the plurality of continuous via conductors 12, the continuous via conductor 12 which does not need to be electrically conductive can be insulated, and the upper side green sheets g8 and g9 surrounding the cavity 16 can be formed in the cavity in the laminating process, the crimping process, and the firing process. Since the situation of tilting toward the side 16 could be suppressed, the multilayer ceramic substrate 1b having the substrate body 2b including the cavity 16 having the required shape and size could be reliably manufactured at a relatively low cost.

本発明は、以上において説明した各形態に限定されるものではない。
例えば、前記セラミック層のセラミックは、前記アルミナに限らず、ムライトや窒化アルミニウムなどの高温焼成セラミックとしたり、ガラス−セラミックなどの低温焼成セラミックとしても良い。後者の場合、前記連続ビア導体や配線層などの導体には、CuあるいはAgが適用される。
また、前基板本体を構成するセラミック層の数は、少なくとも2層であるが、4層以上としても良い。これらに応じて、前記グリーンシートの数も定められる。
更に、前記基板本体内に複数の導通しない前記連続ビア導体が併設されている場合、これらの連続ビア導体を絶縁する前記絶縁層は、異なる位置のセラミック層間ごとに位置する前記隙間に形成しても良い。
加えて、前記キャビティは、1個の基板本体に2つ以上を併設しても良く、例えば、基板本体の同じ表面に2つのキャビティを開口させた形態や、同じ基板本体の表面と裏面とに厚み方向で対称に2つのキャビティを併設しても良い。
The present invention is not limited to the embodiments described above.
For example, the ceramic of the ceramic layer is not limited to the alumina, but may be a high-temperature fired ceramic such as mullite or aluminum nitride, or a low-temperature fired ceramic such as glass-ceramic. In the latter case, Cu or Ag is applied to the conductor such as the continuous via conductor or the wiring layer.
The number of ceramic layers constituting the front substrate body is at least two, but may be four or more. Accordingly, the number of green sheets is also determined.
Further, when a plurality of non-conducting continuous via conductors are provided in the substrate body, the insulating layer that insulates these continuous via conductors is formed in the gaps that are located between the ceramic layers at different positions. Also good.
In addition, two or more cavities may be provided in one substrate body. For example, two cavities are opened on the same surface of the substrate body, or on the front and back surfaces of the same substrate body. Two cavities may be provided symmetrically in the thickness direction.

本発明によれば、複数のセラミック層を厚み方向に沿って同軸状に貫通する複数の連続ビア導体を有し、導通が不要な連続ビア導体のみを絶縁し、且つ基板本体の寸法および形状が正確な多層セラミック基板、および該多層セラミック基板を比較的低コストによって確実に得られる製造方法を提供するできる。   According to the present invention, there are a plurality of continuous via conductors that pass through a plurality of ceramic layers coaxially along the thickness direction, only the continuous via conductors that do not require conduction are insulated, and the size and shape of the substrate body are It is possible to provide an accurate multilayer ceramic substrate and a manufacturing method capable of reliably obtaining the multilayer ceramic substrate at a relatively low cost.

1a,1b……………………………多層セラミック基板
2a,2b……………………………基板本体
3〜5,8〜10……………………セラミック層
6b……………………………………表面
12……………………………………連続ビア導体
12h…………………………………ビアホール
12u…………………………………単位ビア導体
13,23……………………………配線層
13s,13g,23s,23g…隙間
16……………………………………キャビティ
17……………………………………底面
18……………………………………側面
20,22……………………………絶縁層(セラミック系の絶縁層)
20p…………………………………絶縁ペースト
22a…………………………………絶縁層の周辺部
g3〜g5,g8〜g10…………グリーンシート
1a, 1b ......................................................... Multilayer ceramic substrate 2a, 2b ........................... ………… Substrate body 3-5, 8-10 …………………… Ceramic layer 6b …………………………………… Surface 12 …………………………………… Continuous via conductor 12h ………………………………… Via hole 12u ………………………………… Unit via conductors 13, 23 …………………………… Wiring layers 13s, 13g, 23s, 23g… Gap 16 …………………… ……………… Cavity 17 …………………………………… Bottom 18 …………………………………… Side 20, 22 …………………… ……… Insulating layer (ceramic insulating layer)
20p …………………………………… Insulating paste 22a ………………………………… Periphery of insulating layer g3 to g5, g8 to g10 ……… Green sheet

Claims (4)

複数のセラミック層が積層された基板本体と、
上記基板本体において、隣接する複数のセラミック層を厚み方向に沿って同軸状に貫通する複数の連続ビア導体と、を備えた多層セラミック基板であって、
上記連続ビア導体の少なくとも1つは、該連続ビア導体において隣接する上記複数のセラミック層間に位置するセラミック系の絶縁層により絶縁されていると共に、かかる絶縁層は、隣接する上記セラミック層間に形成された配線層内の隙間、あるいは、複数の配線層同士間の間隙に位置している、
ことを特徴とする多層セラミック基板。
A substrate body in which a plurality of ceramic layers are laminated;
In the above substrate body, a multilayer ceramic substrate comprising a plurality of continuous via conductors coaxially passing through a plurality of adjacent ceramic layers along the thickness direction,
At least one of the continuous via conductors is insulated by a ceramic insulating layer located between the plurality of adjacent ceramic layers in the continuous via conductor, and the insulating layer is formed between the adjacent ceramic layers. Located in the gap between the wiring layers or between the plurality of wiring layers,
A multilayer ceramic substrate characterized by the above.
前記基板本体は、該基板本体の表面の中央側に開口するキャビティを有し、隣接する複数の前記セラミック層は、該キャビティの底面と側面とを形成するものであり、前記絶縁層の周辺部の一部は、上記キャビティの側面と面一状であるか、あるいは該キャビティの底面側に延在し且つ当該キャビティ内に露出している、
ことを特徴とする請求項1に記載の多層セラミック基板。
The substrate body has a cavity opened to the center side of the surface of the substrate body, and the plurality of adjacent ceramic layers form a bottom surface and a side surface of the cavity, and a peripheral portion of the insulating layer A part of the surface is flush with the side surface of the cavity, or extends to the bottom surface side of the cavity and is exposed in the cavity.
The multilayer ceramic substrate according to claim 1, wherein:
複数のセラミック層が積層された基板本体と、該基板本体において、隣接する複数のセラミック層を厚み方向に沿って同軸状に貫通する複数の連続ビア導体と、を備えた多層セラミック基板の製造方法であって、
複数のセラミックグリーンシートに複数のビアホールを形成する工程と、
上記グリーンシートごとのビアホールに導電性ペーストを充填して未焼成の単位ビア導体を形成する工程と、
上記グリーンシートの表面および裏面の少なくとも一方に導電性ペーストを印刷して、未焼成で内部に隙間を有する配線層、あるいは未焼成で隣接する複数の配線層を形成する工程と、
少なくとも1つの上記グリーンシートの表面および裏面の少なくとも一方において、上記単位ビア導体の端面が露出する位置およびその周囲に、セラミック系の絶縁ペーストを配置して未焼成の絶縁層を形成する工程と、
複数の上記グリーンシートを、該グリーンシートごとの上記単位ビア導体が軸方向に沿って同軸状に連続するように積層する工程と、を含み、
上記絶縁層を形成する工程において、上記未焼成の絶縁層は、上記配線層内の隙間、あるいは上記複数の配線層同士間の間隙に形成される、
ことを特徴とする多層セラミック基板の製造方法。
A method of manufacturing a multilayer ceramic substrate comprising: a substrate body on which a plurality of ceramic layers are laminated; and a plurality of continuous via conductors that pass through the adjacent ceramic layers coaxially along the thickness direction in the substrate body. Because
Forming a plurality of via holes in a plurality of ceramic green sheets;
Filling the via hole for each green sheet with a conductive paste to form an unfired unit via conductor;
A step of printing a conductive paste on at least one of the front and back surfaces of the green sheet to form a wiring layer that is unfired and has a gap inside, or a plurality of wiring layers that are unfired and adjacent to each other;
Forming a green insulating layer by disposing a ceramic-based insulating paste at and around the position where the end face of the unit via conductor is exposed in at least one of the front surface and the back surface of the at least one green sheet;
Laminating a plurality of the green sheets such that the unit via conductors for each green sheet are coaxially continuous along the axial direction,
In the step of forming the insulating layer, the unfired insulating layer is formed in a gap in the wiring layer or in a gap between the plurality of wiring layers.
A method for producing a multilayer ceramic substrate.
前記複数のグリーンシートは、前記基板本体の表面の中央側に開口するキャビティの底面と、該キャビティの側面とを構成するものであり、
上記複数のグリーンシート間に形成される前記未焼成の絶縁層の周辺部の一部は、前記積層工程において、上記キャビティの側面と面一状であるか、あるいは該キャビティの底面に延在し且つ当該キャビティ内に露出している、
ことを特徴とする請求項3に記載の多層セラミック基板の製造方法。
The plurality of green sheets constitute a bottom surface of a cavity that opens to the center side of the surface of the substrate body, and a side surface of the cavity.
A part of the periphery of the unfired insulating layer formed between the plurality of green sheets is flush with the side surface of the cavity or extends to the bottom surface of the cavity in the stacking step. And exposed in the cavity,
The method for producing a multilayer ceramic substrate according to claim 3.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019129189A (en) * 2018-01-22 2019-08-01 京セラ株式会社 Wiring board, package, and electronic device
JP2019133987A (en) * 2018-01-29 2019-08-08 京セラ株式会社 Substrate for storing electronic component and package using the same

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05102342A (en) * 1991-04-03 1993-04-23 Coors Electron Package Co Method for obtaining via-pattern in ceramic sheet and device fabricated therewith
JPH06291463A (en) * 1993-03-31 1994-10-18 Ngk Insulators Ltd Multilayer interconnection ceramic board and its manufacture
JPH11346057A (en) * 1998-06-01 1999-12-14 Ngk Spark Plug Co Ltd Multilayered ceramic board
JP2002353626A (en) * 2001-05-28 2002-12-06 Kyocera Corp Multilayer wiring board and method of manufacturing the same
US6541712B1 (en) * 2001-12-04 2003-04-01 Teradyhe, Inc. High speed multi-layer printed circuit board via
JP2004165247A (en) * 2002-11-11 2004-06-10 Matsushita Electric Ind Co Ltd Multilayer ceramic substrate, its manufacturing method, device for communication and communication apparatus using the same
JP2007266196A (en) * 2006-03-28 2007-10-11 Dainippon Printing Co Ltd Multilayer printed-wiring board and manufacturing method thereof
JP2008532326A (en) * 2005-03-04 2008-08-14 サンミナ−エスシーアイ コーポレーション Simultaneous and selective division of via structure with plating resist
JP2011040662A (en) * 2009-08-18 2011-02-24 Ngk Spark Plug Co Ltd Wiring board and method of manufacturing the same

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05102342A (en) * 1991-04-03 1993-04-23 Coors Electron Package Co Method for obtaining via-pattern in ceramic sheet and device fabricated therewith
JPH06291463A (en) * 1993-03-31 1994-10-18 Ngk Insulators Ltd Multilayer interconnection ceramic board and its manufacture
JPH11346057A (en) * 1998-06-01 1999-12-14 Ngk Spark Plug Co Ltd Multilayered ceramic board
JP2002353626A (en) * 2001-05-28 2002-12-06 Kyocera Corp Multilayer wiring board and method of manufacturing the same
US6541712B1 (en) * 2001-12-04 2003-04-01 Teradyhe, Inc. High speed multi-layer printed circuit board via
JP2004165247A (en) * 2002-11-11 2004-06-10 Matsushita Electric Ind Co Ltd Multilayer ceramic substrate, its manufacturing method, device for communication and communication apparatus using the same
JP2008532326A (en) * 2005-03-04 2008-08-14 サンミナ−エスシーアイ コーポレーション Simultaneous and selective division of via structure with plating resist
JP2007266196A (en) * 2006-03-28 2007-10-11 Dainippon Printing Co Ltd Multilayer printed-wiring board and manufacturing method thereof
JP2011040662A (en) * 2009-08-18 2011-02-24 Ngk Spark Plug Co Ltd Wiring board and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019129189A (en) * 2018-01-22 2019-08-01 京セラ株式会社 Wiring board, package, and electronic device
JP2019133987A (en) * 2018-01-29 2019-08-08 京セラ株式会社 Substrate for storing electronic component and package using the same

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