JP2014216382A - Epitaxial wafer, light-receiving element, optical sensor device and epitaxial wafer manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an epitaxial wafer and the like which can obtain good crystallinity so as to enable inhibition of a dark current.SOLUTION: An epitaxial wafer according to the present invention is formed on a substrate of a III-V semiconductor and comprises a buffer layer which is located in contact with the substrate and contains phosphor (P) and a light-receiving layer located on the buffer layer. A thickness d of the buffer layer is 0.002 times or more of a thickness t of a laminate from a top face of the buffer layer to a top face of the epitaxial layer.

Description

  The present invention relates to an epitaxial wafer, a light receiving element, an optical sensor device, and an epitaxial wafer manufacturing method, and more specifically, an epitaxial wafer, a light receiving element, an optical sensor device, and an epitaxial wafer having excellent crystallinity. This relates to a manufacturing method.

  Since III-V compound semiconductors using an InP substrate have a band gap energy corresponding to the near infrared region, research and development of light receiving elements for communication, biopsy, night imaging, and the like are being conducted. Among these, since the absorption spectrum of a substance related to a living body or the environment is located in the near-infrared to infrared wavelength range, the light receiving sensitivity using the InP substrate is extended to the long wavelength range. It has become an important theme. For example, practical research has been conducted in which an InGaAs light receiving layer epitaxially grown on an InP substrate is used for a light receiving element in the near infrared region. In addition, in order to increase sensitivity in a longer wavelength region, there has been proposed a photodiode including a light-receiving layer having an InGaAs / GaAsSb type 2 multiple quantum well (MQW) structure on an InP substrate (non-patent document). Reference 1). This photodiode has a cut-off wavelength of 2.39 μm, and shows a sensitivity characteristic from a wavelength of 1.7 μm to 2.7 μm.

  Further, type 2 (InGaAs / GaAsSb) MQW is formed on an InP substrate, and p-type impurity zinc (Zn) is selectively diffused by using a selective diffusion mask pattern, so that the regions are not selectively diffused. There has been a proposal of a planar photodiode in which the formed pixels are formed (Patent Document 1). (InP window layer / InGaAs diffusion concentration distribution adjusting layer) is disposed on the MQW. Since this planar photodiode does not require etching accompanying the formation of the mesa structure, it can maintain good crystallinity and suppress dark current to a low level.

JP 2009-206499 A

R. Sidhu, et.al. "ALong-Wavelength Photodiode on InP Using Lattice-Matched GaInAs-GaAsSb Type-II Quantum Wells, IEEE Photonics Technology Letters, Vol.17, No.12 (2005), pp.2715-2717

  When an epitaxial wafer made of type 2 (InGaAs / GaAsSb) MQW, window layer, etc. is manufactured by metal organic vapor phase epitaxy (MOVPE) method, the cause is not fully understood, but due to the surface properties of the substrate, the crystal May decrease. In extreme cases, convex portions may be generated on the surface of the epitaxial wafer as the crystallinity decreases. In general, the present invention is not limited to the above-mentioned type of photodiode, and it is beneficial not only to the light receiving element but also to various semiconductor elements if a predetermined epitaxial wafer can be efficiently manufactured and excellent crystallinity can be secured.

  An object of the present invention is to provide an epitaxial wafer, a method for manufacturing the same, a light receiving element using the epitaxial wafer, and an optical sensor device that can obtain good crystallinity so as to suppress dark current. The application of the present invention is not limited to the metal organic vapor phase epitaxy, but is effective for other growth methods. Therefore, it is not necessary to limit the epitaxial growth method to any one of the epitaxial growth methods in the present invention.

  The epitaxial wafer of the present invention is an epitaxial wafer formed on a substrate of a group III-V semiconductor, and is a buffer layer containing phosphorus (P) located in contact with the substrate, and a light receiving layer located on the buffer layer The thickness d of the buffer layer is 0.002 times (0.002 t) or more of the thickness t of the stacked body from the upper surface of the buffer layer to the upper surface of the epitaxial layer. The epitaxial wafer manufacturing method of the present invention includes a step of growing a buffer layer containing phosphorus (P) in contact with a substrate, a step of growing a light-receiving layer on the buffer layer, and an epitaxial layer formed from the upper surface of the buffer layer. In this manufacturing method, the thickness of the laminate reaching the upper surface is t, and the thickness d of the buffer layer is 0.002 t or more.

  Another epitaxial wafer of the present invention is an epitaxial wafer formed on a group III-V semiconductor substrate, which is in contact with the substrate and does not contain phosphorus (P), and is positioned on the buffer layer. The buffer layer has a thickness d that is 0.25 times (0.25 t) or more the thickness t of the stacked body from the upper surface of the buffer layer to the upper surface of the epitaxial layer. Another epitaxial wafer manufacturing method according to the present invention includes a step of growing a buffer layer not containing phosphorus (P) in contact with a substrate, a step of growing a light-receiving layer on the buffer layer, and an upper surface of the buffer layer. In this manufacturing method, the thickness of the stacked body reaching the upper surface of the epitaxial layer is t, and the thickness d of the buffer layer is 0.25 t or more.

  According to the epitaxial wafer and the like of the present invention, good crystallinity can be obtained while efficiently producing.

It is a figure which shows the epitaxial wafer in embodiment of this invention. It is sectional drawing which shows the light receiving element manufactured from the epitaxial wafer of FIG. It is sectional drawing when a convex-shaped part produces | generates on the epitaxial wafer surface from a foreign material. FIG. 3B is a plan view of the epitaxial wafer of FIG. 3A. It is a flowchart of the manufacturing method of the epitaxial wafer of FIG. It is a figure which shows the piping system etc. of the film-forming apparatus of all the organic MOVPE method. It is a figure which shows the flow of an organometallic molecule | numerator, and the flow of temperature. It is a schematic diagram of the organometallic molecule in the substrate surface.

[Description of Embodiment of Present Invention]
First, the contents of the embodiments of the present invention will be listed and described.
1. Epitaxial wafer:
(1) Buffer layer thickness range:
When the buffer layer contains phosphorus (P), the thickness from the upper surface of the buffer layer to the upper surface of the epitaxial wafer is t, and the thickness d of the buffer layer is 0.002 t or more, more preferably 0.01 t or more, more preferably 0. .05t or more. Thereby, the crystallinity of the epitaxial wafer can be improved and dark current can be suppressed. After the surface properties of the InP substrate are thoroughly cleaned by etching or the like, a buffer layer is grown on the substrate. At this time, there may be an inconvenient surface property whose cause has not been fully grasped, for example, a surface portion collectively referred to as a foreign matter. These unfavorable surface properties are literally covered by the buffer layer 2. In the presence of unfavorable surface properties, crystallinity deteriorates and dark current increases. As described above, a convex portion may be generated on the surface along with a decrease in crystallinity, resulting in a decrease in product yield. The buffer layer can completely or partially embed the foreign material in the buffer layer to prevent the crystallinity from deteriorating and to prevent the crystal defects from expanding.

  When the buffer layer does not contain P, the thickness d of the buffer layer is set to 0.25 t or more. More preferably, it is 0.3 t or more, and further preferably 0.5 t or more. Thereby, similarly, the crystallinity of the epitaxial wafer can be improved and the dark current can be suppressed. Moreover, it is common also in the point which suppresses the influence on an unfavorable surface property, for example, deterioration of the crystallinity of a foreign material.

  Usually, t = about 3.5 μm to 6 μm, and the average is 4.75 μm. When the buffer layer contains P, the lower limit is about 0.01 μm (4.75 μm × 0.002) as the average thickness t of the laminate is 4.75 μm. The thicker the buffer layer, the more effective it is to embed adhering foreign matter. Therefore, the thickness is more preferably 0.05 μm or more, and further preferably 0.25 μm or more. In the case where P is not included, the thickness is preferably about 1.2 μm (4.75 μm × 0.25) or more, more preferably 1.4 μm or more, and further preferably 2.4 μm or more.

  The upper limit of the thickness d of the buffer layer is about 0.5 t regardless of the presence or absence of P. As the average thickness t is 4.75 μm, the upper limit is about 2.4 μm regardless of the presence or absence of P. Although the buffer layer is grown in contact with the substrate, the light receiving layer may or may not be in contact with the buffer layer. The same applies to the relationship of the window layer to the light receiving layer.

(2) Substrate and buffer layer materials:
(I) When the substrate is an InP substrate and the buffer layer contains phosphorus (P):
The buffer layer is preferably an InP single layer or an (InP / InGaAs) composite layer. This facilitates lattice matching with the InP substrate, improves the crystallinity of the light receiving layer, and lowers the dark current. In particular, in the case of an (InP / InGaAs) composite layer, lattice matching with the InP substrate is taken, and if the light receiving layer includes an InGaAs layer that is often used in the near infrared, the compatibility with the light receiving layer is also improved. The crystallinity of the layer can be improved.
(Ii) When the substrate is an InP substrate and the buffer layer does not contain phosphorus (P):
The buffer layer is preferably an InGaAs single layer. In this case, in order to improve the degree of lattice matching between the InP substrate and the upper light receiving layer, the thickness d is preferably increased as described above.

(3) Light receiving layer:
The light receiving layer may have a type 2 (GaAs _1-x Sb _x (0 <x ≦ 1) / In _y Ga _1-y As (0 <y ≦ 1)) multiple quantum well structure. As a result, an epitaxial wafer including a light-receiving layer having a multiple quantum well structure, which is difficult to manufacture with good yield while ensuring good crystallinity, can be obtained while ensuring economic efficiency.

(4) Foreign matter dispersed on the substrate before growing the buffer layer:
One of the unfavorable surface properties is a foreign object whose cause is not fully understood. When the epitaxial wafer is seen in a plan view, foreign matters are dispersed at an average density of 0.5 cm ⁻² or less, and the buffer layer is seen in a cross section so that the foreign matters are partially or completely embedded. Good. Here, the foreign matter is a foreign matter adhering to the substrate immediately before the growth of the buffer layer. There are various cases of the cause of the foreign object at that time, and it may not be particularly specified. However, in extreme cases where convex portions are generated on the surface of the epitaxial wafer due to deterioration of crystallinity, the distribution of foreign matters dispersed on the substrate imaged at the stage of the substrate at the same growth opportunity, and the distribution of the convex portions described above Is known to overlap. For example, foreign substances having an average diameter of 5 μm or less may be dispersed on the substrate at an average density of 0.05 cm ^{−2 to} 0.5 cm ⁻² . Foreign matter dispersed on the substrate can be observed with an EDX (energy dispersive X-ray spectroscopy), AES (Auger electron spectroscopy), SEM (scanning electron microscope), analytical SEM, etc. density of the epitaxial wafer Can be weighed. As described above, the buffer layer can partially or completely embed the foreign material to ensure good crystallinity. In a predetermined case, surface defects can be suppressed and the yield can be increased.

(5) Board type:
The substrate can be any one of (GaAs, GaP, GaSb, InP, InAs, InSb, AlSb, and AlAs). As a result, by selecting a substrate from the group III-V semiconductors described above, suitable light-receiving layers and epitaxial wafers can be manufactured with high yield according to the wavelength range in the wide range from the near infrared to the far infrared. It becomes possible to do.

(6) The reason why the buffer layer does not have to completely embed foreign matter:
The reason why the buffer layer does not need to be completely embedded with foreign matter is based on the following reason.
(I) Even if the foreign matter is not completely embedded, good crystallinity can be obtained so that the dark current can be suppressed sufficiently low. The reason is not fully understood.
(Ii) When a convex portion is generated on the surface of the epitaxial wafer starting from the foreign matter dispersed in the substrate, the crystallinity is also lowered. In this case, if it is limited to the influence of the convex portion itself on the surface of the epitaxial wafer, the average diameter of the epitaxial wafer should not be about 30 μm when viewed in plan. The numerical value of the average diameter of about 30 μm is based on the fact that the pixel pitch of the light receiving element array manufactured using this epitaxial wafer is about 30 μm. The convex portions having an average diameter of 30 μm appearing on the surface are substantially the same as the pitch of the pixels P. For this reason, according to the convex part of this level, it can be accommodated to the extent that about 1 to 4 pixels cannot be formed. Conversely, the thickness of the buffer layer is set in the above range so that the average diameter of the convex portions after the epitaxial wafer is formed does not exceed 30 μm. By suppressing the growth of the convex portion, the deterioration of crystallinity can be limited. With respect to the convex portion, a loss of about 1 to 4 pixels at a single place can be compensated by software (program). If the defect has a larger plane size, the missing pixel can be clearly recognized. In general, the density of the convex portions having a diameter of 30 μm or more on the surface of the epitaxial wafer is preferably 0.05 cm ⁻² or more and 0.5 cm ⁻² or less. By suppressing the growth of such convex portions, it is possible to reduce the decrease in crystallinity.

(7) Light receiving element and optical sensor device:
The light receiving element of the present invention has a laminated structure on any of the above epitaxial wafers. As a result, a light receiving element having a low dark current, no large pixel omission, and a good display image can be obtained with a high yield and a low manufacturing cost. An optical sensor device of the present invention includes the light receiving element described above. This optical sensor device includes a CMOS (Complementary Metal Oxide Semiconductor) having readout electrodes from each pixel of the light receiving element, a spectroscope (diffraction grating), an optical element such as a lens, a control device such as a microcomputer, and the like. An optical sensor device with excellent performance can be obtained with high economic efficiency.

2. Epitaxial wafer manufacturing method:
(1) An epitaxial wafer manufacturing method according to the present invention is a method for manufacturing an epitaxial wafer comprising a substrate of a III-V group semiconductor, a buffer layer, and a light receiving layer, wherein the epitaxial wafer is in contact with the substrate and is made of phosphorus (P) The step of growing a buffer layer containing, the step of growing a light receiving layer on the buffer layer, and the thickness of the stacked body from the upper surface of the buffer layer to the upper surface of the epitaxial layer is t. This is the manufacturing method as described above. The reason why the thickness d of the buffer layer containing P is in the above range is as described in the epitaxial wafer. By setting it as such a thickness range, favorable crystallinity can be ensured and dark current can be suppressed. In addition, when foreign matter is dispersed on the surface of the substrate, the foreign matter is partially or completely embedded to ensure good crystallinity and suppress the growth of the convex portion on the surface of the epitaxial wafer. be able to. In this case, for example, the substrate can be an InP substrate, and the buffer layer containing P can be an InP layer or an (InP / InGaAs) composite layer. The reason is also as described above. Any growth method may be used for the growth of the epitaxial layer, but the MOVPE method can efficiently obtain an epitaxial layer with good crystallinity. Further, an all-organic metal vapor phase epitaxy method described in detail later may be used.

(2) Another method for producing an epitaxial wafer according to the present invention is a method for producing an epitaxial wafer comprising a substrate of a III-V semiconductor, a buffer layer, and a light receiving layer. The step of growing the buffer layer not containing P), the step of growing the light-receiving layer on the buffer layer, and the thickness d of the stack from the upper surface of the buffer layer to the upper surface of the epitaxial layer is t. This is a manufacturing method of 0.25 t or more. The reason why the thickness d of the buffer layer not containing P is in the above range is the same as described in the section of the epitaxial wafer. By setting it as such a thickness range, favorable crystallinity can be ensured and dark current can be suppressed. In addition, when foreign matter is dispersed on the surface of the substrate, it is possible to ensure good crystallinity and to suppress the occurrence of convex portions on the surface of the epitaxial wafer by almost completely embedding the foreign matter. . In this case, for example, the substrate can be an InP substrate and the buffer layer not containing P can be an InGaAs layer. The reason is also as described above.

(3) Foreign matter:
The foreign matter is as described above. As described above, the buffer layer partially or completely embeds the foreign matter, thereby ensuring good crystallinity. In addition, these buffer layers can suppress the growth of surface defects and prevent the yield from decreasing.

(4) Buffer layer growth temperature:
The growth temperature of the buffer layer can be 400 ° C. or higher and 600 ° C. or lower. By setting the growth temperature of the buffer layer to 400 ° C. or more and 600 ° C. or less, a specific element that promotes defects in the foreign matter, for example, an element such as antimony (Sb) is hardly activated. However, when the light-receiving layer contains antimony (Sb), it is preferably grown at 400 ° C. or higher and 480 ° C. or lower.

(5) Growth temperature of epitaxial layer:
The growth temperature of each epitaxial layer from the upper layer in contact with the buffer layer to the window layer is preferably 400 ° C. or more and 525 ° C. or less. Accordingly, for example, when the light receiving layer contains Sb, the surfactant action of Sb can be made relatively small, and the size of the convex portion appearing in the window layer can be suppressed.

(6) Light receiving layer:
The light receiving layer may have a type 2 (GaAs _1-x Sb _x (0 <x ≦ 1) / In _y Ga _1-y As (0 <y ≦ 1)) multiple quantum well structure. As a result, an epitaxial wafer provided with the light-receiving layer having the antimony-containing multiple quantum well structure, which is difficult to manufacture with good yield while ensuring good crystallinity, can be obtained while ensuring economic efficiency.

[Details of the embodiment of the present invention]
Next, specific examples of the epitaxial wafer and the like according to the embodiment of the present invention will be described with reference to the drawings. In addition, this invention is not limited to these illustrations, is shown by the claim, and intends that all the changes within the meaning and range equivalent to the claim are included.

FIG. 1 is a cross-sectional view showing an epitaxial wafer 1a according to an embodiment of the present invention. The epitaxial wafer 1a includes an InP substrate 1, a buffer layer 2 that is epitaxially grown in contact with the InP substrate 1, and an epitaxial multilayer 7 positioned thereon. The thickness of the epitaxial laminate 7 is assumed to be t (μm). The contents of the buffer layer 2 are as follows.
(InP substrate 1 / n-type buffer layer 2 / type 2 (InGaAs / GaAsSb) multi-quantum well (MQW) light-receiving layer 3 / InGaAs diffusion concentration distribution adjusting layer 4 / InP window layer 5)
Of the above, the InGaAs diffusion concentration distribution adjusting layer 4 may be omitted. The buffer layer 2 is preferably as follows.

  In the case of a buffer layer containing P, the buffer layer 2 is an InP single layer or an (InP / InGaAs) composite layer. In this case, the total thickness d of the buffer layer 2 is set to 0.002 times (0.002 t) or more of the thickness t of the stacked body 7 of epitaxial wafers. This makes it possible to increase the degree of lattice matching with the InP substrate 1 even when the thickness is relatively small. In particular, in the case of an (InP / InGaAs) composite layer, not only the degree of lattice matching with the substrate 1 but also The degree of lattice matching with InGaAs / GaAsSb having a type 2 multiple quantum well structure can also be increased. In particular, when a foreign substance whose cause cannot be specified is dispersed in the substrate immediately before the buffer layer 2 is grown in the thin film growth chamber, the foreign substance is partially or completely embedded to form the upper type 2 multiple quantum well structure. The crystallinity of the light receiving layer 3 can be maintained. In particular, the coarse growth of the convex portion that may be generated on the surface of the window layer 5 can be suppressed. In the case of a buffer layer not containing P, the InGaAs buffer layer 2 has a thickness of 0.25 t or more, for example, about 1.2 μm (4.75 μm × 0.25), more preferably 1.4 μm or more, It should be 2.4 μm or more.

  Immediately before the growth of the buffer layer 2, foreign matter may be scattered on the surface of the InP substrate 1 due to the reason that it is not sufficiently grasped as described above. In this case, when any one of the buffer layers 2 is grown thick as described above, the buffer layer 2 grows so as to embed foreign substances in itself. As a result, the foreign matter may form some convex portions K on the surface of the buffer layer 2, but does not grow as a surface defect. Even if the foreign matter is embedded in the buffer layer 2 and the light receiving layer 3 thereabove contains a layer containing Sb, it does not grow into a large-sized defect.

  On the buffer layer 2, a type 2 (GaAsSb / InGaAs) MQW light-receiving layer 3 is grown by 250 pairs of GaAsSb having a thickness of 5 nm and InGaAs having a thickness of 5 nm as a pair, and then an InGaAs diffusion concentration distribution adjusting layer 4 is formed. For example, a thickness of about 0.3 μm is grown, and an InP window layer 5 is grown thereon, for example, with a thickness of about 0.8 μm. By making the buffer layer 2 thick, most of the convex portions K appearing in the window layer 5 can have a diameter of 30 μm or less.

  FIG. 2 is a diagram showing the light receiving element 50 in the embodiment of the present invention. The light receiving element 50 is formed using the epitaxial wafer 1a of FIG. A pixel P and electrodes 11 and 12 are formed on the epitaxial wafer 1a. The light receiving element 50 is a planar light receiving element. However, the epitaxial wafer in the present embodiment is not limited to a planar photodiode, and may be used as a mesa photodiode. As shown in FIG. 2A, a characteristic point of the planar photodiode is an arrangement structure of the pixels P. The p-type region 6 located from the InP window layer 5 through the InGaAs layer 4 and into the light-receiving layer 3 is formed by selectively diffusing Zn of the p-type impurity from the opening of the selective diffusion mask pattern 36 of the SiN film. The p-type region 6 is separated by a region that is not selectively diffused, and becomes a main part of the pixel P. By adjusting the distance between the openings of the selective diffusion mask pattern 36, the p-type region 6 is separated from the adjacent pixel or side surface by a predetermined distance.

  A p-side electrode 11 made of AuZn is provided in the p-type region 6, and an n-side electrode 12 made of AuGeNi is provided in ohmic contact with the back surface of the InP substrate 1. The InP substrate 1 is doped with an n-type impurity to ensure a predetermined level of conductivity. The InP substrate 1 may be insulative or semi-insulating. In that case, the n-side electrode 12 is disposed in ohmic contact with the n-type buffer layer.

  Pixels P are arranged at a pitch of 30 μm. In this embodiment, in order to prevent a decrease in crystallinity and to suppress a decrease in yield, the diameter (plan view) of most convex portions appearing on the window layer 5 starting from foreign matters is set to 30 μm or less. The convex portion appearing in the window layer 5 becomes coarse if no measures are taken, and the pixel P may be lost. If the plane diameter (vertical and horizontal average) of most convex portions appearing in the window layer 5 is 30 μm or less, the number of missing pixels P is estimated to be about four. If there is such a missing pixel, it can be compensated by software (program), and the quality of the image is not deteriorated. In the present embodiment, even if the defect is enlarged by the light receiving layer 3 containing Sb starting from the foreign matter, the plane diameter D of most of the convex portions appearing in the window layer 5 is set based on such a reason. The guideline was to make it 30 μm or less.

For the convex portion that may appear in the window layer 5, the following means (A1) to (A3) are used in order to reduce the diameter (vertical and horizontal average) D to 30 μm or less.
(A1) When the light receiving layer contains Sb, when the buffer layer 2 contains P with the thickness of the buffer layer 2 being t, the lower limit is about 0.02 μm, and the lower limit is about 0.05 μm. Further, the lower limit is preferably about 0.5 μm, and the lower limit may be 1.0 μm to 1.25 μm. Further, when the buffer layer does not contain P, it is preferably about 1.2 μm (4.75 μm × 0.25) or more, more preferably 1.5 μm or more, and further preferably 2 μm or more. FIG. 3A shows the epitaxial wafer 1a when the buffer layer 2 is grown so as to completely embed the foreign matter G therein.

(A2) The growth temperature of the buffer layer 2 is basically 400 ° C. or higher and 600 ° C. or lower, more preferably 400 ° C. or higher and 480 ° C. or lower. When the growth temperature of the buffer layer 2 exceeds 480 ° C., the surfactant action of Sb in the light receiving layer 3 is exhibited, and the effect of embedding foreign matter by the buffer layer 2 becomes difficult to act. By setting the temperature to 480 ° C. or lower, the buffer layer 2 can be completely or partially embedded without activating foreign matter.

(A3) Growing the growth temperature of each layer above the buffer layer 2 to 400 ° C. or more and 525 ° C. or less in order to reduce the plane diameter of most convex portions K appearing in the window layer 5 to 30 μm or less, It works effectively. In particular, the growth temperature is preferably 500 ° C. or lower. That is, the growth temperature of each layer in the light receiving layer 3 / window layer 5 or the light receiving layer 3 / diffusion concentration distribution adjusting layer 4 / window layer 5 is preferably 400 ° C. or more and 525 ° C. or less or 400 ° C. or more and 500 ° C. or less. .
By the above (A1) to (A3), as shown in FIG. 3B, the diameter (vertical / horizontal average) D of most convex portions K appearing in the window layer 5 can be made 30 μm or less.

Next, a method for manufacturing epitaxial wafer 1a in the present embodiment will be described with reference to FIG. The growth method uses the MOVPE method. First, an InP substrate 1 is prepared and placed in a growth chamber. The InP substrate 1 is placed on the substrate table in a state where the surface properties are thoroughly cleaned by etching or the like. At this time, there may be an inconvenient surface property whose cause has not been fully grasped, for example, a surface portion collectively referred to as a foreign matter. These unfavorable surface properties are literally covered by the buffer layer 2. That is, the buffer layer 2 having the above thickness range is grown on the InP substrate 1 by the MOVPE method. For example, the n-type InP buffer layer 2 is epitaxially grown to a thickness of 0.5 μm (500 nm) or more, for example. The thickness of the buffer layer 2 may be about 0.5 μm to 1.5 μm (500 nm to 1500 nm) or more. TeESi (tetraethylsilane) is preferably used for n-type doping of the buffer layer 2. At this time, TMIn (trimethylindium) and PH ₃ (phosphine) are used as the source gas. TBP (tertiary butyl phosphine) may be used instead of PH ₃ . In the growth of the InP buffer layer 2, the growth temperature is generally 400 ° C. or more and 600 ° C. or less, but is preferably 480 ° C. or less as described above. Although the thickness of the buffer layer is also increased, the growth temperature is preferably an unusually low temperature. The reason is as described in (A2) above.

  Also for the growth of each layer above the buffer layer 2, by using the MOVPE method, good crystallinity can be secured efficiently at a low growth temperature. After the buffer layer 2, the type 2 (InGaAs / GaAsSb) MQW light receiving layer 3, the InGaAs diffusion concentration distribution adjusting layer 4 and the InP window layer 5 are consistently grown in the same growth chamber by the MOVPE method. At this time, as described in the above (A3), the growth temperature or the substrate temperature is preferably maintained in the range of 400 ° C. or more and 525 ° C. or less. When the growth temperature is higher than this temperature range, there is a high possibility that the crystallinity is lowered and the size of the defect is increased, and the possibility that the GaAsSb in the light receiving layer 3 is damaged by heat and causes phase separation. To do.

  If the growth temperature is lower than 400 ° C., the diameter of the convex portion K that may be generated is small or the density of the convex portion K is sparse, but the source gas of the MOVPE method is not sufficiently decomposed. , Carbon is incorporated into the epitaxial layer. This is hydrocarbon carbon bonded to metal in the source gas. When carbon is mixed into the epitaxial layer, an unintended p-type region is formed, and performance degradation occurs in a state where the semiconductor element is finished. For example, in the state of the light receiving element, there is a lot of dark current, and it cannot be a practical product.

The semiconductor element or the epitaxial wafer can be manufactured by a normal MOVPE method as described above. In other words, the above-described semiconductor element or the like can be manufactured using a commercially available metal organic vapor phase growth apparatus and using a source gas commonly used therein. However, by using the all-organometallic vapor phase epitaxy method, it is possible to manufacture a material having further excellent crystallinity. The all-organic metal vapor phase growth method is a method using an organic metal gas for all film forming materials, and the difference from a normal metal organic vapor phase growth method is a raw material for growing a III-V group semiconductor layer containing phosphorus. Appears. The difference between all metalorganic vapor phase epitaxy (total organic MOVPE) and ordinary MOVPE is whether tertiary phosphine (TBP) or inorganic phosphine (PH ₃ ) is used as the phosphorus raw material. It appears briefly.

  FIG. 5 shows a piping system and the like of the film formation apparatus 60 of the all-organic metal vapor phase epitaxy method. Although it is a film formation apparatus of all metal organic vapor phase epitaxy, almost the same film formation apparatus is used in the MOVPE method. A quartz tube 65 is disposed in the growth chamber (chamber) 63, and a raw material gas is introduced into the quartz tube 65. A substrate table 66 is disposed in the quartz tube 65 so as to be rotatable and airtight. The substrate table 66 is provided with a heater 66h for heating the substrate. The temperature of the surface of the epitaxial wafer 1 a during film formation is monitored by the infrared temperature monitoring device 61 through a window 69 provided on the ceiling of the growth chamber 63. This monitored temperature is a temperature at the time of growth or a temperature called a film forming temperature or a substrate temperature. In the manufacturing method of the present invention, when the InP buffer layer 2 is formed at a temperature of 400 ° C. or higher and 480 ° C. or lower, 400 ° C. or higher and 480 ° C. or lower are temperatures measured by this temperature monitor. The forced exhaust from the quartz tube 65 is performed by a vacuum pump.

  Every time an epitaxial wafer or the like is grown, an organic metal gas or the like adheres to the inner wall of the growth chamber 63 and accumulates. When the InP substrate 1 is placed on the substrate table 66 and the temperature rises, the deposit may fall into the quartz tube 65 due to a thermal shock such as a difference in thermal expansion, and may scatter and adhere to the surface of the InP substrate 1. . Such a phenomenon is not limited to all metal organic vapor phase epitaxy, but also occurs in common with MOVPE. In the present embodiment, even if foreign matter is accidentally scattered on the InP substrate 1, the means (A 1) to (A 3) keeps the portion with low crystallinity locally, and the convex portion By making the planar diameter 30 μm or less, it is possible to manufacture without reducing the yield.

The source gas is supplied by a pipe communicating with the quartz tube 65. The all-organometallic vapor phase growth method is characterized in that all source gases are supplied in the form of an organometallic gas. That is, the source gas takes the form of a metal combined with various hydrocarbons. In FIG. 5, source gases such as impurities that determine the conductivity type are not specified, but impurities are also introduced in the form of an organometallic gas. An organic metal gas source gas is put in a thermostat and maintained at a constant temperature. Hydrogen (H ₂ ) and nitrogen (N ₂ ) are used as the carrier gas. The organometallic gas is transported by a transport gas, and is sucked by a vacuum pump and introduced into the quartz tube 65. The amount of carrier gas is accurately adjusted by an MFC (Mass Flow Controller). Many flow controllers, solenoid valves, and the like are automatically controlled by a microcomputer.

  After the growth of the buffer layer 2, a type 2 MQW light-receiving layer 3 having InGaAs / GaAsSb as a pair of quantum wells is formed. The thickness of GaAsSb in the quantum well is 5 nm, for example, and the thickness of InGaAs3b is also 5 nm, for example. In the film formation of GaAsSb, TEGa (triethylgallium), TBAs (tertiary butylarsine), and TMSb (trimethylantimony) are used. For InGaAs, TEGa, TMIn, and TBAs can be used. These source gases are all organometallic gases, and the molecular weight of the compound is large. Therefore, it can be completely decomposed at a relatively low temperature of 400 ° C. or more and 525 ° C. or less and contribute to crystal growth. The MQW light-receiving layer 3 can be made sharp in the composition change at the interface of the quantum well by the all-organic metal vapor deposition method. As a result, highly accurate spectrophotometry can be performed.

As a raw material for Ga (gallium), TEGa (triethylgallium) or TMGa (trimethylgallium) may be used. The raw material for In (indium) may be TMIn (trimethylindium) or TEIn (triethylindium). As a raw material of As (arsenic), TBAs (tertiary butylarsine) or TMAs (trimethylarsenic) may be used.
The raw material for Sb (antimony) may be TMSb (trimethylantimony) or TESb (triethylantimony). Further, TIPSb (triisopropylantimony) or TDMASb (trisdimethylaminoantimony) may be used.

The source gas is transported through the piping, introduced into the quartz tube 65, and exhausted. Any number of source gases can be added to the quartz tube 65 by increasing the number of pipes. For example, even a dozen kinds of source gases are controlled by opening and closing the electromagnetic valve.
The flow rate of the source gas is controlled by a flow rate controller (MFC) shown in FIG. 5, and the flow into the quartz tube 65 is turned on and off by opening and closing the electromagnetic valve. The quartz tube 65 is forcibly exhausted by a vacuum pump. There is no stagnation in the flow of the source gas, and it is performed smoothly and automatically. Therefore, the composition is switched quickly when forming the quantum well pair.

  6A is a diagram showing the flow of organometallic molecules and the flow of temperature, and FIG. 6B is a schematic diagram of organometallic molecules on the substrate surface. The surface of the epitaxial wafer 1a is set to a monitored temperature. As shown in FIG. 6B, when large-sized organometallic molecules flow through the wafer surface, the compound molecules that decompose and contribute to crystal growth are in contact with the surface and several organometallic molecules from the surface. It is considered that the film thickness range is limited. However, when the surface temperature of the epitaxial wafer or the substrate temperature is excessively low, such as less than 400 ° C., huge molecules of the source gas, particularly carbon, are not sufficiently decomposed and removed and are taken into the epitaxial wafer 1a. Carbon mixed in the group III-V semiconductor becomes a p-type impurity and forms an unintended semiconductor element. For this reason, the original function of a semiconductor is reduced, and performance deterioration is brought about in the state manufactured to the semiconductor element.

  When a source gas suitable for the chemical composition of the above pair is introduced by switching with an electromagnetic valve while forcibly evacuating with a vacuum pump, after the crystal of the previous chemical composition is grown with a slight inertia, the influence of the previous source gas The crystal having the changed chemical composition can be grown. As a result, the composition change at the hetero interface can be made steep. This means that the previous source gas does not substantially remain in the quartz tube 65.

  When the buffer layer 2 is formed, if it grows in a temperature range exceeding 480 ° C., it becomes difficult to bury the foreign matter as it is. In order to embed foreign matter, it is important to epitaxially grow the buffer layer 2 at 480 ° C. or lower at an unusual low temperature. All metal organic vapor phase epitaxy enables the growth of the buffer layer 2 at such an unusual low temperature with a margin. The reason is as described above. The reason why the buffer layer 2 is grown at 400 ° C. or more is that carbon inevitably contained in the source gas is taken into the epitaxial wafer and causes performance deterioration. However, if it is 600 degrees C or less, it can embed without a problem depending on the property of a foreign material.

  When the type 2 (InGaAs / GaAsSb) MQW light-receiving layer 3 is formed, if it grows in a temperature range exceeding 525 ° C., phase separation occurs in the MQW GaAsSb layer on a large scale, and the size and density of the convex portion K described above are increased. Contribute to the increase. On the other hand, as described above, when the growth temperature is lower than 400 ° C., carbon inevitably contained in the source gas is taken into the epitaxial wafer. Since the mixed carbon functions as a p-type impurity, it may cause performance deterioration to a level that does not result in a product when the semiconductor element is finished.

As shown in FIG. 5, from the formation of the buffer layer 2 to the formation of the InP window layer 5, it is another point that the growth is continued in the same film formation chamber or quartz tube 65 by the all metal organic vapor phase growth method. Become. That is, the epitaxial wafer 1a of the present embodiment does not have a regrowth interface. At the regrowth interface, at least one of the oxygen concentration of 1e17 cm ⁻³ or more and the carbon concentration of 1e17 cm ⁻³ or more is satisfied, the crystallinity is deteriorated, and the surface of the epitaxial multilayer is difficult to be smooth. In the present invention, the oxygen and carbon concentrations are both less than 1e17 cm ⁻³ .

  In the present embodiment, a non-doped InGaAs diffusion concentration distribution adjusting layer 4 having a film thickness of, for example, about 0.3 μm is formed on the MQW light receiving layer 3. The InGaAs diffusion concentration distribution adjusting layer 4 is provided for adjusting the high-density Zn that enters the MQW light-receiving layer 3 when the light-receiving element is formed. After forming the InP window layer 5, the p-type impurity Zn is selectively diffused from the InP window layer 5 to the MQW light receiving layer 3 by a selective diffusion method. The InGaAs diffusion concentration distribution adjustment layer 4 may be arranged as described above, but may not be provided.

  Even when the InGaAs diffusion concentration distribution adjusting layer 4 is inserted, since the InGaAs has a small band gap, the electric resistance of the light receiving element can be lowered even if it is non-doped. By reducing the electrical resistance, it is possible to improve the responsiveness and obtain a moving image with good image quality. An undoped InP window layer 5 is continuously formed on the InGaAs diffusion concentration distribution adjusting layer 4 while the epitaxial wafer 1a is disposed in the same quartz tube 65 by a metal organic chemical vapor deposition method, for example, with a film thickness of 0.8 μm. It is better to grow epitaxially to the extent. As described above, trimethylindium (TMIn) and tertiary butylphosphine (TBP) are used for the source gas. By using this source gas, the growth temperature of the InP window layer 5 can be set to 400 ° C. or more and 525 ° C. or less. As a result, the GaAsSb of MQW located under the InP window layer 5 is not damaged by heat or receives only relatively small heat damage. For this reason, the density of the convex part with a diameter of 30 μm or more that may occur can be lowered to a practically acceptable level, and the carbon concentration can be lowered.

For example, in order to grow the InP window layer 5 by the MBE (molecular beam epitaxy) method, it is necessary to use a solid raw material as a phosphorus raw material, which has a problem in terms of safety. There was also room for improvement in terms of manufacturing efficiency. After the MQW light-receiving layer 3 and the InGaAs diffusion concentration distribution adjusting layer 4 are grown by the MBE method suitable for the growth of the MQW light-receiving layer 3 whose composition changes in small increments, the InP window layer 5 is formed by the MBE method for safety reasons. It is often grown by other methods. In this case, the interface between the InGaAs diffusion concentration distribution adjusting layer 4 and the InP window layer 5 becomes a regrowth interface once exposed to the atmosphere. The regrowth interface can be specified by satisfying at least one of the oxygen concentration of 1e17 cm ⁻³ or more and the carbon concentration of 1e17 cm ⁻³ or more by secondary ion mass spectrometry. The regrowth interface forms a crossing line with the p-type region, and a charge leak occurs at the crossing line, thereby significantly degrading the image quality. Further, for example, when the InP window layer 5 is grown by the MOVPE method instead of the all-organic metal vapor phase epitaxy method, phosphine (PH ₃ ) is used as the raw material of phosphorus, so that the decomposition temperature is high and the heat of GaAsSb located in the lower layer There is a high risk of inducing damage.

  According to the epitaxial wafer, the light receiving element, and the like of the present invention, it is possible to efficiently manufacture a product with good crystallinity. In addition, when a foreign substance whose cause cannot be specified is located on the substrate surface, the crystal defect is not enlarged and grown from the foreign substance, and crystallinity is maintained and the size of the defect cannot be practically reduced in yield. You can As a result, a light receiving element having a sensitivity in the near infrared to infrared region and having a low dark current can be manufactured at a low manufacturing cost.

1 InP substrate, 1a wafer, 2 buffer layer (InP and / or InGaAs), 3 type 2 MQW light receiving layer, 4 InGaAs layer (diffusion concentration distribution adjusting layer), 5 InP window layer, 6 p-type region, 11 p side Electrode (pixel electrode), 12 n-side electrode, 15 pn junction, 35 AR (antireflection) film, 36 selective diffusion mask pattern, 50 light receiving element (light receiving element array), 60 all organic MOVPE film forming apparatus, 61 infrared Temperature monitor device, 63 growth chamber, 65 quartz tube, 69 growth chamber window, 66 substrate table, 66h heater, d buffer layer thickness, D convex portion average diameter, G foreign matter, K convex portion, P pixel, t The thickness of the laminate of the light receiving layer to the window layer.

Claims (10)

An epitaxial wafer formed on a group III-V semiconductor substrate,
A buffer layer containing phosphorus (P), located in contact with the substrate;
A light receiving layer located on the buffer layer,
An epitaxial wafer in which the thickness d of the buffer layer is 0.002 times (0.002 t) or more of the thickness t of the stacked body from the upper surface of the buffer layer to the upper surface of the epitaxial layer.   The epitaxial wafer according to claim 1, wherein the substrate is an InP substrate, and the buffer layer is an InP layer or an (InP / InGaAs) composite layer. An epitaxial wafer formed on a group III-V semiconductor substrate,
A buffer layer not in contact with the substrate and containing no phosphorus (P);
A light receiving layer located on the buffer layer,
An epitaxial wafer in which the thickness d of the buffer layer is 0.25 times (0.25 t) or more of the thickness t of the stacked body from the upper surface of the buffer layer to the upper surface of the epitaxial layer.   The epitaxial wafer according to claim 3, wherein the substrate is an InP substrate, and the buffer layer is an InGaAs layer. The light receiving layer type _{2 (GaAs 1-x Sb x} (0 <x ≦ 1) / In y Ga 1-y As (0 <y ≦ 1)) is a multiple quantum well structure, of claim 1 The epitaxial wafer according to any one of claims. The foreign matter is dispersed in an average density of 0.5 cm ⁻² or less when the epitaxial layer is viewed in plan, and the foreign matter is partially or completely embedded in the buffer layer when viewed in cross section. Item 6. The epitaxial wafer according to any one of Items 1 to 5.   A light receiving element comprising a laminated structure of a group III-V semiconductor in the epitaxial wafer according to claim 1.   An optical sensor device comprising the light receiving element according to claim 7. A method of manufacturing an epitaxial wafer comprising a substrate of a III-V semiconductor, a buffer layer, and a light receiving layer,
Growing a buffer layer containing phosphorus (P) in contact with the substrate;
Growing the light receiving layer on the buffer layer;
An epitaxial wafer manufacturing method, wherein t is a thickness of a stacked body from the upper surface of the buffer layer to an upper surface of the epitaxial layer, and a thickness d of the buffer layer is 0.002 t or more. A method of manufacturing an epitaxial wafer comprising a substrate of a III-V semiconductor, a buffer layer, and a light receiving layer,
Growing a buffer layer not containing phosphorus (P) in contact with the substrate;
Growing the light receiving layer on the buffer layer;
An epitaxial wafer manufacturing method, wherein t is a thickness of a stacked body from the upper surface of the buffer layer to an upper surface of the epitaxial layer, and a thickness d of the buffer layer is 0.25 t or more.

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