JP2014212451A - Method and apparatus for error rate estimation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To estimate an error rate of parallel signals obtained by dividing a bulk signal into a plurality of parallel lanes.SOLUTION: An error rate estimation apparatus for use in parallel transmission in which a bulk signal is divided into parallel lane signals and transmitted includes: a signal detector unit for detecting a predetermined fixed pattern included in the parallel lane signal for each parallel lane; and an error rate calculation unit for calculating a signal error rate in the parallel lane in which the fixed pattern is detected, on the basis of the number of errors in the fixed pattern detected by the signal detector unit and the length of the fixed pattern.

Description

  The present invention relates to an error rate estimation method and an error rate estimation device in an optical communication system.

  Currently, an OTN (Optical Transport Network) described in Non-Patent Document 1 is widely used as a wide-area optical transport network. FIG. 4 is a diagram showing a frame structure used in OTN. As shown in the figure, the frame can be represented by 4 rows × 4080 columns, and the data of the first column from the first column to the 4080 column, the data of the second row from the first column to the 4080 column (4081). 8160th data), 3rd row, 1st to 4080th column data (8161th to 12240th data), 4th row, 1st column to 4080th column data (12241th data) 16320th data).

  Client data transmitted in the optical communication system is mapped to OPU (Optical channel Payload Unit) from the 17th column to the 3824th column. OPU-OH (Optical channel Payload Unit Overhead) is inserted in the 15th to 16th columns of the frame. The OPU-OH stores information necessary for client signal mapping and demapping. ODU-OH (Optical channel Data Unit Overhead) is inserted in the 1st to 14th columns from the 2nd row to the 4th row. The ODU-OH stores optical transmission path management operation information.

  In the first to seventh columns of the first row, FAS (Frame Alignment Signal) information necessary for frame synchronization and MFAS (Multi-Frame Alignment Signal) information necessary for multiframe synchronization are stored. The MFAS is used when exchanging information with 256 multiframes. An OTU-OH (Optical channel Transport Unit Overhead) that stores optical section monitoring operation information is inserted in the 8th to 14th columns of the first row. Error correction FEC (Forward Error Correction) check bytes are inserted from the 3825th column to the 4080th column of each row.

  5 and 6 are diagrams showing the structures of OTU-OH and ODU-OH. As shown in FIG. 5, SM (Section Monitoring) bytes are arranged in the 8th to 10th columns in the OTU-OH in the 8th to 14th columns of the first row. A TTI (Trail Trace Identifier) is set in the first byte of the SM-OH. TTI is for monitoring section trace. The TTI is information including a SAPI (Source Access Point Identifier) indicating the start point of a section and a DAPI (Destination Access Point Identifier) indicating the end point of the section.

  BIP-8 (Bit Interleaved Parity-level 8) is arranged in the second byte of SM-OH. FIG. 7 is a diagram illustrating a position where BIP-8 is arranged and OPU data corresponding to BIP-8. As shown in the figure, 8-bit parity (BIP-8) for the OPU data two frames before is calculated on the transmission side, and the calculated parity is inserted into BIP-8. On the receiving side, the BIP-8 calculated from the OPU data is compared with the BIP-8 inserted in the SM-OH, and an error occurring in the section monitoring section is detected. The TCM (Tandem Connection Monitoring) byte and PM (Path Monitoring) byte in the ODU-OH are defined as the trace monitoring byte, the BIP-8 byte, and the byte for displaying and transferring the path status in the same manner as the SM-OH. Has been. Management and operation of the optical communication network are performed using each OH (Overhead) information in the OTN frame.

  Along with the increase in transmission speed, for 40 Gbps and 100 Gbps class optical transmission, a method of dividing a serial frame into parallel lanes for transmission is standardized. This is called multilane division. In the case of OTN, it is called OTN-MLD (Multi-Lane Distribution). A 100 Gbps OTU4 frame is divided into 20 logical lanes, and a frame system based on the 20 logical lanes is standardized. This method will be described with reference to FIGS. FIG. 8 is a diagram illustrating an OTU4 frame divided every 16 bytes. FIG. 9 is a diagram illustrating the structure of the OTL 4.20 frame.

  In this method, each data of the OTU4 frame is divided into 16 bytes, and 16 bytes are handled as one unit. Each 16-byte block constituting the OTU4 frame is sequentially mapped to 20 logical lanes as shown in FIG. At this time, after mapping for one frame is completed, the start lane for starting mapping is shifted by one lane, and each 16-byte block is mapped in order.

  In general, an interface obtained by parallelizing an electrical signal of 10 Gbps or 25 Gbps is used for an interface with an optical module that handles a signal of 100 Gbps. In this case, the signal of 20 logical lanes is bit-multiplexed for each bit, and in the case of a 10 Gbps electrical signal, the conversion is realized by converting 5 Gbps × 20 lanes into 10 Gbps × 10 lanes by bit multiplexing. In the case of a 25 Gbps electrical signal, the interface is realized by 20: 4 bit multiplexing in the same manner. In this case, the receiving side performs 10:20 bit separation for 10 Gbps and 4:20 bit separation for 25 Gbps, restores the original 20 logical lanes, establishes synchronization in each logical lane, and identifies the lanes. After that, the serial OTU4 frame is restored. In this case, all multi-lane signals are connected at 1: 1, and after parallel transmission, the original serial OTU4 frame is restored, and BIP-8 bytes are used to monitor signal quality degradation associated with parallel transmission. Can do.

ITU-T G.709 / Y.1331, "Interfaces for the Optical Transport Network (OTN)", December 2009.

  In the future, in order to perform ultra-long distance transmission stably, it can be considered that transmission is performed at a reduced transmission rate for each wavelength. In this case, after the bulk signal to be transmitted is expanded into parallel signals corresponding to each parallel lane, the expanded parallel signals can be divided into a plurality of groups and transmitted using optical signals of a plurality of wavelengths for each group. There is sex. In this case, the transmitter or the transmission unit that transmits the parallel signal of each group does not process all the parallel signals to be transmitted. Although it is conceivable that quality monitoring of the parallel signal to be transmitted is required to isolate various faults, the above transmitter or transmitter does not process all the parallel signals to be transmitted. There is a problem that the used signal quality cannot be monitored.

  In view of the above circumstances, the present invention provides an error rate estimation method and an error rate estimation apparatus for estimating an error rate from a parallel signal obtained by dividing a bulk signal into a plurality of parallel lanes and monitoring signal quality. It is aimed.

  One aspect of the present invention is an error rate estimation method in parallel transmission in which a bulk signal is divided into a plurality of parallel lane signals for transmission, and is determined in advance for each parallel lane included in the parallel lane signal. Based on a detection step for detecting a fixed pattern, and the number of errors in the fixed pattern detected in the detection step and the length of the fixed pattern, an error rate of a signal in the parallel lane in which the fixed pattern is detected is estimated. An error rate estimation method characterized by comprising an estimation step.

One embodiment of the present invention is the above-described invention, wherein the bulk signal is a G.D. 709 is a 100G OTU4 frame signal. The parallel lane signal is a signal divided into four physical lanes of OTL4.4 or a signal divided into ten physical lanes of OTL4.10. In the detection step, an FAS pattern is detected as the fixed pattern for each logical lane signal included in the physical lane signal.
One embodiment of the present invention is the above-described invention, wherein the bulk signal is a G.D. The 40G OTU3 frame signal specified in 709, and the signal of the parallel lane is a signal divided into four physical lanes of OTL3.4 corresponding to the logical lane, and the detection In the step, an FAS pattern is detected as the fixed pattern for each logical lane.

  Another aspect of the present invention is an error rate estimation apparatus used in parallel transmission in which a bulk signal is divided into a plurality of parallel lane signals and transmitted, and is included in the parallel lane signal for each parallel lane. A signal in the parallel lane in which the fixed pattern is detected based on a signal detection unit that detects a predetermined fixed pattern, and the number of errors in the fixed pattern detected by the signal detection unit and the length of the fixed pattern And an error rate calculation unit that calculates an error rate of the error rate.

One embodiment of the present invention is the above-described invention, wherein the bulk signal is a G.D. 709 is a 100G OTU4 frame signal. The parallel lane signal is a signal divided into four physical lanes of OTL4.4 or a signal divided into ten physical lanes of OTL4.10. And the signal detection unit detects an FAS pattern as the fixed pattern for each logical lane signal included in the physical lane signal.
One embodiment of the present invention is the above-described invention, wherein the bulk signal is a G.D. 709, a 40G OTU3 frame signal, and the parallel lane signal is a signal divided into four physical lanes corresponding to logical lanes in the four physical lanes of OTL3.4. The detecting unit detects an FAS pattern as the fixed pattern for each logical lane.

  According to the present invention, the error rate in each parallel lane can be calculated based on the fixed pattern included in the parallel lane signal without referring to all the bulk signals, and the signal quality is monitored by the error rate. Can do.

It is a block diagram which shows the structure of the transmitter 100 to which the error rate estimation method in this embodiment is applied. It is a figure which shows the relationship between an OTL 4.10 signal and an OTL 4.20 signal. It is a block diagram which shows the structure of 50G signal processing circuit 120-1 in this embodiment. It is a figure which shows the frame structure used in OTN. It is a 1st figure which shows the structure of OTU-OH and ODU-OH. It is a 2nd figure which shows the structure of OTU-OH and ODU-OH. It is a figure which shows the position where BIP-8 is arrange | positioned, and OPU data corresponding to BIP-8. It is a figure which shows the OTU4 frame divided | segmented every 16 bytes. It is a figure which shows the structure of OTL4.20 frame.

  Hereinafter, an error rate estimation method and an error rate estimation apparatus according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of a transmission apparatus 100 to which the error rate estimation method according to the present embodiment is applied. The transmission apparatus 100 is an apparatus that converts a client signal, which is an electrical signal, into an optical signal of two systems and transmits the optical signal in an optical communication system. In the present embodiment, a case where the client signal (bulk signal) is 100 G Ethernet (registered trademark) (100 GbE) and the 100 GbE signal is divided into two 50 G signals and transmitted will be described. The client signal (bulk signal) is a signal before being divided into parallel signals in the processing in the transmission apparatus 100.

  The transmission apparatus 100 includes a 100G framer circuit 110, two 50G signal processing circuits 120-1 and 102-2, and two 50GDP-BPSK (Dual Polarization-Binary Phase Shift Keying) transmission circuits 130-1 and 130-2. I have. The 100G framer circuit 110 accommodates a 100 GbE signal as a client signal input to the transmission apparatus 100 in an OPU4 (Optical channel Payload Unit-4) payload. Here, G. of ITU-T (International Telecommunication Union Telecommunication standardization sector). The stuff bytes are inserted according to the speed difference (transmission capacity difference) between the OPU4 payload and the 100 GbE signal by a method called GMP (Generic Mapping Procedure) defined in 709. The 100G framer circuit 110 adds an ODU-OH, an OTU-OH, and an error correction code (FEC) to the 100 GbE signal accommodated in the OPU4 payload, converts the signal to an OTL4.10 signal, and converts the signal into a 50G signal processing circuit 120- 1 and 102-2. That is, the 100G framer circuit 110 divides the bulk signal into a plurality of parallel lane signals (OTL 4.10 signals) and inputs the signals to the 50G signal processing circuits 120-1 and 102-2.

  The OTL 4.10 signal output from the 100 G framer circuit 110 is a 10 lane class 10 lane signal. In this embodiment, the 10-lane signal is divided into 5-lane signals and input to the two 50G signal processing circuits 120-1 and 102-2. The 50G signal processing circuit 120-1 and the 50G signal processing circuit 120-2 have the same configuration. Here, the 50G signal processing circuit 120-1 will be described, and the description of the 50G signal processing circuit 120-2 will be omitted.

  The 50G signal processing circuit 120-1 performs clock data recovery for each input 5-lane signal, and reproduces the clock and data. The 50G signal processing circuit 120-1 performs a 1: 2 separation process for each lane on a data signal reproduced by clock data recovery. A signal obtained by the 1: 2 separation processing is a signal having an OTL 4.20 frame structure composed of the original 20 logical lanes. As shown in FIG. 9, a signal for frame synchronization (FAS) always appears at regular intervals in the signal of each logical lane of the OTL 4.20 signal. A marker signal indicating the lane number of the logical lane is inserted in the sixth byte of the FAS which is a signal for frame synchronization.

  This marker signal is called an LLM (Logical Lane Marker) and is used to identify the lane number of the logical lane. The FAS is a signal indicating a frame boundary. By using the FAS of each logical lane, a delay time difference between lanes transmitted in parallel can be detected. The 50G signal processing circuit 120-1 uses the lane number and delay time difference obtained by FAS and LLM to temporarily convert the input 5-lane signal into a 50G bulk signal, and then, if necessary, an error correction code Insertion, training signal insertion for transmission path condition estimation, differential encoding, and the like are performed, and the signal is converted into a 2-lane OTN-MLD (Optical Transport Unit-Multi Lane Distribution) format signal. The 50G signal processing circuit 120-1 inputs a 2-lane OTN-MLD format signal to the 50GDP-BPSK transmission circuit 130-1.

  Here, the relationship between the OTL 4.10 signal and the OTL 4.20 signal is shown in FIG. FIG. 2 is a diagram illustrating the relationship between the OTL 4.10 signal and the OTL 4.20 signal. In the 100G framer circuit 110, the OTL 4.20 signal of 20 logic lanes is divided into two signal groups, and data is alternately selected from the two signals and output one bit at a time, thereby outputting an OTL 4.10 signal of 10 lanes. Has been converted.

Returning to FIG. 1, the description of the configuration of the transmission apparatus 100 will be continued.
The 50 GDP-BPSK transmission circuit 130-1 assigns the two-lane OTN-MLD format signal input from the 50G signal processing circuit 120-1 to orthogonal X polarization and Y polarization, and for each signal. BPSK modulation is performed and converted into an optical signal and output. Similarly to the 50 GDP-BPSK transmission circuit 130-1, the 50 GDP-BPSK transmission circuit 130-2 converts the 2-lane OTN-MLD format signal input from the 50G signal processing circuit 120-2 into an orthogonal X-polarization signal. Assigned to the wave and Y polarization, BPSK modulation is performed on each signal, converted into an optical signal, and output.

  As described above, the transmission apparatus 100 can transmit a 100 GbE bulk signal as two 50 Gb optical signals modulated by the BPSK modulation method. This makes it possible to perform transmission over a longer distance. In the present embodiment, a configuration is shown in which two BPSK modulation schemes corresponding to two orthogonal XY polarizations are converted into signals in two lanes OTN-MLD format, but four lanes OTN-MLD are used. The format signal may be configured to use an IQ modulator corresponding to two polarizations.

  FIG. 3 is a block diagram showing a configuration of the 50G signal processing circuit 120-1 in the present embodiment. The 50G signal processing circuit 120-1 includes clock data recovery units 121-1 to 121-5 and demultiplexers (DEMUX) 122-1 to 122-5 corresponding to the signals of the five logical lanes that are input, and a frame synchronization unit 123. -1 to 123-10, a frame conversion / transmission digital processing unit 124, a frame synchronization signal detection unit 125, an error determination unit 126, a frame counting unit 127, and an error rate calculation unit 128.

  Each of the clock data recovery units 121-1 to 121-5 receives any one of the five logical lane signals. The clock data recovery units 121-1 to 121-5 perform clock data recovery on the input signal and separate the clock and data. The clock data recovery units 121-1 to 121-5 output data to the corresponding demultiplexers 122-1 to 122-5, respectively.

  The demultiplexers 122-1 to 122-5 alternately distribute the data output from the clock data recovery units 121-1 to 121-5 to the two lanes, thereby converting the data of one lane into the data of two lanes. To do. Specifically, the reverse process of the process shown in FIG. 2 is performed. The demultiplexer 122-1 outputs one of the data in the two lanes to the frame synchronization unit 123-1, and outputs the other data to the frame synchronization unit 123-2. Similarly to the demultiplexer 122-1, the demultiplexers 122-2 to 122-5 transfer one of the data in the two lanes to the frame synchronization units 123-3, 123-5, 123-7, and 123-9. The other data is output to the frame synchronization units 123-4, 123-6, 123-8, 123-10. The demultiplexers 122-1 to 122-5 convert the 10 G data restored by the clock data recovery units 121-1 to 121-5 into a signal of 20 logical lanes by performing a 1: 2 separation process. To do.

  Each of the frame synchronization units 123-1 to 123-10 detects FAS from the data, establishes synchronization with the other frame synchronization units 123-1 to 123-10, and outputs the data. The synchronized data output from each of the frame synchronization units 123-1 to 123-10 is input to the frame conversion / transmission digital processing unit 124, the frame synchronization signal detection unit 125, and the frame counting unit 127.

  The frame conversion / transmission digital processing unit 124 converts the input 10-lane data into a 50G bulk signal, and then inserts an error correction code and a training signal for estimating the transmission path status as necessary. Then, differential encoding or the like is performed to convert the signal into a 2-lane OTN-MLD format signal. The frame conversion / transmission digital processing unit 124 outputs a 2-lane OTN-MLD format signal obtained by the conversion to the 50 GDP-BPSK transmission circuit 130-1. The frame conversion / transmission digital processing unit 124 included in the 50G signal processing circuit 120-2 outputs a 2-lane OTN-MLD format signal to the 50GDP-BPSK transmission circuit 130-2.

  The frame synchronization signal detection unit 125 detects the FAS in each of the input 10 logical lane data, and outputs the detected FAS to the error determination unit 126. The FAS (6 bytes) for frame synchronization in each logical lane is provided at the head of the frame. A marker signal of a logical lane is assigned to the last 6 bytes of the FAS. A predetermined fixed value is assigned to the other 5 bytes. By detecting this fixed value, the frame synchronization units 123-1 to 123-10 can detect the head of the frame.

  Note that the frame synchronization signal detection unit 125 may detect, as FAS, 6-byte data in which the matching rate with the fixed value is equal to or higher than a predetermined ratio in the data of each logical lane. As a result, even if an error is included in the FAS pattern, the FAS can be detected. In this case, there is a possibility that a plurality of patterns regarded as FAS may be detected. However, erroneously detected patterns can be excluded based on the data length between the detected patterns.

  The error determination unit 126 determines whether or not the 5-byte value (pattern) other than the last 6-byte including the marker signal among the 6 bytes constituting the FAS matches a predetermined value (pattern). To do. Further, the error determination unit 126 detects the number of different bits when the values do not match. That is, the error determination unit 126 detects the number of error bits in 5 bytes (40 bits). The error determination unit 126 outputs the detected number of error bits for each logical lane to the error rate calculation unit 128. If the values match, 0 is output to the error rate calculation unit 128 as the number of error bits.

  The frame counting unit 127 detects the number of frames in the input 10 logical lane data, and outputs the detected number of frames to the error rate calculation unit 128. The error rate calculation unit 128 calculates an estimated error rate per frame based on the number of error bits in each logical lane input from the error determination unit 126 and the number of frames input from the frame counting unit 127. To do.

  In the present embodiment, the fact that the frame synchronization pattern defined by OTN is a fixed value is used, and the deviation from the fixed value is used as an error. The error rate of the byte for frame synchronization is obtained, and the error rate is estimated to be the error rate of each logical lane. In the method described in this embodiment, it is possible to estimate the signal error rate without receiving all the parallel signals and returning them to the serial signal, and to grasp the deterioration of the signal quality.

  Specifically, in the transmission device 100, the 50G signal processing circuits 120-1 and 102-2 are assigned a fixed value among FAS (6 bytes) arranged at the head of each frame of 20 logical lanes. Detect the number of erroneous bits in a byte (40 bits). The 50G signal processing circuits 120-1 and 102-2 obtain the error rate in the FAS for each frame from the number of erroneous bits in the FAS, and estimate the error rate in the logical lane by averaging a plurality of frames. Is possible. Further, based on the estimated error rate, signal quality monitoring, device failure detection, and the like can be performed. In addition, since the error rate can be estimated for each of the parallel signals, it is possible to detect a failure in which the functional unit in the transmission apparatus 100 is specified.

  Here, it is assumed that the error rate in FAS and the error rate of the entire frame are comparable, that is, there is no burst error and a random error. However, even if a burst-like error occurs, the error rate estimation accuracy drops, but the error rate for parallel signals divided into multiple parallel lanes can be estimated without changing the frame structure. it can.

  In this embodiment, the configuration in which the OTL4.10 of the parallel transmission frame is input to the 50G signal processing circuits 120-1 and 102-2 using the 100G OTU4 frame has been described. The same applies to the case of OTL4.4 specified in 709. Each signal transmitted in four physical lanes of 25G is fixed by converting it into a signal of 20 logical lanes by 1: 5 separation processing. A pattern FAS appears in each logical lane. Even in this case, not only frame synchronization is established using the FAS pattern, but also the number of bit errors in the FAS pattern can be detected, and the overall error rate can be estimated.

  In addition, G. of ITU-T. In the case of OTL3.4, which is a parallel transmission frame for the 40G OTU3 frame defined in 709, the same processing is possible. In this case, the 40G signal is divided into four 10G physical lane signals. Since each 10G physical lane always includes a FAS for establishing synchronization, synchronization is established using the FAS pattern. In addition, the number of bit errors in the FAS pattern can be detected, and the error rate in each physical lane can be estimated.

  Further, in the present embodiment, the configuration using the OTU frame that is a standardized optical transmission frame has been described. However, in the non-standard frame pattern, if position information and fixed pattern information from the top of the frame are determined in advance, Similarly, the error rate can be estimated. In the present embodiment, the configuration in which the error rate is estimated using the signals of a part of the parallel lanes of the parallel signal has been described. However, the error rate may be estimated based on the signals of all the logical lanes.

Regarding the error rate, when BIP-8 is used, errors in the OPU part of the OTU frame can be monitored, and a maximum of 8 errors are detected per frame. When this is converted into a bit error rate, 8 / (3810 × 4 × 8) ≈6.6 × 10 −5 is obtained. That is, it cannot be detected when the bit error rate is worse than 1 × 10 −5.
On the other hand, in the estimation of the error rate in this embodiment, the error rate is obtained from the number of bit errors using 5 bytes (40 bits) in the FAS pattern of the OTU frame. For example, even when there are 10 errors, an error rate up to 10/40 = 0.25 can be handled by providing a sufficient protection time so that frame synchronization can be established. That is, it is possible to estimate the error rate even in a situation where the error rate is quite bad.

  You may make it implement | achieve the process which estimates the error rate which 50G signal processing circuit 120-1 and 102-2 in embodiment mentioned above performs with a computer. In that case, a program for realizing this function may be recorded on a computer-readable recording medium, and the program recorded on this recording medium may be read into a computer system and executed. Here, the “computer system” includes an OS and hardware such as peripheral devices. The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. Furthermore, the “computer-readable recording medium” dynamically holds a program for a short time like a communication line when transmitting a program via a network such as the Internet or a communication line such as a telephone line. In this case, a volatile memory inside a computer system serving as a server or a client in that case may be included and a program held for a certain period of time. Further, the program may be a program for realizing a part of the above-described functions, and may be a program capable of realizing the functions described above in combination with a program already recorded in a computer system. It may be realized using hardware such as PLD (Programmable Logic Device), FPGA (Field Programmable Gate Array), DSP (Digital Signal Processor).

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention. For example, the configuration using the FAS as the fixed pattern used for estimating the error rate has been described, but any fixed pattern may be used as long as it is a fixed pattern included in the target lane whose error rate is to be estimated. In the embodiment, the configuration for estimating the error rate with respect to an error occurring in the transmission apparatus 100 has been described. However, the error rate may be used in a reception apparatus that receives an optical signal, and an OTU frame may be used from the received optical signal. You may make it estimate an error rate based on the number of error bits of a fixed pattern in the stage before decompression | restoration.

  Further, the error rate may be estimated based on the number of error bits of the fixed pattern at a stage before the OTU frame is restored from the optical signal in the transmission device, the reception device, or the relay device used in the optical communication system. In this case, the frame synchronization signal detection unit 125, the error determination unit 126, the frame counting unit 127, and the error rate calculation unit 128 may be configured as one device, for example, an error estimation device.

  The present invention can also be applied to applications that require detection of error rates in parallel signals divided into a plurality of parallel lanes in an optical communication system.

DESCRIPTION OF SYMBOLS 100 ... Transmitter 110 ... 100G framer circuit 120-1, 120-2 ... 50G signal processing circuit 130-1, 130-2 ... 50 GDP-BPSK transmission circuit 121-1, 121-2, 121-3, 121-4, 121-5: Clock data recovery unit 122-1, 122-2, 122-3, 122-4, 122-5 ... Demultiplexer 123-1, 123-2, 123-3, 123-4, 123-5, 123-6, 123-7, 123-8, 123-9, 123-10... Frame synchronization unit 124... Frame conversion / transmission digital processing unit 125... Frame synchronization signal detection unit 126 .. error determination unit 127. ... Error rate calculator

Claims (6)

An error rate estimation method in parallel transmission in which a bulk signal is divided into a plurality of parallel lane signals and transmitted.
For each of the parallel lanes, a detection step of detecting a predetermined fixed pattern included in the parallel lane signal;
An estimation step of estimating an error rate of a signal in a parallel lane in which the fixed pattern is detected based on the number of errors in the fixed pattern detected in the detection step and the length of the fixed pattern. Error rate estimation method. The error rate estimation method according to claim 1,
The bulk signal is the G.D. 709 is a 100G OTU4 frame signal,
The signal of the parallel lane is a signal divided into four physical lanes of OTL4.4 or a signal divided into ten physical lanes of OTL4.10.
In the detection step,
An error rate estimation method, wherein an FAS pattern is detected as the fixed pattern for each logical lane signal included in the physical lane signal. The error rate estimation method according to claim 1,
The bulk signal is the G.D. 709, a 40G OTU3 frame signal,
The parallel lane signals are four physical lanes of OTL3.4 and are divided into physical lanes corresponding to logical lanes,
In the detection step,
An error rate estimation method, wherein an FAS pattern is detected as the fixed pattern for each logical lane. An error rate estimation device used in parallel transmission for dividing a bulk signal into signals of a plurality of parallel lanes and transmitting the signals,
For each parallel lane, a signal detection unit that detects a predetermined fixed pattern included in the parallel lane signal;
An error rate calculation unit that calculates an error rate of a signal in a parallel lane in which the fixed pattern is detected based on the number of errors in the fixed pattern detected by the signal detection unit and the length of the fixed pattern. An error rate estimation device characterized by the above. The error rate estimation apparatus according to claim 4,
The bulk signal is the G.D. 709 is a 100G OTU4 frame signal,
The signal of the parallel lane is a signal divided into four physical lanes of OTL4.4 or a signal divided into ten physical lanes of OTL4.10.
The signal detector is
An error rate estimation apparatus, wherein an FAS pattern is detected as the fixed pattern for each logical lane signal included in the physical lane signal. The error rate estimation apparatus according to claim 4,
The bulk signal is the G.D. 709, a 40G OTU3 frame signal,
The parallel lane signals are four physical lanes of OTL3.4 and are divided into physical lanes corresponding to logical lanes,
The signal detector is
An error rate estimation apparatus, wherein an FAS pattern is detected as the fixed pattern for each logical lane.

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