JP2014209661A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing moire caused by a dummy pattern even when detection sensitivity for optical defect detection is increased, and to provide a method of manufacturing the semiconductor device.SOLUTION: The semiconductor device comprises: a first layer which is provided on a semiconductor substrate and includes a first wiring pattern 101w flattened by CMP and a plurality of first dummy patterns 101d made of a same material as that of the first wiring pattern 101w; and a second layer which is provided on a semiconductor substrate and includes a second wiring pattern 102w flattened by CMP and a plurality of second dummy patterns 102d made of a same material as that of the second wiring pattern 102w. The center axis of each of the second dummy pattern 102d is aligned with the center axis of each of the corresponding first dummy patterns 101d in a direction perpendicular to the semiconductor substrate.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device using a planarization process by CMP (Chemical Mechanical Polishing) and a manufacturing method thereof.

  In manufacturing a semiconductor device, CMP is often used as a method for planarizing each layer. In the planarization process by CMP, a method of arranging a dummy pattern for CMP is used in order to suppress the occurrence of dishing and erosion (see Patent Document 1). In general, the size, number, and arrangement of dummy patterns for CMP are determined so as to be optimal in each layer where CMP is performed.

JP 2006-39587 A

  However, in recent years, it has been found that the following problems occur when optical defect inspection is performed to detect defects such as particles and pattern shorts in semiconductor devices that have been further miniaturized. .

  That is, with the miniaturization, smaller defects and particles must be detected, and thus it is necessary to increase the detection sensitivity. However, when the detection sensitivity is increased, the dummy pattern is optimized and arranged in each layer as described above, so that the deviation generated between the upper layer dummy pattern and the lower layer dummy pattern becomes moire (interference fringes). In the defect inspection, moire is also detected as a defect, and the defect due to moire is also detected as a defect by mixing particles and defects that should be detected together, increasing the number of defects. turn into. On the other hand, if the detection sensitivity is lowered in order to prevent the occurrence of moire, fine particles and defects cannot be detected, resulting in a decrease in yield.

  A semiconductor device according to the present invention includes a first layer including a first wiring pattern provided on a semiconductor substrate and planarized by CMP, and a plurality of first dummy patterns made of the same material as the first wiring pattern. And a second layer including a plurality of second dummy patterns made of the same material as the second wiring pattern and planarized by CMP, and corresponding to each of the plurality of first dummy patterns Each of the plurality of second dummy patterns has a central axis that coincides with a direction perpendicular to the semiconductor substrate.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming first and second layers that are planarized by CMP on a semiconductor substrate, and the first layer is formed before forming the first and second layers. Determining the number and arrangement of the first CMP dummy patterns to be formed on the second layer, and the center of the first dummy pattern in the direction in which the central axis of the second CMP pattern formed on the second layer is perpendicular to the semiconductor substrate Determining the number and arrangement of the second dummy patterns so as to coincide with the axes.

  According to the present invention, since the central axes of the first dummy pattern provided in the first layer and the second dummy pattern provided in the second layer coincide with each other in the direction perpendicular to the semiconductor substrate, optical defect detection is performed. When performing the above, even if the detection sensitivity is increased, moire caused by the dummy pattern can be suppressed. Alternatively, even if moire due to the dummy pattern occurs, it becomes regular and can be determined to be due to the dummy pattern. Therefore, it becomes possible to detect fine particles and defects and improve the yield.

4 is a flowchart for explaining a method for manufacturing a semiconductor device according to the present invention; It is a figure for demonstrating the structure of the semiconductor device 100 by preferable 1st Embodiment of this invention. 3 is a flowchart for explaining a method of manufacturing the semiconductor device 100 according to the first embodiment. It is a figure for demonstrating the structure of the semiconductor device 100m by the modification of preferable 1st Embodiment of this invention. It is a figure for demonstrating the structure of the semiconductor device 200 by preferable 2nd Embodiment of this invention. 6 is a flowchart for explaining a method of manufacturing the semiconductor device 200 according to the second embodiment. It is a figure for demonstrating the structure of the semiconductor device 300 by preferable 3rd Embodiment of this invention. 12 is a flowchart for explaining a method for manufacturing the semiconductor device 300 according to the third embodiment. It is a figure for demonstrating the structure of the semiconductor device 400 by preferable 4th Embodiment of this invention. 10 is a flowchart for explaining a manufacturing method of the semiconductor device 400 according to the fourth embodiment. It is a figure for demonstrating the structure of the semiconductor device 500 by preferable 5th Embodiment of this invention.

  First, a dummy pattern generation process according to the semiconductor device manufacturing method of the present invention will be conceptually described with reference to the flowchart of FIG.

  As shown in FIG. 1, first, a dummy pattern generation possible area of each layer is extracted (step S1001). Next, it is determined whether or not there is a layer that should be closest packed with the dummy pattern (step S1002). If there is a target layer (X) that is to be closest packed with the dummy pattern (Yes), the target layer The number and arrangement of the dummy patterns are determined so that X is filled with the dummy patterns most closely (Step S1003). On the other hand, when there is no layer to be closely packed (No), a layer having a high priority determined in advance is set as the target layer X, and the number and arrangement of the dummy patterns are set so that the dummy patterns are closely packed. Determination is made (step S1004). Next, it is determined whether or not there is a layer Y that needs to match the central axis of the dummy pattern (step S1005). When there is a layer Y that needs to be matched (Yes), an area that overlaps with the dummy pattern generation area of the layer X is extracted from the dummy pattern generation area of the layer Y (step S1006). On the other hand, if there is no layer that needs to be matched (No), the number and arrangement of dummy patterns are independently determined for each layer without considering the vertical relationship (step S1007), and dummy pattern generation is performed. The process ends.

  Subsequent to step S1006, the number and arrangement of dummy patterns are determined so that the extracted dummy pattern of the layer Y can be similar to the dummy pattern of the layer X and the central axis coincides (step S1008). Next, in the dummy pattern generation possible area of each layer, it is determined whether or not an area where a dummy pattern can be placed remains (step S1009). If no area remains (No), the dummy pattern generation process is terminated. . If it remains (Yes), the number and arrangement of dummy patterns are independently determined for each layer without considering the vertical relationship (step S1010). Steps S1009 and S1010 are repeated until there is no area where dummy patterns can be placed, and the dummy pattern generation process ends when there are no more dummy patterns.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  2A and 2B are diagrams for explaining the structure of the semiconductor device 100 according to the first embodiment of the present invention. FIG. 2A is a schematic cross-sectional view, and FIG. A transparent plan view is shown. In FIG. 2A, for simplification, only a wiring pattern and a dummy pattern for CMP are shown, and a semiconductor substrate, an interlayer insulating film, and the like are omitted. In FIG. 2B, only the dummy pattern is shown.

  As shown in FIG. 2, the semiconductor device 100 according to the present embodiment is provided on a semiconductor substrate (not shown) and is made of the same material as the first wiring pattern 101w and the first wiring pattern 101w that are planarized by CMP. The first layer 101 including the plurality of first dummy patterns 101d and the second wiring pattern 102w and the second wiring pattern 102w provided on the first layer 101 on the semiconductor substrate and planarized by CMP are made of the same material. A second layer including a plurality of second dummy patterns 102d and a plurality of third wiring patterns 103w provided on the second layer 102 on the semiconductor substrate and made of the same material as the third wiring patterns 103w planarized by CMP. And the third layer 103 including the third dummy pattern 103d.

  In each of the layers 101 to 103, regions where the wiring patterns 101w to 103w are not formed become dummy pattern generation regions 10A and 10B, and the dummy patterns 101d to 103d are arranged, respectively. In the present embodiment, the plurality of first dummy patterns 101d are arranged so as to be packed in the dummy pattern generating area 10A in the first layer 101 in the closest packing manner. In the dummy pattern generation region 10A, as indicated by a broken line, each of the plurality of first dummy patterns 101d and each of the plurality of second dummy patterns 102d corresponding to each other coincide with the central axis in the direction perpendicular to the semiconductor substrate. As described above, the second dummy pattern 102d is arranged. Similarly, the central axes of the plurality of third dummy patterns 103d are aligned with each of the plurality of third dummy patterns 103d corresponding to each of the plurality of first dummy patterns 101d in the direction perpendicular to the semiconductor substrate. Is arranged.

  Since the first dummy pattern 101d is not formed in the dummy pattern generation possible region 10B, the second dummy pattern 102d is arranged so as to be closely packed in this region, and corresponds to each of the second dummy patterns 102d. The third dummy pattern 103d is arranged so that the center axes thereof coincide with each of the third dummy patterns 103d in the direction perpendicular to the semiconductor substrate.

  With such a configuration, as shown in FIG. 2B, the dummy patterns 101d to 103d always coincide with each other at the positions where the dummy patterns 101d to 103d are arranged (corresponding) to overlap each other. . Therefore, when optically detecting a defect, it is possible to prevent the occurrence of moiré due to a dummy pattern even if the detection sensitivity is increased. As a result, fine particles and defects can be detected, and the yield can be improved.

  Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described with reference to FIGS.

  FIG. 3 is a flowchart for explaining the manufacturing method of the semiconductor device 100 according to the first embodiment. Before forming the first to third layers 101 to 103 in the semiconductor device 100 shown in FIG. A process for determining the number and arrangement of dummy patterns 101d to 103d is shown.

  First, dummy pattern generation possible areas 10A and 10B are extracted (step S11). Next, in the dummy pattern generation possible region 10A including the first layer 101 to be closest packed, the number and arrangement thereof are determined so that the first dummy pattern 101d is closest packed (step S12). Subsequently, based on the arrangement of the first dummy pattern 101d, the central axis of the second dummy pattern 102d formed in the second layer 102 is aligned with the central axis of the first dummy pattern 101d in the direction perpendicular to the semiconductor substrate. The number and arrangement of the second dummy patterns 102d are determined (step S13). Further, based on the arrangement of the first dummy pattern 101d, the third dummy pattern 103d formed on the third layer 103 is arranged such that the central axis of the third dummy pattern 103d coincides with the central axis of the first dummy pattern 101d in the direction perpendicular to the semiconductor substrate. The number and arrangement of the three dummy patterns 103d are determined (step S14). That is, as indicated by an arrow in the area 10A of FIG. 2A, the position (center axis) of the first dummy pattern 101d is copied to the second layer 102, and the second dummy pattern 102d is placed at that position. If possible, arrange the position of the first dummy pattern 101d (center axis) to the third layer 103 and place the third dummy pattern 103d at that position. .

  Next, in the dummy pattern generation possible region 10B, here, the number and arrangement thereof are determined so that the second dummy pattern 102d is closest packed (step S15). Subsequently, based on the arrangement of the second dummy pattern 102d, the central axis of the third dummy pattern 103d formed in the third layer 103 is aligned with the central axis of the second dummy pattern 102d in a direction perpendicular to the semiconductor substrate. The number and arrangement of the third dummy patterns 103d are determined (step S16). Here, the second layer is close-packed, but when the flatness of the third layer is required to be higher than that of the second layer, the third layer is close-packed. The number and arrangement of the second dummy patterns 102d of the layer 102 may be determined.

  Finally, since the third dummy pattern 103d can be formed in the remaining dummy pattern generation possible area 10Br, it is additionally formed (step S17).

  As described above, the number and arrangement of dummy patterns formed in each layer are determined. In the present embodiment, the planar shapes of the dummy patterns formed in each layer are all the same size, but the size of the dummy pattern in each layer can be appropriately set for each layer according to the design criteria. FIG. 4 shows such an example.

  4A and 4B are diagrams for explaining the structure of a semiconductor device 100m according to a modification of the first embodiment. FIG. 4A is a schematic cross-sectional view, and FIG. FIG. In FIG. 4A, for the sake of simplicity, only the wiring pattern and the dummy pattern for CMP are shown, and the semiconductor substrate, the interlayer insulating film, and the like are omitted. FIG. 4B shows only the dummy pattern. 4 that are the same as in FIG. 2 are assigned the same reference numerals, and descriptions thereof are omitted.

  As shown in FIG. 4, in the semiconductor device 100m, the first dummy pattern 101md of the first layer 101m, the second dummy pattern 102md of the second layer 102m, and the third dummy pattern 103md of the third layer 103m are mutually planar size. Are squares of different sizes. Accordingly, the first to third dummy patterns 101 md to 103 md are centered in the dummy pattern generating area 10 A, and the second and third dummy patterns 102 md and 103 md are centered in the dummy pattern generating area 10 B, as in the semiconductor device 100. Although the axes are arranged so as to coincide with each other, in the plan view, unlike FIG. 2 (b), the patterns do not completely coincide with each other but overlap as shown in FIG. 4 (b). Patterns overlap with the central axis.

  Note that the planar shape of the dummy pattern is not limited to a square, but may be a rectangle or a polygon. However, the upper and lower dummy patterns are preferably similar. Then, when the central axes of the upper and lower dummy patterns are matched and the size of the dummy pattern is changed up and down, the difference between the figures when the upper and lower patterns are superimposed (for example, the difference between the upper, lower, left and right) is the same. It is preferable. However, by using a square pattern, it is possible to efficiently fill the dummy pattern, that is, close-packing is possible, so that it is possible to increase the accuracy of in-chip coarse / dense correction, and more dishing and erosion peculiar to CMP. It becomes possible to suppress efficiently.

  Even in such a configuration of the semiconductor device 100m, as in the semiconductor device 100, the dummy patterns 101md to 103md always have the same center axis at the positions where they are arranged one above the other. When performing the above, even if the detection sensitivity is increased, the generation of moire caused by the dummy pattern can be suppressed.

  Since the manufacturing method of the semiconductor device 100m shown in FIG. 4 is the same as that of the semiconductor device 100, the description thereof is omitted.

  In the first embodiment, the case where the first dummy pattern 101d (101md) formed in the first layer 101 (101m) is closest packed has been described as an example. It differs depending on the design standard, and it is not always necessary to close the dummy pattern of the lowermost layer, but it is determined to the layer where flatness is required most strictly in the design management of the device. Therefore, next, as a second embodiment, an example in which the second layer is closest packed will be described with reference to FIGS. 5 and 6.

  5A and 5B are views for explaining the structure of the semiconductor device 200 according to the second preferred embodiment of the present invention. FIG. 5A is a schematic cross-sectional view, and FIG. A transparent plan view is shown. In FIG. 5A, for the sake of simplicity, only the wiring pattern and the dummy pattern for CMP are shown, and the semiconductor substrate, the interlayer insulating film, and the like are omitted. FIG. 5B shows only the dummy pattern.

  As shown in FIG. 5, the semiconductor device 200 according to the present embodiment is made of the same material as the first wiring pattern 201w and the first wiring pattern 201w provided on the semiconductor substrate (not shown) and planarized by CMP. The first layer 201 including a plurality of first dummy patterns 201d and the second wiring pattern 202w and the second wiring pattern 202w provided on the first layer 201 on the semiconductor substrate and planarized by CMP are made of the same material. A second layer including a plurality of second dummy patterns 202d and a plurality of third wiring patterns 203w provided on the second layer 202 on the semiconductor substrate and made of the same material as the third wiring patterns 203w flattened by CMP. And the third layer 203 including the third dummy pattern 203d.

  In each of the layers 201 to 203, regions where the wiring patterns 201w to 203w are not formed become dummy pattern generation regions 20A and 20B, and the dummy patterns 201d to 203d are arranged, respectively. In the present embodiment, the plurality of second dummy patterns 202d are arranged so as to be closely packed in the dummy pattern generating areas 20A and 20B in the second layer 202. In the dummy pattern generation region 20A, as indicated by a broken line, each of the plurality of second dummy patterns 202d and each of the corresponding plurality of first dummy patterns 201d coincide with each other in the central axis in the direction perpendicular to the semiconductor substrate. Thus, the first dummy pattern 201d is arranged. Similarly, the central axes of the plurality of third dummy patterns 203d also coincide with the center axes of the plurality of second dummy patterns 202d and the corresponding plurality of third dummy patterns 103d in the direction perpendicular to the semiconductor substrate. Is arranged.

  By adopting such a configuration, as shown in FIG. 5B, the dummy putters 201d to 203d always have the same center axis at the place where they are arranged one above the other. Therefore, the same effect as that of the first embodiment can be obtained.

  Next, a manufacturing method of the semiconductor device 200 according to the second preferred embodiment of the present invention will be described with reference to FIGS.

  FIG. 6 is a flowchart for explaining a manufacturing method of the semiconductor device 200 according to the second embodiment. Before forming the first to third layers 201 to 203 in the semiconductor device 200 shown in FIG. A process for determining the number and arrangement of dummy patterns 201d to 203d is shown.

  First, dummy pattern generation possible areas 20A and 20B are extracted (step S21). Next, the number and arrangement are determined so that the second dummy pattern 202d is closest packed in the dummy pattern generation possible regions 20A and 20B including the second layer 202 to be closest packed (step S22). ). Subsequently, based on the arrangement of the second dummy pattern 202d, the central axis of the first dummy pattern 201d formed in the first layer 201 is aligned with the central axis of the second dummy pattern 202d in the direction perpendicular to the semiconductor substrate. The number and arrangement of the first dummy patterns 201d are determined (step S23). Further, based on the arrangement of the second dummy pattern 202d, the third dummy pattern 203d formed in the third layer 203 is arranged such that the central axis of the third dummy pattern 203d coincides with the central axis of the second dummy pattern 202d in the direction perpendicular to the semiconductor substrate. The number and arrangement of the three dummy patterns 203d are determined (step S24). That is, as indicated by an arrow in the area 20A of FIG. 5A, the position (center axis) of the second dummy pattern 202d is copied to the first layer 201, and the first dummy pattern 201d is placed at that position. If possible, arrange the second dummy pattern 202d (center axis) on the third layer 203 as indicated by arrows in the areas 20A and 20B of FIG. Then, if it is possible to place the third dummy pattern 203d at that position, it is arranged.

  Finally, since the third dummy pattern 203d can be formed in the remaining dummy pattern generation possible region 20Br, it is additionally formed (step S25).

  In the first and second embodiments, the example in which the CMP dummy pattern is formed in the wiring layer on which the wiring pattern is formed has been described. However, the formation of the CMP dummy pattern is not limited to the wiring layer. . Therefore, as a third embodiment, an example in which a CMP dummy pattern is provided in an STI (Shallow Trench Isolation) region which is an element isolation region provided in a semiconductor substrate will be described.

  7A and 7B are diagrams for explaining a semiconductor device 300 according to a third preferred embodiment of the present invention. FIG. 7A is a schematic cross-sectional view, and FIG. A plan view is shown. In FIG. 7A, the interlayer insulating film and the like are omitted for simplification. FIG. 7B shows only the dummy pattern.

  As shown in FIG. 7, the semiconductor device 300 according to the present embodiment is provided on the semiconductor substrate 303 and is planarized by CMP. The first wiring pattern 301 w and the plurality of first wirings made of the same material as the first wiring pattern 301 w are provided. A first layer 301 including a dummy pattern 301d and a plurality of second layers made of the same material as the second wiring pattern 302w and the second wiring pattern 302w provided on the first layer 301 on the semiconductor substrate and planarized by CMP. A plurality of fourth layers including a second layer including the dummy pattern 302d, a wide STI region 303t provided in the element isolation region 303i of the semiconductor substrate 303, and a part of the semiconductor substrate 303 provided in the STI region 303t. And a dummy pattern 303d.

  In the first and second layers 301 and 302, regions where the wiring patterns 301w and 302w are not formed become dummy pattern generation regions 30A and 30B, and in the semiconductor substrate 303, a wide STI region 303t is generated as a dummy pattern. This is a possible area 30A. Then, dummy patterns 301d to 303d are respectively arranged. In the present embodiment, the plurality of first dummy patterns 301d are arranged so as to be packed in the dummy pattern generating area 30A in the first layer 301 in the closest packing manner. In the dummy pattern generation possible region 30A, as indicated by broken lines, the central axes of each of the plurality of first dummy patterns 301d and each of the plurality of second dummy patterns 302d corresponding to each other are perpendicular to the semiconductor substrate 303. As described above, the second dummy pattern 302d is arranged. Similarly, the central axes of the plurality of third dummy patterns 303d also coincide with each of the plurality of first dummy patterns 301d and the corresponding plurality of third dummy patterns 303d in the direction perpendicular to the semiconductor substrate. Is arranged.

  Since the first dummy pattern 101d is not formed in the dummy pattern generation possible region 30B, the second dummy pattern 302d is arranged so as to be packed most closely in this region.

  Thus, according to the present embodiment, as shown in FIG. 7B, not only the dummy patterns 301d and 302d provided in each wiring layer but also the dummy patterns 303d provided in the semiconductor substrate 303 are vertically moved. The central axes of the corresponding dummy patterns are the same. Therefore, also in the present embodiment, it is possible to obtain the same effect as in the first and second embodiments.

  Next, a method for manufacturing the semiconductor device 300 according to the third embodiment will be described with reference to FIGS.

  FIG. 8 is a flowchart for explaining a manufacturing method of the semiconductor device 300 according to the third embodiment. Before the element isolation region 303i and the first and second layers 301 and 302 are formed in the semiconductor device 300 shown in FIG. 4 shows a process for determining the number and arrangement of dummy patterns 301d to 303d in each layer.

  First, dummy pattern generation possible areas 30A and 30B are extracted (step S31). Next, the number and arrangement are determined so that the first dummy pattern 301d is closest packed in the dummy pattern generation possible region 30A including the first layer 301 to be closest packed (step S32). Subsequently, based on the arrangement of the first dummy pattern 301d, the central axis of the second dummy pattern 302d formed in the second layer 302 is aligned with the central axis of the first dummy pattern 301d in a direction perpendicular to the semiconductor substrate 303. Next, the number and arrangement of the second dummy patterns 302d are determined (step S33). Next, based on the arrangement of the first dummy pattern 301d, the central axis of the third dummy pattern 303d formed on the semiconductor substrate 303 is aligned with the central axis of the first dummy pattern 301d in a direction perpendicular to the semiconductor substrate 303. The number and arrangement of the third dummy patterns 303d are determined (step S34). That is, as indicated by an arrow in the area 30A of FIG. 7A, the position (center axis) of the first dummy pattern 301d is copied to the second layer 302, and the second dummy pattern 302d is placed at that position. If possible, it is arranged, and similarly, the position (center axis) of the first dummy pattern 301d is copied to the semiconductor substrate 303 and the third dummy pattern 303d is arranged at that position.

  Finally, the number and arrangement of the second dummy patterns 302d are determined in the dummy pattern generation possible area 10B so that the second dummy patterns 302d are closest packed (step S35).

  Next, as a fourth embodiment of the present invention, an example in which an impermeable film is provided on a semiconductor substrate will be described with reference to FIGS.

  9A and 9B are views for explaining the structure of the semiconductor device 400 according to the fourth embodiment of the present invention. FIG. 9A is a schematic cross-sectional view, and FIG. A transparent plan view is shown. In FIG. 9A, for simplification, only a wiring pattern and a dummy pattern for CMP are shown, and a semiconductor substrate, an interlayer insulating film, and the like are omitted. FIG. 9B shows only the dummy pattern.

  As shown in FIG. 9, the semiconductor device 400 according to the present embodiment is provided on a semiconductor substrate (not shown) and is made of the same material as the first wiring pattern 401w and the first wiring pattern 401w that are planarized by CMP. The first layer 401 including the plurality of first dummy patterns 401d and the second wiring pattern 402w and the second wiring pattern 402w provided on the first layer 401 on the semiconductor substrate and planarized by CMP are made of the same material. A plurality of layers made of the same material as the third wiring pattern 403w and the third wiring pattern 403w provided between the second layer including the plurality of second dummy patterns 402d and the semiconductor substrate and the first layer and planarized by CMP. The third layer 403 including the third dummy pattern 403d, and the non-transmissive film 41 provided between the third layer 403 and the first layer 401. And it is configured to include and. Here, examples of the non-permeable film 410 include amorphous carbon used as an insulating film, and a metal film used as a plate electrode of a capacitor.

  In each of the layers 401 to 403, regions where the wiring patterns 401w to 403w are not formed become dummy pattern generation regions 40A and 40B, and the dummy patterns 401d to 403d are arranged, respectively. In the present embodiment, the plurality of first dummy patterns 401d are arranged so as to be closely packed in the dummy pattern generating regions 40A and 40B in the first layer 401. In the dummy pattern generation regions 40A and 40B, as indicated by broken lines, each of the plurality of first dummy patterns 401d and each of the plurality of second dummy patterns 402d corresponding to the central axis are perpendicular to the semiconductor substrate. The second dummy patterns 402d are arranged so that the two match.

  On the other hand, in the third layer 403 below the non-transmissive film 410, a plurality of third dummy patterns are formed so as to be packed in the dummy pattern generating area 40A without being based on the arrangement of the first dummy patterns 401d and 402d. 403d is arranged. This is because, in optical defect detection, inspection light does not pass through the non-transmissive film 410, so that what is below the non-transmissive film 410 does not appear in the detection result. Therefore, in the third layer 403, the number and arrangement of the third dummy patterns 403d can be determined independently regardless of the first and second dummy patterns 401d and 402d.

  Therefore, as shown in FIG. 9B, the first dummy pattern 401d and the second dummy pattern 402d always have the same center axis at the position where they are arranged one above the other, but the third dummy pattern 403d corresponds to each of the first dummy patterns 401d (at least partially overlaps the upper and lower sides) and each of the third dummy patterns 403d has a configuration in which the central axis is shifted in a direction perpendicular to the semiconductor substrate. . According to such a configuration, in optical defect detection, it is possible to prevent the occurrence of moiré due to the dummy pattern, and in the layer below the non-transmissive film 410, the dummy pattern is further improved in flatness by CMP. Can be arranged.

  Next, a method for manufacturing the semiconductor device 400 according to the preferred fourth embodiment of the present invention will be described with reference to FIGS.

  FIG. 10 is a flowchart for explaining a manufacturing method of the semiconductor device 400 according to the fourth embodiment. Before forming the first to third layers 401 to 403 in the semiconductor device 400 shown in FIG. A process for determining the number and arrangement of dummy patterns 401d to 403d is shown.

  First, dummy pattern generation possible areas 40A and 40B are extracted (step S41). Next, the number and arrangement are determined so that the first dummy pattern 401d is closest packed in the dummy pattern generation possible regions 40A and 40B including the first layer 401 to be closest packed (step S42). ). Subsequently, based on the arrangement of the first dummy pattern 401d, the central axis of the second dummy pattern 402d formed on the second layer 402 is aligned with the central axis of the first dummy pattern 401d in a direction perpendicular to the semiconductor substrate. The number and arrangement of the second dummy patterns 402d are determined (step S43). Next, the number and arrangement of the dummy patterns 403d in the third layer are determined so that the third dummy patterns 403d are closest packed (step S44).

  Finally, since the second dummy pattern 402d can be formed in the remaining dummy pattern generating area 40Br, it is additionally formed (step S45).

  In the first to fourth embodiments, the example in which the central axes of the dummy patterns of the respective layers are matched is shown, but the central axes need not necessarily be matched. Therefore, as a fifth embodiment, a semiconductor device including a dummy pattern whose central axis does not coincide with other layers will be described.

  11A and 11B are views for explaining the structure of a semiconductor device 500 according to a preferred fifth embodiment of the present invention. FIG. 11A is a schematic cross-sectional view, and FIG. A transparent plan view is shown. In FIG. 11A, for simplification, only a wiring pattern and a dummy pattern for CMP are shown, and a semiconductor substrate, an interlayer insulating film, and the like are omitted. FIG. 11B shows only the dummy pattern.

  As shown in FIG. 11, the semiconductor device 500 according to the present embodiment is made of the same material as the first wiring pattern 501w and the first wiring pattern 501w provided on the semiconductor substrate (not shown) and planarized by CMP. The first layer 501 including the plurality of first dummy patterns 501d and the second wiring pattern 502w and the second wiring pattern 502w provided on the first layer 501 on the semiconductor substrate and planarized by CMP are made of the same material. A second layer including a plurality of second dummy patterns 502d and a plurality of third wiring patterns 503w and third wiring patterns 503w, which are provided on the second layer 502 on the semiconductor substrate and planarized by CMP, are made of the same material. And a third layer 503 including the third dummy pattern 503d.

In each of the layers 501 to 503, regions where the wiring patterns 501w to 503w are not formed become dummy pattern generation possible regions 50A and 50B, and the dummy patterns 501d to 503d are respectively arranged. In the dummy pattern generatable region 50A, a plurality of first dummy patterns 501d are arranged so as to be closely packed in the dummy pattern generatable region 50A in the first layer 501. In the present embodiment, a rectangular second dummy pattern 502d is arranged in the dummy pattern generating area 50A in the second layer 502. The central axis (indicated by a dotted line) of the second dummy pattern 502d does not coincide with the central axis (indicated by a broken line) of the first dummy pattern 501d. That is, one rectangular second dummy pattern 502d is provided corresponding to the two first dummy patterns 501d. One and two first dummy pattern 501d and the rectangular second dummy pattern 502d, the dotted line of the first dummy pattern 501d of the left central axis the distance _{L 1} and the dotted line between the central axis of the second dummy pattern 502d We have a relationship that the center of the right side of the first dummy pattern 501d axis and the distance L ₂ between the center axis of the second dummy pattern 502d is in the same distance.

  As for the third dummy pattern 503d in the dummy pattern generation possible region 50A, each of the plurality of third dummy patterns 503d corresponding to each of the plurality of first dummy patterns 501d is the same as in the first to fourth embodiments. The central axes are arranged in the direction perpendicular to the semiconductor substrate.

Since the first dummy pattern 501d is not formed in the dummy pattern generating area 50B, the third dummy pattern 503d is arranged in this area so as to be closely packed. A rectangular second dummy pattern 502d is arranged in the dummy pattern generating area 50B in the second layer 502. The central axis (indicated by a dotted line) of the dummy pattern 502d does not coincide with the central axis (indicated by a broken line) of the third dummy pattern 503d. That is, one rectangular second dummy pattern 502d is provided corresponding to the two third dummy patterns 503d. The two third dummy pattern 503d and one of the rectangular second dummy pattern 502d, the dotted line of the third dummy pattern 503d of the left center axis of the distance _{L 3} and dotted line with the central axis of the second dummy pattern 502d a relationship that the right side of the central axis of the third dummy pattern 503d and the distance L ₄ between the center axis of the second dummy pattern 502d is in the same distance.

  Even with such a configuration, since there is a predetermined relationship as described above between the upper and lower dummy patterns, it is possible to suppress the occurrence of moire due to the dummy pattern when optically detecting defects. it can. As a result, only fine particles and defects can be detected, and the yield can be improved.

  In the present embodiment, the width of the second dummy pattern 502d (long side in the planar shape) is set to be larger than twice the width of the first dummy pattern 501d and twice the width of the third dummy pattern 503d according to the design criteria. This is an example of the case. Here, in the dummy pattern generation possible region 50A, as in the first to fourth embodiments, the second dummy pattern 501d and the second dummy pattern are made to coincide with the central axis of the first dummy pattern 501d. If the pattern 502 dc is arranged, as shown by a long broken line in FIG. 11, the arrangement is biased toward the wiring 502 w on one side, and a region where no dummy pattern is formed remains on the opposite side. It can be a cause. Therefore, when a dummy pattern having a size that is twice, three times, etc. larger than the size of the dummy pattern of the layer that should be filled with the dummy pattern must be provided in another layer, as in this embodiment. It is preferable to adopt a simple configuration.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the first embodiment, an example in which the plane sizes of all the dummy patterns are the same is shown, and in the second to fourth embodiments, an example in which the plane sizes of the dummy patterns are different for each layer is shown. However, the present invention is not limited to this, and the planar sizes of the dummy patterns in at least two of the plurality of layers may be the same, and the other layers may have different planar sizes.

  In addition, as shown in the first to fourth embodiments, basically, it is preferable that the central axes of all the dummy patterns corresponding to the upper and lower layers coincide with each other. As long as a defect can be detected, there is no problem even if there is a dummy pattern whose central axes do not coincide with each other.

  In each of the above embodiments, the case where any one of the layers is a layer that should be filled with the dummy pattern has been described. However, as described with reference to FIG. However, if there is no layer to be closely packed, the dummy pattern may be packed in the layer having a predetermined high priority.

100, 100m, 200, 300, 400, 500 Semiconductor devices 101, 101m, 201, 301, 401, 501 First layer 102, 102m, 202, 302, 402, 502 Second layer 103, 103m, 203, 403, 503 Third layer 10A, 10B, 10Br, 20A, 20B, 30A, 30B, 40A, 40B, 40Br, 50A, 50B Dummy pattern generation area 101d, 101md, 201d, 301d, 401d, 501d First dummy pattern 102d, 102md, 202d, 302d, 402d, 502d, 502dc Second dummy pattern 103d, 103md, 203d, 303d, 403d, 503d Third dummy pattern 101w, 201w, 301w, 401w, 501w First wiring pattern 102w, 20 w, 302w, 402w, 502w second wiring patterns 103w, 203w, 403w, 503w third wiring patterns 303 a semiconductor substrate 303i isolation region 303t STI region 410 non-permeable membrane

Claims (20)

First and second wiring patterns provided on the main surface of the substrate and arranged with a first gap, and first and second dummy patterns arranged in the first gap and separated from each other, A first wiring structure including the first and second wiring patterns and a first insulating layer covering the first and second dummy patterns;
Third and fourth wiring patterns stacked in a direction perpendicular to the main surface of the substrate with respect to the first wiring structure and disposed with a second gap, and disposed in the second gap A second wiring structure including a third dummy pattern formed, a third insulating pattern covering the third and fourth wiring patterns, and the third dummy pattern,
The third dummy pattern of the second wiring structure is level with the main surface of the substrate so as to continuously overlap both the first and second dummy patterns of the first wiring structure. Semiconductor device extending in various directions.   The semiconductor device according to claim 1, wherein the second wiring structure is stacked on the first wiring structure. The fifth and sixth wiring patterns stacked on the second wiring structure and arranged with a third gap, and the fourth and fifth wiring patterns arranged in the third gap and separated from each other. A third wiring structure including a dummy pattern, a fifth insulating pattern covering the fifth and sixth wiring patterns, and a fourth insulating layer covering the fourth and fifth dummy patterns;
3. The fourth and fifth dummy patterns of the third wiring structure coincide with central axes of the first and second dummy patterns of the first wiring structure, respectively. 4. Semiconductor device.   The semiconductor device according to claim 3, wherein the first, second, and third gaps are different from each other. The first wiring structure further includes at least one additional dummy pattern provided in the first gap and forming a straight line with the first and second dummy patterns,
3. The semiconductor device according to claim 2, wherein the third dummy pattern of the second wiring structure does not overlap with the at least one additional dummy pattern. The first wiring structure further includes at least one additional dummy pattern provided in the first gap,
The number of dummy patterns provided in the first gap of the first wiring structure is greater than the number of dummy patterns provided in the third gap of the third wiring structure. 3. A semiconductor device.   The distance between the central axis of the third dummy pattern and the central axis of the first dummy pattern is substantially equal to the distance between the central axis of the third dummy pattern and the central axis of the second dummy pattern. The semiconductor device of claim 2, which is equal. The distance between the central axis of the third dummy pattern and the central axis of the first dummy pattern is substantially equal to the distance between the central axis of the third dummy pattern and the central axis of the second dummy pattern. equally,
The distance between the central axis of the third dummy pattern and the central axis of the fourth dummy pattern is substantially the same as the distance between the central axis of the third dummy pattern and the central axis of the fifth dummy pattern. The semiconductor device of claim 3, which is equal. The first dummy pattern of the first wiring structure has a larger area than the fourth dummy pattern of the third wiring structure,
4. The semiconductor device according to claim 3, wherein the second dummy pattern of the first wiring structure has a larger area than the fifth dummy pattern of the third wiring structure.   The semiconductor device according to claim 1, wherein the first wiring structure is stacked on the second wiring structure.   The distance between the central axis of the third dummy pattern and the central axis of the first dummy pattern is substantially equal to the distance between the central axis of the third dummy pattern and the central axis of the second dummy pattern. The semiconductor device of claim 10, which is equal. A fifth wiring pattern; a fourth dummy pattern provided adjacent to the fifth wiring pattern; and a third insulating layer covering the fifth wiring pattern and the fourth dummy pattern. A third wiring structure including:
The second wiring structure is the third wiring structure so that the third dummy pattern of the second wiring structure is positioned on the fifth wiring pattern of the third wiring structure. The semiconductor device according to claim 10, which is stacked on the semiconductor device. First and second wiring patterns provided on the main surface of the substrate and disposed with a first gap, two or more first dummy patterns disposed in the first gap, and the first A first layer wiring structure including first and second wiring patterns and a first insulating layer covering the two or more first dummy patterns;
Third and fourth wiring patterns stacked on the first layer wiring structure in a direction perpendicular to the main surface of the substrate and arranged with a second gap, and arranged in the second gap A second layer wiring structure including at least one second dummy pattern formed, a third and fourth wiring pattern, and a second insulating layer covering the at least one second dummy pattern;
Fifth and sixth wiring patterns stacked on the second layer wiring structure in a direction perpendicular to the main surface of the substrate and disposed with a third gap, and disposed in the third gap A third layer wiring structure including at least two third dummy patterns formed, a fifth insulating pattern covering the fifth and sixth wiring patterns, and a third insulating layer covering the at least two third dummy patterns; With
The at least one second dummy pattern extends in a direction horizontal to the main surface of the substrate so as to continuously overlap at least two of the two or more first dummy patterns of the first layer wiring structure. Configure an extended dummy pattern,
The semiconductor device, wherein the at least two third dummy patterns are both arranged on the extended dummy pattern and have a central axis coinciding with the at least two of the two or more first dummy patterns. .   The semiconductor device according to claim 13, wherein the first, second, and third gaps are different from each other.   The semiconductor device according to claim 13, wherein the first gap is larger than the second gap, and the second gap is larger than the third gap.   The distance between the central axis of the at least one second dummy pattern and the central axis of the at least two of the two or more first dummy patterns is the central axis of the at least one second dummy pattern The semiconductor device according to claim 13, wherein the distance between the central axis of the at least two of the two or more first dummy patterns and the other central axis is substantially equal.   The distance between the central axis of the at least one second dummy pattern and the central axis of any one of the at least two third dummy patterns is equal to the central axis of the at least one second dummy pattern and the at least 2 The semiconductor device according to claim 16, which is substantially equal to a distance from the other central axis of one of the third dummy patterns. The second layer wiring structure further includes a fourth dummy pattern provided on the opposite side of the at least one second dummy pattern when viewed from the third wiring pattern,
The third layer wiring structure further includes at least two fifth dummy patterns provided on the opposite side of the at least two third dummy patterns when viewed from the fifth wiring pattern,
14. The semiconductor device according to claim 13, wherein each of the at least two fifth dummy patterns is located on the fourth dummy pattern of the second layer wiring structure.   The distance between the central axis of the fourth dummy pattern and the central axis of one of the at least two fifth dummy patterns is the distance between the central axis of the fourth dummy pattern and the at least two fifth dummy patterns. 19. The semiconductor device according to claim 18, which is substantially equal to a distance from any one of the other central axes.   19. The semiconductor device according to claim 18, wherein the fourth dummy pattern is positioned on the first wiring pattern of the first layer wiring structure.

Images