JP2014207722A - Power supply device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply device capable of charging a desired secondary battery body and monitoring a charging state in a secondary accumulator battery configured by connecting secondary battery bodies in series, and to achieve reduction in the number of selection switches, reduction in wiring load, and simplification of a logical structure.SOLUTION: A power supply device comprises: a secondary accumulator battery 10 configured by connecting a plurality of secondary battery bodies in series; a constant current generation circuit 12; and a selection switch changeover circuit 11 for forming a charging path. The selection switch changeover circuit 11 is configured by a matrix type switch part 14, a row selection signal generation circuit 15, and a column selection signal generation circuit 16. The matrix type switch part 14 consists of a row selection multiplexer part 17 and a column selection multiplexer part 18. A positive electrode terminal and a negative electrode terminal selected by a row selection signal XS and upper column and lower column selection signals YSH and YSL are electrically connected with a supply output terminal BVH and a supply input terminal BVL of the constant current generation circuit 12, respectively.

Description

  The present invention relates to a charging circuit and a power supply device for a secondary battery configured by connecting unit cells and assembled batteries in series.

In electric vehicles, hybrid electric vehicle storage batteries, uninterruptible power supply devices, and renewable energy support storage batteries, secondary batteries such as lead storage batteries, nickel-metal hydride batteries, and lithium batteries are used as unit cells, and these are connected in series. The assembled battery is used. In such an assembled battery, the terminal voltage varies depending on the state of charge (SOC: State of Charge) while charging and discharging are repeated. May become overcharged or overdischarged, resulting in deterioration of the unit cell and failure of the battery body. Further, there is a problem that it is difficult to fully use the battery capacity because the unit cell cannot be sufficiently charged to the rated capacity.

In order to solve such a problem, Patent Document 1 proposes a charge state adjustment device as a method for adjusting variation in the charge state among a plurality of unit cells constituting a charged assembled battery. A capacitor charged in advance to a full unit cell voltage is cyclically connected to each unit cell to temporarily reduce voltage variations between the unit cells.

On the other hand, in Patent Document 2, as shown in FIG. 20, a constant current source generation circuit 20 and a selection switch switching circuit 30 are provided, and an arbitrary secondary battery body 10A is controlled by controlling the selection switches 31A-31H on and off. A power supply circuit device having a chopper circuit including a reactor L formed between a supply output terminal OT and a supply input terminal IT of the constant current generation circuit and a charging switch 22 while forming a charging path for 10D Proposed. In this case, the selection switch is a semiconductor switching element such as a thyristor, a GTO thyristor, an IGBT, a bipolar transistor, or a MOSFET.

  However, the conventional charging circuit device described above has the following problems. In the case of Patent Document 1, the charging process and the adjustment process are separately required, and a plurality of cyclic man-hours are required, so that charging time is required, and the circuit configuration is complicated because of the dynamic circuit. In addition, a large capacity element is required, and since a photo MOS transistor is used as the switching element, the cost increases and the switching circuit is complicated.

  In Patent Document 2, when the secondary battery is composed of a series connection circuit of Nt secondary battery bodies, approximately 2Nt selection switches are required, and there is a problem that the circuit scale becomes large. For example, when Nt = 64, 128 selection switches are required. In addition, the control circuit of the selection switch becomes complicated, and a large number of selection switches are connected to the supply output terminal OT and the supply input terminal IT of the constant current source generation circuit, respectively. And parasitic capacitance increases. Therefore, there is a problem that the influence of switching loss and surge voltage cannot be ignored and the charging time is increased.

JP 2002-17048 A Japanese Patent Application No. 2010-109711 (International Publication WO2011 / 142369)

  The present invention relates to a secondary storage battery that enables equal charging between arbitrary unit cells, assembled batteries, or a series connection body thereof, and intends to solve the problems of such a conventional configuration. Reduce the number of selection switches and simplify the control circuit configuration to reduce the circuit scale, and reduce the parasitic capacitance of the selection switch signal line to suppress switching loss, surge voltage, and charging The purpose is to reduce time.

The second object is to provide a power supply device or a charging circuit that can easily monitor terminal voltage, charge / discharge control, and regenerative operation for each unit cell, assembled battery, or series connection body thereof. Hereinafter, unless otherwise specified, the unit cell, the assembled battery, or the unit unit in which these are connected in series is referred to as a secondary battery body. Here, the assembled battery refers to a battery in which a plurality of unit cells are connected in series to obtain a voltage of several tens of volts. However, the present invention is not limited to these, and a secondary battery such as a unit-type secondary battery. Secondary storage batteries that are connected in series can also be applied.

  The present invention relates to a secondary battery in which secondary battery bodies are connected in series, and a selection switch for selecting a positive electrode and a negative electrode of a desired secondary battery body, and a matrix type switch that enables two-dimensional addressing of columns and rows. The main feature is that it is composed of an array.

In order to achieve the above object, a power storage device according to the first means according to claim 1 is a secondary storage battery configured by connecting a plurality of secondary battery bodies each having a positive electrode terminal and a negative electrode terminal in series; A constant current generating circuit for charging the secondary battery body from the supply output terminal and the supply input terminal, and a selection for individually forming a charging path between the supply output terminal, the supply input terminal and the secondary battery body An address for specifying the electrode terminal position of the secondary battery body, a column address for designating a secondary battery string divided into secondary battery bodies, and an address in the secondary battery array. It consists of a row address that designates the electrode terminal position of the next battery body.

  Specifically, the selection switch switching circuit includes a matrix type switch unit configured by a two-dimensional selection switch of a column switch and a row switch, a column selection signal generation circuit, and a row selection signal generation circuit. The column selection signal generation circuit generates a column switch selection signal from a column address signal that specifies the positions of the positive electrode and the negative electrode terminal to be charged, and the row selection signal generation circuit generates a positive signal to be charged. An upper row and lower row switch selection signal is generated from an upper row address signal and a lower row address signal that specify the positions of the electrode terminal and the negative electrode terminal, respectively.

  Further, the matrix type switch unit is a column selection multiplexer unit composed of a plurality of column multiplexers, each of which includes a column switch group having the electrode terminal of each secondary battery column as an input and the column switch selection signal as a selection control signal. And an output line of the column selection multiplexer unit, and a row selection multiplexer unit selected by an upper row and lower row switch selection signal and having signal terminals of upper row and lower row switches as output terminals. Are connected to the supply output terminal and the supply input terminal, respectively.

  By doing so, the positive electrode terminal and the negative electrode terminal selected by the column switch selection signal and the upper row and lower row switch selection signal are electrically connected to the supply output terminal and the supply input terminal, respectively. By the on / off control of the column switch and the row switch, any electrode terminal can be charged with a small number of switches.

  According to a second means of the present invention, in the power supply apparatus, the column selection signal generation circuit specifies the positions of the positive electrode terminal and the negative electrode terminal of the secondary battery body to be charged. A row selection signal is generated by an OR logic gate circuit that generates a column switch selection signal by taking the logical sum of outputs of an upper address decoder, a lower address decoder, and an upper address decoder and a lower address decoder. The circuit decodes the upper row and lower row address signals that specify the positions of the positive electrode terminal and negative electrode terminal of the secondary battery body to be charged and generates the upper row and lower row switch selection signals, respectively. It consists of a decoder and a lower row address decoder.

  The matrix type switch unit is composed of a plurality of column multiplexers each including a group of column switches, each of which has an electrode terminal having the same row address value of each secondary battery column and a column switch selection signal as a selection control signal. The column selection multiplexer unit and the column selection multiplexer unit are used as inputs and the upper row multiplexer and the lower row switch selection signal are used as selection control signals. Is done.

  Further, the output terminals of the upper row and lower row multiplexers are connected to a supply output terminal and a supply input terminal, respectively. Due to the configuration of the column selection signal generation circuit, only two column switches connected to the positive electrode terminal and the negative electrode terminal respectively corresponding to the upper address signal and the lower address are turned on. For this reason, any electrode terminal can be set as a charge target except between electrode terminals of the same row address (described later).

According to a third means of the present invention, in the power supply device according to the second means, the matrix type switch unit receives an electrode terminal having an equal column address value of each secondary battery column as an input, and the column switch A column selection multiplexer unit composed of a plurality of column multiplexers that use a selection signal as a selection control signal and an output line of the column selection multiplexer unit as inputs, and the upper row and lower row switch selection signals are used as selection control signals, respectively. , And a row selection multiplexer unit including an upper row multiplexer and a lower row multiplexer.
The output terminals of the upper row and lower row multiplexers are connected to a supply output terminal and a supply input terminal, respectively. In this case, since one electrode terminal signal is selectively output in each secondary battery row, a charging path is formed between desired positive electrode terminals and negative electrode terminals in different secondary battery rows.

According to a fourth means of the present invention, in the power supply device according to the first means, the column selection signal generating circuit determines the positions of the positive electrode terminal and the negative electrode terminal of the secondary battery body to be charged. It consists of an address decoder that decodes a designated column address signal to generate a column switch selection signal, and the row selection signal generation circuit designates the positions of the positive electrode terminal and the negative electrode terminal of the secondary battery body to be charged. It consists of an upper row address decoder and a lower row address decoder that decode the upper row and lower row address signals and output the upper row and lower row switch selection signals, respectively.

Further, the matrix type switch unit includes a column multiplexer composed of a plurality of column switch groups, each of which has each electrode terminal of the secondary battery column as an input and a column switch selection signal as a selection control signal. And a row selection multiplexer unit including an upper row multiplexer and a lower row multiplexer, each having an output line of the column selection multiplexer unit as an input and upper and lower row switch selection signals as selection control signals. The output terminals of the upper row and lower row multiplexers are connected to a supply output terminal and a supply input terminal, respectively.

In this means, the column multiplexer is controlled by one column switch selection signal, and the column switches in the column multiplexer section are simultaneously turned on and off. Therefore, a charging path is formed between desired electrode terminals in each secondary battery row. The number of column switch selection signal lines is small, and the column switch selection signal lines, row signal lines, and switch elements can be arranged and wired regularly like a memory. is there.

A fifth means according to an eighth aspect of the present invention differs from the first basic configuration (FIG. 1) in the power supply device according to the first means except that the roles of the row and column switches are reversed. The electrode terminal of the secondary battery column is connected to the column signal line via a desired row switch, and the column signal line data is input / output controlled by the column selection multiplexer unit. The row selection signal generation circuit generates a row switch selection signal from a row address signal that specifies the positions of a positive electrode terminal and a negative electrode terminal to be charged, and the column selection signal generation circuit is a charge target. An upper column and lower column switch selection signal is generated from an upper column address signal and a lower column address signal that specify the positions of the positive electrode terminal and the negative electrode terminal, respectively.

In addition, the matrix type switch unit has a row selection multiplexer unit composed of a plurality of row multiplexers each composed of a row switch group, with the electrode terminal of the secondary battery column as an input and the row switch selection signal as a selection control signal. It consists of a column selection multiplexer unit that takes the output line of the row selection multiplexer unit as input, uses the upper column and lower column switch selection signals as selection control signals, and uses the selected upper column and lower column switch signal terminals as output terminals. . The output terminals of the column selection multiplexer unit are connected to the supply output terminal and the supply input terminal, respectively.

The positive electrode terminal and the negative electrode terminal selected by the row switch selection signal, the upper column, and the lower column switch selection signal are electrically connected to the supply output terminal and the supply input terminal, respectively. In this case, the row switch having the same row address value is turned on, and a charging path is formed between the electrode terminals having the same row address value between different secondary battery columns.

With these configurations, charging / discharging between desired electrode terminals can be performed with a smaller number of switches. For example, if the secondary battery is composed of ^2N secondary battery bodies, as N increases, the number of switches is reduced to nearly 50% of that of the conventional example, thereby reducing the size and cost (described later). ). Further, since the battery and its control wiring can be regularly laid out in the form of a memory, there is an advantage that the circuit configuration can be simplified and compact, and the failure can be easily found. Furthermore, the wiring capacity and the number of fine fanouts can be reduced. The above effects are useful for reducing power consumption and switching loss and suppressing surge voltage.

The selection switch is usually composed of an IGBT, a thyristor, a MOS transistor, or a bipolar transistor. However, the selection switch is not limited to a semiconductor switch, and an electromagnetic relay or the like can also be applied. In addition, it becomes clear from the Example demonstrated below that the batch charge of a secondary battery is also possible.

1 is a first basic configuration showing a power supply device according to the present invention; This is an address bit format for designating electrode terminals. 1 is a block diagram of a power supply device illustrating Example 1. FIG. 1 is a circuit diagram of a power supply device showing Example 1. FIG. 3 is a time chart for explaining the operation of the first embodiment. FIG. 6 is a block diagram of a power supply device showing a second embodiment. FIG. 6 is a circuit diagram of a power supply device showing a second embodiment. FIG. 6 is a block diagram of a power supply device showing a third embodiment. FIG. 6 is a circuit diagram of a power supply device showing Example 3. FIG. 6 is a circuit diagram of a power supply device showing a fourth embodiment. FIG. 10 is a circuit diagram of a power supply device showing a fifth embodiment. FIG. 10 is a circuit diagram of a row selection signal generation circuit showing a sixth embodiment. It is a 2nd basic composition which shows the power supply device by this invention. FIG. 10 is a circuit diagram of a power supply device showing Example 7. It is a circuit diagram which shows the example of a selection switch. FIG. 10 is a circuit diagram of a power supply device using an IGBT as a selection switch, showing an eighth embodiment. FIG. 10 is a circuit diagram of a power supply device using a thyristor as a selection switch, showing a ninth embodiment. 1 is a circuit diagram illustrating a first embodiment of a constant current generating circuit. FIG. FIG. 6 is a circuit diagram illustrating a constant current generating circuit according to a second embodiment. It is a circuit diagram which shows the example of the conventional power supply device.

Hereinafter, embodiments of the present invention will be described with reference to FIGS.
A first basic configuration of a power supply device according to the present invention is shown in FIG. The power supply device 9 includes a secondary storage battery 10 formed by connecting a plurality of secondary battery bodies 10A to 10D in series, a supply output terminal BVH, a constant current generation circuit 12 that charges the secondary battery body through the supply input terminal BVL, and two It consists of a selection switch switching circuit 11 (one-dot chain line portion) that forms an arbitrary charging path with the secondary battery 10. Further, a charging voltage monitoring amplifier circuit 13 may be provided. Here, the secondary battery body refers to a unit cell, an assembled battery, or a unit battery unit in which these are connected in series. The selection switch switching circuit 11 includes a matrix type switch unit 14 (broken line portion) composed of a row switch and a column switch, a column selection signal generation circuit 15, and a row selection signal generation circuit 16. The matrix switch unit 14 includes a column selection multiplexer unit 17 and a row selection multiplexer unit 18. Although the number of secondary battery bodies is four for convenience of explanation, it is needless to say that the number of secondary battery bodies may be composed of more than this, for example, several tens to several hundreds.

Each secondary battery body of the secondary storage battery 10 is divided into secondary battery rows grouped into a plurality of secondary battery bodies, and the electrode terminal positions of the secondary battery bodies are column addresses indicating the secondary battery rows. And a two-dimensional address composed of row addresses indicating electrode terminal positions in the secondary battery column. FIG. 2 shows an address format and a bit name for designating electrode terminal positions in a secondary storage battery composed of 2 ^m × 2 ⁿ secondary battery bodies. 2A shows the positive electrode terminal address (upper address), and FIG. 2B shows the negative electrode terminal address (lower address). Here, in one or more secondary battery bodies to be charged, the address of the positive electrode terminal to which power is supplied from the supply output terminal is the upper address, and power is supplied from the supply input terminal. The address of the negative electrode terminal is called a lower address.

The total address bit number N is represented by m + n, which is the sum of the column address bit number m and the row address bit number n. In this case, a maximum of 2 ^m × 2 ⁿ secondary battery bodies can be addressed. The upper address consists of an m-bit upper column address XAH (m-1) -XAH0 and an n-bit upper row address YAH (n-1) -YAH0, and the lower address is an m-bit lower column address XAL ( m-1) -XAL0 and n-bit lower row address YAL (n-1) -YAL0.

For convenience of explanation, for example, the signal names XAH4-XAH0 may be simply expressed as XAH4-0 or XAH. In some embodiments, the upper column address XAH and the lower column address XAL are the same, or the upper row address YAH and the lower row address YAL are the same. In these cases, the column address may be expressed as XA and the row address as YA unless otherwise specified.

In FIG. 1, the operation of the power supply device 9 in which the secondary storage battery 10 is composed of ^2N secondary battery bodies will be described. The column selection signal generation circuit 15 decodes m column address signals XA to generate 2 ^m column switch selection signals XS, and the column selection multiplexer unit 17 receives 2 ^m two-column signals in response to the column switch selection signal XS. ²ⁿ row signal lines YD are selectively output from the next battery column (not shown) and supplied to the row selection multiplexer unit 18. On the other hand, the row selection signal generation circuit 16 decodes n upper row address signals YAH and n lower row address signals YAL, and 2 ⁿ upper row switch selection signals YSH and lower row switch selection signals YSL, respectively. Is generated. The row selection multiplexer unit 18 selects the upper row and lower row signal lines to be charged from among the row signal lines YD by the upper row switch selection signal YSH and the lower row switch selection signal YSL, and supplies the supply output terminal BVH respectively. The charging path is formed by connecting to the supply input terminal BVL. The secondary battery body between the desired electrode terminals is charged through a path opposite to that described above, and voltage reading is performed along the path described above. Even if the number of secondary battery bodies does not match the power of 2, the effectiveness of the present invention is not impaired.

According to this basic configuration, in the matrix type switch unit having 2 ^m columns × 2 ⁿ rows, the number of necessary switches is basically the number of switches 2 ^m × 2 ⁿ in the column selection multiplexer unit and the number of switches in the row selection multiplexer unit. It is represented by the sum of 2 ⁿ × 2, (2 ^m +2) × 2 ⁿ , and can be reduced in number and cost compared to the number of switches according to the prior art example, for example, 2 ^{m + n + 1} . In particular, this effect increases as the number of secondary battery bodies increases, and it can be seen that the number can be reduced to 56% or less when the number is 64 or more (Table 3).

3 and 4 are a block diagram and a circuit diagram showing a first embodiment based on the first basic configuration of the present invention. In FIG. 4, the constant current generating circuit and the voltage monitoring amplifier are omitted for the sake of simplicity. Hereinafter, in the drawings for explaining the embodiments, for convenience of explanation, unless otherwise specified, 16 secondary battery bodies (2 ^N = 2 ⁴ , m = n = 2) are connected in series. , Consisting of four secondary battery arrays 10A-10D each consisting of four secondary battery bodies, but can be composed of a larger number of secondary battery bodies, and m and n are also selected as appropriate It goes without saying that it is possible. Hereinafter, unless otherwise specified, the same or equivalent components as those described above will be denoted by the same reference numerals, and descriptions of configurations and functions overlapping those described above will be omitted.

In FIG. 3, a column selection signal generation circuit 15 includes an upper address decoder 15H ((N + 1) × 2 ^{N + 1} = 5 × 32 decoder), a lower address decoder 15L (N × 2 ^N = 4 × 16 decoder), and two inputs. It consists of an OR logic gate circuit 19 and a driver circuit 20. The row selection signal generation circuit 16 (dotted line portion) includes an upper row address decoder 16H ((n + 1) × 2 ^{(n + 1)} = 3 × 8 decoder), a lower row address decoder 16L (n × 2 ⁿ = 2 × 4 decoder), It consists of driver circuits 21 and 22. Here, a multiplexer that selects one output from 2 ^a (= A) inputs by a number of selection control lines will be referred to as an A × 1 multiplexer. The column selection multiplexer unit 17 (broken line portion) includes a selector 17A-17D in which each of the four electrode terminals of the secondary battery columns 10A-10D is connected to an input terminal, and an output 4 (= 2) of the selector 17A-17D. ⁿ ) Each of these lines is wired OR connected to the row signal line YD3-0. The reason why there are only five outputs (row signal lines) from the selector 17D is that a row signal line YD4 for outputting the signal of the uppermost electrode terminal BP is specially added. The row selection multiplexer unit 18 includes an upper row multiplexer 18H and a lower row multiplexer 18L that receive the row signal lines YD3-0. However, in the upper row multiplexer 18H, the row signal line YD4 is also connected to the input terminal for the above reason.

Next, the operation will be described. The upper address decoder 15H decodes the 5-bit upper address signal (XAH2-0, YAH1, YAH0), and the lower address decoder 15L decodes the 4-bit lower address signal (XAL1, XAL0, YAL1, YAL0) and decodes each of them. Column switch selection signals XS15-XS0 are generated by the output OR logic output. Upper address signal is 5 bits Nanoha, generates two ⁴ decoding output or column switch selection signal XS16 upper address decoder, turns on the column switch and line switch, in order to off control. On the other hand, the upper row address decoder 16H decodes the 3-bit upper row address signal (XAH2, YAH1, YAH0), and the lower row address decoder 16L decodes the 2-bit lower row address signal (YAL1, YAL0). A row switch selection signal YSH4-0 (YSH4 is not shown) and a lower row switch selection signal YSL3-0 are output.

Any two of the column switch selection signals XS16 to XS0 are set to the active level, and two column switches corresponding to the upper address and the lower address are turned on, so that the selected electrode terminal is connected to the row signal line YD. Is electrically connected. However, the set address needs to maintain the magnitude relationship of the higher address value (XAH2-0, YAH1, YAH0)> the lower address value (XAL1, XAL0, YAL1, YAL0). In addition, since a predetermined signal line (selector output) of each secondary battery row is wired or connected, the difference between the upper and lower address values is 4 (= 2) in order to prevent data from competing on the signal line. ⁿ ) is prohibited. The restriction on the selection of the secondary battery body by this does not impair the effectiveness of the present invention. Table 1 shows the address setting conditions.

A specific description will be given with reference to the circuit diagram 4 of the first embodiment. The selector 17A includes a column switch SW3-0, the selector 17B includes a column switch SW7-4, the selector 17C includes a column switch SW11-8, and the selector D includes a column switch SW16-12. The upper row multiplexer 18H constitutes a 5 × 1 multiplexer with the row signal line YD4-0 as an input, and the lower row multiplexer 18L constitutes a 4 × 1 multiplexer with the row signal line YD3-0 as an input. Reference numerals 20, 21 and 22 denote driver circuits for driving the switches, and driver ICs incorporating a level shift circuit and an insulating photocoupler are used.

By setting the upper address signal to 5 bits, a column switch selection signal XS16 is generated, and the column switch SW16 and the row switch SWH4 are turned on by this signal to secure a selection path for the terminal BP of the highest electrode. Note that the upper row address signal has a 3-bit configuration in which the MSB bit XAH2 of the entire address is added to the row address (YAH1, YAH0). When the row switch SWH4 is turned on, the other upper row switches SWH3-SWH0 are turned off It is to make it. As the row switch selection signal of the upper row switch SWH4, a ^{2 second} decode output of the upper row address decoder 16H instead of XS16, it may be used row switch selection signal YSH4 (not shown). Table 2 shows the relationship between the column address and row address with respect to the electrode terminal number, and the range of addresses that can be set.

For example, when the upper address signals (XAH2-0, YAH1, YAH0) = (01111) and the lower address signals (XAL1, XAL0, YAL1, YAL0) = (1101) are set, the column switch selection signal XS15 = “1”, Since XS13 = “1”, the column switches SW13 and SW15 are turned on, and the row switch selection signal YSH3 = “1” and YSL1 = “1”. Therefore, the upper row switch SWH3 and the lower row switch SWL1 are turned on. A charging path indicated by a broken line is formed, and the secondary battery bodies BC14 and BC15 are charged. When performing batch charging (charging between secondary storage battery terminals BP and BN), the upper and lower addresses are (XAH2-0, YAH1, YAH0) = (10000), (XAL1, XAL0, YAL1, YAL0) = (0000) Should be set. In the following, in the circuit diagrams showing the embodiments, examples of the same charging path are indicated by broken lines, but the description is omitted.

FIG. 5 shows an example of an operation time chart when each secondary battery body is sequentially charged. Each address is sequentially counted up at a fixed period T while maintaining the relationship of upper address = lower address + 1. Since the column switch selection signal is a logical sum output of the upper and lower address decoders, the pulse width thereof is twice the period T except for the most significant bit selection signal XS16. In this case, it is desirable to delay the upper address signal from the lower address signal so that no hazard occurs at the center of the pulse width. The usual technology adopted in power electronics circuits for suppressing switching loss, surge voltage, and power consumption can be applied. The upper address signal makes a round to “16” and then returns to “1”, and the lower address signal makes a round to “15” and then returns to “0”. In a dummy cycle DMY or initial setting cycle (not shown) after one round of sequential charging of the secondary battery body, the upper address value> the lower address value is set, or the address decoder is disabled and all switch selection signals are turned off. Must be active level. This term chart shows the case where each secondary battery body is sequentially charged, but sequential charging with an arbitrary number of secondary battery bodies as a unit, or charging in which the voltage (current) measurement period and the charging period are alternately repeated. Any sequence is possible.

It is desirable to use an address decoder with an enable function in order to reduce power consumption. That is, it is effective for disabling the address decoder and making the output inactive in the sleep state or the dummy cycle in order to stabilize the operation and reduce power consumption (not shown). Further, in order to prevent a short circuit of the power source due to the simultaneous turning on of the switches, and to ensure a signal settling time at the time of switching, it is preferable to provide a dummy time between each cycle. Note that the present invention is configured by combining a column selection signal generation circuit and a row selection signal generation circuit with a combination circuit, a storage circuit, or the like while maintaining the basic configuration even for applications where the charging electrode interval is predetermined. Obviously, it can be applied.

Table 3 shows a comparison table of the number of switches with the conventional one. It can be seen that as the number of secondary battery bodies increases, the effect of miniaturization becomes larger, and when the number of secondary battery bodies is 64 or more, it can be reduced to about 52 to 63%. Moreover, it changes also with (m, n), and the tendency of size reduction is recognized, so that m is large (the number of secondary battery rows increases).

FIG. 6 is a detailed block diagram of the power supply apparatus according to the second embodiment, and FIG. 7 is a circuit diagram thereof. The overall configuration is the same as in the first embodiment. The difference is that the selectors 17A-17D constituting the column selection multiplexer unit 17 (broken line portion) each constitute a 4 × 1 multiplexer, and the output lines (row signal lines) YD3-0 of the four multiplexers are upper row multiplexers. 18H, connected to the input of the lower row multiplexer 18L. Similarly to the above, in order to secure a charging path for the uppermost electrode terminal BP, the selector 17D (column multiplexer) has a 5 × 2 multiplexer having the terminal BP as an additional input and the row signal line YD4 as an additional output terminal. It has become. In FIG. 7, the row switch selection signal of the row switch SWH4 uses the (100) decode output signal YSH4 of the upper row address decoder 16H.

In this embodiment, a charging path between electrode terminals in the same secondary battery row cannot be formed, but a charging path between arbitrary electrode terminals between different secondary battery rows can be formed. It is suitable for charging while monitoring relative variations and fluctuations between secondary battery arrays.

FIG. 8 shows a detailed block diagram of a power supply apparatus according to the third embodiment, and FIG. 9 shows a circuit diagram thereof. The column selection multiplexer unit 17 (broken line portion) is configured by wire OR connection of the data lines of the selectors 17A-17D, and the row selection multiplexer unit 18 receives the row signal line YD connected by the wired OR connection. The upper row selection multiplexer 18H and the lower row selection multiplexer 18L. In the following, points different from the previous embodiment will be mainly described.

Unlike the first and second embodiments, the column selection signal generation circuit 15 includes a column address decoder 15D (2 × 4 decoder) that generates column switch selection signals XS3 to XS0 from 2-bit column address signals XA1 and XA0 and a driver circuit 20. Become. The row selection signal generation circuit 16 (dotted line portion) includes an upper row address decoder 16H (3 × 8 decoder), a lower row address decoder 16L (2 × 4 decoder), and driver circuits 21 and 22 as in the previous embodiment. The upper row switch selection signal YSH and the lower row switch selection signal YSL are output. In the column selection multiplexer unit 17, each of the selectors 17 </ b> A to 17 </ b> D has the five electrode terminals of the secondary battery column connected to the data terminal and the other data terminal connected to the row signal lines YD <b> 0-4, and the column switch selection signal XS <b> 0. -XS3 is input to each selection control terminal. The row selection multiplexer unit 18 includes an upper row multiplexer 18H and a lower row multiplexer 18L, each of which receives the row signal line YD and uses the row switch selection signals YSH and YSL as selection control signals. The output terminals of the upper row and lower row multiplexers 18H and 18L are connected to the supply output terminal BVH and the supply input terminal BVL, respectively. The secondary battery body between the desired electrode terminals is charged along the reverse path as described above, and the voltage is read in the order described above.

In the circuit diagram of FIG. 9, SW4D, SW8D, SW12D, and SW16 are additional switches for taking out the signal of the uppermost electrode terminal from the four secondary battery bodies connected in series in the secondary battery array. . Two column switches for selecting the uppermost electrode and the lowermost electrode are connected to a connection point between adjacent secondary battery columns. SW4D and SW4, SW8D and SW8, SW12 and SW12 correspond to this. The lowermost electrode terminal outputs (outputs of the column switches SW0, SW4, SW8, SW12) of the selectors 17A-17D are output to the row signal line YD0, and the uppermost electrode terminal outputs (outputs of the column switches SW4D, SW8D, SW12D, SW16) are Connected to the row signal line YD4.

In this embodiment, the lowest row selection switch SWH0 (not shown) of the secondary battery column of the upper row multiplexer 18H and the highest row selection switch SWL4 (not shown) of the secondary battery column of the lower row multiplexer 18L are provided. Since it is redundant, the row selection multiplexer section is composed of eight row switches. Therefore, the upper row address decoder input is 3 bits (YAH2-0), and YSH4 (100 decode output) -YSH1 (001 decode output) is used as the upper row switch selection signal.

Table 4 shows a truth table showing the relationship between the set column address and the row address for each electrode terminal number. Note that this is not a representation of the actual set address combination. The same applies to the truth table shown below. The shaded area in the table corresponds to the set address of the uppermost electrode terminal of each secondary battery column. Thus, when selecting the highest electrode position of the same secondary battery column, the 2-bit column address is controlled so as not to change the column address. (Not shown in the column selection signal generation circuit 15). For example, in the case of terminal number 4, the column address (XA1, XA0) is normally incremented to (01), but in this case, the previous state (00) is retained and only the upper row address YAH2-0 (100 Increment to).

In this embodiment, charging between desired electrode terminals in the secondary battery array is possible, and the entire secondary battery can be charged while sequentially scanning the secondary battery array. It is also useful as a power supply device for a secondary storage battery in which different types of secondary batteries are connected in series. In addition, the number of control signal lines, particularly the column switch selection signal lines is small, the addressing circuit is simple, and there is an effect that it can be formed compactly.

FIG. 10 is a circuit diagram illustrating a fourth embodiment in which the secondary battery body, the column switch, and the row switch are arranged and mounted in a matrix in the power supply device circuit according to the third embodiment. 34 (one-dot chain line portion) is a block in which the secondary storage battery 10 and the column selection multiplexer unit 17 are integrated. The secondary battery body unit 33 (broken line portion) includes a secondary battery body and a column switch having one end connected to a positive electrode terminal (or negative electrode terminal). The secondary battery body units are connected in series to form a secondary battery body unit row, and the secondary battery body unit row is provided side by side in the row direction. And each adjacent secondary battery body unit row | line | column is connected in series by the return | turnback wiring pattern. In this case, there is an effect that the secondary battery is configured and mounted in a memory shape, and the circuit configuration can be simplified and downsized.

Example 5 is shown in FIG. In the present embodiment, unlike the fourth embodiment, adjacent secondary battery body unit rows are arranged in parallel in a substantially antisymmetric manner in the row direction. That is, the secondary battery arrays are alternately arranged upside down, and adjacent secondary battery arrays are connected by a short wiring pattern. The row selection signal generation circuit 16 includes a two's complement generation circuit (not shown) of the upper row address signal YAH and the lower row address signal YAL. The upper row address decoder 16H and the lower row address decoder 16L are odd secondary When a secondary battery column having an odd column address is selected by the battery column selection signal OD / EVN, the complement output of a 2's complement generation circuit (not shown) is used as an upper row and lower row address signal, thereby allowing adjacent secondary batteries The row address arrangement order is reversed between columns. The odd-numbered secondary battery column selection signal OD / EVN may use the least significant bit XA0 of the column address.

Table 5 shows the relationship between the set column address and the row address with respect to the electrode terminal number. In the odd address column, the complement row address in the table is adopted. As described above, the setting address of the uppermost electrode terminal in the secondary battery column does not change the column address but only the row address. In this embodiment, the wiring pattern length for connecting the secondary battery rows can be shortened, and the wiring resistance value between the secondary battery rows can be reduced and the size can be reduced.

A row signal generating circuit showing the sixth embodiment is shown in FIG. The row selection signal generation circuit 16 includes an upper row address decoder 16H, a lower row address decoder 16L, an adder 42, an increment address setting register 41, a lower row address setting register 40, and driver circuits 21 and 22.
A lower row address YAL is set in the lower row address setting register 40, and an increment value YAD of the positive electrode terminal address with respect to the negative electrode terminal address to be charged, that is, the number of secondary battery bodies is set in the incremental address setting register 41. The adder 42 outputs the addition value of both address values as the upper row address YAH. The row selection signal generation circuit 16 can be applied to the above-described embodiment by appropriately changing the function and effect without departing from the function and effect thereof.

FIG. 13 shows a second basic configuration of the power supply device according to the present invention. The difference from the first basic configuration (FIG. 1) described above is that the roles of the row and column switches are reversed, and the electrode terminals of the respective secondary battery columns are connected to the column signal lines via the desired row switches. The signal line is connected to the input terminal of the column selection multiplexer unit for input / output control.
In the power supply device 50, the selection switch switching circuit 11 (one-dot chain line portion) includes a matrix type switch portion 14 (broken line portion), a column selection signal generation circuit 35, and a row selection signal generation circuit 36, each composed of a row switch and a column switch. Consists of The row selection signal generation circuit 36 is a decoder circuit that decodes n row address signals YA to generate 2 ⁿ row switch selection signals YS. On the other hand, the column selection signal generation circuit 35 decodes the m upper column address signals XAH indicating the positive electrode terminal positions and the m lower column address signals XAL indicating the negative electrode terminal positions, and 2 ^m lines each. An upper column switch selection signal XSH and a lower column switch selection signal XSL are generated.

The matrix switch unit 14 includes a row selection multiplexer unit 51 and a column selection multiplexer unit 52. The row selection multiplexer 51, and a selection control signal to the row switch selection signal YS, is composed by 2 ^m pieces of 2 ⁿ × 1 multiplexers for receiving the electrode terminals of the 2 ⁿ the each secondary cell column, 2 ^m the Output line, that is, the column signal line XD is connected to the input of the column selection multiplexer unit 52. The column selection multiplexer unit 52 transmits an input terminal for inputting a column signal line XD, a selection control signal terminal for inputting an upper column switch selection signal XSH, and a lower column switch selection signal XSL, and upper and lower column signals. It has an output terminal. The output terminals are connected to a supply output terminal BVH and a supply input terminal BVL, respectively, thereby forming a charge / discharge path.

FIG. 14 is a circuit diagram showing a seventh embodiment based on the second basic configuration. The column selection signal generation circuit includes an upper row address decoder 35H and a lower row address decoder 35L, and generates upper column and lower column switch selection signals XSH and XSL, respectively. In the column selection multiplexer unit 52, the upper column multiplexer 52H and the lower column multiplexer 52L have the column signal lines XD3-0 as inputs and connect the outputs to the supply output terminal BVH and the supply input terminal BVL, respectively. In the block 51 (one-dot chain line portion) including the secondary storage battery 10 and the row selection multiplexer unit, one row multiplexer receives, for example, the electrode terminals of the secondary battery bodies BC1 to BC4 as row switches SW0 to SW3. , SW4D. The row switches SW4D, SW8D, SW12D, and SW16 driven by the row switch selection signal line YS4 are provided to secure a charging path for the uppermost electrode terminal of each secondary battery column. In this embodiment, a charging path is configured between electrode terminals in the same row (in units of 2 ⁿ battery body columns) between different secondary battery columns. As described above, the second basic configuration of the present invention is obtained by replacing the row and column control / data input / output relationships in the first basic configuration, and in accordance with the spirit of the present invention, the basic configuration described above. An embodiment corresponding to that for 1 is possible. In addition, the charging state of each secondary battery body can be set and monitored by performing calculation processing of the charging voltage and the reading voltage.

In the embodiments described so far, the column switch and the row switch can use semiconductor switching elements in addition to electromagnetic relays, for example, thyristors, GTO thyristors, IGBTs, bipolar transistors, MOSFETs, and the like. In particular, GTO thyristors and IGBTs that are self-extinguishing elements have the advantage of easy on / off switch control. In the basic configuration 1 of the present invention, the column switch (row switch) needs to be a bidirectional switch, but the row switch (column switch) is usually an upper row selection switch (upper column selection switch) and a lower row selection switch. Since the direction of current flow is determined by the (lower column selection switch), a unidirectional switch may be used. Here, the parentheses indicate the case of the basic configuration 2 of the present invention. As the unidirectional switch, the semiconductor switching element alone can be used.
In the case of the basic configuration 1, if the row switch (column switch in the case of the basic configuration 2) is also a bidirectional switch, as will be described later, if the power supply side that supplies the charging power can be regeneratively operated, The secondary battery body having a large current can be discharged and regenerated to the constant current generating circuit side, and as a result, the discharge energy can be used for charging other secondary battery bodies.

An example of a bidirectional switch is shown in FIG. Usually, since an IGBT element or a MOSFET does not have a reverse breakdown voltage characteristic, a diode that prevents energization in the reverse direction is connected in series. In the case of a reverse-blocking IGBT having reverse breakdown voltage characteristics, a diode is unnecessary, and therefore, there is an advantage that the conduction loss of the diode is small. 15A is a circuit in which thyristors CR1 and CR2 are connected in antiparallel, and FIG. 15B is an inverted circuit in which protective diodes D1 and D2 are connected in series to IGBT elements IG1 and IG2 that do not have reverse withstand voltage characteristics. A circuit connected in parallel (wiring shown by a broken line may be applied), FIG. 5C is a circuit in which IGBT elements IG3 and IG4 having reverse breakdown voltage characteristics are connected in reverse parallel, and FIG. A circuit in which NM2 is connected in series, FIG. 5E is a circuit in which PMOSs PM1 and PM2 are connected in series. Here, XSP and XSD represent gate control signal terminals, and BT and DT represent switch electrode terminals. In addition, a circuit in which a MOSFET connected in series and a protective diode are connected in antiparallel, or a MOSFET having a CMOS structure can be used, as in the bidirectional switch using the IGBT shown in FIG. It is necessary to select the voltage region to be used in consideration of the withstand voltage.

FIG. 16 shows an eighth embodiment in which the IGBT circuit switch shown in FIG. 15C is applied to the fourth embodiment (FIG. 10). The column selection switch control signals XSP and XSD (signal lines are indicated by dotted lines) are generated by the column address decoder 15D, and the upper row and lower row selection switch control signals YSH and YSL (signal lines are indicated by dotted lines) are: They are generated by the upper row address decoder 16H and the lower row address decoder 16L, respectively. In this case, in addition to the column switch, the row switch is also composed of both switches, so that a power regeneration operation is possible between the external power supply (not shown) on the charging circuit 12 side and the secondary storage battery 10. In the case of only charging control, the row switches SWH4-1 and SWL3-0 may be unidirectional switches. The battery voltage monitoring amplifier 13 is connected to the output supply terminal BVH and the input supply terminal BVL of the constant current generating circuit, and charging or discharging is performed while monitoring the charging voltage.

FIG. 17 showing the ninth embodiment is obtained by applying the thyristor circuit switch shown in FIG. 15A to the fourth embodiment (FIG. 10).
The constant current generating circuit 12 includes a well-known step-down chopper circuit or step-up chopper circuit. FIG. 18 shows an example of a step-up chopper circuit. A closed circuit including an external power supply Ed, an inductance L1, and an IGBT (IG5), a diode D3 and a capacitor C1 connected in series between the collector and emitter of the IGBT (IG5). The connection point between the cathode terminal of the diode D3 and the capacitor C1 is the supply output terminal BVH, and the other terminal of the capacitor C1 is the supply input terminal BVL.

When the switch IG5 is turned on, a current flows through the closed circuit of Ed-L1-IG5, and energy is stored in the inductance L1. Next, when the switch is turned off when the current value reaches a constant value, the stored energy passes through the diode D3 to a load circuit composed of C1 and a load (not shown) to charge C1. By repeating this, the on-duty of the drive signal of the gate GE1 is changed to produce a boosting action.

In the example described above, both the voltage and current are irreversible in one direction, but if you use a reversible chopper that has been expanded to handle changes in the direction of voltage and current flow, in addition to the powering (charging) mode, The regeneration mode (returning power from the secondary battery to the external power supply Ed) becomes possible. FIG. 19 shows an example of a current reversible chopper circuit. This current reversible chopper circuit is connected in series to an external power supply Ed, a closed circuit composed of two IGBTs (IG6, IG7) each having diodes D4, D5 connected in reverse, and a connection point of the two IGBTs. A load including an inductance L2 and a resistor R1 is provided, and an output terminal of the load is a supply output terminal BVH, and an emitter electrode terminal of the IGBT (IG7) is a supply input terminal BVL.

In this constant current generating circuit, a step-down chopper circuit is configured by the switch IG6 and the diode D5, and a charging (powering) mode in which power is supplied from an external power source to a load (secondary battery) is set. Further, a boost chopper circuit is configured by the switch IG7 and the diode D4, and a regenerative mode is entered in which the electromotive force of the load (secondary battery) is returned to the external power supply Ed. In this way, both the power supply current and the load current can be reversed immediately, and power can be transferred smoothly. For example, in the step-down chopper operation, that is, in the charging mode, the charging voltage is controlled by the on-duty of the driving signal for the gate GE2. It is self-evident that constant current / low voltage charging control is performed by adding a negative feedback circuit to change the on-duty. In addition, a voltage regulator IC or a DC-DC converter control IC with an external power transistor can be used as the constant current generating circuit.

  According to the present invention, in a charging circuit and a power supply device for a secondary battery configured by connecting a plurality of secondary battery bodies in series, charging and discharging control of an arbitrary secondary battery body can be performed with a small number of switches. Even charge, overvoltage / overcurrent charge prevention, overdischarge prevention, etc. can be realized. Therefore, reduction in circuit scale and cost reduction can be achieved. In addition, a two-dimensional array of secondary battery bodies and switches and circuit control similar to a semiconductor memory can be performed, and the circuit configuration can be simplified and made compact. At the same time, by changing the row size and the column size, the wiring / driving gate load can be minimized, thereby increasing the speed. Furthermore, by monitoring the voltage and current of the secondary battery body and measuring the variation and distribution of the charging state and the impedance of each secondary battery body, it is possible to perform detailed evaluation and failure analysis of battery operation. . Needless to say, the present invention can also be used as a power supply circuit capable of reading a voltage between arbitrary electrode terminals and extracting a divided voltage in a power storage element such as a solar battery in which unit cells or unit modules are connected in series.

9, 50 Power supply device 10 Secondary storage battery 10A-10D Secondary battery row BC1-BC16 Secondary battery body BP Secondary storage battery positive electrode terminal (uppermost electrode terminal)
BN secondary battery negative electrode terminal 11 selection switch switching circuit 12 constant current generation circuit 13 voltage monitoring amplifier 14 matrix type switch unit 15, 35 column selection signal generation circuit 15H upper address decoder (upper column address decoder)
15L Lower address decoder (lower column address decoder)
15D Column address decoder 35H Upper column address decoder 35L Lower column address decoder 16, 36 Row selection signal generation circuit 16H Upper row address decoder 16L Lower row address decoder 17, 52 Column selection multiplexer unit 52H Upper column multiplexer 52L Lower column multiplexer 17A -17D selector 18, 51 row selection multiplexer unit 18H upper row multiplexer 18L lower row multiplexer 19 2-input OR logic gate circuit 20, 21, 22 driver circuit SW0-SW16, SW4D, SW8D, SW12D column switch (row switch)
SWH0 to SWH4 Upper row switches SWL0 to SWL3 Lower row switches 40 Lower row address setting register 41 Increment address setting register 42 Adder

Claims (16)

A secondary storage battery comprising a plurality of secondary battery bodies each having a positive electrode terminal and a negative electrode terminal connected in series; a supply output terminal; a constant current generation circuit for charging the secondary battery body from a supply input terminal; A selection switch switching circuit that individually forms a charging path between the supply output terminal, the supply input terminal, and the secondary battery body;
The address specifying the electrode terminal position of the secondary battery body includes a column address designating a secondary battery array divided into secondary battery bodies, and an electrode terminal position of the secondary battery body in the secondary battery array. Consists of a specified line address,
The selection switch switching circuit is composed of a matrix type switch unit composed of a two-dimensional selection switch of a column switch and a row switch, a column selection signal generation circuit, and a row selection signal generation circuit,
The column selection signal generation circuit generates a column switch selection signal from a column address signal that specifies the position of the positive electrode and / or the negative electrode terminal to be charged,
The row selection signal generation circuit generates an upper row and lower row switch selection signal from an upper row address signal and a lower row address signal that respectively specify the positions of the positive electrode terminal and the negative electrode terminal to be charged. Become
The matrix type switch part is
A column selection multiplexer unit including a plurality of column multiplexers, each of which includes the column switch group, wherein the electrode terminals of each of the secondary battery columns are input and the column switch selection signal is a selection control signal;
An output line of the column selection multiplexer unit is used as an input, and is selected by the upper row and lower row switch selection signals. The row selection multiplexer unit has signal terminals of the upper row and lower row switches as output terminals, respectively.
The power supply apparatus, wherein the output terminals of the row selection multiplexer unit are connected to the supply output terminal and the supply input terminal, respectively. A secondary storage battery comprising a plurality of secondary battery bodies each having a positive electrode terminal and a negative electrode terminal connected in series; a supply output terminal; a constant current generation circuit for charging the secondary battery body from a supply input terminal; A selection switch switching circuit for individually forming a charging path between the supply output terminal, the supply input terminal and the secondary battery body,
The address specifying the electrode terminal position of the secondary battery body includes a column address designating a secondary battery array divided into secondary battery bodies, and an electrode terminal position of the secondary battery body in the secondary battery array. Consists of a specified line address,
The selection switch switching circuit is composed of a matrix type switch unit composed of a two-dimensional selection switch of a column switch and a row switch, a column selection signal generation circuit, and a row selection signal generation circuit,
The column selection signal generation circuit decodes upper and lower address signals that respectively specify a positive electrode terminal and a negative electrode terminal position of the secondary battery body to be charged, an upper address decoder, a lower address decoder;
An OR logic gate circuit that generates a column switch selection signal by taking the logical sum of the outputs of the upper address decoder and the lower address decoder,
The row selection signal generation circuit decodes the upper row and lower row address signals that specify the positions of the positive electrode terminal and the negative electrode terminal of the secondary battery body to be charged, and the upper row and lower row switch selection signals, respectively. It consists of an upper row address decoder and a lower row address decoder that generate
The matrix type switch part is
A column selection multiplexer unit including a plurality of column multiplexers each including a group of column switches, each having an electrode terminal having an equal row address value of each secondary battery column as an input and the column switch selection signal as a selection control signal. When,
An output line of the column selection multiplexer unit is used as an input, and the upper row and lower row switch selection signals are used as selection control signals.The row selection multiplexer unit includes an upper row multiplexer and a lower row multiplexer, respectively.
The power supply apparatus, wherein output terminals of the upper row and lower row multiplexers are connected to the supply output terminal and the supply input terminal, respectively. The matrix type switch part is
A column selection multiplexer unit including a plurality of multiplexers each including a group of column switches, the electrode terminals having equal column address values of the secondary battery columns being input and the column switch selection signal being a selection control signal;
An output line of the column selection multiplexer unit is used as an input, and the upper row and lower row switch selection signals are used as selection control signals.The row selection multiplexer unit includes upper row and lower row multiplexers, respectively.
The power supply apparatus according to claim 2, wherein output terminals of the upper row and lower row multiplexers are connected to the supply output terminal and the supply input terminal, respectively. The column selection signal generation circuit comprises an address decoder that generates a column switch selection signal by decoding a column address signal that specifies a positive electrode terminal and a negative electrode terminal position of the secondary battery body to be charged,
The row selection signal generation circuit decodes the upper row and lower row address signals that specify the positions of the positive electrode terminal and the negative electrode terminal of the secondary battery body to be charged, and selects the upper row and lower row switches, respectively. It consists of an upper row address decoder and a lower row address decoder that output signals,
The matrix type switch part is
A column selection multiplexer unit configured by a plurality of column multiplexers each including the column switch group, each electrode terminal of the secondary battery column being an input and the column switch selection signal being a selection control signal;
An output line of the column selection multiplexer unit is used as an input, and the upper row and lower row switch selection signals are respectively selected control signals.The row selection multiplexer unit includes upper row and lower row multiplexers.
The power supply apparatus according to claim 1, wherein output terminals of the upper row and lower row multiplexers are connected to the supply output terminal and the supply input terminal, respectively. The secondary storage battery and the column selection multiplexer unit include a secondary battery body unit including a secondary battery body and a column switch having one end connected to a positive electrode terminal or a negative electrode terminal. 5. The power supply device according to claim 1, wherein the battery unit unit row is configured and the secondary battery unit unit row is provided side by side in a row direction. The secondary storage battery and the column selection multiplexer unit include a secondary battery body unit including a secondary battery body and a column switch having one end connected to a positive electrode terminal or a negative electrode terminal. A battery unit unit row,
Adjacent secondary battery unit columns are arranged in parallel in a substantially antisymmetric manner in the column direction, and the row selection signal generation circuit is a complement generation circuit for the upper row address signal and lower row address signal. When the secondary battery column of the odd column address is selected, the output of the complement generation circuit is used as the upper row address signal and the lower row address signal, thereby reversing the row address arrangement order between the adjacent secondary battery columns. The power supply device according to claim 1, wherein the power supply device is a power supply device. The row selection signal generation circuit includes: a lower row address setting register; an increment row address setting register that specifies an increment value of an upper row address value with respect to a lower row address value; and an adder that adds storage values of both registers; With
7. The power supply device according to claim 1, wherein the output of the adder is an upper row address signal. A secondary storage battery comprising a plurality of secondary battery bodies each having a positive electrode terminal and a negative electrode terminal connected in series; a supply output terminal; a constant current generation circuit for charging the secondary battery body from a supply input terminal; A selection switch switching circuit for individually forming a charging path between the supply output terminal, the supply input terminal and the secondary battery body,
The address specifying the electrode terminal position of the secondary battery body includes a column address designating a secondary battery array divided into secondary battery bodies, and an electrode terminal position of the secondary battery body in the secondary battery array. Consists of a specified line address,
The selection switch switching circuit is composed of a matrix type switch unit composed of a two-dimensional selection switch of a column switch and a row switch, a column selection signal generation circuit, and a row selection signal generation circuit,
The row selection signal generation circuit generates a row switch selection signal from the row address signal to be charged,
The column selection signal generation circuit generates an upper column and a lower column switch selection signal from an upper column address signal and a lower column address signal that specify positions of a positive electrode terminal and a negative electrode terminal to be charged, respectively. And
The matrix type switch part is
A row selection multiplexer unit configured by a plurality of row multiplexers each including a row switch group, wherein the electrode terminals of the secondary battery columns are input and the row switch selection signal is a selection control signal;
A column selection multiplexer having an output terminal for outputting a signal of the selected upper column and lower column switch, using the output line of the row selection multiplexer unit as an input, and using the upper column and lower column switch selection signal as a selection control signal. Consists of parts
The power supply apparatus, wherein the output terminal of the column selection multiplexer unit is connected to the supply output terminal and the supply input terminal, respectively. The column selection signal generation circuit includes an upper column address decoder and a lower column address decoder that generate the upper column and lower column switch selection signals, respectively, with the upper column address signal and the lower column address signal as inputs.
The column selection multiplexer unit includes an upper column and a lower column multiplexer, each having an output line of the row selection multiplexer unit as an input and the upper column and lower column switch selection signals as selection control signals.
9. The power supply apparatus according to claim 8, wherein output terminals of the upper column and lower column multiplexers are connected to the supply output terminal and the supply input terminal, respectively. 10. The power supply device according to claim 1, wherein the column switch and the row switch of the matrix type switch unit are configured by any of a thyristor, a GTO thyristor, an IGBT, a MOSFET, and a bipolar transistor. The power supply apparatus according to claim 10, wherein the column switch and / or the row switch of the matrix type switch unit are bidirectional switches. The power supply apparatus according to claim 1, wherein the constant current generation circuit includes a step-down chopper circuit, a step-up chopper circuit, or a reversible chopper circuit. The constant current generating circuit includes at least an external power source, a closed circuit including an inductance and a chopper switch, and a diode and a capacitor connected in series to both ends of the chopper switch, and a connection point between the inductance and the chopper switch. The anode of the diode is connected, the capacitor is connected to the cathode of the diode and the other end of the chopper switch, and the positive electrode terminal and the negative electrode terminal of the capacitor are connected to the supply output terminal and the supply input terminal, respectively. The power supply apparatus according to claim 12. The constant current generating circuit includes at least an external power source, a closed circuit including two switches each having a diode reversely connected in parallel, and a load including an inductance and a resistor connected in series to a connection point of the switches,
The power supply apparatus according to claim 12, wherein an output terminal of the load is connected to the supply output terminal, and a connection point between the negative terminal of the external power supply and the switch is connected to the supply input terminal. The power supply device according to claim 13 or 14, wherein the switch includes an IGBT element. 16. The power supply device according to claim 1, wherein an input / output terminal of a voltage amplifier for monitoring a power supply voltage is connected to the supply output terminal and the supply input terminal.

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