JP2014197265A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device that efficiently executes read processing of a slow speed and large capacity flash memory on the basis of an effective flag to be set for each one page unit of cache.SOLUTION: A semiconductor memory device according to an embodiment comprises: a CPU; a slow speed and large capacity flash memory; a cache memory storing a part of data stored in the flash memory; a host interface controlling the access of the cache memory; and control means. The control means has a flag register in which the CPU sets a flag indicating an effective bit when data from a host or data from the flash memory is written, and otherwise indicating a non-effective bit, and rewrites the content of the cache memory only in a sector in which the content of the flag register indicates the non-effective bit when data of each page is copied from the flash memory to the cache memory. Rewritten data in a plurality of pages of the cache memory after completing of the copy is written back to the flash memory.

Description

Embodiments described herein relate generally to a semiconductor memory device using a low-speed and large-capacity flash memory.

Currently, most commonly sold SSDs (semiconductor disks) use NAND flash memory as a storage medium. Further, the structure is such that a NAND flash memory chip and a NAND flash controller (LSI) are mounted on a substrate. Such SSD products for the general market are mass-produced, and by purchasing a large number of memory chips from a chip manufacturer, the unit price of the chip can be kept low, and the price per product can be kept low. In addition, the performance (speed) can be maximized by directly controlling the memory chip.

However, in the case of a small quantity product with a special specification for a specific use or a specific customer, the number of purchased memory chips is also small and the price is high. In addition, since memory chips are often reborn to products with new specifications (design rules), the device (= product itself) must be renewed each time, and the ratio of development costs to the product unit price increases. Has the disadvantage of becoming expensive.

In the case of such a product that is inevitably produced in a small amount, a flash memory card represented by a compact flash (registered trademark) memory (hereinafter abbreviated as a CF memory) is effective. The interface of the flash memory card is determined by each standard and is not related to the manufacturer or capacity of the NAND flash chip used internally, so the capacity may increase. Can continue to be used as almost the same compatible product. Since card manufacturers purchase and produce NAND memory chips in large quantities, if a CF memory card is used, there is a possibility that a semiconductor memory device can be manufactured at a cost as low as an SSD.

CF memory is non-volatile that retains its stored contents even when power is cut off, and can repeatedly write and erase data, has no vibration and noise, and has low power consumption. It is widely used as a storage device. In general, NAND flash memory is used for CF memory and SD (Secure Digital) memory.

Data writing or erasing in the NAND flash memory is performed in units of blocks constituting the flash memory. In addition, when data written in the flash memory is rewritten, the previous data is erased in units of blocks and new data is written. However, the NAND flash memory has a lifetime in terms of characteristics, and there is an upper limit on the number of times of writing. Thus, inefficient useless writing or erasing contributes to shortening the lifetime of the flash memory.

Further, the flash memory card has a built-in NAND controller, and the NAND controller performs all NAND control. In general, the performance of a NAND controller is slow, and when a storage device is configured using a flash memory card, it is almost impossible to achieve the performance equivalent to that of an SSD unless special efforts are made.

For example, in a system that uses a CF memory alone or a flash memory device (SSD) that uses a CF memory, as shown in FIG. 9, a host or SSD system (CF memory control unit in the SSD) A and a CF memory B Are connected via the PATA interface C. The CF memory B includes a NAND controller B1 and a NAND chip B2. In such a configuration, when accessing data stored in the NAND chip B2 from the host A, the host A issues an access command to the NAND controller B1, the NAND controller B1 accesses the NAND chip B2, and the result is displayed on the host A. The operation to output to. In such a configuration, there is a problem that the processing speed of the NAND controller B1 is extremely slow compared to the host A.

That is, in a system in which the CF memory B is simply arranged in the necessary capacity and the logical address is fixed and assigned to the CF memory B, the performance degradation is noticeable. In particular, when the data stored in the CF memory B is rewritten from the host A, the data is once read from the NAND chip B2 in the CF memory B, overwritten only on the sector having the rewritten data, and the erased NAND chip B2 The process of writing back to is performed. In this operation, even when only one sector is rewritten, the entire block must be rewritten due to the characteristics of the NAND chip B2. As a result, not only is the processing slow, but it also leads to a fatal defect that the life of the NAND chip B2 is reduced due to a large amount of block erasure.

On the other hand, in the technical field of cache memory, when data is rewritten in units of 1 byte, it is rewritten after erasing in units of physical blocks. And the number of rewrites increases. Paying attention to the technical problem, when rewriting data is written, the exclusive OR of the rewriting data and the data at the position to be rewritten in the first area is taken, and further, the exclusive OR data and the second data are taken. The process of taking an exclusive OR with the data of the area in the area is sequentially repeated, and in the process, when the data of the position of the area is the initial value, the exclusive obtained previously to the position of the area There is a method of writing logical sum data.

JP-A-2005-38518

  The problem to be solved by the present invention is a system using a low-speed and large-capacity flash memory, and a write-back process and garbage collection for the flash memory using the contents of a flag set for each sector of the cache memory. It is an object of the present invention to provide a semiconductor memory device capable of executing processing efficiently.

A semiconductor memory device according to an embodiment stores a CPU, a low-speed, large-capacity flash memory, a part of data stored in the flash memory, and a cache accessed in units of pages composed of a plurality of sectors A host interface for holding memory and data transferred by a write command from an external host and controlling access to the cache memory; and a flag set for each sector of the cache memory, the host A flag register that is set by the CPU with a valid bit when the data from the flash memory or the data from the flash memory is written, and a flag indicating a non-valid bit when there is no such data, Each page of data from memory to the cache memory Control means for rewriting the contents of the cache memory only to sectors in which the contents of the flag register indicate the invalid bit when copying, and a plurality of pages of the cache memory after the copying is completed. The rewritten data is written back to the flash memory.

The semiconductor memory device according to the embodiment stores a CPU, a low-speed, large-capacity flash memory, and a part of data stored in the flash memory, and is accessed in units of pages composed of a plurality of sectors. A cache memory and a flag set for each sector of the cache memory, the flag register having a flag indicating an invalid bit when the CPU determines to execute garbage collection, Control means for writing to the allocated area of the cache memory based on the invalid bit of the flag register when copying valid page data from the flash memory to the cache memory, and the copying is completed After the rewritten data of multiple pages of the cache memory after Characterized in that it is written back to the serial flash memory.

  According to the present invention, it is possible to reduce as much as possible the read operation of the flash memory that occurs when the contents of the flash memory are partially rewritten during a write command. Further, only the valid data is collected in one place, and a garbage collection operation capable of generating a reproducible sector area containing only garbage (garbage) can be performed efficiently.

1 is a diagram illustrating a semiconductor memory device and a system block according to an embodiment. It is a figure which shows the structure of the cache memory which has D flag for the sector unit which concerns on embodiment. It is a figure which shows the information of each page of a cache memory. It is a figure which shows the mechanism which rewrites the data from CF memory by D flag which concerns on embodiment to cache memory. 5 is a flowchart showing the operation of FIG. It is a figure which shows a garbage collection process. It is a figure which shows the mechanism which copies the data from CF memory to the cache memory by the garbage collection process by D flag which concerns on embodiment. 8 is a flowchart showing the operation of FIG. It is a figure which shows the connection structure of the conventional host and CF memory.

Hereinafter, a semiconductor memory device according to an embodiment of the present invention will be described with reference to the drawings.
First, a description will be given of reducing as much as possible the read operation of the flash memory that occurs when a part of the contents of the flash memory is rewritten at the time of a write command.

  FIG. 1 is a diagram illustrating a semiconductor memory device according to an embodiment and a system block using the device. In FIG. 2, a semiconductor memory device 100 includes a CPU 110, a CPU bus 120, a flash memory (hereinafter referred to as a CF memory because a CF memory is used) 130, a CF controller 140, a cache memory (DRAM) 150, A cache controller 160, a host interface 170, a local bus 180, a RAM 190, and a ROM 195 are included. The host interface 170 of the semiconductor memory device 100 is connected to the host bus 210 of the external host 200. The CF memory 130 constitutes a main memory and is a low-speed and large-capacity memory. The cache memory 150 is a high-speed, small-capacity memory that stores a copy of a part of the data stored in the CF memory 130.

  A CPU 110, a CF controller 140, a RAM 190, a ROM 195, and the like are connected to the CPU bus 120 of the semiconductor memory device 100. In addition, a cache controller 160, a host interface 170, a CF controller 140, and the like are connected to the local bus 180. The CPU bus 120 and the local bus 180 are connected directly and via the CF controller 140. The CPU 110 can access the CF memory 130 via the CF controller 140. Further, the CPU 110 can access the cache memory 150 via the cache controller 160 or the CF controller 140 -cache controller 160. The RAM 190 and the ROM 195 are memories serving as a storage area for programs such as the OS, firmware, and applications, and a work area during execution.

  A host bus 210 that connects the host 200 and the host interface 170 of the semiconductor memory device 100 is, for example, a SCSI bus or a SATA bus. The host interface 170 controls command and data transfer with the host 200 via the host bus 210. Data to be written from the host 200 or data to be read from the host 200 is temporarily stored in the cache memory 150. That is, when a read / write command is executed from the host 200 to the semiconductor memory device 100, data is exchanged with the cache memory 150 via the host interface 170 and the cache controller 160.

  When executing a write command from the host 200, the write data sent from the host 200 is held by the host interface 170 and then transferred to the cache memory 150. The cache memory 150 is managed in units of pages. For example, one page = 64 sectors. Thereafter, the write data in the cache memory 150 is transferred to the CF memory 130. The minimum size of transfer between the cache memory 150 and the CF memory 130 is, for example, one page.

  When executing a read command from the host 200, depending on whether the cache memory 150 is hit or missed, the write data by the write command executed for the previous write cache or the CF memory 130 to the cache memory 150 The data transferred to the host 200 is transferred to the host 200. The CF memory 140 is controlled by the CF controller 140. The CPU 110 controls the entire CF controller 140, host interface 170, cache controller 160, and the like.

(Cache memory structure)
Next, the structure of the cache memory 150 will be described. The cache memory 150 generally has a capacity of several megabytes (MB) to several tens of megabytes. Here, as shown in FIG. 2, the capacity of the cache memory 150 is assumed to be 64 MB, for example, and one page = 64 sectors = 32 KB (kilobytes). Therefore, the cache memory 150 is composed of 64 MB ÷ 32 KB = 2048 pages.
As each page information of the cache memory 150, as shown in FIG.
(1) Logical address (2) Valid flag “V” (1 bit)
(3) D flag (64 bits)
(4) It has four types of values called LRU information. The four values may be stored anywhere, but may be stored on the RAM 190 in the CPU space, for example. These four values are stored as one set (one page) for 2048 pages.

(1) A logical address is a logical address corresponding to a page, and has the same meaning as an address specified by a read / write command from the host 200. The value has the top address of each 64 sectors, for example, 0x000000, 0x000040, 0x000080,.
(2) The valid flag “V” is a flag indicating whether or not the page is valid. If it is valid, V = "1", and if invalid, V = "0".
(3) The D flag is a flag indicating whether or not there is valid data in each sector in the page. In this example, since 1 page = 64 sectors, the D flag is 64 bits.
(4) LRU-U / LRU-D decides which page of 2048 pages is to be ejected when there is no more free page in the cache memory 150 and there is a need to purge the page. Information. LRU is a least recently used algorithm. This algorithm is one of the methods for determining the order of eviction, in which eviction starts from the “oldest used” page. As a value, one value is composed of two values from 0 to 2047. For example, it is assumed that a certain page (page number M) is currently the Nth accessed page. The LRU information is a pointer value, and LRU-U indicates the page number of a page that is one higher than that of itself (newly accessed). LRU-D indicates a page one level lower than itself. In this way, each page is a daisy chain in two directions.

  Here, if the page number M in the cache memory 150 is accessed, this entry is moved to the top because it has been used most recently. The movement process to the top is separated from the position of the currently connected rosary and connected to the top end. The cut N-1 and N + 1 must be reconnected, but the page number of these can be found by looking at the two pointers (LRU-U / LRU-D).

  Whether the cache memory 150 is hit or missed can be determined by checking whether or not there is a page having the same address as that specified by the read / write command and the valid flag “V” is “1”. Good.

Next, a write operation from the host 200 to the semiconductor memory device 100 will be described.
When a write command is issued from the host 200 to the host interface 170 of the semiconductor memory device 100, the host interface 170 interrupts the CPU 110 to notify that the write command has been received and the contents of the command. The CPU 110 checks whether the write address is hit in the cache memory 150, and if it is hit, sets the host interface 170 to transfer the write data to the address position of the corresponding cache memory 150, and writes the write data. Perform a write operation.

  If the write cache for the cache memory 150 is a miss (cache miss), a new area for one page is allocated to the cache memory 150, and write data that hits the address position of the new area of the cache memory 150 is assigned. The host interface 170 is set to transfer, and the write data write operation is executed. If there is no empty page in the cache memory 150, the most recently accessed page is written back to the CF memory 130 (= write back) by the cache eviction algorithm (here, the LRU algorithm), and the empty page is deleted. Secure.

(Write back)
The CPU 110 performs write back from the cache memory 150 to the CF memory 130 in units of pages. First, the CPU 110 checks whether or not there is a bit (sector) that is “0” in the D flag register of each page of the cache memory 150 shown in FIG. If there is a sector “0”, data from the corresponding sector of the CF memory 130 must be read into the sector of the cache memory 150.

(Operation of CF memory / cache memory using D flag)
When reading data from the CF memory 130, the CPU 110 must transfer the data avoiding the sector in which the D flag of the cache memory 150 is “1”. That is, the read operation is executed only for the sector in which the D flag of the cache memory 150 is “0” (valid sector). However, if there is a hit page, there is a possibility that the write data is sparsely present, in other words, there is a possibility that “1” and “0” are randomly mixed in the D flag. In such a case, selecting only the sector “0” one by one and performing the read operation on the corresponding CF memory 130 is too complicated in terms of processing, and the overhead of the CF memory 130 is large when actually performing the operation. Too practical performance cannot be achieved.

  Therefore, in the embodiment, the cache memory 150 is provided with a mechanism that operates as if data is read only from the sector having the D flag of “0”. Here, the cache memory 150 is described as a general DRAM as an example, but the same principle applies to higher speed SDRAM, DDR, and the like.

  FIG. 4 is a diagram showing a mechanism for rewriting data from the CF memory 130 to the cache memory 150 by the D flag register. In this mechanism, a D flag register (64-bit shift register) 300 is provided in the cache controller 160. The D flag register 300 shifts bit by bit in accordance with the data transfer for each sector from the CF memory 130 to the cache memory 150. The cache controller 160 outputs DRAM control signals such as addresses and R / W control signals to the DRAM 330 in order to control the DRAM 330 constituting the cache memory 150. Data signals of the DRAM 330 are input / output from the CF memory 130 or the host interface 170. Various types of DRAM 330 are sold for each manufacturer, but each DRAM has a DM (Input Data Mask) signal terminal which is a signal end of write protection. However, although the signal name is different or the form is different depending on the manufacturer and the type of memory, the principle is the same.

  Therefore, in the embodiment, the output terminal of the D flag register 300 and the DM terminal of the DRAM 330 are connected. When this DM signal “H” = “1” is input, the DRAM 330 can perform write protection (write prohibition). The embodiment uses this principle to realize a mechanism in which data can be rewritten only for an effective sector whose value of the D flag register 300 is “0”. On the other hand, the sector whose value in the D flag register 300 is “1” is write-protected and the contents of the DRAM 330 are held as they are.

  Next, the operation of FIG. 4 will be described using the flowchart of FIG. First, the CPU 110 issues a command to the CF controller 140 to read data for one page (64 sectors) from the CF memory 130 (S100). That is, it is not necessary to frequently make read requests to the CF memory 130 in units of sectors depending on the state of the cache memory (invalid sectors). On the other hand, the CPU 110 sets the value (64 bits) of the D flag corresponding to one page of the cache to be read from the CF memory 130 in the D flag register 300 of the cache controller 160 (S110).

  The cache controller 160 performs a write operation on the DRAM 330 of the cache memory 150 every time read data is sent from the CF memory 130 one sector at a time. At the same time, the value of the D flag register 300 is linked to the transfer destination address. Is output to the DM terminal of the DRAM 330. The D flag register 300 shifts by 1 bit for each sector transfer. As a result, when the value of the D flag register 300 is “1”, the DRAM 330 can maintain the original data without being rewritten regardless of whether the data for one sector is transferred from the CF memory 130. it can. On the other hand, when the value of the D flag register 300 is “0”, data for one sector transferred from the CF memory 130 is written to the DRAM 330 (S120). Then, it is checked whether rewriting for one page from the CF memory 130 is completed (S130), and if not completed, S120 is repeatedly executed. After transferring the data for 64 sectors from the CF memory 130 to the DRAM 330 of the cache memory 150, the CPU 110 sets all the D flags of the write target page (64 sectors) of the cache memory 150 to “1”, The process ends (S140).

(Write back)
Write back from the cache memory 150 to the CF memory 130 is performed in units of pages. Generally, since the CF memory 130 performs erase / write in units of physical blocks, it is necessary to perform write back for the physical blocks. . If data is written to the CF memory 130 with a size different from the size of the physical block, data that cannot be rewritten is generated inside the CF memory 130, so that read-modify-write must be performed. Then, a large amount of data read / write back occurs between the NAND memories constituting the CF memory 130, and the performance of the CF memory 130 is greatly reduced due to overhead.

  Further, if one page of the cache memory 150 is made the same size as the physical block, the story becomes simple. However, if the page size of the cache memory 150 is made too large, the total number of pages decreases, and the probability of misses increases. As a result, the performance deteriorates, and the size needs to be determined after careful consideration.

Therefore, since the write back operation is performed in one physical block (for example, 2048 sectors = 32 pages), an area for one continuous physical block (here, 2048 sectors) must be secured on the CF memory 130 at all times. Don't be. Therefore, the following three types of address conversion tables corresponding to the addresses on the CF memory 130 and the cache memory 150 that has been written back are prepared.
(A) Logical-physical address conversion table (b) Physical-logical address conversion table (c) Valid page flag table

(A) The logical-physical address conversion table is a table necessary for normal write-back, and where the requested data is stored in the CF memory 130 when a read / write command is output from the host 200. This is a table for checking. The address specified by the read / write command is a logical address, and the corresponding physical address is obtained from this table.
(B) A physical-logical address conversion table is a table in which a logical address is obtained when an address (physical address) on the CF memory 130 is input. This is necessary for an operation called garbage collection.
(C) The valid page flag table corresponds to 1 bit per 64 sectors of the CF memory 130 and 2048 sectors of the CF memory per 4 bytes.

(Garbage collection)
Next, an efficient operation of garbage collection will be described.
When writing back in one physical block (for example, 32 pages (in 2048 sector units)), the data once written in the CF memory 130 is naturally rewritten someday. Then, old data (garbage: garbage) remains in the CF memory 130 in units of pages (64 sectors) of the cache memory 150. If this old data is left as it is, garbage will be scattered throughout the CF memory 130, and it will not be possible to secure 32 consecutive pages (2048 sectors) and write back will not be possible.

  FIG. 6 is a diagram illustrating an example of garbage generation on the CF memory 130. In the figure, one box represents data in page units, and each row represents data in one physical block unit. Also, the squares in the shaded area indicate pages (invalid data) where garbage has occurred. As a result, in the example of FIG. 6A, data of one physical block (for example, 2048 sectors) can be secured only in the first row block from the bottom and the fourth block from the bottom.

  Therefore, the CPU 110 that has determined such a situation, in each physical block in the CF memory 130, has a lot of garbage (in the example of FIG. 6A, the first row, the third row, the sixth row). ) Are extracted, and the CF controller 140 is read out a valid page (in the example of FIG. 6, symbols (a), (b),... (H)) in each of those physical blocks, and one physical block is read. A read operation is performed to collect the data in the cache memory 150. Thereafter, the CPU 110 instructs the CF controller 140 to write back the data for one physical block written in the cache memory 150 to the CF memory 130. As a result, as shown in FIG. 6B, the CF memory 130 stores data of one physical block in which valid pages are collected in the lowest block, and the first, third, and sixth rows. A reproducible area of one physical block (for example, 2048 sectors) containing only dust is generated in the block on the line. This block containing only dust can be overwritten with new block data at the next write-back. This operation completes garbage collection.

(Garbage collection operation using the D flag)
FIG. 7 shows an effective page of the CF memory 130 (reference numerals (a), (b),... (H) in FIG. 6) using the D flag register shown in FIG. A circuit for reading and writing to the cache memory 150 is shown.

  FIG. 8 is a flowchart showing the operation of the CPU 110, the CF controller 140, or the cache controller 160 in the garbage collection. When the CPU 110 determines that garbage collection is necessary, the CPU 110 searches the above-described valid page flag table and counts the number of bits of “1” (number of valid pages) every 4 bytes (= 32 pages). Perform 64 times (2048 sectors) and examine the part that contains a lot of garbage. That is, the number of bits having a value of “1” in 4 bytes is counted, and the portion where the number is small is checked. The fact that there is even one “1” bit in 4 bytes means that all other “0” bits are garbage. Therefore, when 4 bytes having a small number of “1” bits are found, the logical address of, for example, 64 sectors of the CF memory 130 corresponding to the “1” bit is obtained from the physical-logical address conversion table. When the logical addresses are obtained, all of them are once read into the cache memory 150 (S200).

  During this read operation, the CPU 110 sets a value of all “0” in the D flag register 300 (64 bits) shown in FIG. Then, for example, the 64 sectors of page (a) of the CF memory 130 shown in FIG. 6A are allocated to the cache memory 150, and the valid flag is set to “1” to instruct the CF controller 140 (S210). ). Then, the CF controller 140 writes the data of each sector read from the CF memory 130 in the allocated area of the DRAM 330 constituting the cache memory 150 in the manner of the write back operation (S220). At this time, since the values of the D flag register 300 of the cache controller 160 are all “0”, the write protection for the DRAM 330 is disabled. That is, a normal write operation is performed. The CF controller 140 performs the read operation from the CF memory 130 and the write operation to the cache memory 150 for 64 sectors of the page (a) (S230), and executes the move operation for one page. The CF controller 140 performs the same operation for other valid pages (pages (b), (c),... (G) in FIG. 6A) (S240, S250). Thereby, the data movement for one physical block is completed in the allocated area of the cache memory 150.

  Thereafter, when the CPU 110 issues a write back command to the CF controller 140, the CF controller 140 writes the data of the one physical block in the cache memory 150 back to the CF memory 130 (S260). As a result, the CF memory 130 transitions to the state of FIG. That is, as shown in FIG. 6B, the CF memory 130 stores data of one physical block in which valid pages are collected in the lowest block, and the first, third, and sixth rows. An area of one reproducible physical block (for example, 2048 sectors) containing only dust is generated in the eye block. Therefore, by using the circuit shown in FIG. 7, the operation is the same as when a write command without write data is sent from the host 200, and all processes can be simplified.

  The effect that can be expected here is the area where garbage collection is performed, for example, 2048 sector, where the garbage is increasing at present, and a large number of rewrites are generated by the write command from the host 200 in the vicinity. it is conceivable that. Then, the remaining valid page (64 sectors) is likely to be rewritten soon. If garbage collection is performed independently without using the D flag register 300, all of the current garbage can be removed, but if garbage collection is performed using the D flag register 300 as in the present embodiment, One page allocated this time is also filled with a write command later, and there is a greater possibility that it will not be necessary to read from the CF memory 130. This also improves the speed of garbage collection. Therefore, by using the D flag register 300, it is possible to increase the efficiency and speed of the write command execution. In addition, garbage collection can be simplified and made more efficient.

  As described above, according to the present embodiment, in the read operation of the flash memory at the time of the write command, the D flag is provided for each sector of the cache memory, and the sector of the cache memory to which the write data is transferred or the data read from the CF memory The D flag is set to “1” for the transferred cache memory sector so that it can be determined that valid data exists. When executing the write command, based on the D flag, if “1”, the write protection is applied, and the data from the CF memory is written only in the sector “0”, so that the rewritten data on the cache memory, Alternatively, only the data that existed in the past should exist. Then, the data is written back to the CF memory when all the pages have data. Thereby, the write operation of the DRAM constituting the cache memory can be reduced.

  In the garbage collection, even if the data of the valid page of the CF memory is moved to the cache memory and then written back, the D flag is set to “0” for the DRAM of the cache memory and the CF memory. Since the contents of the valid page can be copied to the cache memory, the operation is the same as when a write command without write data is sent from the host, and all processing can be simplified.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, changes, and combinations can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 100 ... Semiconductor memory device, 110 ... CPU, 120 ... CPU bus, 130 ... CF memory, 140 ... CF controller, 150 ... Cache memory, 160 ... Cache controller, 170 ... Host interface, 180 ... Local bus, 200 ... Host, 210 ... Host bus, 300 ... D flag register, 330 ... DRAM of cache memory,

Claims (4)

CPU,
Low-speed, large-capacity flash memory,
A cache memory that stores a part of the data stored in the flash memory and is accessed in units of pages composed of a plurality of sectors;
A host interface for holding data transferred by a write command from an external host and controlling access to the cache memory;
A flag set for each sector of the cache memory, in which the valid bit is written when the data from the host or the data from the flash memory is written, and the invalid bit when there is no such data And a flag register that is set by the CPU, and when copying the data of each page from the flash memory to the cache memory, only the sector in which the content of the flag register indicates the invalid bit A control means for rewriting the contents of the cache memory;
Comprising
A semiconductor memory device, wherein a plurality of pages of rewritten data in the cache memory after the copying is completed is written back to the flash memory. CPU,
Low-speed, large-capacity flash memory,
A cache memory that stores a part of the data stored in the flash memory and is accessed in units of pages composed of a plurality of sectors;
A flag that is set for each sector of the cache memory, and a flag register that sets a flag indicating an invalid bit when the CPU determines to execute garbage collection; Control means for writing to the allocated area of the cache memory based on the non-valid bit of the flag register when copying valid page data to the memory;
Comprising
A semiconductor memory device, wherein a plurality of pages of rewritten data in the cache memory after the copying is completed is written back to the flash memory.   The flag register is a shift register that shifts one bit every time one sector is transferred, and an output terminal of the flag register is connected to a write protection signal terminal of a RAM constituting the flash memory. The semiconductor memory device according to claim 1 or 2.   2. The semiconductor memory device according to claim 1, wherein when the flag indicating the valid bit is output from the flag register, the RAM is in write protection.

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