JP5762930B2 - Information processing apparatus and semiconductor memory device - Google Patents

Description

  Embodiments described herein relate generally to an information processing apparatus including a host device having a main memory and a semiconductor storage device having a nonvolatile semiconductor memory.

  There is a technology called UMA (Unified Memory Architecture) in which a single memory is shared among a plurality of arithmetic processors, such as a GPU (Graphical Processing Unit) in which a plurality of arithmetic processors are integrated. According to UMA, the memory cost can be reduced.

JP-A-10-269165

  An object of one embodiment of the present invention is to reduce the capacity of a buffer memory of a semiconductor memory device without increasing the interface bandwidth between the host device and the semiconductor memory device.

  According to one embodiment of the present invention, the information processing apparatus includes a host device and a semiconductor memory device. The host device separates a write request for the main memory and the semiconductor memory device into a write command and write data corresponding to the write command, outputs the write command to the semiconductor memory device, and stores the write data in the main memory A first control unit. The semiconductor storage device receives the write command transferred from the nonvolatile semiconductor memory and the host device, and stores the write data corresponding to the write command stored in the main memory when the write command is executed. And a second control unit for transferring to the device and writing to the nonvolatile semiconductor memory.

FIG. 1 is a block diagram illustrating a configuration example of an information processing apparatus. FIG. 2 is a flowchart illustrating an operation example on the information processing apparatus side during the write process. FIG. 3 is a flowchart illustrating an operation example of the semiconductor memory device and the information processing apparatus side during the write process. FIG. 4 is a flowchart showing an operation example on the semiconductor memory device and information processing apparatus side during the read processing.

(Embodiment)
FIG. 1 shows a configuration example of the information processing apparatus of the present embodiment. The information processing apparatus includes a host device (hereinafter abbreviated as a host) 10 and a memory system (semiconductor storage device) 20 that functions as a storage device of the host 10. The memory system 20 is a flash memory for embedded use conforming to the eMMC (Embedded Multi Media Card) standard, an SSD (Solid State Drive), or the like. The information processing device is, for example, a personal computer, a mobile phone, an imaging device, or the like.

  The memory system 20 includes a NAND flash 21 as a nonvolatile semiconductor memory, a NAND interface (NAND I / F) 24, a DMA controller 25, a buffer memory 26, an ECC circuit 27, a storage controller 28, and a storage interface (storage I / F) 29. Have.

  The NAND flash 21 has a memory cell array in which a plurality of memory cells are arranged in a matrix. Individual memory cells can be stored in multiple values using the upper page and the lower page. The NAND flash 21 is configured by arranging a plurality of blocks, which are data erasing units. Further, each block is composed of a plurality of pages. Each page is a unit for writing and reading data. The NAND flash 21 is constituted by a plurality of memory chips, for example.

  The NAND flash 21 stores user data transmitted from the host 10, management information of the memory system 20, and an OS 23 used by the host 10.

  The OS 23 functions as a control program for the host 10.

  The logical physical conversion table (L2P table) 22 includes a logical block address (LBA) used when the host 10 accesses the memory system 20, and a physical address (block address + page address +) in the NAND flash 21. This is address conversion information that associates (in-page storage position). Hereinafter, the L2P table 22 stored in the NAND flash is referred to as an L2P main body.

  The NAND I / F 24 reads / writes data and management information from / to the NAND flash 21 based on the control of the storage controller 28.

  The buffer memory 26 is used as a buffer for storing data to be written to the NAND flash 21 or data read from the NAND flash 21. The buffer memory 26 also includes a command queue 26a for queuing commands related to a write request, a read request, etc. input from the host 10, and tag information 26b of L2P information cached in the main memory 13 of the host 10 to be described later. Remember. For example, the buffer memory 26 is configured by SRAM or DRAM, but may be configured by a register or the like.

  The ECC circuit 27 performs an encoding process in an ECC process (error correction process) on the data transferred from the buffer memory 26 and to be written to the NAND flash 21, and adds the encoding result to the data to the NAND interface 24. Output. The ECC circuit 27 performs decoding processing (error correction processing using an error correction code) in ECC processing on the data read from the NAND flash 21 through the NAND interface 24, and the error-corrected data is obtained. The data is output to the buffer memory 26.

  The DMA controller 25 controls data transfer among the NAND interface 24, the ECC circuit 27, and the buffer memory 26. Note that data transfer between the register 14a in the storage interface (storage I / F) 14 of the host 10 and the buffer memory 26 may be performed by the DMA controller 25. In this embodiment, the register 14a And the buffer memory 26 perform data transmission by the storage I / F 29.

  The storage interface (storage I / F) 29 is an interface for connecting to the host 10. The storage I / F 29 has a function of controlling data transmission between the register 14 a in the storage I / F 14 of the host 10 and the buffer memory 26 of the memory system 20.

  The storage controller 28 realizes its function with firmware, and comprehensively controls each component in the memory system 20 connected to the bus 30.

  In the memory system 20, the relationship between the logical address (LBA) and the physical address (storage location of the NAND flash 21) is not statically determined, but is dynamically related when data is written. For example, when data of the same LBA is overwritten, the following processing is performed. It is assumed that valid data having a block size is assigned to the logical address A1, and the block B1 of the NAND flash 21 is used as a storage area. When a command for overwriting update data having a block size of logical address A1 is received from the host 10, one unused free block (referred to as block B2) in the NAND flash 21 is secured and received from the host 10 in that free block. Write the data. Thereafter, the logical address A1 is related to the block B2. As a result, the block B2 becomes an active block including valid data therein, and the data stored in the block B1 becomes invalid, so the block B1 becomes a free block.

  As described above, in the memory system, even if the data has the same logical address A1, the block used as the actual recording area changes every time writing is performed. Note that, in writing update data with a block size, the write destination block always changes, but with update data writing with a block size less than that, update data may be written in the same block. For example, when page data smaller than the block size is updated, old page data having the same logical address in the block is invalidated, and the latest page data newly written is managed as a valid page. When all the data in the block is invalidated, the block is released as a free block.

  In the memory system 20, block arrangement is executed. In the memory system, when the data erasure unit (block) is different from the data management unit, when the NAND flash 21 is rewritten, the block becomes perforated due to invalid (not latest) data. When the number of such perforated blocks increases, the number of blocks that can be used substantially decreases, and the storage area of the NAND flash 21 cannot be effectively used. Therefore, for example, when the number of free blocks in the NAND 21 becomes smaller than a predetermined threshold value, the latest effective data is collected, and block arrangement such as compaction and garbage collection for rewriting to a different block is executed to secure free blocks.

  Further, in the memory system 20, for example, when updating some sectors in a page, the storage data of the NAND flash 21 is read, changed, and written to the NAND flash 21 and read-modify-write (RMW). ). In the RMW process, first, a page or block including an update sector is read from the NAND flash 21, and the read data is integrated with the write data received from the host 10. Then, this integrated data is written into a new page or a new block of the NAND flash 21.

  The host 10 includes a CPU 11, a main memory interface 12, a main memory 13, a storage interface (storage I / F) 14, and a bus 16 for connecting them. The main memory I / F 12 is an interface for connecting the main memory 13 to the bus 16.

  The main memory 13 is a main storage device that can be directly accessed by the CPU 11, and in this example, a DRAM (Dynamic Random Access Memory) is used. The main memory 13 is used as a storage area for the L2P cache 13a and the write cache 13b in addition to the function as the main memory used by the CPU 11. The main memory 13 is also used as a work area 13c. The L2P cache 13 a is a part or all of the L2P main body 22 stored in the NAND flash 21 of the memory system 20. The storage controller 28 of the memory system 20 uses the L2P cache 13 a cached in the main memory 13 and the L2P main body 22 stored in the NAND flash 21 to access data stored in the NAND flash 21. Address resolution.

  Write data to be written from the host 10 to the memory system 20 is temporarily stored in the write cache 13b. The work area 13c is a work area for writing data to the NAND flash 21, and is specifically used when executing the above-described arrangement of blocks, RMW, or the like.

  The storage I / F 14 is an interface for connecting to the memory system 20. The storage I / F 14 includes a DMA controller 15 and a register 14a. The DMA controller 15 executes data transfer control between the L2P cache 13a, the write cache 13b, the work area 13c of the main memory 13 and the register 14a in the storage I / F 14.

  The CPU 11 is a processor that controls the operation of the host 10 and executes the OS 23 loaded from the NAND flash 21 to the main memory 13. The OS 23 includes a device driver 23 a that controls the memory system 20. When receiving a write request for the memory system 20 from the OS 23 or an application on the OS 23, the device driver 23a separates the write request into a write command and write data. The command includes a field for identifying the type of command (read, write, etc.), a field for specifying the head LBA, a field for specifying the data length, and the like. The device driver 23a transmits the command directly to the memory system 20 via the storage I / F 14. On the other hand, the device driver 23 a temporarily stores the separated data in the write cache 13 b of the main memory 13.

  FIG. 2 shows an operation procedure of the device driver 23a when a write request is received. When receiving a write request for the memory system 20 from the OS 23 or an application on the OS 23, the device driver 23a separates the write request into a command and data (step S100). Next, the device driver 23a transmits the command directly to the memory system 20 via the storage I / F 14. The device driver 23a temporarily stores the separated data in the write cache 13b of the main memory 13 (step S110). Thereafter, the data cached in the write cache 13 b is transferred to the memory system 20 side under the control of the storage controller 28 of the memory system 20.

  FIG. 3 shows an operation procedure on the memory system 20 side when a write command is received. The write command transmitted from the host 10 to the memory system 20 is set in the command queue 26a of the buffer memory 26 by the storage I / F 29 (steps S200 and S210). When the storage controller 28 becomes the execution order of the write command set in the command queue 26a and the write command can be executed (step S220), whether or not the LBA included in the write command is in an unwritten state. Is determined (step S230). Here, the LBA unwritten state is a state in which valid data corresponding to the LBA is not stored in the NAND flash 21.

  Specifically, whether or not the LBA is in an unwritten state is determined by the following procedure, for example. That is, the storage controller 28 determines whether or not the LBA included in the write command hits the tag information 26b, and if not, determines whether or not the L2P main body 22 stored in the NAND flash 21 is hit. To do. Note that the tag information 26b is data in which L2P information cached in the L2P cache 13b of the main memory 13 of the host 10 is registered. By searching the tag information 26b, the L2P cache 13b stores the L2P corresponding to the LBA. It is possible to determine whether information is stored.

  As described above, when it is determined by the search of the tag information 26b and the L2P main body 22 that the LBA does not hit (step S230: Yes), the storage controller 28 writes the write command corresponding to the write command to the DMA controller 15 of the host 10. A data transfer command for transferring data from the write cache 13b is output (step S240). The DMA controller 15 that has received this data transfer command transfers the write data stored in the write cache 13 b of the main memory 13 from the write cache 13 b of the main memory 13 to the register 14 a of the storage I / F 14. When data is set in the register 14a, the storage I / F 14 notifies the storage I / F 29 to that effect, and the storage I / F 29 that has received the notification sends the write data set in the register 14a to the buffer memory 26. (Step S250).

  In order to enable the storage controller 28 to specify the storage location of the write data stored in the write cache 13b on the main memory 13, the storage location in the main memory 13 may be included in the write command. Further, the write controller 13 can have a FIFO structure or a ring buffer structure so that the storage controller 28 can specify the storage location of the write data. That is, the write data is set in the FIFO command write cache 13b in the order in which the write commands are generated. Since the write command includes the data length, if the storage controller 28 recognizes the initial address of the write cache 13b having the FIFO structure, the data length is added to the address every time the write command is received. As a result, the storage position of the write data on the main memory 13 can be grasped.

  When the write data is set in the buffer memory 26 by the processing in step S250, the storage controller 28 encodes the write data in the ECC circuit 27 and then writes it in the NAND flash free block via the NAND I / F 24 (step S250). S350). Thereafter, the L2P cache 13a, the tag information 26b, and further the L2P main body 22 are updated so that the LBA specified by the write command is associated with this free block (step S360). The L2P main body may be updated periodically instead of being updated every time the NAND flash 21 is written.

  The L2P cache 13a is updated as follows. After creating new L2P information in the buffer memory 26, the storage controller 28 adds the tag information to the tag information 26 b in the buffer memory 26, notifies the storage I / F 29, and further notifies the DMA controller 15 of the host 10. A transfer command for transferring the L2P information is output. As a result, the storage I / F 29 sets the new L2P information created in the buffer memory 26 in the register 14a of the storage I / F 14. The DMA controller 15 transfers the L2P information set in the register 14a to the main memory 13, and caches the L2P information in the L2P cache 13a.

  On the other hand, in step S230, when the LBA included in the write command hits the tag information 26b (step S230: No), the storage controller 28 outputs an L2P information transfer command to the DMA controller 15 of the host 10. Thereby, the DMA controller 15 transfers the hit L2P information stored in the L2P cache 13a of the main memory 13 from the main memory 13 to the register 14a of the storage I / F 14. As described above, when data is set in the register 14a, the storage I / F 14 notifies the storage I / F 29 to that effect, and the storage I / F 29 that has received the notification notifies the L2P information set in the register 14a. Is transferred to the buffer memory 26. The storage controller 28 performs address resolution using the L2P information transferred to the buffer memory 26.

  Next, the storage controller 28 reads the page or block including the data stored at the physical address corresponding to the LBA obtained by the address resolution from the NAND flash 21 and transfers it to the buffer memory 26 (step S260). Next, the storage controller 28 outputs a data transfer command for transferring the write data stored in the write cache 13b to the DMA controller 15 of the host 10 (step S270). The DMA controller 15 that has received this data transfer command transfers the write data stored in the write cache 13 b of the main memory 13 from the main memory 13 to the register 14 a of the storage I / F 14. The data set in the register 14a is transferred to the buffer memory 26 by the storage I / F 29 in the same manner as described above (step S280).

  Next, the storage controller 28 combines the data read from the NAND flash 21 and written to the buffer memory 26 with the data transferred from the write cache 13b and written to the buffer memory 26 on the buffer memory 26 (step S290). . When this synthesis is completed, the storage controller 28 notifies the storage I / F 29 to that effect, and further outputs a transfer command for transferring data to the DMA controller 15 of the host 10 (step S300). As a result, the storage I / F 29 sets the data combined in the buffer memory 26 in the register 14a of the storage I / F 14. The DMA controller 15 transfers the composite data set in the register 14a to the main memory 13, and stores this composite data in the work area 13c (step S310).

  Thereafter, the storage controller 28 determines whether or not the data composition process has been completed (step S320). If the data composition process has not been completed, the data composition process is completed according to the steps S260 to S310. Repeat until. In this way, as many block unit data as possible are created on the work area 13 c of the main memory 13.

  When the data synthesizing process is completed, the storage controller 28 outputs a data transfer command for transferring the synthesized data stored in the work area 13c of the main memory 13 to the DMA controller 15 of the host 10 (step S330). . The DMA controller 15 that has received this data transfer command transfers the composite data stored in the work area 13 c of the main memory 13 from the main memory 13 to the register 14 a of the storage I / F 14. The data set in the register 14a is transferred to the buffer memory 26 by the storage I / F 29 in the same manner as described above (step S340).

  When the combined data is set in the buffer memory 26 by the processing in step S340, the storage controller 28 encodes the write data in the ECC circuit 27 and then writes the data in the NAND flash free block via the NAND I / F 24 (step S340). S350). Thereafter, the LBA is associated with the free block, and the L2P cache 13a, the tag information 26b, and the L2P main body 22 are updated so as to invalidate the old active block (step S360).

  When the synthesis process ends with one data transfer from the main memory 13 to the buffer memory 26, the data synthesized in the buffer memory 26 may be directly written to the NAND flash 21.

  FIG. 4 shows an operation procedure on the memory system 20 side when a read command is received. The read command received by the memory system 20 via the storage I / F 29 is set in the command queue 26 a of the buffer memory 26 by the storage I / F 29. When the read command becomes executable, the storage controller 28 determines whether or not the LBA included in the read command hits the tag information 26b (step S420). If there is a hit (step S420: Yes), the storage controller 28 outputs an L2P transfer command to the DMA controller 15 of the host 10 (step S430). Thereby, the DMA controller 15 transfers the hit L2P information stored in the L2P cache 13a of the main memory 13 from the main memory 13 to the register 14a of the storage I / F 14. The L2P information set in the register 14a is transferred to the buffer memory 26 by the storage I / F 29 in the same manner as described above (step S440).

  The storage controller 28 performs address resolution using the L2P information transferred to the buffer memory 26. That is, the storage controller 28 acquires the physical address associated with the LBA from the L2P information, and causes the NAND flash 21 to read data corresponding to the acquired physical address. The ECC circuit 27 performs a decoding process in the ECC process on the data read from the NAND flash 21 via the NAND interface 24 and outputs error-corrected data to the buffer memory 26. Thereafter, the storage controller 28 outputs the read data stored in the buffer memory 26 to the host 10.

  On the other hand, in step S420, when the LBA included in the read command does not hit the tag information 26b (step S420: No), the storage controller 28 stores part or all of the L2P main body stored in the NAND flash 21 in the buffer memory. 26 is read and searched (step S460). If the LBA does not hit the L2P main body, the read process is terminated and an error is returned to the host 10. When the LBA hits in the L2P main body (step S470), the storage controller 28 performs address resolution using the hit L2P information. That is, the storage controller 28 acquires the physical address associated with the LBA from the L2P information, and causes the NAND flash 21 to read data corresponding to the acquired physical address. The ECC circuit 27 performs a decoding process in the ECC process on the data read from the NAND flash 21 via the NAND interface 24 and outputs error-corrected data to the buffer memory 26. Thereafter, the storage controller 28 outputs the read data stored in the buffer memory 26 to the host 10 (step S480).

  The storage controller 28 stores the L2P information corresponding to the LBA included in the read command or the L2P information corresponding to the peripheral LBA including the LBA included in the read command, out of the L2P main body read into the buffer memory 26. The storage I / F 29 is instructed to transfer the data to the register 14a, and a transfer command for transferring the L2P information to the DMA controller 15 of the host 10 is output. As a result, the storage I / F 29 sets the L2P information buffered in the buffer memory 26 in the register 14a of the storage I / F 14. The DMA controller 15 transfers the L2P information set in the register 14a to the main memory 13, and caches this L2P information in the L2P cache. Accordingly, the storage controller 28 updates the tag information 26b in the buffer memory 26.

  The work area 13c formed on the main memory 13 is also used as a work area when performing the above-described block arrangement, RMW, and the like. In the above embodiment, the tag information 26b of the L2P cache 13a is held on the memory system 20 side. However, the L2P cache 13a may be directly searched without the tag information 26b. Further, although the storage I / F 29 of the memory system 20 performs data transfer between the register 14a and the buffer memory 26, the storage controller 28 may perform this data transfer. Further, direct data transfer may be performed between the main memory 13 and the buffer memory 26.

  Thus, in this embodiment, the main memory 13 of the host 10 is used as a storage area for the write cache 13b and the L2P cache 13a. Thereby, the memory capacity of the buffer memory 26 can be reduced. Further, in the present embodiment, when a write request is made, the write command and the write data are separated, the write data is stored in the main memory 13 of the host 10, and the write command is stored in the buffer memory 26 of the memory system. Then, when the write command is executed in the memory system 20, the write data is read from the main memory 13 of the host 10 and written to the NAND flash 21. Thereby, the interface bandwidth between the host 10 and the memory system 20 can be reduced as compared with the case where the write command and the write data are not separated. In other words, when the write command and the write data are not separated, the write command and the write data are transferred from the host to the memory system at the time of the write request, then the memory system separates the write command and the write data and the separated write data is sent to the host. The operation is to transfer to 10 main memories 13. In this case, the write data is transferred three times through the bus between the host 10 and the memory system 20 in response to a single write request, thereby increasing the interface bandwidth. On the other hand, according to the configuration of the present embodiment, such a problem can be solved.

  Note that the L2P main body 22 stored in the NAND flash 21 may be loaded into the main memory 13 of the host when the memory system is activated. In addition, a primary cache of L2P information is provided on the memory system 20 side, and a secondary cache of L2P information is provided in the main memory of the host. When there is no hit in the primary cache and secondary cache, these are stored in the NAND flash 21. The L2P main body 22 may be searched.

  In this embodiment, since the work area 13c used by the storage controller 28 of the memory system 20 is provided on the main memory 13, the capacity of the buffer for the work area on the memory system side and the exclusive area are reduced. It becomes possible to reduce.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  10 host device, 11 CPU, 13 main memory, 13a L2P cache, 13b write cache, 13c work area, 14 storage interface, 14a register, 15 DMA controller, 20 memory system, 21 NAND flash, 22 L2P main unit, 23a device driver , 25 DMA controller, 26 buffer memory, 26a command queue, 26b tag information, 27 ECC circuit, 28 storage controller.

Claims (10)

In an information processing apparatus including a host device and a semiconductor storage device,
The host device is
Main memory,
A first control unit that transmits a read request to the semiconductor memory device ;
The semiconductor memory device
Non-volatile semiconductor memory;
A second control unit that receives the read request from the host device ,
The nonvolatile semiconductor memory stores address conversion information that associates a logical address used when the host device accesses the semiconductor storage device and a physical address in the nonvolatile semiconductor memory,
The main memory stores at least a part of the address conversion information;
The second control unit converts a logical address included in the read request into a physical address using the address conversion information held in the main memory, and uses the physical address to correspond to the read request. Is read from the non-volatile semiconductor memory . The first control unit transmits a write request to the semiconductor memory device,
The second control unit converts a logical address included in the write request into a physical address using the address conversion information held in the main memory, and uses the physical address to correspond to the write request. Is written to the nonvolatile semiconductor memory
The information processing apparatus according to claim 1 . The first control unit separates a write request for the semiconductor memory device into a write command and write data corresponding to the write command, outputs the write command to the semiconductor memory device, and outputs the write data to the main memory Remember
When the second control unit receives the write command transferred from the host device, the second control unit transfers write data corresponding to the write command stored in the main memory to the semiconductor memory device, and the transferred write data Is written into the nonvolatile semiconductor memory as data corresponding to the write request
The information processing apparatus according to claim 2 . The second control unit updates the address conversion information stored in the main memory and the nonvolatile semiconductor memory after writing data corresponding to the write request to the nonvolatile semiconductor memory. The information processing apparatus according to claim 2 or 3 . The second control unit uses the tag information indicating the address conversion information stored in the main memory to generate address conversion information corresponding to the logical address included in the read request or write request from the host device in the main memory. The information processing apparatus according to claim 2, wherein it is determined whether or not the information is stored . In a semiconductor memory device connectable to a host device having a main memory,
The semiconductor memory device
Non-volatile semiconductor memory;
A control unit for receiving a read request from the host device;
With
The nonvolatile semiconductor memory stores address conversion information that associates a logical address used when the host device accesses the semiconductor storage device and a physical address in the nonvolatile semiconductor memory,
The control unit stores at least a part of the address conversion information in the main memory, and converts a logical address included in the read request into a physical address using the address conversion information held in the main memory. And reading data corresponding to the read request from the nonvolatile semiconductor memory using the physical address
A semiconductor memory device . When receiving a write request from the host device, the control unit converts the logical address included in the write request into a physical address using the address conversion information held in the main memory, and uses the physical address. Write data corresponding to the write request to the nonvolatile semiconductor memory
The semiconductor memory device according to claim 6 . The host device separates a write request for the semiconductor storage device into a write command and write data corresponding to the write command, outputs the write command to the semiconductor storage device, and stores the write data in the main memory. ,
When the control unit receives the write command transferred from the host device, the control unit causes the write data corresponding to the write command stored in the main memory to be transferred to the semiconductor memory device, and the transferred write data is transferred to the write command. Write to the nonvolatile semiconductor memory as data corresponding to the request
The semiconductor memory device according to claim 7 . The control unit updates the address conversion information stored in the main memory and the nonvolatile semiconductor memory after writing data corresponding to the write request to the nonvolatile semiconductor memory. 8. The semiconductor memory device according to 6 or 7 . The controller uses the tag information indicating the address conversion information stored in the main memory to store address conversion information corresponding to the logical address included in the read request or write request from the host device in the main memory. 10. The semiconductor memory device according to claim 7, wherein it is determined whether or not there is any .

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