JP2014191250A - Optical control element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an optical control element where an electro-optic device chip can be downsized by devising a connection structure of the electro-optic device chip and a circuit board.SOLUTION: An optical control element includes: a circuit board; an element substrate; an optical waveguide formed in the element substrate; a first electrode which is provided for one main surface side in a thickness direction of the element substrate; and a second electrode provided for the other main surface side of the element substrate. A signal electrode comprises a control unit for controlling phase of light that passes the optical waveguide and a connection land part connected to the control unit. The connection land part is built up at a position higher than the main surface of the element substrate and is provided with a low conductivity layer having lower conductivity than that of the element substrate between itself and the main surface of the element substrate. A second electrode has at least a second grounding electrode and is placed so that it applies an electric field to the optical waveguide in cooperation with the control unit. The connection land part has a wider width than an electrode width of the control unit, is connected to the control unit, and electrically connects the control unit and a wiring electrode of the circuit board.

Description

  The present invention relates to a light control element.

Wire bonding and ribbon bonding are widely used for the electrical connection between the control unit of the electro-optic device chip such as LiNbO ₃ (LN) and the connection land, the connection wiring and the electrical connector, the relay substrate, etc. The electro-optic device chip The connection land portion (pad portion) of the signal electrode above needs to be sized according to the process. The interval between the optical waveguides in the portion where the signal electrode, which is the main functional portion as the optical modulator (light control element), is arranged is generally 20 μm to 200 μm, and at most about 300 μm. In addition, several hundred μm is required as a minute. Accordingly, the width of the chip is increased, and the number of elements obtained from a wafer for producing one electro-optic device is reduced. Further, in the case of a nested MZ modulator or a modulator having a plurality of electrodes, it is necessary to match the timing of the control signal, and a configuration such as bending the wiring electrode is necessary. In such a configuration, since a wider chip width is required, the number of elements obtained from one LN wafer is further reduced.

  There are also problems such as attenuation of control signals and deterioration of high-frequency characteristics caused by bending the wiring electrodes greatly. Further, when an electrode is taken out to the side of the chip using a material having a large dielectric anisotropy in the main surface of the substrate, such as an LN X plate, as shown in Patent Document 5 and Patent Document 6. Such wiring design is required, and there is a problem that the design for preventing discontinuity of impedance becomes complicated.

  In order to solve this problem, Patent Document 1 is proposed. This is a method of mounting an electro-optic device chip face down on a wiring board using flip chip mounting or the like. In this configuration, it is assumed that the electrode width of the connection land portion is the same as the electrode width at the action portion of the optical waveguide. In a high-frequency modulator using a chip using LN as an electro-optic material, the electrode width is At 10 μm or less, a high aspect structure with a height of 30 μm or more is obtained.

  However, with such thin electrodes, wire breakage due to melting with solder is likely to occur, and mounting on a wiring board by solder reflow requires strict control of the amount of solder, temperature, etc. It's not easy. In addition, since it has a high aspect structure, it is easily deformed by stress, and in connection by flip chip bonding, the signal electrode is likely to be deformed or collapsed, and it is not easy to apply to mass production.

JP 2006-284838 A International Publication No. WO2007 / 114367 JP 2008-250258 A JP 2009-139842 A JP 2010-237615 A JP 2010-237629 A "Coplanar-Microstrip Transitions for Ultra-Wideband Communications" Mohammed El-Gibari, Dominique Averty, Cyril Lupi, Yann Mahe Hongwu Li and Serge Toutain, chapter 8, Ultra Wideband Communications: Novel Trends-Antennas and Propagation, Edited by Mohammad Matin, ISBN 978-953-307-452-8, Hard cover, 384 pages, Publisher: InTech, Published: August 09, 2011

  For the chip configuration that enables solder reflow process and flip chip bonding, the connection land is basically formed large. However, if the wiring is thick with a simple configuration, impedance mismatch and parasitic capacitance will occur. As a result, the characteristics as an electro-optical device, particularly in the high frequency band, are greatly deteriorated.

  In particular, in the structure in which both surfaces of a thin electro-optical device chip as described in Patent Document 2 (FIG. 3) are sandwiched between electrodes, the above problem is remarkable. The problem of impedance mismatch and parasitic capacitance can be alleviated to some extent by omitting the ground electrode in the connection land portion, as described in Patent Document 3. However, in the case of a thin substrate, since the land for electrical connection is also formed on the thin substrate, there is a problem that the thin substrate having the electro-optic effect is damaged by cracking and deformation due to heat and high frequency during bonding. It is remarkable. When the damage reaches the optical waveguide portion, the device functions such as an increase in optical loss and a deterioration in extinction ratio are greatly impaired. As a countermeasure, it is necessary to increase the width of the chip by separating the wiring land portion from the optical waveguide. As described above, the electro-optical device configured as in Patent Document 2 has extremely high efficiency per unit length, and can greatly reduce the length of the chip of the device. There was a limit to downsizing the chip to avoid damage.

  In the case of an electro-optic polymer material containing a hyperpolarizability dye, a method for avoiding damage at the time of mounting by the method shown in Patent Document 4 is shown. This is a method in which a protective layer is provided on the working part electrode to alleviate damage during wire bonding, and it is shown that an insulating material may be used as a material for the protective layer. Although this method is effective for any device that works with a simple rectangular connection land as shown in the literature, it can be expected to have a certain effect in preventing damage, but it has an adverse effect on the operating characteristics of the device at high frequencies. Unavoidable. It is necessary to design the dielectric constant of the protective film, the complex dielectric constant (tan δ), the film thickness, electrode shape, and electrode arrangement according to these characteristics.

  In the case of an electro-optic polymer material, it is known that the problem of impedance mismatch and parasitic capacitance can be reduced by the method shown in FIG. In the electro-optic polymer device, it is necessary to make the thickness of the electro-optic polymer layer uniform by the spin coat film forming method in order to perform the poling process for expressing the electro-optic effect uniformly. However, as shown in FIG. 8 of Non-Patent Document 1, if an electrode pattern is formed on the Back Plane side in advance, it is extremely difficult to spin-coat the electro-optic polymer layer to a precise uniform thickness.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an optical modulator in which an electro-optical device chip and a circuit board are mounted in a small area.
Another object of the present invention is to provide a light control element capable of reducing the size of the electro-optic device chip without degrading the characteristics of the light control element by devising the connection configuration between the electro-optic device chip and the circuit board. It is said.

  The light control element according to the present invention includes a circuit board provided with wiring electrodes, an element substrate having a thickness of 10 μm or less made of a material having an electro-optic effect, an optical waveguide formed on the element substrate, and the element substrate A first electrode provided on one main surface side in the thickness direction and a second electrode provided on the other main surface side of the element substrate, wherein the first electrode includes at least a signal electrode and a first electrode The signal electrode is composed of a control unit for controlling the phase of light passing through the optical waveguide and a connection land unit connected to the control unit, and the connection land unit is a coplanar electrode composed of a single ground electrode. A low dielectric constant layer having a dielectric constant lower than the dielectric constant of the element substrate is provided between the principal surface of the element substrate and built up at a position higher than the principal surface of the element substrate. The second electrode has at least a second contact. It has an electrode and is arranged so as to apply an electric field to the optical waveguide in cooperation with the control unit, and the connection land portion has a width wider than the electrode width of the control unit. And the control unit and the wiring electrode of the circuit board are electrically connected.

  The low dielectric constant layer may be formed on a part of the element substrate so as to include a main surface of the element substrate facing the connection land portion.

  Further, the connection land portion may be provided on at least one of the longitudinal ends of the signal electrode.

  Further, a plurality of the signal electrodes may be provided, and independent control signals may be input to the plurality of signal electrodes.

  The connection land portion may be a coplanar electrode type, and the distance between the center conductor and the ground electrode may be smaller than the thickness of the low dielectric constant layer.

  The connection land portion may be a coplanar electrode type, and the layer of the first electrode corresponding to the position of the connection land portion may have an opening having a width larger than the sum of the distances between the central conductor and the ground electrode of each portion. Good.

  The low dielectric constant layer may be formed using a resin.

  According to the present invention, the electrode structure in the light control element has a G-CPW structure in the main part electrode, while the electrode structure in the connection land part has a CPW structure instead of the G-CPW structure. Even under compact mounting such as reflow bonding, impedance mismatch, increase in parasitic capacitance, and deterioration of high frequency characteristics can be avoided.

  Conventionally, since the end of the control unit is curved toward the side of the element substrate, it has been necessary to increase the width of the chip. However, in the present invention, the end of the control unit is arranged on the side of the element substrate. The chip width can be reduced because of the structure that does not bend toward the tip.

  Further, since the propagation direction of the control signal does not change on the main surface of the element substrate, the electrode design does not become complicated even when a material having anisotropy in dielectric constant is used as the element substrate.

  In addition, since the connection land portion is built up at a position higher than the main surface of the element substrate through a low dielectric constant layer having a dielectric constant lower than that of the element substrate, the wiring of the connection land portion Even when the width is wide, it is possible to suppress the occurrence of impedance mismatch and the increase in parasitic capacitance as described above, and in particular, it is possible to prevent deterioration of characteristics of light modulation in a high frequency region. In addition, it is not necessary to route wiring on the main surface of the element substrate, and the degree of freedom in designing a circuit for adjusting the phase difference of a plurality of signals is significantly improved.

  As a result, the degree of freedom in electrode design is improved, and the number of chips taken from one wafer can be greatly improved without degrading the characteristics of the light control element.

Sectional drawing which shows schematic structure of the light control element which concerns on embodiment of this invention. FIG. 2 is a plan view illustrating a schematic configuration of an electro-optical device chip according to the embodiment. FIG. 3 is a cross-sectional view illustrating a schematic configuration of an electro-optical device chip according to the embodiment. The top view which shows the structure of the connection land part and surface side ground part which concern on this embodiment. The perspective view which shows the structure of the circuit board which concerns on this embodiment. FIG. 6 is a cross-sectional view illustrating the mounting operation of the electro-optic device chip according to the embodiment. The perspective view which shows schematic structure of the conventional light control element. FIG. 9 is a plan view illustrating a schematic configuration of an electro-optical device chip according to a modification. FIG. 9 is a cross-sectional view illustrating a schematic configuration of an electro-optical device chip according to a modification. FIG. 9 is a plan view illustrating a schematic configuration of an electro-optical device chip according to a modification. FIG. 9 is a plan view illustrating a schematic configuration of an electro-optical device chip according to a modification. FIG. 9 is a cross-sectional view illustrating a schematic configuration of an electro-optical device chip according to a modification.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view illustrating a schematic configuration of a light control element 100 according to the present embodiment.
As shown in FIG. 1, the light control element 100 includes an electro-optical device chip 10 and a circuit board 30. In the light control element 100, the electro-optical device chip 10 and the circuit board 30 are connected by, for example, flip chip bonding which is one form of face-down bonding.
FIG. 2 is a plan view showing a schematic configuration of the electro-optic device chip 10. FIG. 3 is a diagram illustrating a cross-sectional configuration taken along the line XX in FIG. 2, and illustrates the optical waveguides 13 a and 13 d for the sake of convenience.
As shown in FIGS. 2 and 3, the electro-optic device chip 10 has an element substrate 11 formed in a flat plate shape having a thickness of 10 μm or less using a lithium niobate crystal (LN) as a dielectric. . The element substrate 11 is cut so as to be long in one direction. Inside the element substrate 11, a plurality of optical waveguides 13a, 13b, 13c, and 13d are formed. The plurality of optical waveguides 13a, 13b, 13c, and 13d are arranged near the first surface (one main surface) 11a of the element substrate 11 or near the second surface (the other main surface) 11b of the element substrate 11 or the element substrate. 11 is formed along the longitudinal direction of the element substrate 11.

  One end of the optical waveguide 13a is connected to the input optical fiber 41, and the other end is connected to the two optical waveguides 13b and 13c by a Y branch. The optical waveguides 13 b and 13 c are arranged side by side in the short direction of the element substrate 11. The optical waveguides 13 b and 13 c have straight portions extending in parallel with each other along the longitudinal direction of the element substrate 11. The straight line portion is a portion where the branched light from the MZ interferometer of the optical waveguides 13a to 13d propagates in parallel. The optical waveguides 13 b and 13 c are connected to one optical waveguide 13 d by a Y branch, and the other end is connected to an output optical fiber 42. The optical waveguides 13a to 13d in the present embodiment constitute Mats Ender (MZ) type optical waveguides.

  The optical waveguides 13a to 13d are directly formed by providing recesses and grooves on both sides of the optical waveguides 13a to 13d on the first surface 11a of the element substrate 11 or the second surface (the other main surface) 11b of the element substrate 11. Or a ridge-type optical waveguide formed by partial film formation on the first surface 11a of the element substrate 11 or on the second surface (the other main surface) 11b of the element substrate 11. The present invention is not limited to this and can be applied to other optical waveguide structures such as a conventional structure having no grooves on both sides of the optical waveguide.

  A first electrode 21 and a low dielectric constant layer 12 are formed on the first surface 11a of the element substrate 11 on which the optical waveguides 13a to 13d are disposed. The first electrode 21 is a coplanar waveguide (CPW) electrode having the signal electrode 14 and the first ground electrode 15. The signal electrode 14 and the first ground electrode 15 are formed in the same layer using, for example, gold (Au).

  The signal electrodes 14 are arranged one by one in regions overlapping the straight portions of the optical waveguides 13b and 13c in plan view, and are formed linearly. By applying a control signal to the signal electrode 14, the phase of light parallel to the optical waveguides 13b and 13c can be changed, and the phase and intensity of the output light can be controlled. Thus, the signal electrode 14 has a portion (control unit 19) that contributes to a change in the phase of light in the optical waveguides 13b and 13c. In the present embodiment, the substantially entire section in the longitudinal direction of the signal electrode 14 corresponds to the control unit 19, but is not limited thereto. For example, by making the dimension in the longitudinal direction of the signal electrode 14 larger than the dimension in the longitudinal direction of the straight portions of the optical waveguides 13 b and 13 c, only the partial section in the longitudinal direction of the signal electrode 14 becomes the control unit 19. You may do it.

  In the present embodiment, two signal electrodes 14 are provided, but one or three or more may be provided. For example, when the electro-optical device chip 10 is mounted on the circuit board 30 on which a peripheral path including an auto bias circuit or the like is arranged, independent control signals are input to the plurality of signal electrodes 14. In the conventional configuration, the light control element having three or more electrodes further increases the width of the electro-optical device chip. However, the width of the electro-optical device chip can be suppressed by applying the configuration of the present invention. In addition, since the number of chips taken from one wafer can be improved, the effect is further increased.

  The first ground electrode 15 is provided with a pair of openings 15a formed in a size including a region corresponding to at least a straight portion (control unit 19) of the optical waveguides 13b and 13c (signal electrode 14). The opening 15a has a larger opening area than the formation region of the signal electrode 14, and the signal electrode 14 is arranged at a substantially central portion in each opening 15a. The opening 15a is formed with a predetermined dimension.

  The low dielectric constant layer 12 is formed so as to cover the signal electrode 14 and the first ground electrode 15 and to cover almost the entire first surface 11 a of the element substrate 11. As a constituent material of the low dielectric constant layer 12, for example, a material having a smaller dielectric constant (or dielectric loss) than polyimide or epoxy is desirable from the viewpoint of securing high frequency characteristics. Examples of such a material include BCB, fluorine resin, and silicone resin. A resin containing particles of a resin having a pore structure, a foamed resin, or a resin having a lower dielectric constant may be used. In the low dielectric constant layer 12, contact holes 14 A and 14 B connected to the signal electrode 14 and a contact hole 15 C connected to the first ground electrode 15 are formed.

  On the surface 12a of the low dielectric constant layer 12, connection land portions 16A and 16B and a surface side ground portion 16C are formed. The connection land portions 16A and 16B are for electrically connecting the signal electrodes 14 of the electro-optic device chip 10 and the wiring electrodes of the circuit board 30 when the electro-optic device chip 10 is mounted on the circuit board 30. is there. The front surface side ground portion 16 </ b> C is for electrically connecting the first ground electrode 15 of the electro-optic device chip 10 and the ground electrode of the circuit board 30.

  The connection land portion 16A extends in the longitudinal direction of the element substrate 11 from the upper end of the contact hole 14A toward the end portion on the optical fiber 41 side (hereinafter referred to as the first end portion) of the surface 12a. Is formed. The connecting land portion 16A is formed so that the dimension in the width direction (direction perpendicular to the extending direction) gradually increases toward the first end portion.

  The connection land portion 16B extends in parallel with the longitudinal direction of the element substrate 11 from the upper end of the contact hole 14B toward the end portion on the optical fiber 42 side (hereinafter referred to as a second end portion) of the surface 12a. It is formed to exist. The connection land portion 16B is formed so that the dimension in the width direction gradually increases toward the second end portion.

  FIG. 4 is a plan view showing the configuration of the connection land portion 16A and the front surface side ground portion 16C. Hereinafter, in describing the configuration of the connection land portions 16A and 16B, the connection land portion 16A will be described as an example with reference to FIG. The following description is applicable to the connection land portion 16B.

  The connection land portion 16A has three portions (a routing portion 61, a taper portion 62, and a connection portion 63) arranged from the contact hole 14A side toward the first end portion side. The routing portion 61 is connected to the contact hole 14A, and is formed to have a uniform width. The tapered portion 62 is formed so that the width gradually increases from the routing portion 61 toward the connecting portion 63. The connection part 63 is connected to the wiring electrode of the circuit board 30. The connecting portion 63 is formed so as to maintain the width W1 expanded by the tapered portion 62 over the entire extending direction. The width W1 of the connection part 63 is larger than the width of the signal electrode 14 (control part 19), for example.

  The surface side ground portion 16C has an opening 64 formed in a region including the connection land portion 16A. The opening 64 is formed in a shape corresponding to the shapes of the routing portion 61, the taper portion 62, and the connection portion 63 of the connection land portion 16A. Specifically, in the opening 64, distances (widths) W2 and W3 between the connection land portion 16A and the surface side ground portion 16C are formed over the entire extending direction of the connection land portion 16A. With this configuration, the design freedom and characteristics of the connection land portion 16A can be ensured, the impedance of the connection land portion 16A can be avoided from being discontinuous, and deterioration due to signal wraparound can be suppressed.

  Note that the design between the connecting portion 63 and the width W1 of the gap 65 and the widths W2 and W3 of the gap 65 is simple, such as W1: W2: W3 = 1: 5: 5. As long as the discontinuity is small, the shape may be a parabolic taper shape, a multi-step staircase shape, or the like. It is preferable that the reflection due to impedance mismatch is minimized, but the ratio is not limited to this. Moreover, the dimension (W1 + W2 + W3) of the width direction of the opening part 64 may be larger than the layer thickness D1 (see FIG. 2) of the low dielectric constant layer 12 so that it can be easily connected to the wiring electrode of the circuit board 30. With this configuration in which the dimension (W1 + W2 + W3) in the width direction of the opening 64 is wide, the wraparound of the electric field tends to easily occur between the first ground electrode 15 and the surface side ground portion 16C. However, by taking the following configuration, the first ground electrode 15 formed between the low dielectric constant layer 12 and the surface side ground portion 16C It is possible to prevent the wraparound of the electric field from occurring. The layer thickness D1 of the low dielectric constant layer 12 is larger than the value of the width W2 (or W3) of the gap 65 (D1> W2 (or W3)). When the layer thickness D1 is smaller than the value of the width W2 (or W3) of the gap 65 due to circuit characteristic design convenience or manufacturing restrictions, the opening 15a of the first ground electrode 15 and the surface side ground The first ground electrode 15 is cut away so that the distance between the portion 16C and the opening 64 is larger than the width W2 (or W3).

  On the other hand, the second electrode 22 and the low dielectric constant layer 17 are formed on the second surface (the other main surface) 11 b of the element substrate 11. The second electrode 22 has a second ground electrode 23 that applies an electric field to the optical waveguides 13 a to 13 d in cooperation with the signal electrode 14 provided on the surface side of the element substrate 11. The second ground electrode 23 is formed over a predetermined region of the second surface 11b.

  The low dielectric constant layer 17 is formed so as to cover the second ground electrode 23 and almost the entire second surface 11b. Examples of the constituent material of the low dielectric constant layer 17 include known materials such as silicon oxide, silicon nitride, and alumina, and resins containing an adhesive. When the material constituting the element substrate 11 is a ferroelectric crystal or a paraelectric crystal, it is faster to configure the material with a material having a dielectric constant lower than that of the material constituting the element substrate 11. This is advantageous.

  In the present embodiment, in the regions other than the connection land portions 16A and 16B, the electrode configuration of the first electrode 21 is a G-CPW structure due to the configuration of the second ground electrode 23, and the electrode configuration of the connection land portions 16A and 16B is the same. It has a CPW structure, a microstrip line structure, or a connection bump structure.

  A reinforcing substrate (holding substrate) 18 is provided on the low dielectric constant layer 17. The reinforcing substrate 18 is made of a glass substrate such as quartz glass. The reinforcing substrate 18 is not particularly limited in terms of electrical characteristics such as dielectric properties and conductivity, but is required to have mechanical characteristics as a reinforcing substrate, and in particular has the same thermal expansion coefficient as the material constituting the element substrate 11. Is desirable. In addition, since the predetermined | prescribed intensity | strength can be ensured by forming the low dielectric constant layer 12 thick (for example, about 100 micrometers-500 micrometers), in this case, the reinforcement board | substrate 18 can be abbreviate | omitted.

  When a voltage is applied to the signal electrode 14 of the electro-optic device chip 10 configured as described above to generate an electric field, the electro-optic effect that changes the refractive index of the crystal of the electro-optic device chip 10, that is, lithium niobate, The phase of the light passing through the two optical waveguides 13b and 13c arranged below the signal electrode 14 changes. Then, two lights having different phases are combined in the Y branch synthesized by these two optical waveguides 13b and 13c, and intensity modulation is performed. In this way, the light output from the optical fiber 41 for light output is modulated.

Next, the configuration of the circuit board 30 will be described.
FIG. 5 is a perspective view showing the configuration of the circuit board 30.
As shown in FIG. 5, the substrate 31 of the circuit board 30 is a wiring board compatible with high frequency, and the material is ceramic, glass or resin with low dielectric loss. Electrodes and wirings are arranged on the surface of the substrate 31, and circuit components constituting a drive circuit, an auto bias circuit, etc. for controlling the electro-optical device chip 10 are attached. However, such wirings and circuit components are omitted in FIG. A pair of signal electrodes 32a, a pair of signal electrodes 32b, three ground electrodes 33a, and three ground electrodes 33b for connecting the electro-optic device chip 10 are shown.

  The signal electrode 32a is disposed on one side in the longitudinal direction of the substrate 31, the signal electrode 32b is disposed on the other side in the longitudinal direction of the substrate 31, and a connection land portion is provided at one end of each of the signal electrodes 32a and 32b. 35a and 35b are provided. Specifically, a connection land portion 35a is provided at one end of the signal electrode 32a on the signal electrode 32b side, and a connection land portion 35b is provided at one end of the signal electrode 32b on the signal electrode 32a side.

  When the electro-optical device chip 10 shown in FIG. 2 or the like is mounted with its surface facing the surface of the circuit board 30, connection land portions respectively provided at one end of each signal electrode 14 of the electro-optical device chip 10. 16A is connected to the connection land portion 35a of the signal electrode 32a of the circuit board 30 via the bump 34, and the connection land portion 16B provided at the other end of the signal electrode 14 is the connection land portion of the signal electrode 32b of the circuit board 30. 35b is connected to each other via a bump 34.

  The ground electrode 33a and the ground electrode 33b are arranged in a region that does not overlap with the signal electrodes 32a and 32b in a plan view with a predetermined interval therebetween, and in the width direction of the circuit board 30, three ground electrodes 33a and Two signal electrodes 32a are alternately arranged, and three ground electrodes 33b and signal electrodes 32b are alternately arranged. A connection land portion 36 is provided at one end of each of the ground electrode 33a and the ground electrode 33b. When the electro-optical device chip 10 is mounted on the circuit board 30, the connection land portion 36 is connected to the surface side ground portion 16 </ b> C of the electro-optical device chip 10.

  Each of the pair of signal electrodes 32a and the pair of signal electrodes 32b has a bent shape toward one side in the short direction of the substrate 31 with a gentle curvature at each end side, and reaches each side of the substrate 31. The end is connected to a connector (not shown). The wiring shapes and pitches of the signal electrodes 32a and 32b and the ground electrodes 33a and 33b can be appropriately selected depending on conditions such as the package and its connector position.

  Next, a method for mounting the electro-optic device chip 10 on the circuit board 30 will be described. FIG. 6 is a cross-sectional view showing the mounting operation of the electro-optic device chip 10. The signal electrodes 32a and 32b and the ground electrodes 33a and 33b on the circuit board 30 are connected to the signal electrode 14 and the first ground electrode 15 on the electro-optic device chip 10 as follows.

  As shown in FIG. 6, first, bumps 34 such as gold and solder are formed on the connection land portions 35 a and 35 b and the connection land portion 36 of the circuit board 30. Then, on the circuit board 30 on which the bumps 34 are formed on the connection land portions 35a, 35b, 36, the side on which the first electrode 21 is formed with the electro-optic device chip 10 facing upside down (the first surface 11a). Side) is placed facing the circuit board 30. At this time, the electro-optical device chip 10 is connected to the connection land portions 16A and 16B and the front surface side ground portion 16C and the connection land portions 35a, 35b, and 36 of the circuit board 30 while the electro-optic device chip 10 is electro-optically arranged on the circuit board 30. The device chip 10 is placed, and bonding is performed by a method such as reflow, thermocompression bonding, ultrasonic bonding, or surface activated room temperature bonding. In this way, the light control element 100 shown in FIG. 1 is configured.

  As a method for connecting the electro-optic device chip 10 and the circuit board 30, a general apparatus such as a flip chip bonder can be used. A pair of connection land portions 16A of the electro-optic device chip 10 and a pair of connection land portions 35a of the circuit board 30, a pair of connection land portions 16B of the electro-optic device chip 10 and a pair of connection land portions 35b of the circuit board 30, and an electro-optic device The front surface side ground portion 16 </ b> C of the chip 10 and the circuit board 30 connection land portion 36 (ground electrodes 33 a and 33 b) are connected via bumps 34, respectively.

  When a thin base material made of a material having a high relative dielectric constant such as LN is used as the element substrate 11, the width of the connection land portion is set to a G-CPW configuration in which the connection land portion and the ground electrode face each other in the thickness direction. If it is widened, the impedance becomes very small, and impedance discontinuity occurs or high frequency characteristics deteriorate due to increase in parasitic capacitance.

  However, as in the present embodiment, the connection land portions 16A and 16B have a lower dielectric constant layer 12 having a dielectric constant lower than that of the element substrate 11, and are more than the first surface 11a of the element substrate 11. Since it is built up at a high position, even when the wiring width of the connection land portions 16A and 16B is wide, it is possible to suppress the occurrence of impedance mismatch and increase in parasitic capacitance as described above. It is possible to prevent deterioration of characteristics of light modulation in a high frequency region.

  Further, unlike the prior art shown in FIG. 7, it is not necessary to form the end of the signal electrode 14 (control unit 19) by curving to the side of the electro-optic device chip 10, so that the manufacture is facilitated. Conventionally, since the end portion of the signal electrode 14 (control unit 19) is curved toward the side of the element substrate 11, it has been necessary to increase the width of the chip. Since the end portion of 14 is not curved toward the side of the element substrate 11, the width of the chip can be narrowed, and the number of chips taken from one wafer can be greatly improved. In particular, in the case of a ridge type optical waveguide, the number of processes and processing time are increased, so that the cost effect is very large. In addition, since the electro-optical device chip 10 and the peripheral circuit can be mounted on one circuit board 30, the cost can be reduced.

  In addition, since the signal electrode 14 is formed in a straight line, that is, in a straight line shape, the transmission direction of the control signal does not change. Therefore, even when the element substrate 11 is made of an anisotropic material, the electrode design Will not be complicated. Further, unlike the conventional configuration in which the signal electrode 14 has a curved structure, it is possible to reduce deterioration and reflection of the high frequency response component. In addition, it is not necessary to route the signal electrode 14 on the electro-optic device chip 10, and the degree of freedom in designing the adjustment path for the phase difference of a plurality of signals is increased, and the length can be shortened, thereby improving the characteristics.

  The connection land portions 16A and 16B are set according to the connection method between the electro-optical device chip 10 and the circuit board 30, and have an appropriate width (thickness) and planar shape. As a result, at the time of connection by solder reflow, wire breakage due to melting with solder can be avoided, and the strict amount of solder, the allowable control range of temperature, etc. are alleviated, and application to mass production becomes easy.

  Further, since the signal electrode 14 has a G-CPW structure, simply widening the line width for connection to the circuit board 30 may cause impedance mismatch and increase in parasitic capacitance. There is a concern that the characteristics of the However, as in the present embodiment, the connection land portions 16A and 16B having a width wider than that of the signal electrode 14 are provided at both ends of the signal electrode 14, so that the signal electrode due to stress at the time of mounting the chip chip on the circuit board 30 is obtained. 14 deformation, collapse, etc. can be avoided. In addition, since the signal electrode 14 of the electro-optical device chip 10 and the circuit board 30 are directly connected via the connection land portions 16A and 16B, there is little room for excessive increase in parasitic capacitance.

The technical scope of the present invention is not limited to the above-described embodiment, and appropriate modifications can be made without departing from the spirit of the present invention.
For example, as shown in FIGS. 8 and 9, the connection land portions 216A and 216B may be further built up. In this case, the second low dielectric constant layer 212 is formed on the upper layer side of the low dielectric constant layer 12, and the connection land portions 216A and 216B and the surface side ground portion 216C are formed on the surface 212a of the second low dielectric constant layer 212. Has been.

  The connection land portions 216A and 216B are connected to the connection land portions 16A and 16B through contact holes 214A and 214B penetrating the second low dielectric constant layer 212. Similarly, the front surface side ground portion 216C is connected to the front surface side ground portion 16C through a contact hole 215C.

  Thus, by building up the connection land portions 216A and 216B in a hierarchical manner, the size of the connection land portions 216A and 216B can be increased. In this case, the dimension (W1 + W2 + W3) in the width direction of the opening 64 is the layer thickness D1 of the low dielectric constant layer 12 (see FIG. 9) and the layer thickness D2 of the second low dielectric constant layer 212 (see FIG. 9). May be larger. With this configuration in which the dimension (W1 + W2 + W3) in the width direction of the opening 64 is wide, the wraparound of the electric field tends to easily occur between the first ground electrode 15 and the surface side ground portion 16C. However, by taking the following configuration, the first ground electrode 15 formed between the low dielectric constant layer 12 and the surface side ground portion 16C It is possible to prevent the wraparound of the electric field from occurring. The layer thickness D1 of the low dielectric constant layer 12 is larger than the value of the width W2 (or W3) of the gap 65 (D1> W2 (or W3)). When the layer thickness D1 is smaller than the value of the width W2 (or W3) of the gap 65 due to circuit characteristic design convenience or manufacturing restrictions, the opening 15a of the first ground electrode 15 and the surface side ground The first ground electrode 15 is cut away so that the distance between the portion 16C and the opening 64 is larger than the width W2 (or W3).

  Further, for example, in the above embodiment, the configuration in which the connection land portions 16A and 16B are formed in a straight line has been described as an example, but the present invention is not limited to this. For example, as illustrated in FIG. 10, the connection land portions 16 </ b> A and 16 </ b> B may be formed in a bent state. In the configuration shown in FIG. 10, the two connection land portions 16 </ b> A are formed so as to extend in the longitudinal direction of the electro-optical device chip 10 while expanding in the lateral direction of the electro-optical device chip 10. According to this configuration, the distance between the connection land portions 16A can be increased, the pitch of the wiring interval is increased, and the connection with the external wiring circuit is simplified.

  For example, as illustrated in FIG. 11, the connection land portions 16 </ b> A and 16 </ b> B may be formed to extend from the position of the contact hole 14 </ b> A in the short direction of the electro-optic device chip 10. If this configuration is used for a device in which functional parts acting on a plurality of lights, such as a QPSK optical modulator, a 16QAM optical modulator, and an optical matrix switch, are integrated, the degree of freedom of the control signal wiring can be greatly increased. Can do. In particular, it is effective for layout design of the delay line. Furthermore, if the connection land portions 16A and 16B are folded back from the position of the contact hole 14A in the direction of the signal electrode 14, it is also effective for shortening the chip. The opening 64 is designed according to the arrangement of the connection land 16, but the opening 64 may not be provided in one section for convenience of wiring arrangement, or the opening 64 may include a narrow portion in one section. However, there is no practical problem as long as the one section has a length equal to or less than ¼ of the wavelength of the drive driving frequency of the device.

  Further, in the above-described embodiment, the configuration in which both ends in the extending direction of the signal electrode 14 are built up via the contact holes 14A and 14B has been described as an example, but the present invention is not limited to this, and the signal electrode 14 may be configured such that only one of the end portions is built up.

  Moreover, although the said embodiment gave and demonstrated the structure which builds up connection land part 16A, 16B and the surface side ground part 16C as an example, it is not restricted to this. For example, as shown in FIG. 12, only the connection land portions 16A and 16B may be selectively built up.

  In the configuration shown in FIG. 12, the low dielectric constant layer 312 is locally provided. Specifically, the low dielectric constant layer 312 is provided so as to cover both ends in the extending direction of the signal electrode 14. Contact holes 14A are respectively formed in the low dielectric constant layer 312, and connection land portions 16A and 16B are formed on the upper surface 312a of the low dielectric constant layer 312.

  According to this configuration, since the influence of the dielectric loss received from the low dielectric constant layer 312 by the control signal propagating through the signal electrode 14 (control unit 19) is reduced, the dielectric loss of polyimide or the like as the low dielectric constant layer 312 is relatively low. Large materials can be used. In addition, since the speed of the microwave hardly decreases, the degree of freedom in design is increased.

In the above, description has been given by taking LN as an example where the effect of the present invention is particularly high. However, the present invention is not limited to this. For example, ferroelectrics such as LiTaO ₃ , KH ₂ PO ₄ , PZT, PLZT, KTP, KTN, SrTiO 3, etc. Also effective in devices using high dielectric constant paraelectric crystals, electro-optic polymer materials containing CLD and FTC type dyes, semiconductors such as InP, GaAs, InGaAs, and strained Si, and composite materials thereof It goes without saying that.

  Further, for the sake of simplicity, the low dielectric constant layer 12 and the contact hole 14 have been described using the build-up wiring method. However, other methods can be used. For example, a low dielectric constant layer is once formed as a sacrificial layer from another material, and the low dielectric constant layer 12 or a part thereof is dissolved or dissolved in a solvent or corrosive during or after chip mounting. It is good also as a cavity by removing by methods, such as decomposition | disassembly by gas, mechanical peeling, grinding, ablation, and ultrasonic crushing. Further, the removed space may be replaced with another low-loss dielectric. Needless to say, in designing the characteristics, it is necessary to consider the electrical characteristics (dielectric constant, magnetic permeability, electrical conductivity, etc.) of the material in the final device form when designing characteristics. The same applies to the low dielectric constant layer 17 and the reinforcing substrate (holding substrate) 18.

  In each figure, in order to avoid complication of the figure, the display of the connection part of the grind electrode of the first electrode, the ground electrode of the second electrode, and the surface side ground electrode is omitted. These ground electrodes are connected to each other via via holes, through holes, a supporting housing, and the like.

DESCRIPTION OF SYMBOLS 10 ... Electro-optical device chip | tip 11 ... Element board | substrate 11a ... 1st surface 11b ... 2nd surface 12 ... Low dielectric constant layer 12a ... Surface 13a-13d ... Optical waveguide 14 ... Signal electrode 14A, 14B ... Contact hole 15 ... First ground Electrode 15a ... Opening 15C ... Contact hole 16A, 16B ... Connection land 16C ... Surface side ground part 19 ... Control part 21 ... First electrode 22 ... Second electrode 23 ... Second ground electrode 30 ... Circuit board 100 ... Light control element

Claims (7)

A circuit board provided with wiring electrodes;
An element substrate having a thickness of 10 μm or less made of a material having an electro-optic effect;
An optical waveguide formed on the element substrate;
A first electrode provided on one main surface side in the thickness direction of the element substrate;
A second electrode provided on the other main surface side of the element substrate,
The first electrode is a coplanar electrode composed of at least a signal electrode and a first ground electrode, and the signal electrode is connected to a control unit for controlling the phase of light passing through the optical waveguide and to the control unit. Consisting of the land part,
The connection land portion is built up at a position higher than the main surface of the element substrate, and a low dielectric constant layer having a dielectric constant lower than that of the element substrate is provided between the connection land portion and the main surface of the element substrate. Provided,
The second electrode has at least a second ground electrode and is arranged to apply an electric field to the optical waveguide in cooperation with the controller.
The connection land portion has a width wider than the electrode width of the control portion and is connected to the control portion, and electrically connects the control portion and the wiring electrode of the circuit board. A light control element characterized by the above.   The light control element according to claim 1, wherein the low dielectric constant layer is formed on a part of the element substrate so as to include a main surface of the element substrate facing the connection land portion.   The light control element according to claim 1, wherein the connection land portion is provided on at least one of longitudinal ends of the signal electrode.   4. The light control element according to claim 1, wherein a plurality of the signal electrodes are provided, and independent control signals are input to the plurality of signal electrodes. 5.   The said connection land part is a coplanar electrode type | mold, The space | interval of a center conductor and a ground electrode is smaller than the thickness of a low dielectric constant layer, The Claim 1 characterized by the above-mentioned. Light control element.   The connection land portion is a coplanar electrode type, and the layer of the first electrode corresponding to the position of the connection land portion has an opening having a width larger than the sum of the distances between the center conductor and the ground electrode of each portion. The light control element according to any one of claims 1 to 4.   The light control element according to claim 1, wherein the low dielectric constant layer is formed using a resin.

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