JP2014187605A - Operational amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that when a lateral bipolar transistor having insufficient amplification characteristics is used in the input element of an operational amplifier circuit, guarantee of frequency stability is difficult because of variation in the current amplification factor of a transistor due to manufacturing error or ambient temperature.SOLUTION: A compensation element having electrical characteristics identical to those of an input element generates a current inversely proportional to the current amplification factor of a transistor, and the first amplification stage, i.e., the differential input stage of an operational amplifier circuit, is biased by a tail current corresponding to this current. Consequently, the transconductance gm1 of the first amplification stage can be made constant regardless of the current amplification factor of a transistor, and an operational amplifier circuit having frequency stability and a low 1/f noise can be obtained.

Description

  The present invention relates to an operational amplifier circuit (OP amplifier) having a differential input stage using a bipolar transistor as an input element, and more particularly to a structure that compensates for a change in the current amplification factor of the transistor and improves frequency stability. It is about.

  Conventionally, arithmetic circuits using bipolar transistors as input elements have been proposed.

JP-A-7-57026 (page 5, FIGS. 4 to 7)

  The arithmetic circuit described in Patent Document 1 is an example of a multiplier circuit. 4 and 5 are drawings rewritten without departing from the content disclosed in Patent Document 1. FIG. In particular, Patent Document 1 gives an example in which a bipolar transistor that can be formed by a CMOS process is used as the bipolar transistor. FIG. 5 is a cross-sectional view when such a transistor is formed on a P-type substrate. In the bipolar transistor of FIG. 5, an N-well base 504 is formed on a P-type substrate 501, and an emitter 503 and a lateral collector 502 formed by implanting high-concentration P-type ions inside the region. It is a PNP transistor.

  The arithmetic circuit 40 in FIG. 4 is a multiplication circuit called a Gilbert cell in which two sets of differential circuits are combined. The PNP transistors 406 to 409 process the first input signal Vx, and the PMOS transistors 402 to 405 process the second input signal Vy, thereby outputting a signal obtained by multiplying these input signals.

  The arithmetic circuit 40 applies the exponential characteristic of a bipolar transistor to realize a multiplication function. Generally, a bipolar transistor has a low 1 / f noise as compared with a MOS transistor (MOSFET), and therefore has a low frequency. It is known that it is also useful for reducing noise during signal amplification.

  From this, it can be easily considered to use a bipolar transistor as an input element of the differential input stage of the operational amplifier circuit (OP amplifier). The differential input stage can be easily realized by invalidating the Vy input of the arithmetic circuit 40. For example, the two PMOS transistors 404 and 405 and the two PNP transistors 408 and 409 may be removed, and the source and drain of the two PMOS transistors 402 and 403 may be short-circuited. In this case, the PNP transistors 406 and 407 serve as input elements.

  In general, the operational amplifier circuit has a load driving output stage connected to the subsequent stage of the differential input stage, and has two or more amplification stages. However, if such a transistor is used in the input stage of the operational amplifier circuit, a problem arises in frequency stability, which is one of the important characteristics of the operational amplifier circuit.

  In order to explain this, FIG. 2 shows a block diagram modeling an operational amplifier circuit having two amplification stages. FIG. 3 shows a typical example of the frequency response characteristic of such an operational amplifier circuit.

  The operational amplifier circuit 20 in FIG. 2 is an amplifier circuit in which two amplifier stages, a first amplifier stage 21 and a second amplifier stage 22, are connected in series. Hereinafter, the first stage 21 and the second stage 22 are simply expressed.

When there are a plurality of amplification stages, it is general to perform compensation so as to obtain an appropriate phase margin by a so-called mirror compensation technique. Specifically, a phase compensation capacitor 207 is connected between the input and output of the second stage 22. In the operational amplifier circuit 20 thus phase-compensated, the unity gain frequency ωu (gain intersection) corresponding to the bandwidth is
ωu = gm1 / Cc
Is approximated by On the other hand, the non-major pole frequency ωp is
ωp = gm2 / Co
Is approximated by Here, gm1 is the value of the transconductance 201 of the first stage 21, gm2 is the value of the transconductance 202 of the second stage 22, Cc is the capacitance value of the phase compensation capacitor 207, and Co is the load capacitor 206 driven by the operational amplifier circuit 20. Capacity value.

  Here, the transconductance 201 (gm1) of the first stage 21 is equal to the transconductance gm itself of the input element in the differential input stage as described above.

In general, the transconductance gm of a bipolar transistor is
gm = IC / VT
It is represented by Here, IC is a collector current, and VT is a so-called thermal voltage. Also, the current amplification factor α of the grounded base of the transistor is the ratio between the collector current IC and the emitter current IE, that is, α = IC / IE
It is represented by It is clear that the transconductance gm is proportional to the current amplification factor α. Hereinafter, the current amplification factor described in the present application is the current amplification factor of the grounded base, and is different from the current amplification factor (IC / IB) of the grounded emitter.

  However, it is known that a low-performance bipolar transistor such as a lateral PNP transistor manufactured by a standard bipolar process has a small value of the current amplification factor α, and the value varies greatly due to manufacturing errors.

  On the other hand, a bipolar transistor as shown in Patent Document 1 that can be formed by a standard CMOS process is not only used as a collector current IC flowing out from the lateral collector 502 but also into a substrate 501 acting as a parasitic collector as shown in FIG. Since the parasitic collector current IC ′ flows, the collector current IC that contributes to a substantial amplification operation is much smaller than the emitter current IE. That is, the value of the current amplification factor α is smaller than 1, and the value easily changes depending on the manufacturing process and the ambient temperature.

  When the current amplification factor α changes, the collector current IC changes even if the emitter current IE is constant, so that the transconductance gm also changes. Therefore, the unity gain frequency ωu of the operational amplifier circuit also changes.

  For example, when the current amplification factor α is a typical value and the gain characteristic ga shown in FIG. 3 is designed, when the current amplification factor α changes in the increasing direction, the first stage 21 Since the transconductance 201 (gm1) is increased, the gain characteristic gb is obtained, and the phase margin is reduced as θ (b) shown in FIG. If the phase margin is not sufficient, there is a problem that oscillation easily occurs when the feedback rate is large.

  If the current gain α can be predicted and the maximum gain characteristic ga can be designed, the transconductance of the first stage 21 is changed when the current gain α changes in a decreasing direction. Since 201 (gm1) becomes small, the gain characteristic gc is obtained, and although the phase margin is improved as θ (c), another problem arises that the bandwidth is reduced as ωu (c). As a workaround, there is a method of sufficiently increasing the pole frequency ωp. For this purpose, however, the transconductance 202 (gm2) of the second stage 22 must be increased, and as a result, the power consumption in the output stage is extremely high. It gets bigger.

  Thus, it can be said that it is very difficult to optimally design an operational amplifier circuit that changes the unity gain frequency ωu.

  An object of the present invention is to solve the above problems and to provide an operational amplifier circuit with low noise without impairing frequency stability or bandwidth.

  The operational amplifier circuit of the present invention employs the following configuration.

An operational amplifier circuit having a plurality of amplification stages, wherein the input element of the first amplification stage is composed of bipolar transistors,
A compensation current generating circuit having a compensation element composed of a bipolar transistor having the same electrical characteristics as the input element;
The compensation current generation circuit generates a compensation current that is inversely proportional to the base ground current amplification factor α of the input element based on the compensation element.
By biasing the first amplification stage with a bias current corresponding to the compensation current, the bandwidth becomes constant.

  The operational amplifier circuit of the present invention generates a compensation current that is inversely proportional to the current amplification factor α, using a compensation element having the same electrical characteristics as the input element that is a bipolar transistor. By biasing the differential input stage, which is the first amplification stage of the operational amplifier circuit, with a current based on this compensation current, the transconductance gm1 of the differential input stage is controlled to be constant. Thereby, even if the current amplification factor α changes, the unity gain frequency ωu of the operational amplifier circuit can be controlled to be constant, and a stable frequency response characteristic can be realized.

  The compensation current generation circuit may generate the compensation current so that the compensation current is proportional to the ambient absolute temperature.

  According to such an operational amplifier circuit, the influence of the transconductance gm of the input element, which is a bipolar transistor, being inversely proportional to the absolute temperature T can be compensated by controlling the compensation current to be proportional to the absolute temperature. it can. That is, the operational amplifier circuit of the present invention can cancel the influence of the change in ambient temperature on the frequency response characteristics of the operational amplifier circuit.

  The second and subsequent amplification stages may be constituted by MOSFET circuits that are biased independently of the first amplification stage.

  According to such an operational amplifier circuit, the first and subsequent amplifications are performed so that the change in the bias state of the first amplification stage caused by the transistor current amplification factor compensation operation does not affect the subsequent amplification stage. By biasing the stages independently, it is possible to configure all the subsequent stages from the first with MOS elements. For this reason, it becomes easy to mount a CMOS circuit having high compatibility with a digital circuit and a high degree of design freedom.

  According to the operational amplifier circuit of the present invention, it is possible to dynamically compensate for the influence of the manufacturing error of the current amplification factor of the bipolar transistor that is the input element, the change of the ambient temperature, and the like.

  Therefore, a low noise operational amplifier circuit can be realized without impairing performance such as frequency stability, bandwidth, and power consumption. Since this compensation operation is performed dynamically, there is an effect that portability to a different semiconductor manufacturing process is high.

It is a circuit diagram explaining the structure of the operational amplifier circuit which is embodiment of this invention. It is a block diagram that models an operational amplifier circuit having two amplification stages. It is a diagram explaining the frequency response characteristic of the transfer function of an operational amplifier circuit. FIG. 10 is a circuit diagram illustrating an arithmetic circuit using the bipolar transistor disclosed in Patent Document 1 as an input stage. It is sectional drawing explaining the structure of the bipolar transistor which can be manufactured with a standard CMOS process.

  The best mode for realizing the operational amplifier circuit of the present invention will be described below with reference to the drawings.

[Overall structure description: FIGS. 1 and 5]
First, the overall configuration of the operational amplifier circuit will be described with reference to FIG. 1 and FIG.
The operational amplifier circuit 10 is an operational amplifier circuit composed of a differential input stage circuit 11 and an output stage circuit 12 and having two amplifier stages. Further, a compensation current generation circuit 14 for compensating for the electrical characteristics of the differential input stage circuit 11 is provided.

  In the differential input stage circuit 11, a tail current source on the power source V + side is configured by a PMOS transistor 101, input elements 102 and 103 are configured by PNP transistors having uniform electrical characteristics, and load elements are configured by NMOS transistors 104 and 105. And a cascode circuit connected to the differential amplifier circuit. As the input elements 102 and 103, bipolar transistors that can be manufactured by the standard CMOS process shown in FIG. 5 are used.

  The differential input stage circuit 11 forms a cascode circuit on the power supply V + side with the PMOS transistors 121, 122, 123, and 124, and forms a cascode circuit on the power supply V− side with the NMOS transistors 125, 126, 127, and 128. . Bias circuits 131 and 132 are connected so as to be sandwiched between these cascode circuits.

  The bias circuits 131 and 132 perform the class AB bias with the output stage circuit 12 to be subsequently connected as a common source amplifier circuit. Since these bias circuits are general, a detailed description of the configuration is omitted. The amplification stage included in the operational amplifier circuit 10 corresponds to the first amplification stage. Hereinafter, this amplification stage is also simply referred to as the first stage.

  The NMOS transistors 104 and 127 have their drains in common, and the NMOS transistors 105 and 128 also have their drains in common, so that the differential input stage circuit 11 is configured as a so-called folded cascode amplifier circuit.

The PMOS transistors 123 and 124 and the NMOS transistors 125, 126, 127, and 128 can function as cascode circuits by biasing the gate potential with a well-known MOS transistor bias circuit (not shown). .

  The output stage circuit 12 is an output buffer having an amplification function. This corresponds to the second amplification stage as the amplification circuit included in the operational amplifier circuit 10.

  The output stage circuit 12 is composed of a PMOS transistor 133 and an NMOS transistor 134 and a complementary source ground amplifier circuit. The drains of these transistors are common and serve as the output terminal OUT of the operational amplifier circuit 10. Capacitors 135 and 136 are respectively connected between the gates and drains of the transistors 133 and 134 to form so-called mirror capacitors so that a phase compensation effect can be obtained.

  The compensation current generation circuit 14 as a further constituent element is a circuit that generates a compensation current Ix that is composed of a compensation element 142 that is a PNP transistor and a circuit that generates a current proportional to the absolute temperature T (so-called PTAT current). It is.

  The PTAT circuit 140 is configured to operate so that the reference current I0 is equal to the current value obtained by multiplying the compensation current Ix by the current amplification factor α when the PTAT current flowing therethrough is the reference current I0. In order to realize this multiplication function, the compensation current generation circuit 14 includes a PMOS transistor 141, a compensation element 142, which is a PNP transistor, and an NMOS transistor 143, which are connected in cascade.

  The current mirror path by the NMOS transistor 144, the PMOS transistor 145, and the PMOS transistor 146 is for the current flowing through the PTAT circuit 140 to be equal to the reference current I0 obtained by multiplying the compensation current Ix by the current amplification factor α. . That is, a copy current of the current flowing through the NMOS transistor 143 is supplied from the PMOS transistor 146 and supplied to the PTAT circuit 140. Since the compensation current Ix is the emitter current of the compensation element 142 and the reference current I0 is equal to the collector current of the compensation element 142, the reference current I0 is a value obtained by multiplying the compensation current Ix by the current amplification factor α. Is clear from the definition.

  The compensation current Ix is a current that flows through the PMOS transistor 141, and is configured such that a constant multiple copy current of the compensation current Ix becomes the drain current of the PMOS transistor 101, that is, the tail current of the differential input stage circuit 11. The PMOS transistors 141 and 101 have a current mirror configuration, and the gate voltage VB1 is shared in order to generate a copy current.

  The reference current I0 is equal to the current flowing through the NMOS transistor 143, and a constant multiple copy current of the reference current I0 biases the drain currents of the NMOS transistors 104 and 105, that is, the collectors of the two input elements 102 and 103. Configure. The NMOS transistors 143, 104, and 105 also have a current mirror configuration, and the gate voltage VB2 is shared in order to generate a copy current. With this configuration, the NMOS transistors 104 and 105 can draw currents that are exactly α / 2 times the tail current of the differential input stage circuit 11, respectively.

  The base of the compensation element 142 is a common terminal COM. This is a terminal for applying in-phase level signals of input signals connected to the two input elements 102 and 103 through the same impedance. Thereby, the compensating element 142 can be brought into an electrical state close to the two input elements 102 and 103, and the accuracy of the compensating operation of the compensating current generating circuit 14 can be improved. In a typical example, the common terminal COM is fixed to the signal ground level.

  As the compensation element 142, an element having the same electrical characteristics such as voltage-current characteristics as the input elements 102 and 103 is used. Simply, elements having the same electrical characteristics can be obtained by forming elements having the same planar shape and the same impurity concentration and implantation depth at close positions. This can be realized by a known pattern layout method.

  The PTAT circuit 140 itself includes a reference resistor 151, resistors 152 and 153, PNP transistors 154 and 155, and a differential amplifier 156. The PTAT circuit 140 is a circuit that applies the property that the forward voltage difference generated when currents are passed through two diodes with different current densities is proportional to the absolute temperature T. Here, diode-connected PNP transistors 154 and 155 are used as diodes, and the emitter areas are different in order to make a difference in current density. The reference resistor 151 is for detecting the voltage difference.

  The differential amplifier 156 drives the gate of the PMOS transistor 141 so as to generate a compensation current Ix necessary for flowing an equal current to the PNP transistor 155 and the PNP transistor 154 having a larger emitter area. The PTAT circuit 140 Connect to form a feedback system to function.

[Overall operation description: FIGS. 1 and 3]
Next, the operation of the operational amplifier circuit will be described with reference to FIGS.

  When the operational amplifier circuit 10 is powered on, the PTAT circuit 140 is fed back and becomes stable. In this stable state, a reference current I0 proportional to the absolute temperature T flows to the PMOS transistor 146.

When the resistance value of the reference resistor 151 is R1, the drain current flowing through the PMOS transistor 145 that supplies current to the PTAT circuit 140, that is, the reference current I0 can be expressed as follows.
I0 = VT.Ln (n) / R1
Here, n is an emitter area ratio between the PNP transistors 154 and 155, and Ln is a natural logarithmic function. Since VT is a so-called thermal voltage and is proportional to the absolute temperature, that is, the reference current I0 is proportional to the absolute temperature T.

However, the reference current I0 has a current value obtained by multiplying the compensation current Ix by the current amplification factor α. In other words, the compensation current Ix is proportional to the ambient absolute temperature T and is inversely proportional to the current amplification factor α. That is, Ix ∝ T / α
It is.

Thus, a current obtained by copying the compensation current Ix generated by the compensation current generation circuit 14 becomes the tail current of the differential input stage circuit 11. This tail current supplies current to the input elements 102 and 103. Since the transconductance gm1 of the differential input stage circuit 11 is the transconductance gm of the input elements 102 and 103,
gm1 = IC / VT
= Α ・ IE / VT
∝ α ・ Ix / T
From the relationship of the compensation current Ix described above, it can be seen that the transconductance gm1 of the differential input stage circuit 11 is controlled so as not to depend on the ambient temperature and the current amplification factor α.

  If the transconductance gm1 of the differential input stage circuit 11 does not depend on the ambient temperature and the current amplification factor α, the unity gain frequency ωu of the operational amplifier circuit 10 is also constant regardless of the ambient temperature and the current amplification factor α.

  By the compensation operation of the differential input stage circuit 11 described above, the current biased to the emitters of the two input elements 102 and 103 varies depending on the current amplification factor α, but the collector current is independent of the current amplification factor α. To be biased. Since this bias current is just drawn by the NMOS transistors 104 and 105, only the current signal component generated by the change of the input signal is sent to the subsequent cascode circuit. Since the cascode circuit and the output stage circuit 12 are biased independently of the differential input stage circuit 11, the operating point of the output stage circuit 12 does not change, and its transconductance gm2 is constant. Therefore, as in the conventional operational amplifier circuit, if the value Co of the load capacitor 206 connected to the output terminal of the operational amplifier circuit 10 is fixed, the polar frequency ωp does not change.

  Therefore, since the ratio between the unity gain frequency ωu and the polar frequency ωp is constant, the operational amplifier circuit 10 can be designed to ensure the frequency stability. In FIG. 3, this corresponds to the fact that the characteristic indicated by the gain characteristic ga is always obtained regardless of the change in the current amplification factor α.

  Moreover, since the input elements 102 and 103 of the differential input stage circuit 11 use bipolar transistors, the input conversion noise of the operational amplifier circuit 10 is small. In particular, the 1 / f noise component is extremely small as compared with the MOS transistor, and it is clear that the effect of being suitable for an application that amplifies a low-frequency signal is maintained.

  As can be seen from the above description, according to the operational amplifier circuit of the present invention, a low-noise operational amplifier circuit can be realized without impairing frequency stability and bandwidth.

  In the embodiment of the present invention described above, a bipolar transistor that can be formed by a standard CMOS process is used as an input element. However, the present invention is not limited to this. For example, the present invention can be applied in the same manner even when an element such as a lateral PNP transistor that can be formed by a standard bipolar process but has insufficient performance is used as an input element.

In the above-described embodiment of the present invention, the reference current I0 and the compensation current Ix are proportional to the absolute temperature as shown in FIG. 1, but the present invention is not limited to this.
The transconductance gm1 of the differential input stage circuit 11 depends on the ambient temperature and the current amplification factor α of the input elements 102 and 103 or the compensation element 142. However, if the change in the ambient temperature is slight, the transconductance gm1 can ignore the influence of the temperature, and the PTAT circuit 140 is not necessary. In such a case, the PTAT circuit 140 can be replaced with a circuit that operates as a simple constant current source.

  Since the operational amplifier circuit of the present invention has low 1 / f noise, it can amplify a low-frequency minute analog signal. For example, it is suitable for applications that detect minute signals, such as angular velocity sensors and pressure sensors.

DESCRIPTION OF SYMBOLS 10 Operation amplification circuit 11 Differential input stage circuit 12 Output stage circuit 14 Compensation current generation circuit 20 Operation amplification circuit 40 Operation circuit 50 Bipolar transistor 102, 103 Input element 140 PTAT circuit 142 Compensation element

Claims (3)

An operational amplifier circuit having a plurality of amplification stages, wherein the input element of the first amplification stage is composed of bipolar transistors,
A compensation current generation circuit having a compensation element composed of a bipolar transistor having the same electrical characteristics as the input element;
The compensation current generation circuit generates a compensation current inversely proportional to the base ground current amplification factor α of the input element based on the compensation element,
An operational amplifier circuit characterized in that the bandwidth becomes constant by biasing the first amplification stage with a bias current corresponding to the compensation current. The operational amplifier circuit according to claim 1, wherein the compensation current generation circuit generates the compensation current so that the compensation current is proportional to an ambient absolute temperature. 3. The operational amplifier circuit according to claim 1, wherein the second and subsequent amplification stages are configured by a MOSFET circuit that is biased independently of the first amplification stage.

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