JP2014187297A - Formation method of semiconductor device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a conductive member from a hole bottom without forming a void even for power feeding from an opening part surface layer continuing in a through-hole when forming the conductive member in the through-hole by an electrolytic plating method.SOLUTION: Plating is grown from a hole bottom by electrolytic plating in which power is fed from a surface conductive layer by covering with an insulator layer a portion other than part of a through-hole bottom surface of a power feeding layer continuing from a through-hole opening part surface into the through-hole.

Description

  The present invention relates to a method for forming a conductive member in a through hole of a semiconductor substrate and a semiconductor device.

  Conventionally, a structure in which a conductive layer is formed in a through hole having a large aspect ratio formed in a substrate (hereinafter, a hole opened on one side is referred to as a through hole) has been used as a through electrode for stacking substrates.

  Various methods for forming such a conductive layer have been proposed, but a plating method is often used.

  However, in forming a conductive layer by plating, voids (voids) are likely to be generated in the through holes.

  If a void remains in the through hole, the air or liquid inside the void expands when the temperature rises, and the element is destroyed by bursting.

  In addition, air and liquid inside the void repeat expansion and contraction due to a temperature history such as heating and cooling, causing cracks and the like in the through electrode portion, resulting in poor electrical conduction.

  In order to perform good plating without generating voids in the through-holes, plating current control that uses accelerators and inhibitors and plating current value that slows or changes the plating current value in two stages There are known methods.

  In addition, a method related to plating agitation that creates a flow parallel to the substrate surface and circular vibration, a method that adsorbs the accelerator only in the hole as a pretreatment for plating, and a method that devises the shape of the opening and through hole are proposed. Has been.

  Voids in the through hole are generated when the vicinity of the through hole opening is closed before the conductive layer sufficiently wraps around the through hole.

  The following method is known as a method of forming a conductive layer with good contact with the bottom of the through hole without blocking the vicinity of the opening of the high aspect through hole.

One of the methods relating to the plating solution is a method of adding an additive such as polyethylene glycol to the plating solution.
A method is known in which the resin component of polyethylene glycol is adsorbed to a portion where the electric field near the opening is concentrated, thereby suppressing plating near the opening and preventing the opening from being blocked.

  Also, as one of the methods related to plating current control, when plating through holes with high aspect ratio, the plating solution in the through-holes can be controlled against the plating growth rate by plating at a current density smaller than the current density when plating on a flat surface. Methods for improving the exchange rate and improving the throwing power are known.

JP 2004-315889 A

  However, as a result of investigations by the present inventors, it has been found that the conventional configuration described above causes problems in the following points.

  In the method using an additive, the present inventors examined a gold plating solution which is the most stable and desirable metal in terms of electrical reliability related to resistance and chemical reliability related to corrosion.

  Various studies have been made on copper plating and the effect has been confirmed, but not much has been done on gold plating.

  The gold plating solution is divided into a cyan bath and a non-cyan bath.

  Since the gold cyanide plating solution which is a cyan bath is a very stable solution, most of the gold plating solutions generally used in this technical field are gold cyanide plating solutions.

  However, since the gold cyanide plating solution is very stable, the effect of the additive is hardly obtained, and the fact is that it is not used for high aspect through-hole plating as intended by the present invention. is there.

  First, when the gold cyanide plating solution was plated at the recommended current density, the effect of the additive could not be confirmed, and the opening was closed before the through hole was plated.

  In addition, when a non-cyan bath was examined, the liquid state of the non-cyan bath is very unstable, and the pH and other balances are easily lost. It was found that defects occurred.

  In addition, there was a problem in that the life of the plating solution until the plating failure occurred was significantly shortened.

  In the other plating current control method, when plating was performed at 1/10 or less of the recommended current density, the timing until the opening was blocked was delayed, but the generation of voids could not be eliminated. It was.

  This defect of void generation due to the opening being blocked before the inside of the hole is sufficiently plated becomes more prominent as the opening diameter becomes smaller, and becomes more noticeable as the aspect ratio becomes larger.

    As the semiconductor chip is miniaturized, the through-hole diameter further decreases, and the ratio of the hole depth to the open diameter, that is, the aspect ratio also increases.

  Even in such a situation, when it is desired to flow a large amount of current, and to reduce the resistance, it is necessary to increase the cross-sectional area of the conductive member in the through hole and make the conductive member thicker.

  For this purpose, a conformal shape in which the conductive layer is formed in a uniform thickness along the hole wall hole bottom, but a structure in which the entire hole is filled with the conductive member is required.

If an attempt is made to fill the inside of a through electrode having a small diameter and a high aspect ratio with a conductor using a method by conformal plating, the problem of void generation remains as it is, and more prominently.
FIG. 4 is a schematic cross-sectional view showing an example in which the through hole opening is closed by the conventional technique.

  The present invention solves the above-mentioned problems of the prior art, and enables formation of a conductive member in a small diameter, high aspect through hole, no void generation, improved reliability, and formation of a conductive member in the through hole. A method and a semiconductor device are provided.

The present invention which achieves the above-described problems
Having a conductive layer on one side of the semiconductor substrate;
Having a through hole penetrating from the other surface of the semiconductor substrate to the conductive layer;
A method of manufacturing a semiconductor device having a conductive member electrically connected from the other surface to the conductive layer,
In the through hole, forming a power supply layer reaching the conductive layer from the other surface, and leaving a part of at least one of the conductive layer or the power supply layer on the bottom surface of the through hole, Forming an insulating layer covering the electricity supply layer; supplying electricity to the electricity supply layer; and growing a plating from at least one of the exposed electrically conductive layer or the electricity supply layer; Forming in the through hole;
A method for manufacturing a semiconductor device, comprising:

  According to the manufacturing method according to the present invention, electricity is supplied to the electricity supply layer, and plating is grown from a part of at least one of the exposed conductive layer or the electricity supply layer. When forming by the electrolytic plating method, it is not necessary to use the electrode pad at the bottom of the through electrode hole connected to the element wiring or the GND wiring, that is, the conductive layer at the bottom of the through hole.

  Further, it is possible to supply a plating current from the surface of the substrate formed simultaneously with the inner surface of the through hole, that is, the electric supply layer on the opening surface of the through hole.

  In addition, it is possible to perform plating without worrying about restrictions on the element wiring and GND wiring formed on the conductive layer side of the bottom of the through hole, and conversely without worrying about restrictions on power supply during plating. Free layout of element wiring and GND wiring is possible.

  Further, since the location where current flows in contact with the plating solution is only the bottom surface of the through hole, the opening grows from the bottom of the hole without being blocked by plating, and no void is generated in the through hole.

  At the same time, since plating growth occurs only from the bottom of the hole, even if a current is passed at a large current density close to the limit current of the plating solution characteristics, the opening is not blocked, the plating speed is increased, and the plating time is shortened. It becomes possible.

  In addition, as a part of at least one of the exposed conductive layer or electric supply layer, a step of exposing at least 1/4 of the area of the bottom surface, and the electric supply layer on the side surface of the through hole from the bottom surface to the opening direction of the through hole By including the step of exposing 1/2 or less of the shortest length in the short side direction of the bottom surface, if the insulating layer near the bottom of the through hole is within the covering range, the same effect as described above can be obtained and the yield can be improved.

  In particular, when the plating grows from the side surface of the through hole, the plating speed under the hole is also increased.

  In addition, by using paraxylylene resin (hereinafter also referred to as parylene (registered trademark)) that is excellent in throwing power to minute uneven portions, it is possible to form a uniform and highly reliable insulating film in the through hole.

  In addition, by using gold (Au), which is excellent in chemical resistance and corrosion resistance (ink resistance), the conductive member is not attacked by liquids such as alkaline ink, and the reliability is high and the resistance is low. A through electrode having good thermal conductivity can be formed.

  In addition, gold (Au) has a good familiarity with living bodies and can be safely used for medical MEMS.

  In addition, by forming a Ti layer on Al that is generally used for the conductive layer at the bottom of the through hole that is the electrode pad at the bottom of the through electrode hole, it functions as a barrier layer and prevents migration with Au as the conductive member It becomes possible to do.

  In addition, when an insulating layer (paraxylylene resin) is formed on the outermost wall in the through hole or the semiconductor substrate surface layer to improve insulation, it functions as an adhesion layer by forming a Ti layer in contact with the insulating layer. .

  Further, by improving the adhesion with the insulating layer, it is possible to prevent peeling of the conductive member or the like formed thereon.

  Further, by using Au for the electricity supply layer, it is possible to reduce the resistance as the electricity supply layer, and it is possible to improve the adhesion of the conductive member to Au by electrolytic plating.

  In addition, according to the semiconductor device of the present invention, the insulating layer covering the electric supply layer except for at least one part of the conductive layer or the electric supply layer on the bottom surface of the through hole, and further exposed conductive layer or Since the through hole has a conductive member in contact with at least one part of the electricity supply layer, it is possible to uniformly supply plating current from the electricity supply layer on the surface of the hole opening formed continuously with the inner surface of the through hole. It becomes.

  Further, even when a current is passed at a high current density, the opening can be grown from the bottom of the hole without being blocked by plating, so that the plating speed is increased and the plating time can be shortened.

  In addition, at least one of the conductive layer and the electric supply layer that is not covered with the insulating layer has an area at least a quarter of the area of the bottom surface, and the electric supply layer that is not covered with the insulating layer on the side surface of the through hole If the insulating layer in the vicinity of the bottom of the through hole is within the covering range, the length in the direction from the bottom surface to the other surface is ½ or less of the shortest shortest length of the bottom surface. The effect is obtained and the yield is improved.

  In particular, when the plating grows from the side surface of the through hole, the plating speed under the hole is also increased.

  In addition, by forming the insulating layer with paraxylylene resin, it is possible to form a uniform and highly reliable insulating film in the through electrode hole.

  In addition, by using gold (Au), which is excellent in chemical resistance and corrosion resistance (ink resistance), the conductive member is not attacked by liquids such as alkaline ink, and the reliability is high and the resistance is low. A through electrode having good thermal conductivity can be formed.

  Further, by forming the electricity supply layer at least one of titanium (Ti) and gold (Au), it is possible to prevent migration between the Al electrode pad at the bottom of the through electrode hole and Au.

  In addition, the adhesion with the insulating layer is improved by forming the Ti layer, and the resistance as the electric supply layer can be lowered by forming the Au layer.

1 is a cross-sectional view showing a state where a SiO ₂ thermal oxide film 6 and a conductive layer 5 are formed on one surface of a semiconductor substrate 1. 2 is a cross-sectional view showing a state in which a resist 7 for forming a through hole in a semiconductor substrate 1 is formed by mask patterning. FIG. 2 is a cross-sectional view showing a state in which a through hole 8 is formed in a semiconductor substrate 1. FIG. FIG. 5 is a cross-sectional view showing a state in which a mask pattern is formed with a resist 7 except for an opening of a through hole 8, the SiO ₂ thermal oxide film 6 on the bottom surface of the through hole 8 is removed, and a conductive layer 5 is exposed. 3 is a cross-sectional view showing a state in which a parylene insulating layer 10 is formed on the other surface of the semiconductor substrate and the inner surface of the through hole 8. FIG. FIG. 6 is a cross-sectional view showing a state in which a portion other than the opening of the through hole 8 is mask-patterned with a resist 9, the parylene insulating layer 10 at the bottom of the hole is removed, and the conductive layer 5 is exposed. FIG. 3 is a cross-sectional view showing a state in which the electricity supply layer 2 is formed on the other surface of the semiconductor substrate and the inner surface of the through hole 8. 3 is a cross-sectional view showing a state in which an insulating layer 3 is formed on the electricity supply layer 2. FIG. FIG. 5 is a cross-sectional view showing a state in which a portion other than the opening of the through hole 8 is mask-patterned with a resist 9, the insulating layer 3 at the bottom of the through hole 8 is removed, and the electricity supply layer 2 is exposed. It is sectional drawing which shows the state which electroplated and formed the electrically-conductive member 4 from the bottom face of the through-hole 8 to the opening part vicinity by supplying electricity to the electric supply layer 2, and performing electroplating. FIG. 3 is a cross-sectional view showing a state where an insulating layer 3 on the surface of a semiconductor substrate 1 is removed and an electricity supply layer 2 is exposed. It is sectional drawing which shows the state (penetration electrode which concerns on Example 1 of this invention) in which the electroconductive member 4 was further electroplated also on the surface of the semiconductor substrate. It is sectional drawing which shows the state which is performing the electroplating from a bottom face in the state which the electric supply layer 2 of the side surface of the through-hole 8 exposed only length L1 from the bottom face. It is sectional drawing which shows the state (penetrating electrode which concerns on Example 2 of this invention) in which the electrically-conductive member 4 was formed to the semiconductor substrate 1 surface. It is sectional drawing which shows the state which is performing the electroplating from a hole bottom in the state which the electric supply layer 2 of the side surface of the through-hole 8 exposed only length L3 from the bottom face. 2 is a cross-sectional view showing a state in which a conductive member 4 is formed up to the surface of a semiconductor substrate 1. FIG. FIG. 6 is a cross-sectional view showing a state where the electric supply layer 2 on the bottom surface of the through hole 8 is exposed from between the insulating layers 3 by an area corresponding to the length d1 (through electrode according to Example 3 of the present invention). It is sectional drawing which shows the state which removed the insulating layer 3 of the bottom face by forming overhang so that the resist 9 may be opened smaller than opening shape. It is sectional drawing explaining the plating method which concerns on the prior art of this invention.

  According to the present invention, when the conductive member in the through electrode is formed by the electrolytic plating method, first, the surface of the semiconductor substrate that becomes the through hole opening surface for forming the through electrode and the inner surface of the through hole in which the through electrode is formed are formed. A seed layer is formed that serves as an electricity supply layer during electroplating.

  Next, an insulating layer is formed on the electricity supply layer formed on the surface of the semiconductor substrate and the inner surface of the hole.

  Further, after masking the insulating layer other than the through hole opening using patterning by photolithography, the insulating layer on the bottom surface of the through hole is removed by etching from the through hole opening not masked.

  As a result, the electricity supply layer on the bottom surface of the through hole is exposed, and a configuration in which current flows only in this portion, that is, a configuration that is a point of the present invention is completed.

  Since the surface of the semiconductor substrate and the inner side surface of the through hole are covered with an insulating layer, no current flows and plating does not grow.

  The electricity supplied from the electricity supply layer on the surface of the semiconductor substrate reaches the bottom surface of the through hole through the electricity supply layer.

  Only the exposed electricity supply layer portion that is not covered with the insulating layer on the bottom surface of the through hole comes into contact with the plating solution, and a current flows.

  Therefore, it is possible to grow the plating only from the bottom surface of the through hole, and no void is generated because the plating growth is from one direction.

  In addition, since there is no plating growth from the side surface near the opening of the through hole, the opening is not blocked, and the plating growth is only from the bottom surface. Therefore, it is possible to increase the current density and increase the plating growth rate, thereby reducing the plating time. It can be made shorter.

As described above, by taking a form in which plating grows only from the bottom surface of the through hole, it is possible to form a conductive member without generating voids in the through hole.
The above embodiment will be described in detail with reference to the drawings.

  FIG. 1-1 is a cross-sectional view showing Embodiment 1 of the through electrode which is the semiconductor device of the present invention.

  A parylene insulating layer made of a paraxylylene resin material continuous from the surface of the semiconductor substrate 1 to the inner surface of the through hole 8 is provided on the outermost periphery of the through hole 8 formed in the semiconductor substrate 1 in order to maintain electrical insulation with the semiconductor substrate 1. 10 is formed.

  An inside of the parylene insulating layer 10 is formed with an electricity supply layer 2 for flowing electricity at the time of electrolytic plating, and covers the electricity supply layer 2 other than the bottom surface in order to allow current to flow only from the bottom surface of the through hole 8. 3 is formed.

  A conductive member 4 grown by electrolytic plating is formed from the bottom surface.

A conductive layer 5 serving as an electrode pad is formed on the bottom surface of the through hole 8, and SiO ₂ thermal oxidation for maintaining insulation between the semiconductor substrate 1 and the conductive layer 5 around the lowermost part of the through hole 8. A film 6 is formed.

  Hereinafter, the through electrode will be described along its manufacturing process.

  First, FIG. 1A shows a semiconductor substrate on which a through electrode is formed.

  As a material of the semiconductor substrate 1, silicon is generally used, and a substrate having specifications adjusted to a desired resistance value is used.

On one surface of the semiconductor substrate 1, a SiO ₂ thermal oxide film 6 is formed as an insulating layer for maintaining insulation. As such an insulating layer, a SiN film or the like can also be used.

  Next, a conductive layer 5 serving as an electrode pad is formed at a portion constituting the bottom of the through electrode. As a material for the conductive layer, an Al layer is generally used. Other conductive materials can be used, but the metal material to be laminated thereafter is a material that does not cause problems such as migration.

  Next, as shown in FIG. 1B, the semiconductor substrate 1 is mask-patterned with a resist 7 at a portion that becomes an opening of the through hole 8.

  Thereafter, as shown in FIG. 1-c, the through holes 8 are formed by etching silicon using ICP-RIE (inductively coupled plasma type reactive ion etching) called a Bosch process.

When the etching proceeds to the bottom of the hole, the SiO ₂ thermal oxide film 6 is exposed, and the etching in the depth direction stops there.

However, if the etching is further advanced, the etching proceeds in the lateral direction along the SiO ₂ thermal oxide film 6, so that the etching is terminated by adjusting the conditions.

  If the etching proceeds in the lateral direction, the side surface near the bottom of the through hole 8 is swelled in a drum shape, and when forming a conductive layer to be an electric supply layer, a shadowed portion is formed on the side surface of the through hole 8 and the wire breaks. It becomes a state.

Next, as shown in FIG. 1-d, the SiO ₂ thermal oxide film 6 is etched using the resist 7 having the same pattern as that of silicon etching, so that the Al layer of the conductive layer 5 is exposed.

  Further, as shown in FIG. 1-e, the parylene insulating layer 10 is deposited on the entire surface of the substrate and the through hole. This ensures higher insulation between the substrate and the through electrode.

  Next, as shown in FIG. 1-f, the bottom surface of the through-hole 8 of the parylene insulating layer 10 is formed from the opening of the resist 9 that has the same pattern as the inner diameter of the parylene insulating layer 10 deposited on the inner surface of the through-hole 8. Etching is removed to expose the conductive layer 5.

  Further, as shown in FIG. 1-g, the electricity supply layer 2 is formed on the other surface of the semiconductor substrate 1 and the inner surface of the through hole 8.

  The electricity supply layer 2 is a barrier layer for the conductive layer 5 exposed on the bottom surface of the through hole 8 and is also a seed layer for the subsequent electrolytic plating.

  Using a vapor deposition method called a sputtering method or an ion plating method, vapor deposition is performed on the inner surface of the through hole by vertical incidence and oblique incidence.

  As the electric supply layer 2, first, titanium (Ti) as a barrier layer is vapor-deposited, and then gold (Au) as a plating seed layer is vapor-deposited.

  Au also plays a role in preventing oxidation of Ti.

  Next, as shown in FIG. 1-h, the insulating layer 3 for growing the plating only from the bottom surface of the through hole 8, that is, for preventing the current from flowing except for the bottom of the hole, first penetrates the hole opening surface and Vapor deposition is performed on the inner surface of the hole 8 by a method such as CVD.

  As this second insulating layer, paraxylylene resin is used.

  Paraxylylene resin is excellent in throwing power to minute irregularities.

  Further, as shown in FIG. 1-i, in order to expose the electric supply layer 2 on the bottom surface of the through hole 8, the resist 9 is subjected to mask patterning except for the opening portion of the through hole 8, and is dried from the opening portion of the resist 9. The insulating layer 3 on the bottom surface of the through hole 8 is removed using an etching method to expose the electricity supply layer 2.

  This completes a form in which plating is grown only from the bottom surface of the through-hole 8, which is the point of the present invention.

  Next, as shown in FIG. 1-j, the conductive member 4 is formed by an electrolytic plating method using the electricity supply layer 2 exposed on the bottom surface of the through hole 8 as a seed layer.

  Specifically, Au plating is grown from the bottom surface of the through hole 8 and plated to the vicinity of the surface of the opening.

  When a plating voltage is applied from the electric supply layer 2 on the surface of the semiconductor substrate 1, no current flows because the surface and the electric supply layer 2 on the inner surface of the hole are covered with the insulating layer 3. Since only the exposed portion of the electric supply layer 2 is in contact with the plating solution, the plating grows only from the bottom surface.

  This formation process is the point of the present invention and is the most important place.

  In the embodiment shown in FIG. 1-j, the insulating layer 3 is formed on the surface of the semiconductor substrate 1 and the side surface of the through hole 8 so that electricity does not flow except for the bottom surface of the through hole 8 during electrolytic plating. The surface of the semiconductor substrate 1 may be covered with a jig or the like made of an insulating member instead of the insulating layer 3.

  Next, the surface of the semiconductor substrate 1 on which no plating is formed and the surface of the opening are plated to increase the thickness of the electric supply layer 2 on the surface of the semiconductor substrate 1 and the formed plating is grown from the bottom surface of the through hole 8. The conductive member 4 in the through hole and the conductive layer 2 on the bottom surface of the through hole 8 are electrically connected.

  Specifically, as shown in FIG. 1-k, the insulating layer 3 on the surface of the semiconductor substrate 1 is removed by dry etching, and the electricity supply layer 2 is exposed.

  Then, as shown in FIG. 1-l, plating is grown using the electric supply layer 2 exposed on the surface of the semiconductor substrate 1 as a plating seed layer, and the conductive member 4 is formed to a necessary thickness corresponding to a desired current amount and resistance value. Form.

  The method for forming the conductive member 4 on the surface of the semiconductor substrate is not limited to electrolytic plating, and electroless plating, vapor deposition, sputtering, CVD, or the like may be used.

Through the above steps, the conductive member 4 is formed in the through hole 8 to complete the through electrode.
Moreover, about the vapor deposition film material of the electric supply layer 2, even if it is other single materials, such as Ni, TiN, and TaN, the plating growth from the bottom face of the through-hole 8 is possible.

  Next, in Embodiment 2 shown in FIG. 2B, the electric supply layer 2 on the bottom surface of the through hole 8 is only partially formed, and the electric supply layer 2 on the side surface near the hole bottom of the through hole 8 is exposed. explain.

  FIG. 2A shows that the electric supply layer 2 on the side surface of the through-hole 8 is exposed from the bottom surface in the opening direction of the through-hole 8 by a length L1 and is not covered with the insulating layer 3 from the bottom surface. It is sectional drawing which shows the state which exists.

  In the figure, L1 represents the exposed length of the electric supply layer on the side surface of the through hole 8 in the direction from the bottom surface to the other surface.

  L2 is the shortest length of the bottom surface of the through hole 8 in the short direction.

  L1 is desirably 1/2 or less of L2. That is, it is desirable that the electricity supply layer on the side surface of the through hole 8 is exposed to ½ or less of the shortest length in the short direction of the bottom surface from the bottom surface to the opening direction of the through hole.

  Therefore, when the shape of the bottom surface of the through hole 8 is circular, L2 is a diameter, and L1 is a length equal to or less than the radius.

  When the shape of the bottom surface is a shape other than a circle, such as a quadrangle or an ellipse, it is less than the shortest length in the short direction.

  If L1 is 1/2 or less of L2 and circular, L1 is made not more than the radius of the circle, so that plating grows from the side surface of the through hole 8 toward the center of the hole, and the connecting hole is closed near the center. Since the plating growth from the bottom surface of the through hole 8 is the same or faster than that, no void is generated.

  When L1 is a radius, the plating from the side surface grows toward the center of the circle and grows by the radius, that is, when reaching the center of the circle, the plating grown from the bottom also grows by the radius, and the growth edge The parts just overlap and the hole is closed.

  If L1 is smaller than the radius, the plating growth from the bottom surface is faster than the plating growth edge from the side surface is connected.

  If the exposed length L1 of the electricity supply layer 2 on the side surface near the bottom of the through hole 8 is within this range, the plating from the side surface does not block the hole first, and no void is generated below the hole.

  For the conductive layer 5, a Ti layer and an Au layer are deposited on the Al layer so that problems such as oxidation and migration do not occur even if a part of the bottom surface of the through hole 8 is exposed. It is Au layer.

  FIG. 2B is a cross-sectional view showing a state in which the conductive member 4 is formed up to the surface of the semiconductor substrate 1, and the conductive member 4 without voids can be formed.

  FIG. 2C and FIG. 2D are cross-sectional views illustrating the case where L1 is larger than ½ of L2.

  FIG. 2C is a cross-sectional view showing a state where electrolytic plating is performed from the bottom of the hole with the electric supply layer 2 on the side surface of the through hole 8 exposed by a length L3 from the bottom.

  L3 at this time is the same length as L4, and when the hole is circular, it is the same length as the diameter.

  When L1 which is the exposed length of the side surface near the hole of the electricity supply layer 2 becomes long, the same problem as the problem of the conventional technique occurs under the hole.

  The problem with the prior art is that the electric field is stronger and more electricity flows more easily on the hole, so that the hole is blocked.

  Even in the case of FIG. 2C, when the exposed portion of the electricity supply layer 2 increases and approaches the hole, the electric field is stronger and more current flows on the hole, so that the plating growth from the side surface close to the hole is faster. turn into.

  Before the plating grew from the bottom surface, the plating grew from the side surface and the hole was closed at the center, so that a void 11 was generated under the hole.

  FIG. 2D is a cross-sectional view showing a state in which the conductive member 4 is further formed on the surface of the semiconductor substrate 1, and the conductive member 4 is formed with the void 11 remaining under the hole.

  FIG. 3A is a diagram illustrating the third embodiment, and is a cross-sectional view illustrating a configuration in which the electric supply layer 2 on the bottom surface of the through hole 8 is not covered with the insulating layer 3 by an area corresponding to the length d1. .

  d1 is a length corresponding to the area of the exposed surface of the conductive layer 5 or the electricity supply layer 2 exposed on the bottom surface of the through hole 8. Here, “corresponding length” means, for example, the diameter of the circle when the exposed surface is circular, or the length of one side of the square when the exposed surface is square.

  d2 is a length corresponding to the through hole bottom surface area. Here, “corresponding length” means, for example, the diameter of the circle when the bottom surface of the through hole is circular, or the length of one side of the square when it is square.

  The area corresponding to d1 is preferably ¼ or more of the area corresponding to d2, that is, the conductive layer 5 or the electric supply layer 2 is exposed at least ¼ or more of the area of the bottom surface of the through hole. .

  When the exposed area corresponding to d1 is smaller than 1/4 of the area of the bottom surface of the through hole, the plating current density is four times or more to flow the same current value as compared with the same area as that corresponding to d2, Since it is close to the limit plating conditions, plating defects are likely to occur.

  In addition, the allowable current as a semiconductor device is reduced, and the connection area with the electricity supply layer 2 is reduced, so that a bonding failure is likely to occur.

  FIG. 3B shows an example in which the opening shape of the resist 9 is made smaller than the opening shape of the insulating layer 3 in order to partially expose the electric supply layer 2 on the bottom surface of the through hole 8 as shown in FIG. It is sectional drawing which shows the state which removed the insulating layer 3 of the bottom face by forming hang | hanging.

  Hereinafter, embodiments of the present invention will be described based on examples with reference to the drawings.

  1-1 is a schematic cross-sectional view of the semiconductor device in Example 1 according to Embodiment 1 of the present invention. FIGS. 1-a to 1-1 are schematic cross-sectional views for explaining the main manufacturing steps. FIG.

  In this embodiment, the semiconductor substrate 1 is made of Si (silicon) having a thickness of 200 μm.

  A conductive layer 5 is formed on one surface of the semiconductor substrate 1, and an electric supply layer 2, a conductive member 4, a through hole opening and a through hole 8 are formed on the other surface of the semiconductor substrate 1 on the opposite side. Is formed.

  In this embodiment, the conductive layer 5 and the electricity supply layer 2 are electrically connected by the conductive member 4 formed in the through hole.

As shown in FIG. 1A, the semiconductor substrate 1 and the conductive layer 5 are insulated by a SiO ₂ thermal oxide film 6.
An Al material was used for the conductive layer 5 to form an Al layer.

Next, as shown in FIG. 1B, a through hole was formed by first coating a resist 7 on the semiconductor substrate 1 and then patterning the through hole opening shape by photolithography.
The opening diameter of the through hole in this example was φ50 μm.

  Next, as shown in FIG. 1-c, the through hole 8 was opened using ICP-RIE (inductively coupled plasma type reactive ion etching).

  In this embodiment, the etching and deposition were repeated and called the Bosch process.

A plasma etching process using SF ₆ gas and a plasma deposition process in which a fluorocarbon-based polymer is deposited as a protective film on the inner wall surface of the trench using C ₄ F ₈ gas are alternately repeated.

  By this process, silicon was etched at a high speed and a trench shape in which the inner wall of the through hole 8 was perpendicular to the substrate surface could be obtained.

  The aspect ratio was about 4 from a depth of 200 μm / opening diameter of 50 μm, and a through hole 8 having a high aspect was formed.

  As an apparatus for silicon etching, AMS200 manufactured by Alcatel was used.

The gas used is SF ₆ and C ₄ F ₈ , the gas flow rate is SF ₆ / C ₄ F ₈ = 300 sccm / 150 sccm, the gas pressure ratio is SF ₆ / C ₄ F ₈ = 5.78 / 3.3, power Was 1800 W, and the ICP etching rate was 5 μm / min.

Under this condition, the SiO ₂ thermal oxide film 6 became a stop layer and the etching was completed.

Next, as shown in FIG. 1-d, the SiO ₂ thermal oxide film 6 is removed by etching using a DFRI-4500 apparatus manufactured by Canon Anelva Co., Ltd., so that the conductive layer 5 becomes an etching stop layer and the through hole 8 is obtained. It was.

  Next, as shown in FIG. 1-e, in order to maintain insulation with the semiconductor substrate 1 on the other side of the semiconductor substrate 1 and the outermost peripheral side surface and bottom surface of the through hole 8, paraxylylene resin (trade name: dix- C: Parylene insulating layer 10 made of a material manufactured by Daisan Kasei Co., Ltd. was formed by CVD deposition.

  Next, as shown in FIG. 1-f, in order to establish electrical continuity with the conductive layer 5 on the bottom surface of the through hole 8, the bottom surface portion of the deposited through hole 8 of the parylene insulating layer 10 is removed to expose the conductive layer 5. I let you.

  Specifically, mask patterning was formed with a resist 9 other than the opening of the through hole 8, the parylene insulating layer 10 on the bottom surface of the through hole 8 was removed by ECR dry etching, and the conductive layer 5 was exposed.

  A dry film resist or the like can be used as a resist material for the mask.

  Next, as shown in FIG. 1-g, after removing the resist 9, the electric supply layer 2 which is a barrier layer and a plating seed layer was formed on the other surface of the semiconductor substrate 1 and the inner surface of the through hole 8.

  First, a titanium (Ti) layer was formed, and a gold (Au) layer was formed thereon.

  The Ti layer serves as a barrier layer.

  Although the bottom surface of the through hole 8 is the conductive layer 5, since it is an Al layer, corrosion due to migration occurs when an Au layer is formed directly thereon.

  In order to prevent this corrosion, a Ti layer as a first layer was deposited on the bottom surface of the through hole 8 to form a Ti layer as a barrier layer between the conductive layer 5 and the Au layer.

  Here, a method for forming the Ti layer as the electricity supply layer 2 will be described.

  The through hole 8 is a high aspect through hole.

  If the substrate has no process temperature restriction, vapor deposition into the through hole 8 is possible using other vapor deposition methods such as CVD and sputtering.

  However, in the present embodiment, there is a process temperature restriction of 140 ° C. or lower due to the characteristics of other used members formed on the semiconductor substrate 1, and it is not possible to use CVD or sputtering methods that rise to 300 ° C. to 400 ° C. .

  Therefore, in this example, an evaporation method called an ion plating method was used.

  Shin Meiwa Kogyo Co., Ltd.'s vapor deposition system heats the deposited metal crucible with an electron beam while cooling the processing substrate in a vacuum, and applies high-frequency plasma and bias to perform straight-line low temperature vapor deposition. It becomes possible.

  By this method, the Ti seed layer 2 was formed in the through hole 8 having a high aspect ratio.

  The substrate was placed horizontally on the bottom surface of the through hole 8 for vertical deposition, and the substrate was deposited on the side surface of the through hole 8 by tilting and rotating.

  Although it is necessary to adjust the inclination angle depending on the diameter of the through hole and the penetration depth, in this example, the Ti layer was deposited to a thickness of 2000 mm by inclining the semiconductor substrate 1 by 9 °.

  The Ti layer alone has a high resistance even by itself, and further increases the resistance when oxidized in the atmosphere.

  When exposed to the atmosphere for plating, Ti is oxidized, so that Au plating for forming a conductive layer is not applied.

  Therefore, an Au layer was vapor-deposited to a thickness of 4200 on the Ti layer continuously in the same manner as the Ti layer.

  Next, as illustrated in FIG. 1-h, the insulating layer 3 was formed by vapor deposition on the electric supply layer 2 formed on the other surface of the semiconductor substrate 1 and the inner surface of the through hole 8.

  Here, the same paraxylylene resin material as the parylene insulating layer 10 was used for the insulating layer 3.

  Paraxylylene resin is excellent in throwing power to fine irregularities.

  Next, as shown in FIG. 1-i, the insulating layer 3 on the bottom surface was removed in order to establish electrical continuity with the electricity supply layer 2 on the bottom surface of the through hole 8.

  As described with reference to FIG. 1-f, mask patterning is formed with a resist 9 other than the opening of the through hole 8, the insulating layer 3 on the bottom surface of the through hole 8 is removed by ECR dry etching, and the electric supply layer 2 is exposed. I let you.

  Thus, a form for forming the conductive member 4 by growing the plating from the bottom surface of the through-hole 8 using electrolytic plating, which is the point of the present invention, has been prepared.

  Next, as shown in FIG. 1-j, after removing the resist 9, a cyan Au plating solution is used to supply electricity from the electricity supply layer 2 on the other surface of the semiconductor substrate 1, and through holes are formed by electrolytic plating. The Au conductive member 4 was formed by plating growth from the bottom of 8 to the vicinity of the opening.

  As the plating solution, “K-710 Pure Gold (trade name)” manufactured by Kojima Chemical Co., Ltd. was used.

The plating conditions were a current density of 0.5 ASD (A / dm ² ) and a plating bath temperature of 60 ° C.

  Next, as shown in FIG. 1-k, the insulating layer 3 on the surface of the semiconductor substrate 1 is removed by ECR dry etching in order to form a conductive member for allowing a sufficient amount of current to flow on the other surface of the semiconductor substrate 1 as well. did.

  At that time, since the opening of the through hole 8 is covered with plating, it remains without being etched.

  The electricity supply layer 2 that becomes the plating power supply layer on the surface of the semiconductor substrate 1 was exposed by etching removal.

  Next, as shown in FIG. 1-1, electricity is supplied from the electricity supply layer 2 on the other surface of the semiconductor substrate 1 in the same manner as the plating formation from the bottom surface of the through-hole 8, and from the hole bottom by electrolytic plating. The conductive member 4 of the surface layer was formed continuously with the conductive member 4.

  The conductive member 4 on the surface of the semiconductor substrate 1 was formed by plating and connected to the conductive member 4 in the through hole.

  By the manufacturing method described above, it is possible to grow the plating only from the bottom surface of the through hole, even in the case of power supply from the surface layer in the minute and high aspect through hole, and form a conductive member and through electrode without voids. I was able to.

  In this embodiment, the method of forming the insulating layer 3 covering the outermost parylene insulating layer 10 and the electricity supply layer 2 in the through hole 8 is vapor-deposited on the entire surface, then masked with a resist, and only unnecessary portions are removed by etching. doing.

  However, in addition to this method, the vapor deposition conditions may be changed so that the parylene layer is not formed near the hole bottom or under the hole during vapor deposition, and a method in which an insulating layer is not formed near the hole bottom from the vapor deposition may be used. .

  The condition content includes a method of lowering the parylene supply pressure at the time of parylene vapor deposition and making it difficult to enter the hole so that only the surface layer and the inner wall of the hole are vapor-deposited so as not to adhere to the hole bottom or the vicinity of the hole bottom.

  FIG. 2B is a schematic cross-sectional view of the semiconductor device of Example 2 according to Embodiment 2 within a desirable range of the present invention.

  FIG. 2A is a schematic cross-sectional view illustrating the main manufacturing process of the semiconductor device.

  FIG. 2D is a schematic cross-sectional view of a semiconductor device in which a void defect has occurred in the example according to the second embodiment outside the desirable range of the present invention.

  FIG. 2C is a schematic cross-sectional view illustrating a main manufacturing process of the semiconductor device in which the void defect has occurred.

  As shown in FIG. 2A, the difference between the second embodiment and the first embodiment is that the insulating layer on the inner surface of the through hole 8 is not formed in the vicinity of the hole bottom. The lower part of the supply layer 2 is exposed.

  The other is that the electricity supply layer 2 on the bottom surface of the through hole 8 is not partially formed.

  The removal of the insulating layer 3 on the side surface near the bottom of the through hole 8 is to increase the dry etching time in the bottom surface etching of the insulating layer 3 described with reference to FIG. Thus, the etching of the bottom surface extends to the side surface near the hole bottom, and the side surface near the hole bottom can be removed.

  In Example 2 described with reference to FIGS. 2A and 2B, the through-hole opening diameter was 20 μm, L2 = 20 μm, and L1 = 10 μm. That is, the exposed length of the electricity supply layer 2 near the hole was 10 μm.

  In Example 2, since the plating growth from the bottom surface of the through hole 8 is faster than the plating growth from the side surface of the through hole near the hole bottom, the through electrode is formed without generating a void under the hole. I was able to.

  When the semiconductor device of Example 2 shown in FIG. 2B was evaluated through a heat cycle reliability test, good results were obtained without causing defects such as disconnection failure up to 1000 cycles.

  On the other hand, in the examples shown in FIGS. 2C and 2D, the through hole opening diameters were 20 μm, L4 = 20 μm, and L3 = 40 μm. That is, the exposed length of the electric supply layer 2 near the hole was 40 μm.

  In this example, since the plating growth from the side surface near the bottom of the through hole 8 was faster than the plating growth from the bottom surface, a void was generated under the hole.

  When the semiconductor device of this example shown in FIG. 2D was evaluated through a heat cycle reliability test, 1000 cycles were not reached and a disconnection failure occurred.

  The electric field distribution in the through-hole becomes stronger as it is above the hole, and the plating becomes easier to grow. However, if the distance is less than the radius from the bottom surface, there is almost no difference in the electric field distribution from the bottom surface, and no voids are generated. The absence was confirmed by Example 2.

  In the second embodiment and the other embodiments, the conductive layer 5 is exposed because the electricity supply layer 2 on the bottom surface of the through hole 8 is not partially formed, but the exposed surface of the conductive layer 5 is an Au layer. It is possible to prevent corrosion due to plating solution or migration.

  FIG. 3A is a schematic cross-sectional view of the semiconductor device of Example 3 according to Embodiment 3 within a desirable range of the present invention.

  FIG. 6 is a view in which the electricity supply layer 2 on the bottom surface of the through hole 8 is exposed from the space between the insulating layers 3 by an area corresponding to the length d1.

Since the through-hole opening diameter is 20 μm, the bottom surface portion diameter is 20 μm, and the exposed portion diameter is 10 μm, the area corresponding to d1 = about 78.5 μm ² and the area corresponding to d2 = about 314 μm ² .

  FIG. 3B illustrates a method for partially exposing the electricity supply layer 2 to the bottom surface of the through hole 8.

A part of the insulating layer 3 on the bottom surface was removed by overhanging the resist 9 with an opening diameter smaller than the opening diameter of the through hole.
As a result of the above steps, a through electrode without voids was formed.

  When the semiconductor device of this Example 3 was evaluated through a heat cycle reliability test, defects such as disconnection failure did not occur up to 1000 cycles, and good results were obtained.

  High aspect and fine diameter hole-filling plating can be performed without generating voids, and can be effectively used for manufacturing an inkjet high-speed print head.

1 semiconductor substrate 2 electrically supplying layer 3 insulating layer 4 the conductive member 5 conductive layer 6 SiO ₂ thermal oxide film 7 resist 8 through holes 9 resist 10 parylene insulating layer 11 voids

Claims (10)

Having a conductive layer on one side of the semiconductor substrate;
Having a through hole penetrating from the other surface of the semiconductor substrate to the conductive layer;
A method of manufacturing a semiconductor device having a conductive member electrically connected from the other surface to the conductive layer,
In the through hole, forming a power supply layer reaching the conductive layer from the other surface, and leaving a part of at least one of the conductive layer or the power supply layer on the bottom surface of the through hole, Forming an insulating layer covering the electricity supply layer; supplying electricity to the electricity supply layer; and growing a plating from at least one of the exposed electrically conductive layer or the electricity supply layer; Forming in the through hole;
A method for manufacturing a semiconductor device, comprising: Exposing at least ¼ or more of the area of the bottom surface as an area of at least one of the exposed conductive layer or the electricity supply layer; and exposing the electricity supply layer on the side surface of the through hole from the bottom surface. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of exposing to the opening direction of the through hole not more than 1/2 of the shortest shortest length of the bottom surface.   The method for manufacturing a semiconductor device according to claim 1, wherein the insulating layer includes a step of forming the insulating layer from paraxylylene resin.   The manufacturing method according to claim 1, further comprising a step of forming the conductive member from gold (Au).   The method for manufacturing a semiconductor device according to claim 1, wherein the electricity supply layer includes a step of forming at least one of titanium (Ti) and gold (Au). Having a conductive layer on one side of the semiconductor substrate;
Having a through hole penetrating from the other surface of the semiconductor substrate to the conductive layer;
A semiconductor device having a conductive member electrically connected from the other surface to the conductive layer,
In the through hole, having an electricity supply layer reaching the conductive layer from the other surface;
Having an insulating layer covering the electricity supply layer except for a part of at least one of the conductive layer or the electricity supply layer on the bottom surface of the through hole;
A conductive member in contact with at least one part of the exposed conductive layer or the electricity supply layer in the through hole;
A semiconductor device characterized by the above. The area of a part of at least one of the conductive layer or the electric supply layer not covered with the insulating layer is at least 1/4 or more of the area of the bottom surface, and the insulating layer on the side surface of the through hole The length in the direction from the bottom surface to the other surface of the electricity supply layer that is not covered with the bottom surface is ½ or less of the shortest shortest length of the bottom surface. Semiconductor device.   The semiconductor device according to claim 6, wherein the insulating layer is made of paraxylylene resin.   The semiconductor device according to claim 6, wherein the conductive member is made of gold (Au).   The semiconductor device according to claim 6, wherein the electricity supply layer is made of at least one of titanium (Ti) and gold (Au).

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