JP2014183195A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2014183195A5 JP2014183195A5 JP2013056803A JP2013056803A JP2014183195A5 JP 2014183195 A5 JP2014183195 A5 JP 2014183195A5 JP 2013056803 A JP2013056803 A JP 2013056803A JP 2013056803 A JP2013056803 A JP 2013056803A JP 2014183195 A5 JP2014183195 A5 JP 2014183195A5
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- semiconductor
- substrate
- insulating film
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims 122
- 239000000758 substrate Substances 0.000 claims 42
- 230000003287 optical Effects 0.000 claims 13
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 6
- 229910052732 germanium Inorganic materials 0.000 claims 6
- 239000002184 metal Substances 0.000 claims 6
- 238000004519 manufacturing process Methods 0.000 claims 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims 4
- 239000000203 mixture Substances 0.000 claims 4
- 229910052710 silicon Inorganic materials 0.000 claims 4
- 239000010703 silicon Substances 0.000 claims 4
- -1 silicon germanium Chemical compound 0.000 claims 4
- 230000015572 biosynthetic process Effects 0.000 claims 3
- 238000005755 formation reaction Methods 0.000 claims 3
- 239000012535 impurity Substances 0.000 claims 3
- 238000005530 etching Methods 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
Claims (15)
前記半導体基板上に形成され、第1の開口部を有する第1の絶縁膜と、
前記第1の開口部直下の前記半導体基板内に形成された第1の溝と、
前記第1の溝内の前記半導体基板上に形成され、前記半導体基板の主成分を成す元素とは異なる元素をその一部に含み、禁制帯幅が前記半導体基板よりも小さい第1の半導体層と、
前記第1の溝内の前記第1の半導体層上に形成され、前記半導体基板の主成分を成す元素とは異なる元素をその一部に含み、禁制帯幅が前記半導体基板よりも小さい第1導電型の第2の半導体層と、
前記第1の開口部内の前記第2の半導体層上に形成され、前記半導体基板の主成分を成す元素と同一元素をその一部に含み、禁制帯幅が前記第1の半導体層及び前記第2の半導体層よりも大きい第1導電側の第3の半導体層と、
前記第1の開口部内の前記第3の半導体層上に形成された金属層とを備え、
前記第1の溝の上部の開口領域は前記第1の開口部を取り囲むように形成され、前記第1の溝の上部では前記第1の絶縁膜からなる庇が形成され、前記第1の溝の側壁は前記半導体基板の(111)面を含み、前記第1の溝の底部は前記半導体基板の(100)面を含み、
前記第1の半導体層は、前記第1の溝底部を構成する前記半導体基板の(100)面と、前記第1の溝側壁を構成する半導体基板の(111)面と、前記第1の絶縁膜から成る庇の下部表面と、前記第2の半導体層とに接しており、
前記第2の半導体層は、前記第1の半導体層と、前記第1の絶縁膜から成る庇の下部表面と、前記第3の半導体層とに接しており、
前記第1の半導体層と前記第2の半導体層の界面は、前記第1の半導体層と前記第1の絶縁膜との界面よりも下部に位置し、
前記第3の半導体層と前記金属層の界面は、前記第1の絶縁膜の下部表面と前記第1の絶縁膜の上部表面の間に位置し、
前記第2の半導体層は前記半導体基板から空間的に分離していることを特徴とする半導体装置。 A semiconductor substrate;
A first insulating film formed on the semiconductor substrate and having a first opening;
A first groove formed in the semiconductor substrate immediately below the first opening;
A first semiconductor layer formed on the semiconductor substrate in the first trench, including an element different from an element constituting the main component of the semiconductor substrate, and having a forbidden band width smaller than that of the semiconductor substrate. When,
A first element formed on the first semiconductor layer in the first groove, including an element different from an element constituting the main component of the semiconductor substrate, and having a forbidden band width smaller than that of the semiconductor substrate. A conductive second semiconductor layer;
The first semiconductor layer is formed on the second semiconductor layer in the first opening and includes a part of the same element as the main component of the semiconductor substrate, the band gap being the first semiconductor layer and the first semiconductor layer. A third semiconductor layer on the first conductive side larger than the second semiconductor layer;
A metal layer formed on the third semiconductor layer in the first opening ,
An opening region in the upper part of the first groove is formed so as to surround the first opening part, and a ridge made of the first insulating film is formed in the upper part of the first groove, and the first groove is formed. The side wall of the semiconductor substrate includes a (111) plane of the semiconductor substrate, the bottom of the first groove includes a (100) plane of the semiconductor substrate,
The first semiconductor layer includes a (100) plane of the semiconductor substrate that constitutes the first groove bottom, a (111) plane of the semiconductor substrate that constitutes the first trench sidewall, and the first insulating layer. In contact with the lower surface of the ridge formed of a film and the second semiconductor layer;
The second semiconductor layer is in contact with the first semiconductor layer, a lower surface of a ridge formed of the first insulating film, and the third semiconductor layer,
The interface between the first semiconductor layer and the second semiconductor layer is located below the interface between the first semiconductor layer and the first insulating film,
The interface between the third semiconductor layer and the metal layer is located between the lower surface of the first insulating film and the upper surface of the first insulating film,
The semiconductor device, wherein the second semiconductor layer is spatially separated from the semiconductor substrate.
前記第2の光導波路と前記第3の半導体層はシリコンまたはシリコン・ゲルマニウムで構成され、
前記第1の半導体層と前記第2の半導体層はゲルマニウムまたはシリコン・ゲルマニウムで構成され、
前記第1の半導体層と前記第2の半導体層のゲルマニウム組成が、共に前記第2の光導波路と前記第3の半導体層のいずれのゲルマニウム組成よりも大きいことを特徴とする請求項1乃至9のいずれか一項に記載の半導体装置。 The semiconductor support substrate and the first optical waveguide are made of silicon,
The second optical waveguide and the third semiconductor layer are made of silicon or silicon germanium,
Said second semiconductor layer and the first semiconductor layer is composed of germanium or silicon-germanium,
10. The germanium composition of the first semiconductor layer and the second semiconductor layer are both larger than the germanium composition of the second optical waveguide and the third semiconductor layer. The semiconductor device according to any one of the above.
前記第1の絶縁膜に前記半導体基板が露出した第1の開口部を有する工程と、
前記第1の開口部直下の前記半導体基板内に第1の溝を形成する工程と、
前記第1の溝内の前記半導体基板上に、前記半導体基板の主成分を成す元素とは異なる元素をその一部に含み、禁制帯幅が前記半導体基板よりも小さい第1の半導体層を形成する工程と、
前記第1の溝内の前記第1の半導体層上に、前記半導体基板の主成分を成す元素とは異なる元素をその一部に含み、禁制帯幅が前記半導体基板よりも小さい第1導電型の第2の半導体層を形成する工程と、
前記第1の開口部内の前記第2の半導体層上に、前記半導体基板の主成分を成す元素と同一元素をその一部に含み、禁制帯幅が前記第1の半導体層及び前記第2の半導体層よりも大きい第1導電側の第3の半導体層を形成する工程と、
前記第1の開口部内の前記第3の半導体層上に金属層を形成する工程とを有し、
前記第1の溝を形成する工程は、前記第1の溝上部の開口領域が前記第1の開口部よりも広くなるよう、水平方向にも前記半導体基板のエッチングを施すことで前記第1の溝上部に前記第1の絶縁膜の庇を形成すると共に、前記第1の溝の底部が前記半導体基板の(100)面を有し、前記第1の溝の側壁が前記半導体基板の(111)面を有するように溝形成条件を調整する工程を含み、
前記第1の半導体層を形成する工程は、前記第1の半導体層が、前記第1の溝底部を構成する前記半導体基板の(100)面と、前記第1の溝側壁を構成する前記半導体基板の(111)面と、前記第1の絶縁膜から成る庇の下部表面とに接すると共に、前記第1の半導体層と前記第2の半導体層の界面が、前記第1の半導体層と前記第1の絶縁膜の界面よりも下部に位置するように前記第1の半導体層の形成条件を調整する工程を含み、
前記第2の半導体層を形成する工程は、前記第2の半導体層が前記第1の半導体層と、前記第1の絶縁膜の庇の下部表面とに接するように前記第2の半導体層の形成条件を調整する工程を含み、
前記第3の半導体層を形成する工程は、前記第3の半導体層と前記金属層の界面が前記第1の絶縁膜の下部表面と前記第1の絶縁膜の上部表面との間に位置するように前記第3の半導体層の形成条件を調整する工程を含むことを特徴とする半導体装置の製造方法。 Forming a first insulating film on the semiconductor substrate;
A step of having a first opening in which the semiconductor substrate is exposed in the first insulating film;
Forming a first groove in the semiconductor substrate immediately below the first opening;
On the semiconductor substrate in the first groove, a first semiconductor layer that includes an element that is different from an element that is a main component of the semiconductor substrate and has a forbidden band width smaller than that of the semiconductor substrate is formed. And a process of
A first conductivity type that includes a part of the first semiconductor layer in the first groove that is different from an element that is a main component of the semiconductor substrate, and has a forbidden band width smaller than that of the semiconductor substrate. Forming a second semiconductor layer of:
On the second semiconductor layer in the first opening , the same element as the element constituting the main component of the semiconductor substrate is included in a part thereof, and the forbidden band width is the first semiconductor layer and the second semiconductor layer. Forming a third semiconductor layer on the first conductive side larger than the semiconductor layer of
Forming a metal layer on the third semiconductor layer in the first opening ,
The step of forming the first groove is performed by etching the semiconductor substrate in a horizontal direction so that an opening region of the upper part of the first groove is wider than the first opening. A ridge of the first insulating film is formed on the top of the groove, the bottom of the first groove has the (100) surface of the semiconductor substrate, and the side wall of the first groove is (111) of the semiconductor substrate. ) Including a step of adjusting the groove forming conditions so as to have a surface,
In the step of forming the first semiconductor layer, the first semiconductor layer includes the (100) plane of the semiconductor substrate constituting the first groove bottom and the semiconductor constituting the first groove sidewall. The interface between the first semiconductor layer and the second semiconductor layer is in contact with the (111) surface of the substrate and the lower surface of the first insulating film, and the interface between the first semiconductor layer and the second semiconductor layer. Adjusting the formation conditions of the first semiconductor layer so as to be located below the interface of the first insulating film,
The step of forming the second semiconductor layer includes the step of forming the second semiconductor layer so that the second semiconductor layer is in contact with the first semiconductor layer and a lower surface of the first insulating film. Including the step of adjusting the forming conditions,
In the step of forming the third semiconductor layer, the interface between the third semiconductor layer and the metal layer is located between the lower surface of the first insulating film and the upper surface of the first insulating film. As described above, the method for manufacturing a semiconductor device includes a step of adjusting a formation condition of the third semiconductor layer.
前記第2の光導波路と前記第3の半導体層をシリコンまたはシリコン・ゲルマニウムとし、
前記第1の半導体層と前記第2の半導体層をゲルマニウムまたはシリコン・ゲルマニウムとし、
前記第1の半導体層と前記第2の半導体層のゲルマニウム組成が、共に前記第2の光導波路と前記第3の半導体層のいずれのゲルマニウム組成よりも大きくすることを特徴とする請求項11乃至14のいずれか一項に記載の半導体装置の製造方法。 A substrate in which the semiconductor support substrate and the first optical waveguide are made of silicon;
The second optical waveguide and the third semiconductor layer are made of silicon or silicon germanium,
Said second semiconductor layer and the first semiconductor layer is germanium or silicon-germanium,
12. The germanium compositions of the first semiconductor layer and the second semiconductor layer are both larger than the germanium compositions of the second optical waveguide and the third semiconductor layer. The method for manufacturing a semiconductor device according to claim 14.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013056803A JP6091273B2 (en) | 2013-03-19 | 2013-03-19 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013056803A JP6091273B2 (en) | 2013-03-19 | 2013-03-19 | Semiconductor device and manufacturing method thereof |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2014183195A JP2014183195A (en) | 2014-09-29 |
JP2014183195A5 true JP2014183195A5 (en) | 2016-03-31 |
JP6091273B2 JP6091273B2 (en) | 2017-03-08 |
Family
ID=51701617
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013056803A Active JP6091273B2 (en) | 2013-03-19 | 2013-03-19 | Semiconductor device and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP6091273B2 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6514904B2 (en) * | 2015-02-05 | 2019-05-15 | 富士通株式会社 | Optical semiconductor device |
JP6184539B2 (en) * | 2016-02-18 | 2017-08-23 | 沖電気工業株式会社 | Semiconductor light receiving element, photoelectric fusion module, and method for manufacturing semiconductor light receiving element |
JP2018049856A (en) * | 2016-09-20 | 2018-03-29 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP2019117855A (en) | 2017-12-27 | 2019-07-18 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method for manufacturing the same |
US11393939B2 (en) * | 2019-09-20 | 2022-07-19 | Taiwan Semiconductor Manufacturing Company Ltd. | Photo sensing device and method of fabricating the photo sensing device |
US11404590B2 (en) * | 2019-09-20 | 2022-08-02 | Taiwan Semiconductor Manufacturing Company Ltd. | Photo sensing device and method of fabricating the photo sensing device |
US11393940B2 (en) | 2019-09-20 | 2022-07-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Photodetector and method for forming the same |
WO2021145077A1 (en) * | 2020-01-15 | 2021-07-22 | 東京エレクトロン株式会社 | Film forming method, film forming device, and method for manufacturing semiconductor device |
JP7468791B1 (en) | 2022-12-01 | 2024-04-16 | 三菱電機株式会社 | Waveguide-type photodetector |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51107768A (en) * | 1975-02-17 | 1976-09-24 | Siemens Ag | HEIMENDONOTAKAISHIRIKONKUBOMINOSEIZOHOHO |
JPS57180147A (en) * | 1981-04-30 | 1982-11-06 | Fujitsu Ltd | Semiconductor device |
EP0227523A3 (en) * | 1985-12-19 | 1989-05-31 | SILICONIX Incorporated | Method for obtaining regions of dielectrically isolated single crystal silicon |
JP2988353B2 (en) * | 1995-03-13 | 1999-12-13 | 日本電気株式会社 | Semiconductor device for photodetection and method of manufacturing the same |
CN101836295A (en) * | 2007-08-08 | 2010-09-15 | 新加坡科技研究局 | A semiconductor arrangement and a method for manufacturing the same |
-
2013
- 2013-03-19 JP JP2013056803A patent/JP6091273B2/en active Active
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2014183195A5 (en) | ||
US10249714B2 (en) | Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction | |
US9123744B1 (en) | Semiconductor device and method for fabricating the same | |
KR102285120B1 (en) | Photodetector | |
US9064893B2 (en) | Gradient dopant of strained substrate manufacturing method of semiconductor device | |
RU2015151123A (en) | DEVICES BASED ON SELECTively EPITAXIALLY GROWED MATERIALS OF III-V GROUPS | |
JP2016532296A5 (en) | ||
JP2012199527A5 (en) | Method for manufacturing semiconductor device | |
TWI456752B (en) | Semiconductor image sensor apparatuses and semiconductor image sensor devices and methods for manufacturing the same | |
US10707224B2 (en) | FinFET vertical flash memory | |
KR102321839B1 (en) | Selective etching method for epitaxial films on source/drain regions of transistors | |
JP2013191828A5 (en) | ||
JP2012195493A5 (en) | ||
JP2019161047A5 (en) | ||
CN104254951A (en) | Variable bandgap modulator for modulated laser system | |
US10505017B2 (en) | Semiconductor device and formation thereof | |
US10204981B2 (en) | Semiconductor structure and manufacturing method thereof | |
US20170133488A1 (en) | High-voltage junctionless device with drift region and the method for making the same | |
CN104979162B (en) | Semiconductor devices and its manufacturing method | |
TWI748021B (en) | Method of forming strained channel layer | |
KR20130054010A (en) | Semiconductor device using iii-v group material and method of manufacturing the same | |
KR20060119359A (en) | Si-ge photodiode used image sensor | |
TWI490950B (en) | Trench mos structure and method for forming the same | |
US9633904B1 (en) | Method for manufacturing semiconductor device with epitaxial structure | |
TW201436207A (en) | Germanium FINFET structure |