JP2014179511A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid a micro scratch problem.SOLUTION: A semiconductor device manufacturing method comprises: a process of forming on a principal surface of a semiconductor substrate, a first pattern having a first wafer edge cut width; a process of forming an interlayer insulation film on the first pattern; a process of coating a negative resist on the interlayer insulation film; a process of performing first exposure on the negative resist by using a peripheral exposure device; a process of performing second exposure on the negative resist; a process of performing a development process on the negative resist to form a second pattern which is a blank pattern provided in a region occupying a second wafer edge cut width larger than the first wafer wedge cut width and covers a part of the first pattern, and a third pattern having the second wafer edge cut width; and a process of removing a part of the interlayer insulation film located on the first pattern by using the second pattern and the third pattern as masks.

Description

  The present invention relates to a manufacturing process of a semiconductor device, and more particularly to a manufacturing method in forming a capacitor of a dynamic random access memory (DRAM).

  In DRAM memory cells, in recent years, capacitors having a three-dimensional structure have been used with the miniaturization of cell size. As such a capacitor structure, a crown type capacitor structure has become mainstream. The crown-type capacitor structure includes a cylindrical lower electrode (storage electrode), a dielectric film (capacitor insulating film) covering the inner and outer peripheral surfaces of the lower electrode, and an upper electrode (counter electrode) on the dielectric film. ). For example, Patent Document 1 and Patent Document 2 describe a DRAM having a crown-type capacitor structure and a manufacturing method thereof.

  At first, the crown type capacitor structure adopted a manufacturing method (a process without external removal) described in Patent Document 2. That is, when the lower electrode is formed, the sacrificial oxide film is left outside the memory mat (memory cell group), and the height adjustment inside and outside the memory mat is performed simultaneously with the formation of the lower electrode. As a result, there is a merit that the planarization process in forming the interlayer film on the capacitor after forming the upper electrode can be eliminated. However, this manufacturing method has a problem that, as seen in 33 of FIG. 2b of Patent Document 2, a penetration defect that greatly affects the product yield is likely to occur.

  For this reason, the crown-type capacitor structure is manufactured by a manufacturing method (a process with external removal) as described in Patent Document 1, that is, a production that suppresses the occurrence of a permeation defect itself by removing a sacrificial oxide film outside the memory mat. The method has come to be adopted. When the lower electrode is formed, the sacrificial oxide film outside the memory mat is also removed at the same time, and the height inside and outside the memory mat is adjusted with respect to the formed interlayer film when the interlayer film on the capacitor is formed after the upper electrode is formed. This is performed using an etch back method by etching or a CMP (Chemical Mechanical Polishing) method.

JP 2003-264245 A JP 2010-129770 A

  The manufacturing method of the process with an outside opening examined by the present inventors will be described. Since the height of the crown type capacitor reaches about 2 μm, it is necessary to form an interlayer film (after forming the capacitor PL interlayer) of 2 μm or more after forming the upper electrode (after forming the capacitor plate (PL)). Thereafter, in order to match the height of the interlayer film inside and outside the memory mat, it is very difficult to match the height inside and outside the memory mat that originally has a large step even if CMP is suddenly performed.

  Therefore, the present inventors have studied to eliminate the difference in height between the inside and outside of the memory mat in advance by using lithography and dry etching before CMP. The CMP in this case has a first purpose of removing the outer edge of the memory mat and the frame-shaped convex portion generated outside the memory mat, and finally, planarization can be obtained by removing the convex portion.

  However, it is difficult for CMP to make the polishing rate in the wafer plane uniform. In particular, the edge portion of the wafer (the end of the memory mat on the wafer outer peripheral side) is subject to excessive pressing pressure, and the polishing rate is remarkably increased. Therefore, in the outer peripheral portion of the wafer, the interlayer film disappears at an early stage of CMP, and a defect that even the pattern of the crown type capacitor is scraped occurs. Then, it was confirmed that the scraped portion of this crown type capacitor becomes dust, and it adheres to the effective chip inside the wafer and causes a new problem of defects such as pattern destruction (such as micro scratch). Yes.

  Accordingly, an object of the present invention is to prevent the pattern of the crown type capacitor on the outermost peripheral portion of the wafer from being scraped in a manufacturing method with an outer opening.

According to one aspect of the invention,
In the first pattern region on the main surface of the semiconductor substrate, excluding the first ring-shaped region including the outermost periphery of the semiconductor substrate and having the first width (outer diameter-inner diameter), the first pattern Forming a step;
Forming a first interlayer insulating film on the first pattern so as to cover the main surface of the semiconductor substrate;
Applying a first resist on the first interlayer insulating film;
On the main surface of the semiconductor substrate, a second pattern that covers the first interlayer insulating film is formed in a second ring-shaped region having a second width (outer diameter-inner diameter) from the outermost periphery of the semiconductor substrate. A first exposure step for forming;
In the second pattern region excluding the second ring-shaped region, an opening is included in the first pattern in plan view on the main surface of the semiconductor substrate, and the second pattern is A second exposure step for forming a different third pattern;
A first developing step for developing the first resist;
Using the second pattern and the third pattern as a mask, removing a part of the first interlayer insulating film on the first pattern,
The semiconductor device manufacturing method is characterized in that the second width of the second ring-shaped region is larger than the first width of the first ring-shaped region.

  According to the method for manufacturing a semiconductor device of the present invention, the region occupying the edge cut width at the outer peripheral portion of the wafer (second ring region) and the region covering the cell mat on the outermost peripheral side of the wafer (second pattern region) Since exposure is performed so as to intentionally leave the resist (second and third patterns), it is possible to prevent the pattern of the crown type capacitor on the outermost peripheral portion of the wafer from being scraped.

It is typical sectional drawing for demonstrating the 1st flow of the capacitor formation process in the manufacturing method of the semiconductor device of related technology. It is typical sectional drawing for demonstrating the 2nd flow of the capacitor formation process in the manufacturing method of the semiconductor device of related technology. It is typical sectional drawing for demonstrating the 3rd flow of the capacitor formation process in the manufacturing method of the semiconductor device of related technology. It is typical sectional drawing for demonstrating the 4th flow of the capacitor formation process in the manufacturing method of the semiconductor device of related technology. It is typical sectional drawing for demonstrating the 5th flow of the capacitor formation process in the manufacturing method of the semiconductor device of related technology. It is typical sectional drawing for demonstrating the 6th flow of the capacitor formation process in the manufacturing method of the semiconductor device of related technology. It is typical sectional drawing for demonstrating the 7th flow of the capacitor formation process in the manufacturing method of the semiconductor device of related technology. It is typical sectional drawing for demonstrating the 8th flow of the capacitor formation process in the manufacturing method of the semiconductor device of related technology. It is typical sectional drawing for demonstrating the 9th flow of the capacitor formation process in the manufacturing method of the semiconductor device of related technology. It is typical sectional drawing for demonstrating the 10th flow of the capacitor formation process in the manufacturing method of the semiconductor device of related technology. It is typical sectional drawing for demonstrating the 11th flow of the capacitor formation process in the manufacturing method of the semiconductor device of related technology. It is typical sectional drawing for demonstrating the 12th flow of the capacitor formation process in the manufacturing method of the semiconductor device of related technology. It is typical sectional drawing for demonstrating the 13th flow of the capacitor formation process in the manufacturing method of the semiconductor device of related technology. FIG. 2 is a plan view of the vicinity of the bevel in FIG. 1K. It is a top view which shows shot arrangement | positioning in a wafer. It is a top view which shows the pattern arrangement | positioning in a chip | tip. It is a top view which shows chip arrangement | positioning in a wafer. It is typical sectional drawing for demonstrating one process in the manufacturing method of the semiconductor device which concerns on the 1st Example of this invention. It is typical sectional drawing for demonstrating one process in the manufacturing method of the semiconductor device which concerns on the 1st Example of this invention. It is typical sectional drawing for demonstrating one process in the manufacturing method of the semiconductor device which concerns on the 1st Example of this invention. It is typical sectional drawing for demonstrating one process in the manufacturing method of the semiconductor device which concerns on the 1st Example of this invention. It is typical sectional drawing for demonstrating one process in the manufacturing method of the semiconductor device which concerns on the 1st Example of this invention. It is typical sectional drawing for demonstrating one process in the manufacturing method of the semiconductor device which concerns on the 1st Example of this invention. It is typical sectional drawing for demonstrating the 1st flow of the capacitor formation process in the manufacturing method of the semiconductor device which concerns on the 1st Example of this invention. It is typical sectional drawing for demonstrating the 2nd flow of the capacitor formation process in the manufacturing method of the semiconductor device which concerns on the 1st Example of this invention. It is typical sectional drawing for demonstrating the 3rd flow of the capacitor formation process in the manufacturing method of the semiconductor device which concerns on the 1st Example of this invention. It is typical sectional drawing for demonstrating the 4th flow of the capacitor formation process in the manufacturing method of the semiconductor device which concerns on the 1st Example of this invention. It is typical sectional drawing for demonstrating the 5th flow of the capacitor formation process in the manufacturing method of the semiconductor device which concerns on the 1st Example of this invention. It is typical sectional drawing for demonstrating the 6th flow of the capacitor formation process in the manufacturing method of the semiconductor device which concerns on the 1st Example of this invention. It is typical sectional drawing for demonstrating the 7th flow of the capacitor formation process in the manufacturing method of the semiconductor device which concerns on the 1st Example of this invention. It is typical sectional drawing for demonstrating the 8th flow of the capacitor formation process in the manufacturing method of the semiconductor device which concerns on the 1st Example of this invention. It is typical sectional drawing for demonstrating the 9th flow of the capacitor formation process in the manufacturing method of the semiconductor device which concerns on the 1st Example of this invention. It is a typical sectional view for explaining the 10th flow of the capacitor formation process in the manufacturing method of the semiconductor device concerning the 1st example of the present invention. It is a typical sectional view for explaining the 11th flow of the capacitor formation process in the manufacturing method of the semiconductor device concerning the 1st example of the present invention. It is a typical sectional view for explaining the 12th flow of the capacitor formation process in the manufacturing method of the semiconductor device concerning the 1st example of the present invention. It is a typical sectional view for explaining the 13th flow of the capacitor formation process in the manufacturing method of the semiconductor device concerning the 1st example of the present invention. It is a top view of the bevel vicinity of FIG. 12K. It is typical sectional drawing for demonstrating one process after capacitor formation in the manufacturing method of the semiconductor device which concerns on the 1st Example of this invention. It is typical sectional drawing for demonstrating the first half part of the 11th flow of the capacitor formation process in the manufacturing method of the semiconductor device which concerns on the 2nd Example of this invention. It is typical sectional drawing for demonstrating the second half part of the 11th flow of the capacitor formation process in the manufacturing method of the semiconductor device which concerns on the 2nd Example of this invention.

  Before describing the present invention, in order to facilitate understanding of the present invention, related techniques studied by the present inventors will be described with reference to FIGS. 1A to 1M and FIG.

  FIG. 1A to FIG. 1M are diagrams showing a flow of a capacitor forming process in a method of manufacturing a semiconductor device according to a related technique studied by the present inventors.

  Referring to FIG. 1A, a transistor (not shown) is formed on a silicon substrate (semiconductor substrate) 1. A cylinder stopper nitride film 11 is deposited to a thickness of, for example, 50 nm so as to cover a capacitor contact pad (not shown).

After the cylinder stopper nitride film 11 is grown, planarization CMP is performed after the cylinder interlayer film 12 / sacrificial oxide film having a thickness of 2 μm is stacked. Thereafter, a support nitride film 13 having a thickness of 100 nm, a mask plasma oxide film 14 having a thickness of 80 nm, an α-C (amorphous carbon) film 15 having a thickness of 600 nm, and an ARL (Anti reflection layer) film having a thickness of 70 nm. 16 and resist 17 are applied to form a resist pattern (cylinder hole transfer pattern) of cylinder photoresist (PR). The ARL film 16 is made of SiO ₂ having a thickness of 55 nm and SiON having a thickness of 15 nm.

  At this time, the α-C film 15 has poor coverage in the vicinity of the bevel, and the film thickness rapidly deteriorates from around 2 mm toward the inside from the outermost periphery of the wafer. Therefore, as for the resist pattern of the cylinder photoresist (PR), the outer peripheral edge cut width is 0.7 mm (the resist pattern is removed from the outermost periphery of the wafer to 0.7 mm, and a normal pattern is formed from 0.7 mm to the inner side. However, the inside from 0.7 mm to 1.7 mm becomes overexposed when the resist is exposed and defocusing occurs. That is, the resist film becomes thin with a large hole shape.

  Since the peripheral edge cut uses a positive resist as a photoresist, it can be removed by a subsequent development process by exposing the edge resist using a peripheral exposure machine.

  Subsequently, as shown in FIG. 1B, a cylinder hole 12A penetrating to the stopper nitride film 11 (on the capacitor contact pad) is formed by oxide film dry etching, and the resist 17, the ARL film 16, and the α-C film 15 are formed. It is removed by plasma peeling, dry etching, or plasma peeling.

  Next, as shown in FIG. 1C, a lower electrode film 18 having a thickness of 25 nm is formed on the sidewall of the cylinder hole 12A. The lower electrode film 18 is made of TiN having a thickness of 15 nm and Ti having a thickness of 10 nm. Thereafter, the lower electrode film 18 formed from the outermost periphery of the wafer to 0.7 mm and the lower electrode film 18 that has gone around the back surface of the wafer are removed by back surface etching.

  Note that the back surface etching is a spray-type wet etching, and a conductive film (polysilicon, metal film, etc.) formed on the back surface can be selectively removed by spraying a hydrofluoric acid chemical solution on the back surface. Then, a part of the chemical solution wraps around the front side, and a part of the outer periphery on the front side can be removed simultaneously.

  Subsequently, as shown in FIG. 1D, in order to transfer the support pattern onto the support nitride film 13, a resist pattern of a support photoresist (PR) 20 formed of a resist film 19 is provided. At this time, most of the cylinder holes 12A on the outer peripheral portion of the wafer are already in the state without the support nitride film 13, and the resist film 19 easily flows into the space where the support nitride film 13 is lost. The outer peripheral edge cut width is set to 0.7 mm. Note that, since the process is a process with external removal, the resist pattern of the support photoresist (PR) 20 exists only in the memory mat area and does not exist on the surrounding peripheral circuits. Further, before the resist film 19 is applied, a plasma oxide film (not shown) having a film thickness of 80 nm is grown so as to close the opening of the cylinder hole 12A so that the resist film 19 does not easily flow into the cylinder hole 12A. Let

  Next, as shown in FIG. 1E, the plasma oxide film having a thick film of 80 nm, the lower electrode film 18, the mask plasma oxide film 14, and the support nitride film 13 in the space region other than the support photoresist (PR) 20 are formed. Are removed by dry etching. The dry etching at this time has a multi-step condition in which the above four film types can be selectively removed sequentially. Then, the support photoresist (PR) 20 is removed by plasma peeling, and the above-described 80 nm-thick plasma oxide film and the lower electrode under the support photoresist (PR) 20 and on the support oxide film 13 are formed. 18 is removed by tri-etching.

  Subsequently, as shown in FIG. 1F, the cylinder interlayer film 12 on the stopper nitride film 11 is completely removed using a hydrofluoric acid-based chemical solution. In FIG. 1F, the lower electrode 18 on the outermost periphery of the wafer is present without being connected to the support nitride film 13. For this reason, at the outermost periphery of the wafer, there is a problem that the lower electrode 18 falls or the collapsed cylinder scatters to the inside of the wafer to lower the product yield. If the outer peripheral edge cut width is set to about 1.7 mm in the formation of the resist pattern of the cylinder photoresist (PR), the defocused portion of the cylinder photoresist can be removed and the lower electrode 18 can be prevented from scattering. There is a reason why the peripheral edge cut width cannot be easily changed because the amount of overpolishing in the subsequent plate interlayer CMP increases.

  Next, as shown in FIG. 1G, a capacitor insulating film having a film thickness of 7.2 nm (not shown, using a laminated film of an alumina film and a zirconium oxide film, etc.), an upper portion made of titanium nitride having a film thickness of 10 nm. An electrode film (not shown), a conductive film 21 on the upper electrode having a thickness of 240 nm, and a plate mask plasma oxide film 22 having a thickness of 100 nm are formed. The upper electrode conductive film 21 is made of W / B-doped polysilicon / B-SiGe, the film thickness of W is 100 nm, and the total film thickness of B-doped polysilicon / B-SiGe is 140 nm. The upper electrode film and B-doped polysilicon / B-SiGe are also formed on the bevel and the back surface, but are removed by back surface etching.

  Subsequently, as shown in FIG. 1H, a resist pattern of a capacitor PL photoresist (PR) 23 is formed on the memory cell. The capacitor PL photoresist (PR) 23 covers the lower capacitor in units of the memory mat 32 (see FIG. 2). The outer peripheral edge cut width is set to 0.7 mm. As is clear from FIG. 1H, the peripheral circuit portion 31 exists around the memory mat 32.

  Next, as shown in FIG. 1I, the plate mask plasma oxide film 22 having a thickness of 100 nm outside the mask is selectively dry-etched using the capacitor PL photoresist (PR) 23 as a mask. Next, the capacitor insulating film, the upper electrode film, and the upper electrode conductive film 21 are dry-etched using the remaining plate mask plasma oxide film 22 as a mask.

  As shown in FIG. 1J, after the formation of the capacitor PL, a plate interlayer film 24 having a thickness of 3 μm is formed. At this time, a large step occurs inside and outside the memory mat 32 (see FIG. 2).

  Subsequently, as shown in FIG. 1K, a resist pattern 25 of a step-reducing photoresist (PR) is formed in the lower portion (peripheral circuit portion). The outer peripheral edge cut width is set to 0.7 mm.

  FIG. 2 is a plan view of the vicinity of the bevel in FIG. 1K.

  Next, as shown in FIG. 1L, in order to reduce the level difference between the inside and outside of the memory mat 32, the high portion without the step reducing photoresist (PR) 25 (that is, on the memory mat excluding the outer edge of the memory mat) is etched by dry etching. To do. At this stage, the step inside and outside the memory cell may be completely eliminated. This may be adjusted in any way by feeding back the quality after the CMP. Further, the step-reducing photoresist (PR) 25 is removed by plasma peeling.

  Here, a portion covered with the step-reducing photoresist (PR) 25 in the peripheral circuit portion between the memory mat 32 and the peripheral circuit portion in the memory mat 32 remains as a convex portion 24A. As can be seen from FIG. 2, the memory mat (the wafer mat outer side surface of the memory mat straddling the line with the outer peripheral edge cut width of 0.7 mm) 32 facing the outermost peripheral side of the wafer is a portion where no convex portion remains. There are many 24B.

  Then, as shown in FIG. 1M, the region of the convex portion 24A on the plate interlayer film 24 is selectively polished using the oxide film CMP. Further, further planarization may be performed by CMP. Further, when the predetermined plate interlayer film thickness is not reached after polishing, a plate interlayer film (second plate oxide film) may be additionally grown again.

  The wafer outer peripheral portion is also a portion where the wafer pressing pressure during CMP is particularly strong, and the polishing rate of the plate interlayer film 24 becomes abnormally large. For this reason, overpolishing occurs on the outermost periphery of the cylinder pattern. In addition, the cylinder pattern shaved by overpolishing reattaches to the inside of the wafer and becomes dust (pattern abnormality), or induces frequent occurrence of microscratches due to the dust during polishing.

[Premise of invention]
Next, the premise of the embodiment of the present invention will be described.

  In general, a pattern on a wafer is formed by forming a resist pattern by Lithography technology and transferring it onto a semiconductor substrate using the resist pattern as a mask. This resist pattern is formed on the wafer in the basic flow of 1) resist application by a coating machine → 2) exposure by an exposure machine → 3) resist development by a developing machine.

  By the way, since the exposure apparatus is a very expensive apparatus, it is required to maximize the wafer processing amount per unit time and speed up the investment recovery.

  FIG. 3 shows an example of shot arrangement in the exposure machine. Exposure on the wafer is performed in units called shots of several chips. The smaller the number of shots, the higher the wafer throughput per unit time. For this reason, the entire wafer is not exposed, and the non-shot region 33 (non-exposed portion) exists in the vicinity of the outer periphery of the wafer. That is, in a shot near the wafer outer periphery, if there is no effective chip 34 (a chip that can be shipped), it is normal that the shot is not shot (not exposed).

  In FIG. 3, 35 indicates the outermost peripheral line of the silicon substrate, and 36 indicates the outermost peripheral line of the effective region. The effective chip 34 is obtained when the entire chip is inside the effective area outermost peripheral line 36. Reference numeral 37 denotes a field shot unit, and reference numeral 38 denotes an ineffective chip.

  FIG. 4 is a plan view showing an in-chip pattern arrangement. In FIG. 4, 39 indicates the center of the scribe line, and 40 indicates the scribe area.

FIG. 5 is a diagram showing an actual on-wafer transfer state (chip arrangement) with respect to the shot arrangement shown in FIG. Defocus failure tends to occur at the outer periphery of the wafer during exposure. When this defocusing failure occurs, it will cause peeling of the pattern in the subsequent process. Therefore, the outer periphery of the resist pattern is removed / edge cut (also referred to as Wafer Edge Exclusion). It is. The area of the active chip 34, the edge than the cutting width _{W ec} is set inside the region, in general, entering from the wafer outermost periphery to 2.0 mm (1.8 to 2.2 mm) degree inside Separated by areas.

As can be seen from FIG. 5, the edge cut width _Wec refers to a region partitioned by an arbitrary circular line set between the silicon substrate outermost peripheral line 35 and the effective region outermost peripheral line 36.

[Embodiment]
Next, an embodiment of the present invention will be described.

  In order to prevent overpolishing of the outermost peripheral portion of the wafer, it is necessary to install the plate interlayer 24 with the corners of the memory mat 32 on the outer peripheral side of the wafer thick and wide before CMP. This prevents overpolishing of the outermost peripheral portion of the wafer. As the thickness, the initial film thickness (film thickness before etching) of the plate interlayer film 24 is secured, and as the width, the distance (several tens of μm) between the adjacent memory mats 32 is not sufficient, and the minimum is about 0.1 mm. (Distance between the mat end of the chip and the center 39 of the scribe line, see FIG. 4) is required. A portion surrounded by an ellipse in the lower part of FIG. 5 is a portion close to the scribe region 40 of the outer peripheral effective tip 34, and overpolishing does not occur. Therefore, about 0.1 mm is considered necessary.

  As one means, in the resist pattern formation of the step-reduced photoresist (PR), we also considered using positive type resist and not performing edge cutting. However, as shown in FIG. Since there is a portion to be processed (ineffective chip 38), it is considered impossible to leave the resist continuously over the entire outer periphery of the wafer.

  Therefore, in the embodiment of the present invention, a step-reducing photoresist (PR) is subjected to a main exposure using a negative type resist, and then a wafer using a peripheral exposure machine generally used in a semiconductor device manufacturing line. Peripheral exposure is performed so that the resist is intentionally left in a region occupying the edge cut width of the outer peripheral portion and a region (width of 0.1 mm or more) covering the cell mat on the outermost peripheral side of the wafer. The resist pattern that is exposed by this peripheral exposure machine and passed through the development process is not a fine pattern, but is a resist pattern (blank pattern) that remains in a wide band on the outer periphery of the wafer, so that peeling, etc. Don't worry about the problem. In this case, since the non-shot area 33 is not exposed, no resist remains. In the negative type resist, the exposed portion of the resist opposite to the positive type resist remains after development. Therefore, in general, when applying negative resist and cutting the edge of the wafer edge, an organic solvent that can dissolve the resist is applied to the wafer edge through a thin nozzle tube without using a peripheral exposure machine. (While rotating the wafer).

  Next, a first embodiment of the present invention will be described.

  Before describing the capacitor forming step in the method of manufacturing a semiconductor device according to the first embodiment of the present invention, a step of forming a transistor on a silicon substrate (semiconductor substrate) with reference to FIGS. The process up to before forming is described.

As shown in FIG. 6, in order to partition the active region on the main surface of a semiconductor substrate (silicon substrate) 1 made of P-type silicon, an insulating film such as silicon oxide (SiO ₂ ) is formed by STI (Shallow Trench Isolation) method. An element isolation region 3 in which is embedded is formed in a portion other than the active region.

  Next, the groove pattern 2 for the gate electrode of the MOS transistor Tr1 (see FIG. 14) is formed. The groove pattern 2 is formed by etching using a pattern (not shown) in which silicon of the semiconductor substrate 1 is formed of a photoresist as a mask.

  Next, as shown in FIG. 7, the silicon surface of the semiconductor substrate 1 is oxidized to form silicon oxide by thermal oxidation, thereby forming a gate insulating film 5a having a thickness of about 4 nm in the transistor formation region. As the gate insulating film, a laminated film of silicon oxide and silicon nitride or a high-K film (high dielectric film) may be used.

Thereafter, polycrystalline silicon containing phosphorus (P) as an N-type impurity by a CVD (Chemical Vapor Deposition) method using monosilane (SiH ₄ ) and phosphine (PH ₃ ) as source gases on the gate insulating film 5a. Deposit a film. At this time, the film thickness is set such that the inside of the groove pattern 2 for the gate electrode is completely filled with the polycrystalline silicon film. A polycrystalline silicon film not containing impurities such as phosphorus may be formed, and desired impurities may be introduced into the polycrystalline silicon film by an ion implantation method in a later step. Next, a high melting point metal such as tungsten, tungsten nitride, tungsten silicide, or the like is deposited on the polycrystalline silicon film as a metal film by sputtering to a thickness of about 50 nm. The polycrystalline silicon film and the metal film are formed on the gate electrode 5 through the steps described later.

Next, a cap insulating film 5c made of silicon nitride is deposited to a thickness of about 70 nm by plasma CVD using monosilane and ammonia (NH ₃ ) as source gases on the metal film constituting the gate electrode 5. . Next, a photoresist (not shown) is applied on the cap insulating film 5c, and a photoresist pattern for forming the gate electrode 5 is formed by photolithography using a mask for forming the gate electrode 5.

  Then, the cap insulating film 5c is etched by anisotropic etching using the photoresist pattern as a mask. After removing the photoresist pattern, the metal film and the polycrystalline silicon film are etched using the cap insulating film 5c as a hard mask to form the gate electrode 5. The gate electrode functions as a word line.

  Next, as shown in FIG. 8, phosphorus is ion-implanted as an N-type impurity to form an impurity diffusion layer 8 in the active region not covered with the gate electrode 5.

  Thereafter, a silicon nitride film is deposited to a thickness of about 20 to 50 nm on the entire surface by CVD, and etching back is performed to form a side wall 5b on the side wall of the gate electrode 5.

  Next, an interlayer insulating film (not shown) of a silicon oxide film is formed by a CVD method so as to cover the cap insulating film 5c and the side wall 5b on the gate electrode, and the unevenness derived from the gate electrode 5 is flattened. Therefore, the surface is polished by a CMP (Chemical Mechanical Polishing) method. The polishing of the surface is stopped when the upper surface of the cap insulating film 5c on the gate electrode is exposed.

  Thereafter, the substrate contact plug 9 is formed as shown in FIG. Specifically, first, etching is performed using a pattern formed of a photoresist as a mask so as to form an opening at the position of the substrate contact portion, and the previously formed interlayer insulating film is removed. The opening can be provided between the gate electrodes 5 by self-alignment using the cap insulating film 5c formed of silicon nitride and the sidewall 5b. Thereafter, after depositing a polycrystalline silicon film containing phosphorus by the CVD method, polishing is performed by the CMP method, the polycrystalline silicon film on the cap insulating film 5c is removed, and the substrate contact filled in the opening is obtained. Plug 9 is used.

  Thereafter, an interlayer insulating film 4 made of silicon oxide is formed with a thickness of, for example, about 600 nm so as to cover the cap insulating film 5c and the substrate contact plug 9 on the gate electrode by CVD. Thereafter, the surface of the interlayer insulating film 4 is polished and planarized to a thickness of, for example, about 300 nm by CMP.

  Next, as shown in FIG. 10, an opening (contact hole) is formed at the position of the substrate contact portion in the interlayer insulating film 4 to expose the surface of the substrate contact plug 9. A bit line contact plug 4A is formed by depositing a film of tungsten (W) laminated on a barrier film such as TiN / Ti so as to fill the inside of the opening and polishing the surface by CMP. .

  Thereafter, bit wiring 6 is formed so as to be connected to bit line contact 4A.

  An interlayer insulating film 7 is formed of silicon oxide or the like so as to cover the bit wiring 6.

  Next, as shown in FIG. 11, an opening (contact hole) is formed at the position of the substrate contact portion so as to penetrate the interlayer insulating film 4 and the interlayer insulating film 7, and the surface of the substrate contact plug 9 is exposed. A capacitor contact plug 7A is formed by depositing a film of tungsten (W) laminated on a barrier film such as TiN / Ti so as to fill the inside of the opening and polishing the surface by CMP.

  A capacitive contact pad 10 is formed on the interlayer insulating film 7 using a laminated film containing tungsten. The capacitor contact pad 10 is placed in a size that is electrically connected to the capacitor contact plug 7A and is larger than the size of the bottom of the lower electrode of the capacitor element to be formed later.

  Thereafter, a stopper nitride film 11 is deposited to a thickness of, for example, 50 nm using silicon nitride so as to cover the capacitor contact pad 10.

  Next, with reference to FIG. 12A thru | or FIG. 12M and FIG. 13, the flow of the capacitor formation process in the manufacturing method of the semiconductor device which concerns on the 1st Example of this invention is demonstrated.

  Note that the same reference numerals are assigned to the same steps (components) as the capacitor forming step of the related art examined by the present inventors shown in FIG. 1A to FIG. 1M, for the sake of simplifying the description. Those descriptions are omitted. Accordingly, only the differences will be described below.

  Referring first to FIG. 12A, the membrane configuration is set to be the same as the related art discussed by the inventors shown in FIG. 1A. However, the outer peripheral edge cut width was changed from 0.7 mm to 1.7 mm.

  The peripheral edge cut width is also called a first width or a first wafer edge cut width. The region having the first width is also called a first ring-shaped region. The area excluding the first ring-shaped area is also called a first pattern area.

  This eliminates the point where defocusing occurs on the wafer. (In the related art studied by the inventors, defocusing occurs sporadically in an area of 1.7 mm inside the wafer from the outermost peripheral portion of the wafer.) The effective chip area is 1 from the outermost periphery of the silicon substrate 1 as in the prior art. It was set to a region excluding a region having 9 mm.

  Here, a width of 1.9 mm from the outermost periphery of the silicon substrate (semiconductor substrate) 1 is also referred to as a second width (outer diameter-inner diameter) or a second wafer edge cut width. A region having a second width (outer diameter−inner diameter) from the outermost periphery of the semiconductor substrate 1 is also referred to as a second ring-shaped region. The effective chip area, which is an area excluding the second ring-shaped area, is also referred to as a second pattern area. Therefore, the second width (second wafer edge cut width) of the second ring-shaped region is larger than the first width (first wafer edge cut width) of the first ring-shaped region.

  Next, as shown in FIG. 12B, a cylinder hole 12A penetrating to the stopper nitride film 11 (capacitor contact pad 10) is formed by oxide film dry etching, as in the related technique examined by the present inventors (see FIG. 1B). Then, the resist 17, the ARL film 16, and the α-C film 15 are removed by plasma peeling, dry etching, and plasma peeling.

  Next, as shown in FIG. 12C, the lower electrode film 18 having a film thickness of 25 nm is formed on the side wall of the cylinder hole 12A in the same manner as the related technique (see FIG. 1C) studied by the present inventors. The lower electrode film 18 is made of TiN having a thickness of 15 nm and Ti having a thickness of 10 nm. Thereafter, the lower electrode film 18 formed from the outermost periphery of the wafer to 0.7 mm and the lower electrode film 18 that has gone around the back surface of the wafer are removed by back surface etching.

  Next, as shown in FIG. 12D, in order to transfer the support pattern onto the support nitride film 13, the resist pattern of the support photoresist (PR) 20 is transferred in the same manner as the related technique (see FIG. 1D) examined by the present inventors. Provide. Since there is no defocusing of the cylinder PR, there is no pattern in which the support nitride film 13 disappears, and the support photoresist and the resist pattern (PR) 20 are all formed normally. The outer peripheral edge cut width is set to 1.7 mm in accordance with the cylinder photoresist (PR). This outer peripheral edge cut width of 1.7 mm is also referred to as a first width or a first wafer edge cut width as described above.

  Next, as shown in FIG. 12E, the lower electrode film 18 and the mask plasma oxide film 14 in the space region other than the support pattern are removed by dry etching, as in the related technique (see FIG. 1E) studied by the present inventors. Thereafter, the lower electrode 18 on the support nitride film 13 under the support photoresist (PR) 20 is removed.

  Next, as shown in FIG. 12F, the cylinder interlayer film 12 on the stopper nitride film 11 is completely removed using a hydrofluoric acid-based chemical solution as in the related technique examined by the present inventors (see FIG. 1F). All of the cylinders on the outer periphery of the wafer are connected by the support nitride film 13.

  Next, as shown in FIG. 12G, as in the related technique examined by the present inventors (see FIG. 1G), a capacitive insulating film having a thickness of 7.2 nm composed of a laminated film of an alumina film and a zirconium oxide film (see FIG. 12G). (Not shown), an upper electrode film (not shown) made of titanium nitride with a thickness of 10 nm, an upper electrode conductive film 21 with a thickness of 240 nm made of W / B-doped polysilicon / B-SiGe, and a film thickness A plate mask plasma oxide film 22 having a thickness of 100 nm is formed.

  Next, as shown in FIG. 12H, a resist pattern of a capacitor PL photoresist (PR) 23 is formed on the memory mat, as in the related technique (see FIG. 1H) studied by the present inventors. The capacitor PL photoresist (PR) 23 covers the underlying capacitor in units of memory mats. The outer peripheral edge cut width is set to a first width of 1.7 mm (first wafer edge cut width).

  Next, as shown in FIG. 12I, similarly to the related technology examined by the present inventors (see FIG. 1I), the resist pattern of the capacitor PL photoresist (PR) 23 is used as a mask and the film thickness is 100 nm. The plate mask plasma oxide film 22 is selectively dry etched. Next, the capacitor insulating film, the upper electrode film, and the upper electrode conductive film 21 are dry-etched using the remaining plate mask plasma oxide film 22 as a mask. Thereby, a first pattern having a first wafer edge cut width is formed on the main surface of the semiconductor substrate 1. In other words, the first pattern is formed in the first pattern region on the main surface of the semiconductor substrate 1.

  Next, as shown in FIG. 12J, the plate interlayer film 24 having a thickness of 3 μm is formed after the formation of the capacitor PL, as in the related technique (see FIG. 1J) studied by the present inventors. At this time, a large step occurs inside and outside the memory cell. The plate interlayer film 24 is also called a first interlayer insulating film or simply an interlayer insulating film. Therefore, a first interlayer insulating film (interlayer insulating film) 24 is formed on the first pattern so as to cover the main surface of the semiconductor substrate 1.

  Next, as shown in FIG. 12K, the resist is changed from the positive type resist to the negative type resist 25A, and is applied onto the wafer. This negative type resist 25A is also referred to as a first resist. Therefore, a negative type resist (first resist) 25 </ b> A is applied on the plate interlayer film 24.

  Peripheral exposure (first exposure process) for leaving the resist 26A in a strip shape on the outer periphery of the wafer (an area of about 1.8 mm from the outermost periphery) is performed by a peripheral exposure machine, and the portion where the plate interlayer film 24 is low Exposure (second exposure step) is performed to form a resist pattern of the step-reducing photoresist (PR) 26B using a reticle in the (peripheral circuit portion). Here, the order of exposure does not matter.

  The strip-shaped resist 26A is also called a second pattern, and the step-reduced PR photoresist (PR) 26B is also called a third pattern. Therefore, the first exposure process is an exposure process for forming the second pattern 26A covering the plate interlayer film 24 in the second ring-shaped region on the main surface of the semiconductor substrate 1. In the second exposure step, in the second pattern region, the opening is included in the first pattern in plan view on the main surface of the semiconductor substrate 1 and is different from the second pattern 26A. This is an exposure process for forming the third pattern 26B.

  Thereafter, by performing development processing, as shown in FIG. 13, the resist pattern 26B may be left on the outer periphery of the peripheral circuit portion and the memory mat 32, and the resist pattern 26A may be left in a band shape (ring shape) on the outer peripheral portion of the wafer. it can. This development process is a first development process for developing the first resist 25A.

  Therefore, by performing development processing on the negative type resist 25A, it is a resist pattern (blank pattern) that remains in a strip shape with a width provided in a region occupying the second wafer edge cut width, A second pattern 26A that overlaps the portion in plan view and a third pattern 26B having a second wafer edge cut width are formed.

  The third pattern 26B is connected to the second pattern 26A and overlaps the first pattern in plan view. As described above, the third pattern 26B is a pattern having an opening, and the opening includes the first pattern in plan view.

  The second pattern 26A and the third pattern 26B are also collectively referred to as second patterns (26A, 26B). Accordingly, the second pattern (26A, 26B) is a reverse pattern of the first pattern formed immediately below the interlayer insulating film 24 by exposing and developing the negative type resist 25A.

Peripheral exposure machines (see US Patent No: US 7,651,285 B2), single units or those incorporated in the developing device or the present exposure machine may be used. For example, if a 500 W ultra-high pressure mercury lamp is used as the light source and the illuminance is 1000 mW / cm ² or more, it can be fully utilized. For reference, the peripheral exposure machine can be ACT12 (coating / development specification) manufactured by Tokyo Electron or PE-250 R2 manufactured by USHIO.

  In the peripheral exposure, there is no particular problem even if the outermost peripheral tip is not covered as shown in FIG. 12K. As in the case of the peripheral exposure machine used in the first embodiment of the present invention, there is a case where sufficient illuminance (light quantity) does not reach the tip, but if it is only a part of the tip and a part of the wafer outer periphery. There is no particular problem.

  Next, as shown in FIG. 12L, the height of the plate interlayer 24 without the resist pattern is high in order to reduce the level difference between the inside and outside of the memory mat 32, as in the related technique examined by the present inventors (see FIG. 1L). The portion is etched by dry etching. Therefore, a part of the plate interlayer film 24 on the first pattern is removed using the second pattern and the third pattern as a mask. At this stage, the steps inside and outside the memory mat may be completely eliminated. This may be adjusted in any way by feeding back the quality after the CMP. Further, the resist pattern is removed by plasma peeling. That is, the second pattern 26A and the third pattern 26B are removed.

  As can be seen from FIG. 13, the plate interlayer film 24 remains at one end facing the outside of the outermost periphery of the cylinder pattern without being etched.

  In FIG. 12L, a portion surrounded by an ellipse is a portion that receives a strong pressing pressure in the subsequent CMP.

  Next, as shown in FIG. 12M, similarly to the related technique examined by the present inventors (see FIG. 1M), the region of the convex portion on the plate interlayer film 24 is selectively polished using the oxide film CMP. After polishing, when the predetermined plate interlayer film thickness is not reached, a plate interlayer film (second plate interlayer film) may be additionally grown again. In this manner, the plate interlayer film 24 is planarized using CMP.

  Here, since the plate interlayer film 24 remains in an as-deposited state on the outer periphery of the wafer, there is no risk of overpolishing to the cylinder pattern even if the polishing rate is high.

  As described above, the capacitor element 30 (see FIG. 14) is formed.

  Next, referring to FIG. 14, in the memory cell portion, a lead contact plug (not shown) for applying a potential to the upper electrode conductive film 21 of the capacitor element 30 is formed.

  Thereafter, the upper wiring layer 27 is formed of aluminum (Al), copper (Cu), or the like. Further, if the protective film 28 on the surface is formed of silicon oxynitride (SiON) or the like, the memory cell portion of the DRAM element is completed.

As described above, the semiconductor manufacturing method according to the first embodiment of the present invention is as follows.
Forming a first pattern having a first wafer edge cut width on the main surface of the semiconductor substrate (1);
Forming an interlayer insulating film (24) on the first pattern;
Applying a negative type resist (25A) on the interlayer insulating film (24);
Performing a first exposure using a peripheral exposure machine on the negative type resist (25A);
Performing a second exposure on the negative type resist (25A);
The first pattern is a blank pattern provided in a region occupying a second wafer edge cut width larger than the first wafer edge cut width by developing the negative resist (25A). Forming a second pattern (26A) covering a part of the second pattern and a third pattern (26B) having the second wafer edge cut width;
Removing a part of the interlayer insulating film (24) on the first pattern using the second pattern (26A) and the third pattern (26B) as a mask;
A method for manufacturing a semiconductor device having

  The effect of the first embodiment of the present invention will be described.

  Step exposure reduction PR is performed using the negative type resist 25A (second exposure), and then the peripheral exposure machine is used to occupy the edge cut width (second width) of the outer periphery of the wafer (second width). The resist (first and second patterns) 26A and 26B are intentionally left in the region covering the cell mat 32 on the outermost peripheral side of the wafer (width of 0.1 μm or more), so that pressing during CMP is performed. The thick plate interlayer 24 can be left in the portion with the strongest pressure (the portion surrounded by the ellipse in FIG. 12L). As a result, the capacitor element 30 in the cell mat 32 on the outermost peripheral side of the wafer is not destroyed by overpolishing. Therefore, it was possible to avoid the problems of dust caused by overpolishing and microscratches caused by dust, which have been generated conventionally. As a result, the product yield was improved by 3% to 4%, and problems related to product reliability were suppressed.

  Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described.

  In the second embodiment, a blank pattern (second pattern) is formed in a region (second ring-shaped region) having an edge cut width (second width) at the outer periphery of the wafer as a resist for level difference reduction PR. And then forming a main exposure pattern (third pattern) with a positive resist. Either order may be used first, but pattern formation with a negative resist with few process problems is selected first.

  That is, in the method of manufacturing the semiconductor device according to the second embodiment of the present invention, the step of forming the step-reducing photoresist (PR) shown in FIG. 12K is divided into two steps of FIG. Except for these points, the method is the same as that of the semiconductor device manufacturing method according to the first embodiment of the present invention described above.

  More specifically, the steps up to the step of forming the step reduction PR are the same as those in the first embodiment (see FIGS. 12A to 12J).

  In the second embodiment, as shown in FIG. 15A, in the step of forming the step reduction PR, first, a negative type resist 25A is applied onto the wafer, and peripheral exposure (first exposure) is performed to a predetermined width A on the outer periphery of the wafer. 1), a blank pattern (second pattern) 26A is formed on the outer peripheral portion of the wafer (second ring-shaped region) by development.

  Next, as shown in FIG. 15B, a positive type resist 25 is applied on the wafer, and a main exposure (second exposure) is performed using a reticle. This positive type resist 25 is also called a second resist. Further, if the resist remains on the entire surface in the non-shot portion, the polishing rate is lowered in the subsequent CMP process as described above. Therefore, the entire wafer surface is shot without forming the non-shot portion. Further, peripheral exposure is performed to a predetermined width B on the outer periphery of the wafer, which is an area not exceeding the blank pattern (second pattern), and development is performed. Thereby, the third pattern 26B is formed.

  The subsequent flow is the same as that of the first embodiment (see FIGS. 12L to 12M).

  The effect of the semiconductor device manufacturing method according to the second embodiment of the present invention will be described.

  Using a peripheral exposure machine with a negative resist (first resist) 25A, the resist (second pattern) 26A is intentionally left in the region occupying the edge cut width of the outer periphery of the wafer. By applying a positive type resist 25 on the wafer and performing a main exposure (second exposure) using a reticle, the portion with the strongest pressing pressure during CMP (the portion surrounded by an ellipse in FIG. 12L) is thick. The plate interlayer 24 can be left. As a result, the capacitor element on the cell mat 32 on the outermost peripheral side of the wafer is not destroyed by overpolishing. Therefore, it was possible to avoid the problems of dust caused by overpolishing and microscratches caused by dust, which have been generated conventionally. As a result, the product yield was improved by 3% to 4%, and problems related to product reliability were suppressed.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  The present invention can be used in a manufacturing method related to planarization of a DRAM or other memory product having a high step element such as a DRAM capacitor.

1 Semiconductor substrate (silicon substrate)
2 Gate pattern 3 Element isolation region 4 Interlayer insulating film 4A Bit line contact plug 5 Gate electrode 5a Gate insulating film 5b Side wall 5c Cap insulating film 6 Bit wiring 7 Interlayer insulating film 7A Capacitor contact plug 8 Impurity diffusion layer 9 Substrate contact plug 10 Capacitance contact pad 11 Stopper nitride film 12 Cylinder interlayer film 12A Cylinder hole 13 Support nitride film 14 Mask plasma oxide film 15 Amorphous carbon film (α-C film)
16 ARL film 17 Resist 18 Lower electrode film 19 Resist film 20 Support photoresist (PR)
21 upper electrode conductive film 22 plate mask plasma oxide film 23 capacitance PL photoresist (PR)
24 Plate interlayer film 24A Convex part 24B Part where no convex part remains 25 Positive type resist (step-reducing photoresist (PR))
25A Negative type resist 26A, 26B Step-reducing photoresist (PR)
27 Wiring layer 28 Protective film 30 Capacitor element 31 Peripheral circuit portion 32 Memory mat 33 Non-shot area 34 Effective chip 35 Silicon substrate outermost peripheral line 36 Effective area outermost peripheral line 37 Field shot unit 38 Ineffective chip 39 Scribe line center 40 Scribe area

Claims (18)

In the first pattern region on the main surface of the semiconductor substrate, excluding the first ring-shaped region including the outermost periphery of the semiconductor substrate and having the first width (outer diameter-inner diameter), the first pattern Forming a step;
Forming a first interlayer insulating film on the first pattern so as to cover the main surface of the semiconductor substrate;
Applying a first resist on the first interlayer insulating film;
On the main surface of the semiconductor substrate, a second pattern that covers the first interlayer insulating film is formed in a second ring-shaped region having a second width (outer diameter-inner diameter) from the outermost periphery of the semiconductor substrate. A first exposure step for forming;
In the second pattern region excluding the second ring-shaped region, an opening is included in the first pattern in plan view on the main surface of the semiconductor substrate, and the second pattern is A second exposure step for forming a different third pattern;
A first developing step for developing the first resist;
Using the second pattern and the third pattern as a mask, removing a part of the first interlayer insulating film on the first pattern,
The method for manufacturing a semiconductor device, wherein the second width of the second ring-shaped region is larger than the first width of the first ring-shaped region.   The method for manufacturing a semiconductor device according to claim 1, wherein the second pattern is connected to the third pattern and overlaps the first pattern in a plan view. After removing the part of the first interlayer insulating film on the first pattern using the second pattern and the third pattern as a mask,
Removing the second pattern and the third pattern;
Planarizing the first interlayer insulating film using CMP; and
The method of manufacturing a semiconductor device according to claim 1, wherein: After the step of planarizing the first interlayer insulating film using the CMP,
4. The method of manufacturing a semiconductor device according to claim 3, further comprising a step of forming a second interlayer insulating film.   The method of manufacturing a semiconductor device according to claim 1, wherein the first resist is a negative type resist.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second exposure step is an exposure step using a wafer edge exposure machine. In the step of forming the first pattern,
Forming a lower electrode of a crown-shaped capacitor having a cylindrical shape;
Forming a capacitive insulating film covering the lower electrode;
Forming an upper electrode covering the capacitive insulating film,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the first pattern is formed in units of memory mats. The method of manufacturing a semiconductor device according to claim 7, wherein the first pattern further includes a laminated film of a B-doped polysilicon film and a B—SiGe film on the upper electrode. Before the second exposure step, the first development step,
A step of stripping the first resist;
And a positive resist second resist coating step,
Furthermore, after the second exposure step,
The method of manufacturing a semiconductor device according to claim 1, further comprising a second development step of developing the second resist. Forming a first pattern having a first wafer edge cut width on a main surface of a semiconductor substrate;
Forming an interlayer insulating film on the first pattern;
Applying a negative type resist on the interlayer insulating film;
Performing a first exposure using a peripheral exposure machine on the negative type resist;
Performing a second exposure on the negative type resist;
A blank pattern provided in a region occupying a second wafer edge cut width larger than the first wafer edge cut width by developing the negative resist, and a part of the first pattern Forming a second pattern that overlaps in plan view and a third pattern having the second wafer edge cut width;
Removing a part of the interlayer insulating film on the first pattern using the second pattern and the third pattern as a mask;
A method for manufacturing a semiconductor device comprising:   The method of manufacturing a semiconductor device according to claim 10, wherein the third pattern is a pattern having an opening, and the opening includes the first pattern in a plan view. After the step of removing a part of the interlayer insulating film using the second pattern and the third pattern as a mask,
Removing the second pattern and the third pattern;
Using CMP to planarize the interlayer insulating film; and
The method of manufacturing a semiconductor device according to claim 10, comprising:   11. The semiconductor device according to claim 10, wherein the step of removing a part of the insulating interlayer film using the second pattern and the third pattern as a mask is a dry etching step. Production method. The step of forming the first pattern includes:
Forming a lower electrode of a crown-shaped capacitor having a cylindrical shape;
Forming a capacitive insulating film covering the lower electrode;
Forming an upper electrode covering the capacitive insulating film,
11. The method of manufacturing a semiconductor device according to claim 10, wherein the first pattern is formed in units of memory mats. The method of manufacturing a semiconductor device according to claim 14, wherein the first pattern further includes a laminated film of a B-doped polysilicon film and a B—SiGe film on the upper electrode. Forming a first pattern with a first wafer edge cut width on a main surface of a semiconductor substrate;
Forming an interlayer insulating film on the first pattern;
A step of applying a negative type resist on the interlayer insulating film and exposing / developing the negative type resist to form a second pattern which is a reverse pattern of the first pattern immediately below the interlayer insulating film And a process of
Removing a part of the interlayer insulating film on the first pattern using the second pattern as a mask,
The method for manufacturing a semiconductor device, wherein the exposure is divided into first exposure using a peripheral exposure machine and second exposure using a reticle.   The method of manufacturing a semiconductor device according to claim 16, wherein the second pattern has a portion overlapping the first pattern in plan view.   17. The method of manufacturing a semiconductor device according to claim 16, wherein the first exposure is exposure for leaving a resist in a region occupying the first wafer edge cut width.

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