JP2014176162A - Voltage generation circuit and ion generation device with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage generation circuit which can fine-tune frequency of a driving signal to a piezoelectric transformer using an inexpensive microcomputer without increasing costs.SOLUTION: A high voltage generation circuit 10 has: a piezoelectric transformer T which outputs output voltage VT in accordance with a frequency of a driving signal Sd; and a microcomputer 5. The microcomputer 5 generates the driving signal Sd of variable frequency by dividing a clock signal Sclk to output the driving signal Sd to the piezoelectric transformer T. The microcomputer 5 switches frequency mutually between a frequency f1 which is less than a resonance frequency f0 of the piezoelectric transformer T and a frequency f2 which is equal to or larger than the resonance frequency f0 of the piezoelectric transformer T to determine the frequency of the driving signal Sd.

Description

  The present invention relates to a voltage generation circuit and an ion generation device including the voltage generation circuit, and more particularly to a voltage generation circuit including a piezoelectric transformer and an ion generation device including the voltage generation circuit.

  In order to reduce the size and weight of the power supply device, a voltage generation circuit including a piezoelectric transformer has been studied. For example, a piezoelectric transformer type high voltage power supply device disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2011-250549) includes a DC high voltage generation circuit, detection means, and a control unit. The DC high voltage generation circuit includes a piezoelectric transformer, a driving circuit for the piezoelectric transformer, and a rectifying circuit that rectifies the output of the piezoelectric transformer. The detecting means detects the output voltage or output current of the DC high voltage generation circuit. The control unit controls the direct-current high-voltage generation circuit by giving a drive signal whose output voltage or output current value detected by the detection means is a target value to the drive circuit. The control unit changes the frequency by fixing the duty of the drive signal applied to the drive circuit, and sets the output voltage or output current to a frequency that is within a certain range with respect to the target value. After setting the frequency to be within a certain range, the control unit changes the duty of the drive signal so that the output voltage or the output current becomes a target value.

  A piezoelectric transformer type high voltage power supply device disclosed in Patent Document 2 (Japanese Patent Laid-Open No. 2011-199937) includes a piezoelectric transformer, frequency multiplying means, drive pulse generating means, voltage value detecting means, and frequency calculating means. With. The piezoelectric transformer outputs a voltage corresponding to the frequency of the drive pulse. The frequency multiplication means multiplies the frequency of the clock signal. The drive pulse generator generates a drive pulse from the multiplied clock signal multiplied by the frequency multiplier. The voltage value detection means detects the output voltage of the piezoelectric transformer. The frequency calculation means calculates the frequency of the drive pulse input to the piezoelectric transformer from the difference between the detection result of the voltage value detection means and the target voltage. The piezoelectric transformer type high-voltage power supply device controls the frequency of the drive pulse by changing the multiplication number of the frequency multiplication means according to the frequency calculated by the frequency calculation means. As a result, the piezoelectric transformer type high voltage power supply device controls the voltage output from the piezoelectric transformer to be the target voltage.

JP 2011-250549 A JP 2011-199937 A

  The output voltage of the piezoelectric transformer depends on the driving frequency (frequency of the driving signal). In general, the output voltage-drive frequency curve of a piezoelectric transformer has a sharp peak centered on the resonance frequency. For this reason, the drive frequency is required to be as close as possible to the resonance frequency. Further, the resonance frequency differs for each piezoelectric transformer. Therefore, the piezoelectric transformer type high-voltage power supply device disclosed in Patent Document 1 finely adjusts the drive frequency according to the characteristics of each piezoelectric transformer.

  In general, the resolution of the drive frequency that can be adjusted by the microcomputer depends on the frequency (clock frequency) fclk of the clock signal supplied to the microcomputer. That is, in the piezoelectric transformer drive circuit driven by the microcomputer, the difference value (Ta−Tb) between the cycle Ta of one drive signal and the cycle Tb of another drive signal is a natural value of the clock cycle (clock signal cycle) Tclk. It is equal to several times ((Ta−Tb) = k × Tclk (k is a natural number))).

  As an example, the condition of the clock frequency for adjusting the drive frequency from 100 kHz to 101 kHz will be described. The period of the driving signal having a frequency of 100 kHz is 10 us (microseconds). The period of the drive signal having a frequency of 101 kHz is about 9.9 us (microseconds). For this reason, the difference value of the periods of the drive signals having the frequencies of 100 kHz and 101 kHz is about 100 ns (nanoseconds). In order to be able to adjust such a driving frequency, the natural number multiple of the clock cycle Tclk needs to be about 100 ns (nanoseconds). Therefore, the clock frequency fclk must be at least 10 MHz.

  Also, the condition of the clock frequency for adjusting the drive frequency from 100 kHz to 100.5 kHz will be described. The period of the drive signal having a frequency of 100.5 kHz is about 9.95 us (microseconds). For this reason, the difference value of the periods of the drive signals having the frequencies of 100 kHz and 100.5 kHz is about 50 ns (nanoseconds). Therefore, the natural number multiple of the clock cycle Tclk needs to be about 50 ns (nanoseconds). Thus, the clock frequency fclk must be at least 20 MHz. Thus, in order to reduce the resolution for finely adjusting the drive frequency, a microcomputer having a high clock frequency fclk is required.

  In general, a microcomputer is more expensive as the clock frequency fclk is higher if the functions are the same. Therefore, if an expensive microcomputer is selected for fine adjustment of the driving frequency, the cost of the circuit may increase.

  In addition, the piezoelectric transformer type high-voltage power supply device disclosed in Patent Document 2 requires frequency multiplication means in order to adjust the drive frequency with high accuracy. By adding the frequency multiplication means, the cost of the circuit increases.

  An object of the present invention is to provide a voltage generation circuit capable of finely adjusting the frequency of a drive signal to a piezoelectric transformer using an inexpensive microcomputer without increasing the cost, and an ion generation device including the voltage generation circuit It is to be.

  A voltage generation circuit according to an aspect of the present invention includes a piezoelectric transformer and a control circuit. The piezoelectric transformer outputs a voltage corresponding to the frequency of the drive signal. The control circuit generates a drive signal by dividing the clock signal and outputs a drive signal having a variable frequency to the piezoelectric transformer. The control circuit determines a first frequency that is less than the resonance frequency of the piezoelectric transformer and a second frequency that is greater than or equal to the resonance frequency, and a drive signal so as to switch alternately between the first frequency and the second frequency. Is output.

  Preferably, the voltage generation circuit further includes a first detection circuit. The first detection circuit detects an output voltage from the piezoelectric transformer and outputs a first detection value to the control circuit. The control circuit changes the first and second frequencies in the frequency band including the resonance frequency, and selects the first and second frequencies that maximize the first detection value.

  An ion generation apparatus according to another aspect of the present invention includes the voltage generation circuit and an ion generation unit that generates ions when an output voltage from the voltage generation circuit is applied.

  Preferably, in a state where the first and second frequencies are fixed to a frequency at which the first detection value is maximized, the control circuit changes the duty ratio of the drive signal and is based on the first detection value. Adjust the output voltage.

  Preferably, the voltage generation circuit further includes a second detection circuit. The second detection circuit detects the discharge current and outputs a second detection value to the control circuit. In a state where the first and second frequencies are fixed to a frequency at which the first detection value is maximum, the control circuit changes the duty ratio of the drive signal and discharges based on the second detection value. Adjust the current.

  According to the present invention, a voltage generation circuit capable of finely adjusting the frequency of a drive signal to a piezoelectric transformer and an ion generation device including the voltage generation circuit using an inexpensive microcomputer without increasing the cost are realized. can do.

It is a block diagram which shows roughly the structure of the ion generator provided with the voltage generation circuit which concerns on Embodiment 1 of this invention. FIG. 2 is a circuit block diagram schematically showing a configuration of a voltage generation circuit shown in FIG. 1. It is a figure for demonstrating the resonant frequency of the piezoelectric transformer shown in FIG. FIG. 3 is a diagram for explaining a frequency of a drive signal output from a control circuit shown in FIG. 2. FIG. 3 is a timing chart for explaining the adjustment of the frequency of the drive signal shown in FIG. 2. FIG. It is a figure showing the frequency dependence of the voltage applied to the ion generating part shown in FIG. It is a flowchart showing the frequency scanning process by the control circuit shown in FIG. It is a conceptual diagram for demonstrating the scanning of the frequency in the flowchart shown in FIG. It is a figure showing the result of the frequency scanning process of the flowchart shown in FIG. It is a circuit block diagram which shows roughly the structure of the voltage generation circuit which concerns on Embodiment 2 of this invention. FIG. 11 is a conceptual diagram for explaining the influence of the duty ratio of the drive signal on the applied voltage output from the voltage generation circuit shown in FIG. 10. FIG. 11 is a diagram illustrating a relationship between a duty ratio in a piezoelectric transformer and an output voltage in the voltage generation circuit illustrated in FIG. 10. It is a flowchart showing the duty ratio scanning process by the control circuit shown in FIG. It is a figure showing the result of the duty ratio scanning process of the flowchart shown in FIG. It is a conceptual diagram for demonstrating the quality determination process of the ion generation part in the flowchart shown in FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same or an equivalent part in a figure, and the description is not repeated.

[Embodiment 1]
FIG. 1 is a block diagram schematically showing a configuration of an ion generation apparatus including a high voltage generation circuit according to Embodiment 1 of the present invention. Referring to FIG. 1, ion generator 100 includes an input terminal 1, an AC / DC converter 2, a high voltage generation circuit (voltage generation circuit) 10, an ion generator 3, and a clock oscillator 4. .

  Input terminal 1 receives AC power from an external AC power supply (for example, a commercial power supply, not shown) and outputs the AC power to AC / DC conversion unit 2. The AC / DC converter 2 converts AC power from the input terminal 1 into DC power and outputs the DC power to the high voltage generation circuit 10. The high voltage generation circuit 10 boosts the DC voltage from the AC / DC converter 2 and outputs the voltage to the ion generator 3. The ion generator 3 generates ions when a voltage from the high voltage generation circuit 10 is applied. The clock oscillator 4 supplies a clock signal Sclk to the high voltage generation circuit 10. When receiving DC power from the outside, the AC / DC conversion unit 2 can be omitted, and a constant voltage circuit (not shown) is provided instead of the AC / DC conversion unit 2. Further, the clock signal Sclk may be supplied from, for example, a clock generation circuit (not shown) provided in the high voltage generation circuit 10.

  FIG. 2 is a circuit block diagram schematically showing the configuration of the high voltage generation circuit 10 shown in FIG. Referring to FIG. 2, high voltage generation circuit 10 includes a microcomputer (control circuit) 5, a booster circuit 101, rectifier circuits 102 and 104, and a voltage divider circuit (first detection circuit) 103. The microcomputer 5 includes a CPU (Central Processing Unit) 51, a drive signal generation unit 52, an A / D converter 53, and a memory 54. The ion generator 3 includes a positive discharge electrode Ep, a negative discharge electrode En, and induction electrodes Eg1, Eg2.

  The booster circuit 101 includes a piezoelectric transformer T, an inductor L, a transistor Q, a capacitor C1, and a resistor R1. The transistor Q is, for example, an NMOS (Negative-channel Metal Oxide Semiconductor) transistor. One end of the inductor L receives the DC voltage Vdc generated by the AC / DC converter. The other end of the inductor L is electrically connected to the drain of the transistor Q. The source of the transistor Q is electrically connected to the ground potential GND. Between the drain and source of the transistor Q, a piezoelectric transformer T and a capacitor C1 are connected in parallel.

  The drive signal generator 52 generates a drive signal Sd based on the control of the CPU 51. The drive signal Sd is supplied to the gate of the transistor Q via the resistor R1. The piezoelectric transformer T outputs a voltage corresponding to the drive frequency (frequency of the drive signal Sd) fd from the output node. When the drive frequency fd is matched with the resonance frequency f0 of the piezoelectric transformer T, the output voltage VT of the piezoelectric transformer T becomes maximum.

  The rectifier circuit 102 includes diodes D1 and D2. The diode D <b> 1 is connected between the output node of the piezoelectric transformer T and the voltage dividing circuit 103 in such a direction that the anode is on the output node side of the piezoelectric transformer T. The diode D2 is connected between the anode of the diode D1 and the ground potential GND in such a direction that the anode is on the ground potential GND side. The rectifying circuit 102 rectifies the output voltage VT from the piezoelectric transformer T into a positive voltage and outputs the voltage to the voltage dividing circuit 103.

  The voltage dividing circuit 103 has resistors R2 to R4. The resistor R2 is electrically connected between the cathode of the diode D1 and the positive discharge electrode Ep. The resistors R3 and R4 are connected in series between the positive discharge electrode Ep and the ground potential GND. The voltage rectified by the rectifier circuit 102 is divided by the resistors R2 to R4. The reference voltage Vref at the connection point between the resistor R3 and the resistor R4 is expressed as Vref = VT × R4 / (R2 + R3 + R4).

  The reference voltage Vref is fed back to the A / D converter 53. The A / D converter 53 converts the reference voltage Vref into a digital value and outputs the value of the reference voltage Vref to the CPU 51. The memory 54 stores the value of the drive frequency fd and the value of the reference voltage Vref based on the control of the CPU 51.

  The rectifier circuit 104 includes a capacitor C2, a diode D3, and a diode D4. Capacitor C2 is electrically connected between the output node of piezoelectric transformer T and diode D3 and diode D4. The diode D3 is connected between the capacitor C2 and the negative discharge electrode En so that the cathode is on the capacitor C2 side. The diode D4 is connected between the cathode of the diode D3 and the ground potential GND in such a direction that the cathode is on the ground potential GND side. The rectifier circuit 104 rectifies the output voltage VT from the booster circuit 101 to a negative voltage and outputs the voltage to the negative discharge electrode En.

  The positive discharge electrode Ep receives a positive voltage from the voltage dividing circuit 103. The negative discharge electrode En receives a negative voltage from the rectifier circuit 104. Each of induction electrodes Eg1, Eg2 is electrically connected to ground potential GND. The positive discharge electrode Ep and the induction electrode Eg1 are arranged to face each other. The negative discharge electrode En and the induction electrode Eg2 are disposed so as to face each other. The voltage boosted by the piezoelectric transformer T is applied as a positive voltage between the electrodes (between the positive discharge electrode Ep and the induction electrode Eg1). When the electric field strength between the electrodes exceeds a certain level, positive corona discharge occurs. Thereby, positive ions are generated. On the other hand, the voltage boosted by the piezoelectric transformer T is applied as a negative voltage between the electrodes (between the negative discharge electrode En and the induction electrode Eg2). When the electric field strength between the electrodes exceeds a certain level, negative corona discharge occurs. Thereby, negative ions are generated.

The ion generator 100 can also generate ions of either polarity. However, in this embodiment, ion generator 100 generates substantially equal amounts of bipolar ions. A positive ion is a cluster ion in which a plurality of water molecules are attached around a hydrogen ion (H ⁺ ). The positive ions are represented as H ⁺ (H ₂ O) _m (m is a natural number). A negative ion is a cluster ion in which a plurality of water molecules are attached around an oxygen ion (O ₂ ⁻ ). Negative ions are represented as O ₂ ⁻ (H ₂ O) _n (n is a natural number). When positive ions and negative ions attach to and surround a mold or virus floating in the air, a chemical reaction occurs. By the action of the active species hydroxyl radical (.OH) or hydrogen peroxide (H ₂ O ₂ ) produced at that time, effects such as removal of floating mold or virus inactivation can be obtained. It is also known that positive ions and negative ions adhere to odorous substances to remove or reduce odors.

  In addition, the structure of the electrode of the ion generating part 3 is not limited to said structure. The present invention is also applicable to an ion generator that does not have the induction electrodes Eg1 and Eg2 and generates ions by discharging into the atmosphere from the positive discharge electrode Ep and the negative discharge electrode En. The present invention can also be applied to an ion generator that generates ions by creeping discharge.

  FIG. 3 is a diagram for explaining the resonance frequency f0 of the piezoelectric transformer T shown in FIG. Referring to FIG. 3, the horizontal axis represents drive frequency fd. The vertical axis represents the applied voltage Vp.

  The resonance frequency f0 of the piezoelectric transformer T is, for example, 160 kHz. In general, the piezoelectric transformer has a resonance point where the amplitude amplification factor increases rapidly with respect to the frequency of the drive signal, and the Q value at this resonance point is large (for example, 1,000 or more). Therefore, the applied voltage Vp-drive frequency fd curve has a sharp peak near the resonance point. The half width of this peak varies depending on the characteristics of the piezoelectric transformer T, but is, for example, 1 kHz. If the drive frequency fd is not included in the frequency band near the resonance frequency f0 (for example, the frequency band within the half width), the applied voltage Vp is significantly reduced. In this case, the applied voltage Vp expected at the time of designing the high voltage generation circuit 10 cannot be obtained. Therefore, it is necessary to determine the drive frequency fd so that it is located in the frequency band near the resonance frequency f0. However, the frequency characteristics of the piezoelectric transformer vary from part to part. In addition, the characteristics of the inductor and the characteristics of the capacitor also vary from part to part. Therefore, it is necessary to finely adjust the drive frequency fd of the booster circuit 101.

  FIG. 4 is a diagram for explaining the frequency fd of the drive signal Sd output from the drive signal generation unit 52 shown in FIG. Referring to FIG. 4A, in this embodiment, in the process of finely adjusting the drive frequency fd in accordance with the frequency characteristics of the piezoelectric transformer, the frequencies f1 (first frequency) and f2 (second frequency) Is used. The CPU 51 determines the drive frequency fd so as to alternately switch between the frequency f1 and the frequency f2 every cycle. The period T1 is a period corresponding to the frequency f1. The period T2 is a period corresponding to the frequency f2.

  FIG. 5 is a timing chart for explaining the adjustment of the drive frequency fd shown in FIG. Referring to FIG. 5, the horizontal axis is a time axis. The vertical axis represents the voltage of the clock signal Sclk or the voltage of the drive signal Sd. The clock cycle Tclk is the cycle of the clock signal Sclk.

  The drive signal Sd having the frequencies f1 and f2 is generated by dividing the clock signal Sclk. The period T1 includes, for example, N (N is a natural number) clock periods Tclk (T1 = N × Tclk). In this case, the period T2 can be determined such that (N + 1) clock periods Tclk are included (T2 = (N + 1) × Tclk). That is, the frequencies f1 and f2 can be determined so that the difference value between the cycle T1 and the cycle T2 is equal to the clock cycle Tclk (T1-T2 = Tclk).

  As an example, when the clock frequency fclk = 25 MHz, the clock cycle Tclk = 40 ns (nanoseconds). If it is determined that the frequency f1 = 159.5 kHz and the frequency f2 = 160.5 kHz, the period T1 = 6.27 us (microseconds) and the period T2 = 6.23 us (microseconds). Therefore, the difference value (T1-T2) = 40 ns (nanosecond) between the period T1 and the period T2 is equal to the clock period Tclk. In this way, the widths of the frequencies f1 and f2 are determined.

  The drive frequency fd is alternately switched between the frequencies f1 and f2. In FIG. 5, the difference value between the cycle T1 and the cycle T2 is equal to the clock cycle Tclk. However, the drive frequency fd may be alternately switched between frequencies f1 and f2 at which the difference value between the period T1 and the period T2 is equal to an integer multiple of 2 or more of the clock period Tclk (T1−T2 = nTclk ( n is an integer of 2 or more)). In the process of finely adjusting the drive frequency fd, a condition where the frequencies f1 and f2 are equal to each other can be used (T1 = T2). That is, the drive frequency fd may be set to the frequency f1 (or frequency f2), and the frequency f1 (or frequency f2) may be changed.

  Next, referring to FIG. 4B, the period Tm is an intermediate period between the periods T1 and T2 (Tm = (T1 + T2) / 2). That is, the frequency fm (see FIG. 6) corresponding to the period Tm is an intermediate frequency between the frequencies f1 and f2 (fm = (f1 + f2) / 2). When the output signal corresponding to the input of the drive signal of the frequency fm is obtained when the drive signal of the frequency f1 and the drive signal of the frequency f2 are alternately input to the piezoelectric transformer, the drive signal of the frequency f1 and the frequency f2 It is proved that it is equivalent to alternately input the drive signal of the frequency fm and to input the drive signal of the frequency fm.

  According to the verification experiment of the present inventor, the value of the applied voltage Vp obtained as a result of inputting the drive signal Sd shown in FIG. 4A is the input of the drive signal Sd shown in FIG. It was equivalent to the value of the applied voltage Vp obtained as a result. In other words, by alternately switching the drive frequency fd between the frequencies f1 and f2 for each cycle, the value of the applied voltage Vp equivalent to the case where the drive frequency fd is fixed at the frequency fm was obtained. By using the result of this verification experiment, the control described below becomes possible.

  FIG. 6 is a diagram showing the frequency dependence of the voltage Vp applied to the ion generator 3 shown in FIG. Referring to FIG. 6, the horizontal axis represents drive frequency fd. The vertical axis represents the applied voltage Vp. The voltages V1 and V2 are values of the applied voltage Vp at the frequencies f1 and f2, respectively. The voltage Vm is the value of the applied voltage Vp at the frequency fm. The voltage V0 is the value of the applied voltage Vp at the resonance frequency f0.

  Referring to FIG. 6A, of the frequencies f1, f2, and fm, the frequency fm is closest to the resonance frequency f0. In this case, the voltage Vm is smaller than the voltage V0 but larger than the voltages V1 and V2. Therefore, the input voltage Vp can be increased in the same manner as when a signal having the frequency fm is input by inputting a signal that switches between the frequencies f1 and f2 for each cycle as the drive frequency fd.

  With reference to FIG. 6B, of the frequencies f1, f2, and fm, the frequency f1 is closest to the resonance frequency f0. In this case, the voltage V1 is the largest of the voltages V1, V2, and Vm. That is, when the drive frequency fd is fixed at the frequency f1, the applied voltage Vp becomes the largest. Since the same applies to the case where the frequency f2 is closest to the resonance frequency f0, the detailed description will not be repeated.

  As described above, the drive frequency fd at which the applied voltage Vp is maximized differs depending on the relationship between the frequencies f1, f2, and fm and the resonance frequency f0. Further, the value of the resonance frequency f0 is different for each piezoelectric transformer as described above. Therefore, as described below, the drive frequency fd at which the applied voltage Vp is maximized is determined by scanning the frequencies f1 and f2 in the frequency band including the resonance frequency f0.

  FIG. 7 is a flowchart showing frequency scanning processing by the microcomputer 5 shown in FIG. FIG. 8 is a conceptual diagram for explaining scanning of the frequencies f1 and f2 in the flowchart shown in FIG. Referring to FIG. 8, the horizontal axis represents frequency f1 or frequency f2. The vertical axis represents the reference voltage Vref detected by the A / D converter 53.

  Referring to FIGS. 7 and 8, for example, a series of processes is started when the ion generator 100 is turned on. In the present embodiment, the frequency band in which the frequencies f1 and f2 are scanned is defined by the frequency fa and the frequency fg so that the resonance frequency f0 of the piezoelectric transformer T is included in the band. This frequency band is determined in advance when the ion generator 100 is shipped based on the frequency characteristics of the piezoelectric transformer T (frequency dependence of the output voltage VT). The frequencies f1 and f2 are scanned from the frequency fa toward the frequency fg, for example. The frequency scan widths Δf are all equal.

  In step S11, the CPU 51 sets each of the frequencies f1 and f2 to the maximum value in the frequency range (f1 = f2 = fa). The frequencies f1 and f2 are equal to each other. In this case, the drive signal generator 52 outputs the drive signal Sd fixed at the frequency f1 to the gate of the transistor Q (step S12). The A / D converter 53 converts the reference voltage Vref into a digital value, and outputs the value (Va) of the reference voltage Vref to the CPU 51. The CPU 51 stores the values of the frequencies f1 and f2 and the value of the reference voltage Vref in the memory 54 (Step S13).

  In step S14, the CPU 51 decreases the frequency f1 by the scanning width Δf from the process in step S11, and sets the frequency f2 to the same value as the process in step S11 (f1 = fb, f2 = fa). The drive signal generation unit 52 outputs a drive signal Sd in which the frequency f1 (= fb) and the frequency f2 (= fa) are alternately switched every one cycle to the gate of the transistor Q (step S15).

  In step S <b> 16, the CPU 51 acquires the value (Vab) of the reference voltage Vref from the A / D converter 53. The CPU 51 compares the acquired value of the reference voltage Vref with the value of the reference voltage Vref stored in the memory 54. If the acquired value of reference voltage Vref is greater than or equal to the value stored in memory 54 (YES in step S16), the process proceeds to step S17. On the other hand, when the acquired value of reference voltage Vref is less than the value stored in memory 54 (NO in step S16), the process proceeds to step S18.

  In step S17, the CPU 51 updates the corresponding value stored in the memory 54 with the values of the frequencies f1 and f2 and the new value of the reference voltage Vref in the processes of steps S14 to S16.

  In step S18, the CPU 51 sets the frequency f1 to the same value as the processing in step S14, and decreases the frequency f2 by the scanning width Δf from the processing in step S14 (f1 = f2 = fb). The frequencies f1 and f2 are equal to each other. Therefore, the drive signal generator 52 outputs the drive signal Sd fixed at the frequency f1 to the gate of the transistor Q (step S19).

  In step S <b> 20, the CPU 51 acquires the value (Vb) of the reference voltage Vref from the A / D converter 53. The CPU 51 compares the acquired value of the reference voltage Vref with the value of the reference voltage Vref stored in the memory 54. If the acquired value of reference voltage Vref is greater than or equal to the value stored in memory 54 (YES in step S20), the process proceeds to step S21. On the other hand, when the new detected value of reference voltage Vref is less than the value stored in memory 54 (NO in step S20), the process proceeds to step S22.

  In step S <b> 21, the CPU 51 updates the corresponding value stored in the memory 54 with the values of the frequencies f <b> 1 and f <b> 2 in the processing of steps S <b> 18 to S <b> 20 and the acquired value of the reference voltage Vref.

  In step S22, the CPU 51 determines whether or not the frequency f1 is the minimum value (fg) of the frequency band. If frequency f1 is not the minimum value (NO in step S22), the process returns to step S14. On the other hand, when frequency f1 is the minimum value (YES in step S22), a series of processing is completed.

  FIG. 9 is a diagram illustrating a result of the frequency scanning process of the flowchart illustrated in FIG. Referring to FIG. 9, the horizontal axis is a time axis. The vertical axis represents the reference voltage Vref.

  The reference voltage Vref at time ta corresponds to the drive signal Sd fixed at the frequency f1 = f2 = fa. The reference voltage Vref at time tab corresponds to the drive signal Sd in which the frequency is switched for each cycle between the frequency f1 = fb and the frequency f2 = fa. The reference voltage Vref at time tb corresponds to the drive signal Sd fixed at the frequency f1 = f2 = fb. Since the reference voltage Vref at the later time is the same, detailed description will not be repeated.

  According to FIGS. 8 and 9, the reference voltage Vref at time tde is the maximum. That is, the applied voltage Vp is maximized when the driving frequency is alternately switched between the frequency f1 = fe and the frequency f2 = fd every cycle. Therefore, as a result of the series of processes shown in the flowchart of FIG. 7, the value of the frequency fe is stored in the memory 54 as the frequency f1. The value of the frequency fd is stored as the frequency f2. The value of the voltage Vde is stored as the reference voltage Vref.

  The value of the reference voltage Vref indicated by a white bar is a detection result obtained when the drive frequency fd is fixed at the frequency f1. On the other hand, the value of the reference voltage Vref indicated by the hatched bar is a detection result obtained when the drive frequency fd is alternately switched between the frequencies f1 and f2 in every cycle. . That is, the value of the reference voltage Vref indicated by the hatched bar is a value that can be newly detected using the result of the verification experiment described in FIG.

  As described above, according to the high voltage generation circuit 10 according to the first embodiment, even if the clock frequency fclk of the microcomputer 5 is not increased, the same effect as that obtained when the scanning width Δf of the drive frequency fd is halved is obtained. be able to. In other words, the resolution of the drive frequency fd in adjusting the output voltage VT of the piezoelectric transformer T can be doubled. Therefore, the high voltage generation circuit 10 that can finely adjust the drive frequency fd of the T to the piezoelectric transformer can be realized.

  In FIG. 8, the case where the frequency fm substantially coincides with the resonance frequency f0 of the piezoelectric transformer T (fm≈f0) has been described. It is difficult to make the frequency f1, f2 or the frequency fm exactly match the resonance frequency f0. If a microcomputer having a sufficiently high clock frequency fclk is used, the scanning width Δf becomes small. For this reason, there is a high possibility that the drive frequency fd close to the resonance frequency f0 can be obtained. However, in the present embodiment, the drive frequency fd of the piezoelectric transformer T can be adjusted without using a microcomputer having a high clock frequency. Therefore, an inexpensive microcomputer can be used, which is advantageous in terms of cost.

  In general, the power consumption of a microcomputer increases as the clock frequency increases. As can be understood from the above description, according to the present embodiment, when the scanning width Δf of the drive frequency fd is equivalent to the conventional one, the clock frequency fclk can be halved compared to the conventional one. Therefore, the power consumption of the microcomputer can be reduced.

  In the present embodiment, the case where the drive frequency fd is alternately switched between the frequency f1 and the frequency f2 every cycle has been described for the sake of clarity. However, the number of periods in which the frequency f1 is output and the number of periods in which the frequency f2 is output are not particularly limited. For example, the frequency may be alternately switched between the frequency f1 and the frequency f2 every two cycles. Further, for example, the frequency may be alternately switched between the frequency f1 of two cycles and the frequency f2 of one cycle.

  Further, the frequency characteristic of the piezoelectric transformer T has an aspect that it depends on temperature. That is, the resonance frequency f0 of the piezoelectric transformer T can be changed according to the change in the ambient temperature of the ion generator 100. Furthermore, the amount of ions generated from the ion generator 100 (for example, the number of ions per unit volume) depends on the applied voltage Vp. Therefore, the amount of ions generated can change according to changes in the ambient temperature of the ion generator 100. Therefore, in one embodiment, the series of frequency scanning processes shown in the flowchart of FIG. 7 is executed at predetermined time intervals (for example, every 10 minutes). Thereby, the values of the frequencies f1 and f2 can be updated to values reflecting the temperature change of the piezoelectric transformer T. Therefore, increase / decrease in the amount of ions generated due to temperature change can be prevented.

  In FIG. 7 to FIG. 9, the case where the frequency band is scanned from the high frequency side (frequency fa side) to the low frequency side (frequency fg side) has been described. However, the frequency scanning direction or scanning order is not particularly limited. Within the frequency band, the frequencies f1 and f2 can be changed in an arbitrary order. The output voltage of the piezoelectric transformer obtained by alternately inputting the drive signal of the arbitrary frequency f1 and the drive signal of the arbitrary frequency f2 is compared, and the frequency f1, the frequency when the output voltage becomes the highest is compared. What is necessary is just to fix f2.

[Embodiment 2]
According to the second embodiment, after fixing the frequencies f1 and f2 to the frequency at which the reference voltage Vref is maximized, the duty ratio (the ratio of the on period in one cycle) of the drive signal Sd is further adjusted.

  FIG. 10 is a circuit block diagram schematically showing the configuration of the high voltage generation circuit according to the second embodiment of the present invention. Referring to FIG. 10, high voltage generation circuit 20 includes a rectification circuit 104 a instead of rectification circuit 104 and a high voltage generation circuit 20 in that it further includes a current detection circuit (second detection circuit) 105. 10 (see FIG. 2).

  In the rectifier circuit 104a, the diode D4 is connected between the cathode of the diode D3 and the A / D converter 53 in such a direction that the anode is on the diode D3 side. Since the other configuration of rectifier circuit 104a is the same as that of rectifier circuit 104, detailed description will not be repeated.

  The current detection circuit 105 is provided for detecting a discharge current flowing through the negative discharge electrode En. The magnitude of the discharge current flowing through the negative discharge electrode En is proportional to the amount of negative ions generated at the negative discharge electrode En. According to the present embodiment, approximately equal amounts of bipolar ions are generated. Therefore, by detecting the discharge current, the CPU 51 can acquire the amount of bipolar ions generated.

  The current detection circuit 105 includes resistors R5 and R6. The resistor R5 is electrically connected between the anode of the diode D3 and the negative discharge electrode En. The resistor R6 is electrically connected between the negative discharge electrode En and the A / D converter 53. The current detection circuit 105 detects the magnitude of the discharge current at the negative discharge electrode En by converting it into a voltage (discharge voltage Vi). The discharge voltage Vi is fed back to the A / D converter 53. The amount of ions generated increases as the discharge current increases. Therefore, the amount of ions generated can be monitored by detecting the discharge voltage Vi. The other configuration of the high voltage generation circuit 20 is the same as the configuration of the high voltage generation circuit 10, and therefore detailed description will not be repeated.

  FIG. 11 is a conceptual diagram for explaining the influence of the duty ratio of the drive signal Sd on the applied voltage Vp output from the high voltage generation circuit 20 shown in FIG. Referring to FIG. 11, the horizontal axis represents drive frequency fd. The vertical axis represents the applied voltage Vp. When the duty ratio is decreased from the initial value, the frequency dependence of the applied voltage Vp at the initial value of the duty ratio of the drive signal Sd is shown by a curve a (broken line). The frequency dependence of the applied voltage Vp after the duty ratio of the drive signal Sd is decreased is shown by a curve b (solid line).

There is a normal range for the applied voltage Vp. The normal range is defined by the upper limit value VH and the lower limit value VL. Before the duty ratio of the drive signal Sd decreases, the applied voltage Vp may be equal to or higher than the upper limit value VH. In general, the type of ions generated in the ion generator is determined according to the magnitude of the applied voltage. When H ⁺ (H ₂ O) _m (m is a natural number) is generated as positive ions and O ₂ ⁻ (H ₂ O) _n (n is a natural number) is generated as negative ions, the applied voltage Vp is the upper limit value VH. If the value is greatly exceeded, a desired amount of the desired ionic species cannot be generated. In the present embodiment, instead of the cluster ions, nitrogen ions may be generated from nitrogen existing in large quantities in the air. As a result, the ratio of the generation amount of nitrogen ions to the generation amount of all ions increases, while the ratio of the generation amount of the cluster ions decreases. For this reason, the effect obtained by said cluster ion may fall. Or there is a possibility that the amount of ozone generated will increase. Therefore, the applied voltage Vp is desirably less than the upper limit value VH. Since the upper limit value VH differs depending on the structure of the ion generator 3, it is set by performing a test in advance.

  In addition, fine particles such as dust are present around the electrodes. These fine particles are charged by positive ions and negative ions generated by corona discharge. The positively charged fine particles are attracted to the negative discharge electrode En. The negatively charged fine particles are attracted to the positive discharge electrode Ep. Therefore, with the passage of time, these fine particles are deposited as deposits on each of the positive discharge electrode Ep and the negative discharge electrode En. Corona discharge is less likely to occur due to deposits deposited on the electrodes. As a result, the amount of ions generated is reduced. Therefore, it is desirable to set the lower limit value VL so that the amount of ions generated is not less than a desired value, and to maintain the applied voltage Vp so as not to fall below the lower limit value VL.

  Further, if the applied voltage Vp is higher than the discharge start voltage VS, corona discharge is started. As the deposits accumulate on the electrodes, the discharge start voltage VS gradually increases. Once the corona discharge is started, the corona discharge can be continued even if the applied voltage Vp falls below the discharge start voltage VS. Therefore, at the start of discharge, it is necessary to set the applied voltage Vp so as to be equal to or higher than the discharge start voltage VS.

  Thus, the applied voltage Vp needs to be equal to or higher than the lower limit value VL and lower than the upper limit value VH of the normal range, and more than the discharge start voltage VS at the start of discharge. As will be described below, the applied voltage Vp can be adjusted by adjusting the duty ratio of the drive signal Sd.

  FIG. 12 is a diagram showing the relationship between the duty ratio in the piezoelectric transformer T and the applied voltage Vp in the high voltage generation circuit 20 shown in FIG. Referring to FIG. 12, the horizontal axis represents the duty ratio of drive signal Sd. The vertical axis represents the relative value of the applied voltage Vp based on the value at a duty ratio of 5%.

  As the duty ratio of the drive signal Sd increases, the applied voltage Vp increases. In the region where the duty ratio is about 10% to about 27%, the applied voltage Vp changes almost linearly (see the broken line). The amount of ions generated increases or decreases in accordance with the increase or decrease of the applied voltage Vp. Therefore, the amount of ions generated can be adjusted by adjusting the duty ratio. The specific numerical values shown in FIG. 12 are actually measured values with a specific piezoelectric transformer T. The characteristics of the piezoelectric transformer to which the present invention can be applied are not limited to the characteristics shown in FIG.

  FIG. 13 is a flowchart showing duty ratio scanning processing by the microcomputer 5 shown in FIG. Referring to FIG. 13, the series of processing is executed after completion of the series of processing shown in the flowchart of FIG. That is, each of the frequencies f1 and f2 is fixed to a frequency at which the applied voltage Vp is maximum. The duty ratio scanning range (for example, 10% to 27%) and the scanning width (for example, 1%) are based on the performance of the drive signal generation unit 52 and the characteristics of the piezoelectric transformer T, for example. It is determined in advance at the time of shipment.

  In step S31, the CPU 51 sets the duty ratio to the minimum value (for example, 10%) of the scanning range. The drive signal generator 52 outputs the drive signal Sd to the gate of the transistor Q (step S32).

  In step S33, the A / D converter 53 converts the discharge voltage Vi into a digital value and outputs the value to the CPU 51. The CPU 51 compares the value of the discharge voltage Vi with the lower limit value VL. If the value of discharge voltage Vi is equal to or higher than lower limit value VL (YES in step S33), the process proceeds to step S36. On the other hand, when the value of discharge voltage Vi is less than lower limit value VL (NO in step S33), the process proceeds to step S34.

  In step S34, the CPU 51 determines whether or not the duty ratio is the maximum value (for example, 27%) of the scanning range. If the duty ratio is the maximum value (YES in step S34), the process proceeds to step S36. On the other hand, when the duty ratio is not the maximum value (NO in step S34), the process proceeds to step S35.

  In step S35, the CPU 51 increases the duty ratio by the scanning width (for example, 1%). Thereafter, the process returns to step S32.

  In step S36, the CPU 51 stores the value of the duty ratio, the value of the reference voltage Vref, and the value of the discharge voltage Vi in step S33 in the memory 54. Thereafter, in step S <b> 37, the CPU 51 executes pass / fail determination of the ion generation unit 3 described later. When the process of step S37 ends, a series of processes is completed.

  FIG. 14 is a diagram illustrating a result of the duty ratio scanning process of the flowchart illustrated in FIG. 13. Referring to FIG. 14, the horizontal axis is a time axis. The vertical axis represents the discharge voltage Vi.

  Discharge voltage Vi at time t1 corresponds to drive signal Sd when the duty ratio is a minimum value (for example, 10%). Discharge voltage Vi at time t2 corresponds to drive signal Sd when the duty ratio is increased from the minimum value by a scanning width (for example, 1%). Similarly, the discharge voltage Vi from time t3 to time t6 corresponds to the drive signal Sd when the duty ratio is sequentially increased by the scan width. In the present embodiment, discharge voltage Vi becomes equal to or higher than lower limit value VL for the first time at time t7. As a result, the value of the duty ratio, the value of the reference voltage Vref, and the value of the discharge voltage Vi at time t7 are stored in the memory 54.

  FIG. 15 is a conceptual diagram for explaining quality determination processing of the ion generator 3 in the flowchart shown in FIG. Referring to FIG. 15, the horizontal axis represents discharge voltage Vi. The vertical axis represents the applied voltage Vp. Since the applied voltage Vp is proportional to the reference voltage Vref, the value of the applied voltage Vp can be obtained from the value of the reference voltage Vref stored in the memory 54.

  The value of the applied voltage Vp is classified into three according to the upper limit value VH and the lower limit value VL of the normal range. Further, the value of the discharge voltage Vi is classified into three according to the upper limit value VIH and the lower limit value VIL of the normal range. Therefore, the value of the applied voltage Vp and the value of the discharge voltage Vi are classified into any of the nine regions A to I according to the combination. The CPU 51 determines the quality of the ion generation unit 3 based on the areas A to I to which the ion generation unit 3 belongs. The upper limit value VH and the lower limit value VL, and the upper limit value VIH and the lower limit value VIL are determined in advance when the ion generator 100 is shipped, for example.

  When the applied voltage Vp and the discharge voltage Vi belong to the region E, the applied voltage Vp and the discharge voltage Vi are both in the normal range. Therefore, the CPU 51 determines that the ion generator 3 is “normal”. On the other hand, when the applied voltage Vp and the discharge voltage Vi belong to other than the region E, the CPU 51 determines that an abnormality (failure or initial failure) has occurred in the ion generator 3.

  That is, when the applied voltage Vp and the discharge voltage Vi belong to the region G, the applied voltage Vp is less than the lower limit value VL, and the discharge voltage Vi is less than the lower limit value VIL. That is, the applied voltage Vp is smaller than the normal range, and the amount of ions generated is small. Therefore, the CPU 51 determines that the ion generator 3 is “failure”. Such “failure” means an element failure (defective ion generator 3).

  When the applied voltage Vp and the discharge voltage Vi belong to the regions A and D, the discharge voltage Vi is smaller than the lower limit value VIL even though the applied voltage Vp is equal to or higher than the lower limit value VL. That is, although the applied voltage Vp is in the normal range or larger, the amount of ions generated is small. The decrease in the amount of ions generated can be attributed to the deposition of deposits on the electrode over long periods of use. Therefore, the CPU 51 determines that the ion generator 3 is “failure or life”.

  When the applied voltage Vp and the discharge voltage Vi belong to the region B, the discharge voltage Vi is within the normal range even though the applied voltage Vp is equal to or higher than the upper limit value VH. In other words, although the applied voltage Vp is larger than the normal range, the amount of ions generated corresponding to the applied voltage Vp is not obtained. The decrease in the amount of ions generated can be attributed to the deposition of deposits on the electrode over long periods of use. Therefore, the CPU 51 determines that the ion generator 3 is “failure or life”.

  When the applied voltage Vp and the discharge voltage Vi belong to the regions H and I, the discharge voltage Vi is larger than the lower limit value VIL even though the applied voltage Vp is less than the lower limit value VL. When the applied voltage Vp and the discharge voltage Vi belong to the region F, the discharge voltage Vi is larger than the upper limit value VIH even though the applied voltage Vp is within the normal range. That is, the discharge voltage Vi is larger than the applied voltage Vp.

  This phenomenon may be caused by, for example, a short circuit between the negative discharge electrode En and the induction electrode Eg2 due to adhesion of a conductor. Further, when deposits are deposited on the negative discharge electrode En, the relative permittivity of the deposits is larger than the relative permittivity of air, so that a discharge current easily flows between the negative discharge electrode En and the induction electrode Eg2. As a result, the discharge voltage Vi may have increased. Therefore, the CPU 51 determines that the ion generator 3 is “failure or short circuit”. “Short circuit” is not limited to a phenomenon in which the negative discharge electrode En and the induction electrode Eg2 become equipotential, and current tends to flow due to deposition of deposits on the negative discharge electrode En as described above. Including the phenomenon.

  When the applied voltage Vp and the discharge voltage Vi belong to the region C, the applied voltage Vp is not less than the lower limit value VL and the discharge voltage Vi is not less than the upper limit value VIH. That is, since the applied voltage Vp is larger than the normal range, ions other than the desired ion species (cluster ions) (for example, nitrogen ions) or ozone may be generated. Therefore, the CPU 51 determines that the ion generator 3 is “failure”.

  When it determines with the ion generating part 3 not being normal (in the case other than the area | region E), CPU51 alert | reports abnormality to the user of the ion generator 100. FIG. As a method for notifying abnormality, a method of lighting an abnormality notification lamp (not shown), generating an alarm sound, or notifying with an electric signal can be employed. Thereby, the user can request the manufacturer of the ion generator 100 to replace the ion generator 3. When such a “failure” occurs, the use of the ion generator 3 is prohibited because the direction is unsafe.

  In the present embodiment, the case where the reference voltage Vref to the positive discharge electrode Ep and the discharge voltage Vi of the negative discharge electrode En are detected has been described. However, the voltage value to the negative discharge electrode En and the discharge current to the positive discharge electrode Ep may be detected. In the case of changing the polarity, the configuration of the rectifier circuits 102 and 104 may be changed. Since the control of the high voltage generation circuit in this case is equivalent to the control in the present embodiment, the description thereof will not be repeated. Further, the discharge current I may be detected and used instead of the discharge voltage Vi of the negative discharge electrode En. The normal range of the discharge current I is defined by the upper limit value IH and the lower limit value IL.

Embodiments of the present invention can be summarized as follows.
(1) A piezoelectric transformer T that outputs a voltage corresponding to the frequency of the drive signal Sd, and a drive signal Sd having a variable drive frequency fd are generated by dividing the clock signal Sclk, and the drive signal Sd is output to the piezoelectric transformer T. A microcomputer 5, and the microcomputer 5 switches between a frequency f 1 less than the resonance frequency f 0 of the piezoelectric transformer T and a frequency f 2 greater than or equal to the resonance frequency f 0 to determine the frequency of the drive signal Sd. Voltage generation circuit 10.

  According to the above configuration, it is possible to realize a voltage generation circuit capable of finely adjusting the driving frequency for the piezoelectric transformer without increasing the cost.

  (2) The high voltage generation circuit 10 further includes a voltage dividing circuit 103 that detects the output voltage VT from the piezoelectric transformer T and outputs the reference voltage Vref to the microcomputer 5, and the microcomputer 5 sets the resonance frequency f0. The high voltage generation circuit 10 that selects the frequencies f1 and f2 at which the reference voltage Vref is maximized by changing the frequencies f1 and f2 in the included frequency band.

According to the above configuration, the drive frequency at which the applied voltage becomes maximum can be obtained.
(3) The high voltage generation circuit 10 in which the period corresponding to each scan width Δf of the frequencies f1 and f2 is equal to the clock period Tclk of the clock signal Sclk.

  According to the above configuration, the scanning width of the driving frequency is minimized. For this reason, there is a high possibility that a drive frequency close to the resonance frequency can be obtained.

  (4) The ion generator 100 provided with the high voltage generation circuits 10 and 20 and the ion generator 3 which generates ions when the applied voltage Vp is applied.

  According to the above configuration, it is possible to realize an ion generation apparatus including a high voltage generation circuit that can finely adjust the driving frequency to the piezoelectric transformer without increasing the cost.

  (5) In a state in which the frequencies f1 and f2 are fixed to a frequency at which the reference voltage Vref is maximum, the microcomputer 5 changes the duty ratio of the drive signal Sd, and applies the applied voltage Vp based on the reference voltage Vref. Adjusting the ion generator 100.

  According to the above configuration, the magnitude of the applied voltage can be finely adjusted by changing the duty ratio of the drive signal as compared with the case of changing the drive frequency. Moreover, generation | occurrence | production of ions other than desired ionic species can be suppressed. For this reason, the generation amount of desired ionic species can be increased.

  (6) The high voltage generation circuit 20 further includes a current detection circuit 105 that detects the discharge current and outputs the discharge voltage Vi to the microcomputer 5, and the frequencies f1 and f2 are set to frequencies at which the reference voltage Vref is maximized. In the fixed state, the microcomputer 5 changes the duty ratio of the drive signal Sd and adjusts the discharge current based on the discharge voltage Vi.

  According to the said structure, it can adjust so that the generation amount of ion may turn into a desired generation amount.

  (7) The ion generator 100 in which the microcomputer 5 selects a duty ratio at which the discharge voltage Vi is minimum within a predetermined normal range.

  There is a trade-off relationship between the amount of ions generated and the lifetime of the ion generator. For this reason, according to the said structure, the lifetime of an ion generation part can be extended by suppressing the generation amount of ion.

  (8) The ion generator 100, in which the microcomputer determines that the ion generator 3 is normal when each of the reference voltage Vref and the discharge voltage Vi is within a predetermined normal range.

  According to the said structure, the quality determination of an ion generation part can be implemented. As a result, it is possible to determine that a normal ion generation part is a non-defective product, and an ion generation part in which an abnormality (failure or initial failure, or the ion generation part has reached the end of its life) has occurred.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  100 ion generator, 10, 20 high voltage generation circuit, 1 input terminal, 2 AC / DC converter, 3 ion generator, 4 clock oscillator, 5 microcomputer, 51 CPU, 52 drive signal generator, 53 A / D Converter, 54 memory, 101 booster circuit, 102, 104 rectifier circuit, 103 voltage divider circuit, 105 current detection circuit, T piezoelectric transformer, L coil, Q transistor, C1, C2 capacitor, R1-R6 resistor, D1-D4 diode, Ep positive discharge electrode, En negative discharge electrode, Eg1, Eg2 induction electrode.

Claims (5)

A piezoelectric transformer that outputs a voltage according to the frequency of the drive signal;
A control circuit that generates the drive signal having a variable frequency by dividing a clock signal and outputs the drive signal to the piezoelectric transformer;
The voltage generation circuit, wherein the control circuit alternately switches between a first frequency less than a resonance frequency of the piezoelectric transformer and a second frequency equal to or higher than the resonance frequency to determine the frequency. The voltage generation circuit includes:
A first detection circuit that detects an output voltage from the piezoelectric transformer and outputs a first detection value to the control circuit;
The control circuit changes the first and second frequencies in a frequency band including the resonance frequency, and selects the first and second frequencies that maximize the first detection value. Item 2. The voltage generation circuit according to Item 1. A voltage generation circuit according to claim 2;
An ion generator comprising: an ion generator that generates ions when the output voltage from the voltage generation circuit is applied.   In a state where the first and second frequencies are fixed to a frequency at which the first detection value is maximum, the control circuit changes the duty ratio of the drive signal to change the first detection value. The ion generator according to claim 3, wherein the output voltage is adjusted based on the equation (4). The voltage generation circuit includes:
A second detection circuit that detects the discharge current and outputs a second detection value to the control circuit;
In a state where the first and second frequencies are fixed to a frequency at which the first detection value is maximum, the control circuit changes the duty ratio of the drive signal to change the second detection value. The ion generator according to claim 4, wherein the discharge current is adjusted based on the equation (5).

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