JP2014174849A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device with improved reliability in data reading.SOLUTION: A semiconductor memory device 30 includes: a nonvolatile memory 11 that stores data; a measuring unit 40 that measures the completion time of operation caused by a command in the nonvolatile memory and outputs completion time information; address acquisition units 33 and 34 that obtain an address; a first buffer 38 that stores the command; a command issuing unit 35 that receives the address that is obtained by the address acquisition unit and issues a command according to the completion time information that is output from the measuring unit; command processing units 36 and 37 that store and process the command which is issued from the command issuing unit; and a memory controller 39 that outputs the command, which is processed by the command processing units, to the nonvolatile memory and controls the operation of the nonvolatile memory.

Description

  Embodiments described herein relate generally to a semiconductor memory device.

  A NAND flash memory is known. As a technique for increasing the data storage capacity of the NAND flash memory, a multi-value storage method is used in which the threshold distribution of memory cells is subdivided and the memory cells can store a plurality of bit data (multi-value data).

JP 2011-227664 A

  The problem to be solved by the present invention is to provide a nonvolatile semiconductor memory device that improves the reliability of data reading.

  The semiconductor memory device according to the embodiment includes a nonvolatile memory that stores data, an end time of an operation based on a command in the nonvolatile memory, a measurement unit that outputs end time information, an address acquisition unit that acquires an address, A first buffer for storing a command, a command issuing unit for receiving an address acquired by the address acquiring unit, and issuing a command according to the end time information output from the measuring unit; and the command issuing unit A command processing unit that stores and processes the issued command; and a memory controller that outputs the command processed by the command processing unit to the nonvolatile memory and controls an operation of the nonvolatile memory.

1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment. FIG. 3 is a block diagram showing a configuration of a NAND controller and a nonvolatile semiconductor memory in reading of the semiconductor memory device of the first embodiment. The time diagram which shows the read-out operation | movement of the non-volatile semiconductor memory in 1st Embodiment. The time diagram which shows other operation | movement of the non-volatile semiconductor memory in 1st Embodiment. 3 is a time diagram showing the operation of the nonvolatile semiconductor memory in reading and erasing according to the first embodiment. 3 is a time diagram showing the operation of the nonvolatile semiconductor memory in writing and reading according to the first embodiment. 6 is a time diagram showing another operation of the nonvolatile semiconductor memory in the read of the first embodiment. The block diagram which shows the structure of the semiconductor memory device of 2nd Embodiment. The block diagram which shows the flow of the command in the SSD controller of 2nd Embodiment, and a buffer. The block diagram which shows the structure of the timer in the SSD controller of 2nd Embodiment. The block diagram which shows the structure of the command issuing part in the SSD controller of 2nd Embodiment. The block diagram which shows the structure of the timer in the SSD controller of 3rd Embodiment. The perspective view which shows an example of the personal computer carrying the semiconductor memory device of 4th Embodiment. The block diagram which shows the structural example of the personal computer carrying the semiconductor memory device of 4th Embodiment. FIG. 9 is a block diagram showing a configuration of a semiconductor memory device according to a fifth embodiment. The block diagram which shows the structure of SSD in which device sleep is performed in a personal computer. The time diagram which shows an example when the said device sleep starts in a read. The conceptual diagram which shows the usage example of the server carrying SSD of 4th Embodiment.

  Hereinafter, a memory system according to an embodiment will be described with reference to the drawings. Here, a solid state drive (SSD) will be described as an example of the memory system, but the application target of the present embodiment is not limited to the SSD. In the following description, components having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

  The memory system includes a nonvolatile memory, a command management unit, a command issuing unit, a data control unit, and a command monitoring unit. The nonvolatile memory stores data. The command management unit receives and manages commands. The command issuing unit issues the command received by the command management unit to the nonvolatile memory. The data control unit performs either reading or writing of data with respect to the nonvolatile memory. The command monitoring unit monitors the command management unit, and outputs a reception signal to the data control unit when the command management unit receives a command. The data control unit, when receiving the reception signal from the command monitoring unit, interrupts either reading or writing of data, causes the command issuing unit to issue the command to the nonvolatile memory, and After the issuance, either the data reading or writing is resumed.

[First Embodiment]
The semiconductor memory device 30 of the first embodiment will be described. The semiconductor memory device 30 is, for example, a solid state drive (SSD).

  FIG. 1 is a block diagram showing the configuration of the semiconductor memory device of the first embodiment.

  The a solid state drive (SSD) 10 is connected to a host device (hereinafter referred to as a host) 100, for example, a personal computer, a server, or the like through a communication interface such as an Advanced Technology Attachment (ATA) standard. The SSD 10 functions as an external storage device for the host 100.

  The SSD 10 includes a nonvolatile semiconductor memory 11, an SSD controller 12, a host interface (I / F) 13, a volatile semiconductor memory (eg, DRAM) 14, and the like.

  The nonvolatile semiconductor memory 11 is read / written from the host 100 and stores data. The nonvolatile semiconductor memory 11 includes, for example, a NAND flash memory (hereinafter referred to as “NAND memory”), a NOR flash memory, a magnetic random access memory (MRAM), a reactive random access memory (ReRAM), and the like. Furthermore, the nonvolatile semiconductor memory 11 may be a single package including a single or a plurality of semiconductor chips, or may be a plurality of packages each including a single or a plurality of semiconductor chips. Further, it may be a flip chip of a single semiconductor chip.

  In the present embodiment, the nonvolatile semiconductor memory 11 includes a plurality of NAND memories 11A, 11B, 11C, and 11D, each of which includes a single semiconductor chip. The NAND memory 11A includes a memory circuit 11A1 and a buffer 11A2. Similarly, the NAND memory 11B includes a memory circuit 11B1 and a buffer 11B2, the NAND memory 11C includes a memory circuit 11C1 and a buffer 11C2, and the NAND memory 11D includes a memory circuit 11D1 and a buffer 11D2. The memory circuit includes a plurality of nonvolatile memory cells that store data. The buffer temporarily holds data to be input / output to / from the memory circuit.

  The SSD controller 12 controls the operation of the entire SSD such as the nonvolatile semiconductor memory 11 and the volatile semiconductor memory 14 in accordance with a signal input from the host 100 via the host interface 13. The SSD controller 12 includes a CPU 21, an interface (I / F) circuit 22, a DRAM controller 23, a data buffer 24, and a NAND controller 25 connected by a bus 26.

  The CPU 21 performs various programs and calculation processes, and controls the operation in the SSD controller 12. The interface circuit 22 exchanges signals between the host interface 13 and the SSD controller 12. The DRAM controller 23 controls the operation of the volatile semiconductor memory (DRAM) 14. The data buffer 24 is used when temporarily storing transfer data for the host 100 or the nonvolatile semiconductor memory 11. Further, the NAND controller 25 controls the operation of the NAND memories 11A, 11B, 11C, and 11D in the nonvolatile semiconductor memory 11.

  The host interface 13 exchanges signals between the SSD 10 and the host 100. The volatile semiconductor memory 14 is used for temporarily storing transfer data such as storage of management information of the nonvolatile semiconductor memory 11 and data cache. The volatile semiconductor memory 14 includes, for example, DRAM, SRAM and the like.

  Data transmitted from the host 100 to the host interface 13 is temporarily stored in the data buffer 24 under the control of the CPU 21. Thereafter, the data is transferred from the data buffer 24 and written to the NAND memory in the nonvolatile semiconductor memory 11. On the other hand, the data read from the NAND memory is temporarily stored in the data buffer 24. Thereafter, the data is transmitted from the data buffer 24 to the host 100 via the host interface 13.

  FIG. 2 is a block diagram showing a configuration of the NAND controller 25 and the nonvolatile semiconductor memory 11 in the read of the first embodiment.

  As illustrated, the NAND controller 25 includes a command queue unit 251 (first buffer), a command extraction unit 252, a command issue unit 253, a command monitoring unit 254, a data control unit 255, and a decoder 256. The host interface 13 is connected to the command queue unit 251 and the data buffer 24. Further, the command issuing unit 253 and the data control unit 255 are connected to the NAND memories 11A, 11B, 11C, and 11D via the decoder 256, respectively. The decoder 256 selects one of the NAND memories 11A, 11B, 11C, and 11D in the nonvolatile semiconductor memory 11 based on the address.

  First, a command is input from the host 100 to the command queue unit 251 via the host interface 13. The command queue unit 251 stores and manages the received command. The command extracting unit 252 extracts a command from the command queue unit 251 and transfers the command to the command issuing unit 253. The command issuing unit 253 issues the command received from the command extraction unit 252 to the NAND memory in the nonvolatile semiconductor memory 11 via the decoder 256. The decoder outputs the command issued from the command issuing unit 253 to the NAND memory selected based on the address. The command queue unit 251 and the command extraction unit 252 form a command management unit.

  FIG. 3 is a time diagram showing the operation of the nonvolatile semiconductor memory in the read of the first embodiment. Here, operation control of the NAND memory 11A and the NAND memory 11B in reading is shown.

  The command extraction unit 252 extracts a command from the command queue unit 251, and the command issue unit 253 issues the command received from the command extraction unit 252 to the NAND memory 11 A via the decoder 256. On the other hand, the data control unit 255 monitors the command input status and busy status of each NAND memory, and shifts to the data extraction operation as soon as it is found that data can be extracted.

  The command monitoring unit 254 monitors the arrival of a new command to the command queue unit 251 and notifies the command extraction unit 252 as soon as a new command not extracted by the command extraction unit 252 is found. The data control unit 255 confirms the notification of the command monitoring unit 254 at regular intervals during the period including data extraction, and if there is a new command and the command can be input to the NAND memory, the data control unit 255 extracts the data. Suspend and issue a command.

  Hereinafter, the case where the read commands C0 and C1 are input to the NAND memories 11A and 11B will be described in detail with reference to FIG.

  First, the command issuing unit 253 issues a read command C0 to the NAND memory 11A via the decoder 256. In the period C0, the NAND memory 11A receives the read command C0. Subsequently, the NAND memory 11A extracts data from the memory circuit 11A1 to the buffer 11A2 in the NAND memory 11A in the period BUSY0. Next, in the period OUT0, the data in the buffer 11A2 in the NAND memory 11A is extracted by the data control unit 255.

  During the period, the command monitoring unit 254 monitors the arrival of a new command to the command queue unit 251, and notifies the command extraction unit 252 and the data control unit 255 when the arrival of the read command C1 is found. Upon receiving the notification from the command monitoring unit 254, the command extraction unit 252 extracts the read command C1 from the command queue unit 251 and outputs it to the command issuing unit 253.

  The data control unit 255 confirms the notification of the command monitoring unit 254, and if the read command C1 is a new command and the read command C1 can be input to the NAND memory 11B, the data control unit 255 interrupts the data extraction in the period OUT0. To do. When the command issuing unit 253 confirms that the data extraction by the data control unit 255 is interrupted, the command issuing unit 253 issues a read command C1 to the NAND memory 11B. Thereafter, the data control unit 255 confirms that the issue of the read command C1 by the command issuing unit 253 is completed, and resumes the extraction of data from the buffer 11A2 in the NAND memory 11A.

  That is, in the NAND memory 11A, the data extraction in the period OUT0 is interrupted, and in the period C1, the NAND memory 11B receives the read command C1. When the reception of the read command C1 is completed, the extraction of data in the period OUT0 is resumed in the NAND memory 11A. After receiving the read command C1, the NAND memory 11B takes out data from the memory circuit 11B1 to the buffer 11B2 in the NAND memory 11B in the period BUSY1.

  Here, the extraction of data in the period OUT0 in the NAND memory 11A and the extraction of data in the period BUSY1 in the NAND memory 11B are executed in parallel. As a result, the data extraction from the NAND memories 11A and 11B to the NAND controller 25 by the read commands C0 and C1 can be performed in a short period of time. That is, the time required for extracting data from a plurality of NAND memories to the NAND controller can be shortened. As a result, it is possible to increase the use efficiency of a plurality of NAND memories in reading.

  Note that it is not possible to input a command to the NAND memory when extracting data from the buffer in the NAND memory to the NAND controller or when inputting another command. That is, in FIG. 3, in the period C0 and the period OUT0, since the wiring between the NAND controller 25 and the NAND memory 11A is used, a command cannot be input to the NAND memory 11B.

  Next, although the case where the read commands C0 and C1 are input to the separate NAND memories 11A and 11B has been described with reference to FIG. 3, an example in which the read commands C0 and C1 are input to one NAND memory 11A will be described below.

  FIG. 4 is a time diagram showing another operation of the nonvolatile semiconductor memory according to the first embodiment. Here, operation control of the NAND memory 11A in reading is shown.

  First, the command issuing unit 253 issues a read command C0 to the NAND memory 11A via the decoder 256. In the period C0, the NAND memory 11A receives the read command C0. Subsequently, the NAND memory 11A extracts data from the memory circuit 11A1 to the buffer 11A2 in the NAND memory 11A in the period BUSY0. Next, in the period OUT0, the data in the buffer 11A2 in the NAND memory 11A is extracted by the data control unit 255.

  During the period, the command monitoring unit 254 monitors the arrival of a new command to the command queue unit 251, and notifies the command extraction unit 252 and the data control unit 255 when the arrival of the read command C1 is found. Upon receiving the notification from the command monitoring unit 254, the command extracting unit 255 extracts the read command C1 from the command queue unit 251 and outputs it to the command issuing unit 253.

  The data control unit 255 confirms the notification of the command monitoring unit 254, and if there is a read command C1 as a new command and the read command C1 can be input to the NAND memory 11A, the data control unit 255 interrupts the data extraction in the period OUT0. To do. When the command issuing unit 253 confirms that the data extraction by the data control unit 255 is interrupted, the command issuing unit 253 issues a read command C1 to the NAND memory 11A. Thereafter, the data control unit 255 confirms that the issue of the read command C1 by the command issuing unit 253 is completed, and resumes the extraction of data from the buffer 11A2 in the NAND memory 11A.

  That is, in the NAND memory 11A, the extraction of data in the period OUT0 is interrupted, and in the period C1, the NAND memory 11A receives the read command C1. When the reception of the read command C1 is completed, the extraction of data in the period OUT0 is resumed in the NAND memory 11A. After receiving the read command C1, the NAND memory 11A takes out data from the memory circuit 11A1 to the buffer 11A2 in the NAND memory 11A in the period BUSY1.

  Here, in the NAND memory 11A, the data extraction in the period OUT0 and the data extraction in the period BUSY1 are executed in parallel. Thus, the data extraction from the NAND memory 11A to the NAND controller 25 by the read command C0 and the data extraction from the memory circuit 11A1 to the buffer 11A2 in the NAND memory 11A by the read command C1 are performed in a short period. Can do. That is, it is possible to reduce the time required for extracting data from the NAND memory to the NAND controller. As a result, it is possible to increase the use efficiency of the NAND memory for reading.

  Next, an example in which a read command C0 is input to the NAND memory 11A and an erase command C2 is input to the NAND memory 11B will be described with reference to FIG.

  FIG. 5 is a time diagram showing the operation of the nonvolatile semiconductor memory in reading and erasing according to the first embodiment. Here, operation control of the NAND memories 11A and 11B in reading and erasing is shown.

  First, the command issuing unit 253 issues a read command C0 to the NAND memory 11A via the decoder 256. In the period C0, the NAND memory 11A receives the read command C0. Subsequently, the NAND memory 11A takes out data from the memory circuit 11A1 to the buffer 11A2 in the NAND memory 11A in the period BUSY0. Next, in the period OUT0, the data in the buffer 11A2 in the NAND memory 11A is extracted by the data control unit 255.

  During the period, the command monitoring unit 254 monitors the arrival of a new command to the command queue unit 251 and notifies the command extraction unit 252 and the data control unit 255 when the arrival of the erase command C2 is found. When receiving the notification from the command monitoring unit 254, the command extraction unit 255 extracts the erase command C 2 from the command queue unit 251 and outputs it to the command issuing unit 253.

  The data control unit 255 confirms the notification of the command monitoring unit 254. If there is an erase command C2 as a new command and the erase command C2 can be input to the NAND memory 11B, the data control unit 255 interrupts the data extraction in the period OUT0. To do. When the command issuing unit 253 confirms that the data extraction by the data control unit 255 is interrupted, the command issuing unit 253 issues an erase command C2 to the NAND memory 11B. Thereafter, the data control unit 255 confirms that the issue of the erase command C2 by the command issuing unit 253 is completed, and resumes the extraction of data from the buffer 11A2 in the NAND memory 11A.

  That is, in the NAND memory 11A, the data extraction in the period OUT0 is interrupted, and in the period C2, the NAND memory 11B receives the erase command C2. When the reception of the erase command C2 ends, the NAND memory 11A resumes data extraction in the period OUT0. In the NAND memory 11B, after receiving the erase command C2, data is erased from the block in the memory circuit 11B1 in the period ERASE2.

  Here, the data extraction in the period OUT0 in the NAND memory 11A and the data erasure in the period ERASE2 in the NAND memory 11B are executed in parallel. As a result, the extraction of data from the NAND memory 11A to the NAND controller 25 by the read command C0 and the erasure of data in the NAND memory 11B by the erase command C2 can be performed in a short period of time. That is, it is possible to reduce the time required for extracting and erasing data from a plurality of NAND memories. As a result, it is possible to increase the use efficiency of the plurality of NAND memories in reading and erasing.

  Next, an example in which a write command C3 is input to the NAND memory 11A and a read command C4 is input to the NAND memory 11B will be described with reference to FIG.

  FIG. 6 is a time diagram illustrating the operation of the nonvolatile semiconductor memory in writing and reading according to the first embodiment. Here, operation control of the NAND memories 11A and 11B in writing and reading is shown.

  First, the command issuing unit 253 issues a write command C3 to the NAND memory 11A via the decoder 256. In the period C3, the NAND memory 11A receives the write command C3. Subsequently, the NAND memory 11A receives data from the data control unit 255 to the buffer 11A2 in the NAND memory 11A in the period IN3. Next, the NAND memory 11A writes data from the buffer 11A2 to the memory circuit 11A1 in the NAND memory 11A in the period PROGRAM3.

  During the above period, the command monitoring unit 254 monitors the arrival of a new command to the command queue unit 251, and notifies the command extraction unit 252 and the data control unit 255 when the arrival of the read command C4 is found. Upon receiving the notification from the command monitoring unit 254, the command extraction unit 255 extracts the read command C4 from the command queue unit 251 and outputs it to the command issuing unit 253.

  The data control unit 255 confirms the notification of the command monitoring unit 254, and interrupts the data transfer in the period IN3 if there is a read command C4 as a new command and the read command C4 can be input to the NAND memory 11B. To do. When confirming that the data transfer by the data control unit 255 is interrupted, the command issuing unit 253 issues a read command C4 to the NAND memory 11B. Thereafter, the data control unit 255 confirms that the issue of the read command C4 by the command issuing unit 253 is completed, and resumes the data transfer to the buffer 11A2 in the NAND memory 11A.

  That is, in the NAND memory 11A, the data transfer in the period IN3 is interrupted, and in the period C4, the NAND memory 11B receives the read command C4. When the reception of the read command C4 is completed, the data transfer in the period IN3 is resumed in the NAND memory 11A. After receiving the read command C4, the NAND memory 11B takes out data from the memory circuit 11B1 to the buffer 11B2 in the NAND memory 11B in the period BUSY4.

  Here, the data transfer in the period IN3 in the NAND memory 11A and the data extraction in the period BUSY4 in the NAND memory 11B are executed in parallel. Thus, data transfer from the NAND controller 25 to the NAND memory 11A by the write command C3 and data extraction from the memory circuit 11B1 to the buffer 11B2 in the NAND memory 11B by the read command C4 can be performed in a short period of time. it can. That is, it is possible to reduce the time required for writing and reading data with respect to a plurality of NAND memories. As a result, it is possible to increase the use efficiency of the plurality of NAND memories in writing and reading.

  3 and 4, the case where the command C1 is input from the host 100 during the period when the data in the buffer in the NAND memory 11A is extracted by the data control unit 255 has been described, but the NAND memory 11A is operating. Thus, the host 100 may input the command C1 during a period in which the command can be input without interrupting the operation. For example, the host 100 may input the command C1 to the command queue unit 251 during a period in which data is extracted from the memory circuit 11A1 to the buffer 11A2 in the NAND memory 11A.

  FIG. 7 is a time diagram showing another operation of the nonvolatile semiconductor memory in the read of the first embodiment. Here, operation control of the NAND memories 11A and 11B in reading is shown.

  First, the command issuing unit 253 issues a read command C0 to the NAND memory 11A via the decoder 256. In the period C0, the NAND memory 11A receives the read command C0. Subsequently, the NAND memory 11A extracts data from the memory circuit 11A1 to the buffer 11A2 in the NAND memory 11A in the period BUSY0. Next, in the period OUT0, the data in the buffer 11A2 in the NAND memory 11A is extracted by the data control unit 255.

  During the operation period of the NAND memory 11A described above, the host 100 inputs the read command C1 to the command queue unit 251 via the host interface 13 during the period BUSY0. The command monitoring unit 252 monitors the arrival of a new command to the command queue unit 251 and notifies the command extraction unit 252 and the data control unit 255 when the arrival of the read command C1 is found. Upon receiving the notification from the command monitoring unit 254, the command extraction unit 252 extracts the read command C1 and outputs it to the command issuing unit 253.

  As described above, since the read command C1 is input from the host 100 to the command queue unit 251 during the period BUSY0, the command issuing unit 253 issues the received read command C1 to the NAND memory 11B as it is. Thereafter, the data control unit 255 starts extracting data from the buffer 11A2 in the NAND memory 11A. On the other hand, after receiving the read command C1, the NAND memory 11B takes out data from the memory circuit 11B1 to the buffer 11B2 in the period BUSY1. Thereafter, the data control unit 255 starts extracting data from the buffer 11B2 in the NAND memory 11B.

  That is, after receiving the command C0, the NAND memory 11A takes out data from the memory circuit 11A1 to the buffer 11A2 in the period BUSY0. During this period BUSY0, the NAND memory 11B receives the command C1 input from the host 100. As described above, when the host 100 inputs the command C1 during the period BUSY0, the operations of the period BUSY0 and the operation of the period BUSY1 are executed in parallel in the NAND memories 11A and 11B. The operation in the period BUSY1 is executed in parallel.

  As a result, the data extraction from the NAND memories 11A and 11B to the NAND controller 25 by the read commands C0 and C1 can be performed in a short period of time. That is, the time required for extracting data from a plurality of NAND memories to the NAND controller can be shortened. As a result, it is possible to increase the use efficiency of a plurality of NAND memories in reading.

  The conventional NAND controller does not check whether a new command has been input while extracting the prepared data. Therefore, when a new command is input, the new command is processed after the data is extracted. For this reason, originally, even in the case where the processing can be performed on the NAND memory in parallel with the extraction of data, the parallel processing is not realized and the performance is deteriorated.

  For example, in the case where read processing is performed in parallel using two NAND chips, chipA and chipB, when it is time for chipB to input a command of chipB while BusA is busy, read processing of chipA and chipB is performed in parallel. Can proceed. On the other hand, when it is time to input a command of chipB while extracting data from chipA, the command cannot be input during data extraction. Therefore, the controller needs to input the command after waiting for data extraction. For this reason, the usage efficiency of chipB falls by that much.

  According to the first embodiment described above, the extraction of data from the NAND memory 11A is interrupted in the period OUT0, and the read command C1 is input to the NAND memory 11B. When the input of the read command C1 is completed, the extraction of data from the NAND memory 11A in the period OUT0 is resumed. After receiving the read command C1, the NAND memory 11B takes out data from the memory circuit to the buffer in the NAND memory 11B in the period BUSY1.

  Here, the extraction of data in the period OUT0 in the NAND memory 11A and the extraction of data in the period BUSY1 in the NAND memory 11B are executed in parallel. For this reason, it is possible to reduce the time required for extracting data from the NAND memories 11A and 11B to the NAND controller 25 by the read commands C0 and C1.

  As described above, according to the first embodiment, it is possible to improve the operation performance of reading, writing, and erasing with respect to the nonvolatile memory, and it is possible to improve the usage efficiency of the SSD.

[Second Embodiment]
A semiconductor memory device 30 according to the second embodiment will be described. The semiconductor memory device 30 is, for example, an SSD 30. FIG. 8 is a block diagram showing the configuration of the semiconductor memory device according to the second embodiment.

  As illustrated, the SSD 30 includes a nonvolatile semiconductor memory 11 and an SSD controller 32. The SSD controller 32 includes a read command address acquisition unit 33, a write command address acquisition unit 34, a command issue unit 35, a read command processing unit 36, a write command processing unit 37, a command queue unit 38, a NAND controller 39, and a timer 40 (measurement). Part). The nonvolatile semiconductor memory 11 includes, for example, a plurality of NAND flash memories (hereinafter referred to as NAND memories) 11A, 11B, and 11C.

  The read command address acquisition unit 33 acquires an address based on a signal input from the host. When the address is acquired by the read command address acquisition unit 33, the read command is input to the command issuing unit 35 and further issued from the command issuing unit 35 to the read command processing unit 36.

  Next, the read command is processed by the read command processing unit 36 and output to the command queue unit 38. The command queue unit 38 stores and manages the received read command. Further, the read command is output from the command queue unit 38 to the NAND controller 39.

  Similarly, the write command address acquisition unit 34 acquires an address based on a signal input from the host. When the address is acquired by the write command address acquisition unit 34, the write command is input to the command issuing unit 35 and further issued from the command issuing unit 35 to the write command processing unit 37.

  Next, the write command is processed by the write command processing unit 37 and output to the command queue unit 38. The command queue unit 38 stores and manages the received write command. Further, the write command is output from the command queue unit 38 to the NAND controller 39.

  The NAND controller 39 issues the command received from the command queue unit 38 to any of the NAND memories 11A, 11B, and 11C. The NAND controller 39 also outputs the issued command and the issued NAND memory information to the timer (measurement unit) 40 as issue information.

  Based on the issue information, the timer 40 outputs the command to be ended and the preceding end time information including the NAND memory to the command issuing unit 35. The command issuing unit 35 issues a command according to the preceding end time information, and advances the command processing by the command processing unit. Thus, the end time of the command is obtained, and the processing of the next command is advanced before the end, so that the next command can be input from the NAND controller 39 to the NAND memory as soon as the command ends.

  FIG. 9 is a block diagram illustrating a command flow and a buffer in the SSD controller 32 of the second embodiment.

  When the address is acquired by the read command address acquisition unit 33, a read command R-Com is issued from the command issuing unit 35 and stored in the buffer 36A of the read command processing unit 36. The read command processing unit 36 has one stage of a buffer 36A for storing a read command.

  Next, the read command R-Com is output from the buffer 36A to the NAND controller 39 via the command queue unit 38 and stored in the buffer 39A of the NAND controller 39. Thereafter, the read command R-Com is input to the NAND memory 11A, for example.

  Similarly, when the address is acquired by the write command address acquisition unit 34, the write command W-Com is output from the command issuing unit 35 and stored in the buffer 37A of the write command processing unit 37. At the same time, write data is input from the host to the write command processing unit 37 and stored in the buffer 37 A of the write command processing unit 37. The write command processing unit 37 has one stage of a buffer 37A for storing a write command R-Com and write data.

  Next, the write command R-Com is output from the buffer 37A to the NAND controller 39 via the command queue unit 38 and stored in the buffer 39A of the NAND controller 39. Thereafter, the write command R-Com is input to the NAND memory 11A, for example. At the same time, write data is also output to the NAND memory 11A.

  Here, it is assumed that time t1 and time t2 are required for the read command process and the write command process, respectively, from the address acquisition by the address acquisition units 33 and 34 until the command can be issued to the NAND memory 11A. That is, the preparation time from the acquisition of the address until the read command can be input to the NAND memory 11A is t1, and the preparation time from the acquisition of the address until the write command can be input to the NAND memory 11A is t2. Further, here, t1 <t2.

  Next, the operation of the semiconductor memory device 30 of the second embodiment will be described.

  FIG. 10 is a block diagram illustrating a configuration of the timer 40 in the SSD controller 32 according to the second embodiment.

  As shown in FIG. 10, the timer 40 includes a correspondence table 401, a preparation time 402 for each command, and a counter 403.

  The correspondence table 401 shows correspondence between commands (read, write, erase, etc.) and processing time. The processing time in the correspondence table 401 is time X for a read command, time Y for a write command, and time Z for erase. In the correspondence table 401, a command type and a processing time are set in advance by a setting interface.

  As described above, the preparation time 402 for each command is time t1 for a read command, time t2 for a write command, and time t3 for erase.

  The counter 403 counts the standby time calculated from the correspondence table 401 and the preparation time 402, and outputs a command that reaches the end and the NAND memory information (for example, the number of the NAND memory chip) as the preceding end information.

  FIG. 11 is a block diagram illustrating a configuration of the command issuing unit 35 in the SSD controller 32 of the second embodiment.

  As shown in FIG. 11, the command issuing unit 35 includes a chip status table 351, a command reception table 352, and a scheduler 353.

  The chip status table 351 shows the correspondence between the NAND memories 11A, 11B, and 11C and the states. That is, it indicates whether or not a command can be input for each NAND memory.

  The command reception table 352 shows the commands output from the address acquisition units 33 and 34 and the target NAND memory. The scheduler 353 obtains an executable command from the chip status table 351 and the command reception table 352 and issues the command to the command processing units 36 and 37.

  The operation of the semiconductor memory device 30 of the second embodiment is as follows.

  First, the NAND controller 39 issues the command received from the command queue unit 38 to the NAND memory 11A. At the same time, the NAND controller 39 outputs the issued command and the issued NAND memory information to the timer 40 as issue information.

  The timer 40 refers to the correspondence table 401 and the preparation time 402 for each command, calculates the waiting time from the preceding information, and starts the counter 403. The waiting time calculated by the timer 40 is obtained by subtracting the preparation time from the command processing time. For example, X-t1 for a read command, Y-t2 for a write command, and Z-t3 for an erase command. The counter 403 counts the waiting time, and when the waiting time elapses, the counter 403 outputs a command for ending and NAND memory information to the command issuing unit 35.

  The command issuing unit 35 updates the information in the chip status table 351 in accordance with the command ending and the NAND memory information. The scheduler 353 refers to the chip status table 351 and the command reception table 352, and selects an appropriate command and NAND memory, that is, an executable command and a target NAND memory. Furthermore, the scheduler 353 issues the selected command to the read command processing unit 36 or the write command processing unit 37 according to the command type.

  The conventional SSD controller does not know when the NAND memory becomes usable, that is, when the command in the NAND memory is finished, so that it does not slow down the operation speed, so that at least two stages for storing the command. A buffer was placed. In response to an immediate command request in the first-stage buffer, it is necessary to prepare for the next command request using the second-stage buffer. In the semiconductor memory device 30 according to the second embodiment, the command end in the nonvolatile memory is estimated, and the command issuance is notified to the command issuing unit in advance, thereby reducing the command buffer that is required for two steps to one. It becomes possible.

  In the second embodiment described above, the end of the command in the NAND memory can be calculated, and the end of the command can be notified to the command issuing unit in advance. As a result, even if the command issuing unit receives the command request and enters the command preparation operation, it is not necessary to store the command in the second-stage buffer and prepare for the next request. As a result, the command buffer and data buffer (buffers for storing write data), which required two stages, can be reduced to one stage. In addition, the processing time for each command can be changed by rewriting the correspondence table 401 using the setting interface.

[Third Embodiment]
A semiconductor memory device 30 according to the third embodiment will be described. In the third embodiment, an example will be described in which the standby time is calculated based on the processing time for each command and the offset corresponding to the temperature or power consumption information of the NAND memory.

  FIG. 12 is a block diagram illustrating a configuration of the timer 40 in the SSD controller 32 according to the third embodiment.

  As shown in FIG. 12, the timer 40 includes a correspondence table 404, a preparation time 402 for each command, and a counter 403. The correspondence table 404 shows correspondence between commands (read, write, erase, etc.) and processing time, and commands and offsets according to temperature information or power consumption information. In the correspondence table 404, the command type, processing time, temperature information or power consumption information, and standby time offset are set in advance by the setting interface.

  For the offset corresponding to the temperature information or power consumption information, for example, three conditions I, J, and K are set for each command depending on the temperature of the NAND memory (for example, 25 ° C., 50 ° C., 85 ° C., etc.) or power consumption. ing. Further, offsets L, M, N, O, P, Q, R, S, and P are associated with the conditions I, J, and K for each command, respectively. The offset is the time added to the command issue interval, and is added to the waiting time until issue when issuing the corresponding command.

  The operation of the semiconductor memory device 30 of the third embodiment is as follows.

  First, the NAND controller 39 issues the command received from the command queue unit 38 to the NAND memory 11A. At the same time, the NAND controller 39 outputs the issued command, the issued NAND memory information, and the temperature information or power consumption information to the timer 40 as issue information.

  The timer 40 calculates the waiting time from the preceding information with reference to the processing time for each command described in the correspondence table 404, the offset of the temperature information or the power consumption information, and the preparation time 402 for each command. More specifically, the timer 40 adds the command processing time and the offset of the temperature information or power consumption information, and subtracts the command preparation time from this added value. Thereby, the waiting time is calculated. Further, the counter 403 is activated based on the calculated waiting time. The counter 403 counts the waiting time, and when the waiting time elapses, the counter 403 outputs a command for ending and NAND memory information to the command issuing unit 35.

  The command issuing unit 35 updates the information in the chip status table 351 in accordance with the command ending and the NAND memory information. The scheduler 353 refers to the chip status table 351 and the command reception table 352, and selects an appropriate command and NAND memory, that is, an executable command and a target NAND memory. Furthermore, the scheduler 353 issues the selected command to the read command processing unit 36 or the write command processing unit 37 according to the command type.

  In the third embodiment, as in the second embodiment, the end of the command in the NAND memory can be calculated, and the end of the command can be notified to the command issuing unit in advance. As a result, the command buffer and data buffer (buffers for storing write data), which required two stages, can be reduced to one stage.

  Furthermore, in the third embodiment, the balance between the operation performance of the NAND memory and the temperature or power consumption is achieved by changing the time (offset) to be waited for when issuing the command according to the temperature information or power consumption information. Is possible. In addition, if the third embodiment is used, it is possible to finely control the interval between commands input to the NAND memory, so that it is possible to control the operation performance, power consumption and temperature according to the situation.

  Also, by rewriting the correspondence table 404 using the setting interface, it is possible to set whether to place emphasis on the operating performance, temperature, or power consumption according to the external environment or customer request.

[Fourth Embodiment]
FIG. 13 is a perspective view showing an example of a personal computer on which the semiconductor memory device 30 of the fourth embodiment is mounted. In the fourth embodiment, an application example using the above-described SSD will be described.

  The personal computer 200 includes a main body 201 and a display unit 202. The display unit 202 includes a display housing 203 and a display device 204 accommodated in the display housing 203.

  The main body 201 includes a housing 205, a keyboard 206, and a touch pad 207 that is a pointing device. The housing 205 accommodates a main circuit board, an optical disk device (ODD) unit, a card slot, the SSD 10, and the like.

  The card slot is provided adjacent to the peripheral wall of the housing 205. An opening 208 facing the card slot is provided on the peripheral wall. The user can insert / remove an additional device into / from the card slot from the outside of the housing 205 through the opening 208.

  The SSD 10 may be used as a state of being mounted inside the personal computer 200 as a replacement for a conventional a hard disk drive (HDD), or used as an additional device while being inserted into a card slot included in the personal computer 200. May be.

  FIG. 14 is a block diagram illustrating a configuration example of a personal computer on which the semiconductor memory device 30 according to the fourth embodiment is mounted.

  The personal computer 200 includes a CPU 301, a north bridge 302, a main memory 303, a video controller 304, an audio controller 305, a south bridge 309, a BIOS-ROM 310, an SSD 10, an ODD unit 311, an embedded controller / keyboard controller IC (EC / KBC) 312, And a network controller 313 and the like.

  The CPU 301 is a processor provided for controlling the operation of the personal computer 200 and executes an operating system (OS) loaded from the SSD 10 to the main memory 303. Further, when the ODD unit 311 enables execution of at least one of read processing and write processing on the loaded optical disc, the CPU 301 executes those processing.

  The CPU 301 also executes a basic input output system (BIOS) stored in the BIOS-ROM 310. The BIOS is a program for hardware control in the personal computer 200.

  The north bridge 302 is a bridge device that connects the local bus of the CPU 301 and the south bridge 309. The north bridge 302 also includes a memory controller that controls access to the main memory 303.

  The north bridge 302 also has a function of executing communication with the video controller 304 and communication with the audio controller 305 via an accelerated graphics port (AGP) bus 314 or the like.

  The main memory 303 temporarily stores programs and data and functions as a work area for the CPU 301. The main memory 303 is composed of, for example, a RAM.

  The video controller 304 is a video playback controller that controls the display unit 202 used as a display monitor of the personal computer 200.

  The audio controller 305 is an audio playback controller that controls the speaker 306 of the personal computer 200.

  The south bridge 309 controls each device on the Low Pin Count (LPC) bus and each device on the Peripheral Component Interconnect (PCI) bus 315. The south bridge 309 controls the SSD 10 that is a storage device for storing various software and data via the ATA interface.

  The personal computer 200 accesses the SSD 10 on a sector basis. A write command, a read command, a cache flush command, and the like are input to the SSD 10 via the ATA interface.

  The south bridge 309 also has a function for controlling access to the BIOS-ROM 310 and the ODD unit 311.

  The EC / KBC 312 is a one-chip microcomputer in which an embedded controller for power management and a keyboard controller for controlling the keyboard (KB) 206 and the touch pad 207 are integrated.

  The EC / KBC 312 has a function of turning on / off the power of the personal computer 200 according to the operation of the power button by the user. The network controller 313 is a communication device that executes communication with an external network such as the Internet.

  FIG. 15 is a block diagram showing the configuration of the semiconductor memory device of the fifth embodiment.

  The semiconductor memory device of this embodiment includes a nonvolatile memory 409 that stores data, and a NAND controller 406 that includes a command execution unit 402 and a command output unit 408.

  The command output unit 408 outputs a command to the command execution unit 402 and, at the same time, refers to the output processing time information for each command and the preparation time information for each command, and calculates a waiting time until the next command output. To do.

  Here, it is assumed that time t1 and time t2 are required for the read command process and the write command process, respectively. That is, the preparation time from the acquisition of the address until the read command can be input to the nonvolatile memory 409 is t1, and the preparation time from the acquisition of the address until the write command can be input to the nonvolatile memory 409 is t2. Further, here, t1 <t2.

  The calculated waiting time is obtained by subtracting the preparation time from the command processing time. For example, if the read command, write command, and erase command preparation times are X, Y, and Z, the read command is X-t1, the write command is Y-t2, and the erase command is Z-t3. is there.

When the standby time is measured by the calculated standby time and the standby time has elapsed, the next command is output to the command execution unit 407. The NAND controller 406 repeats this operation.

  As described above, according to the present embodiment, it is possible to improve the performance of reading, writing, and erasing with respect to the nonvolatile memory, and it is possible to improve the usage efficiency of the SSD. Furthermore, it is possible to provide a memory system that can improve user convenience. The command output unit 408 and the command execution unit 407 are not limited to the NAND controller 406.

  An application example in which the SSD operation of the first embodiment is executed in the personal computer shown in FIGS. Here, device sleep in which the SSD 10 is shifted to the power saving state will be described.

  FIG. 16 is a block diagram showing a configuration of an SSD in which device sleep is executed in a personal computer.

  A power supply voltage VDD is supplied to the power supply terminal 15 of the SSD 10. Further, the power supply voltage VDD is supplied from the power supply terminal 15 to the power supply control circuit 16 and the power supply switch circuit 17. The power supply control circuit 16 outputs a control signal for controlling the operation of the power supply switch circuit 17 to the power supply switch circuit 17 in accordance with a signal output from the CPU 301. The power switch circuit 17 is switched to an on state or an off state by the control signal. The power supply switch circuit 17 supplies the power supply voltage VDD to the SSD controller 12 and the non-volatile semiconductor memory (for example, NAND memory) 11 when in the on state. On the other hand, when in the off state, the supply of the power supply voltage VDD to the SSD controller 12 and the nonvolatile semiconductor memory 11 is stopped.

  Hereinafter, an example of an operation in which device sleep is executed will be described.

  A request for transition to the power saving state is issued from the CPU 301 in the personal computer 200 to the power supply control circuit 16. In the power saving state, the power supply voltage is supplied only to the circuits (for example, the power supply control circuit 16 and the power supply switch circuit 17) that control the supply of the power supply voltage VDD in the SSD 10, and other circuits (for example, the SSD controller) in the SSD 10 12 and the nonvolatile semiconductor memory 11) indicate a state in which no power supply voltage is supplied.

  When receiving the request for transition to the power saving state, the power supply control circuit 16 outputs to the power supply switch circuit 17 a control signal (off request) instructing to cut off the supply of the power supply voltage VDD. When the power switch circuit 17 receives the control signal (off request), the power switch circuit 17 is turned off and cuts off the supply of the power supply voltage VDD to the SSD controller 12 and the nonvolatile semiconductor memory 11. Thereby, SSD10 changes to a power saving state.

  On the other hand, when the SSD 10 is returned from the power saving state to the normal state, the CPU 301 issues a request for returning from the power saving state to the normal state to the power supply control circuit 16. The normal state refers to a state in which the power supply voltage is supplied to circuits (for example, the SSD controller 12 and the nonvolatile semiconductor memory 11) other than the circuit that controls the supply of the power supply voltage VDD in the SSD 10 and the operation is normally performed. .

  When receiving the request for returning to the normal state, the power supply control circuit 16 outputs a control signal (ON request) instructing supply of the power supply voltage VDD to the power supply switch circuit 17. When the power switch circuit 17 receives the control signal (ON request), the power switch circuit 17 is turned on and starts supplying the power supply voltage VDD to the SSD controller 12 and the nonvolatile semiconductor memory 11. As a result, the SSD 10 returns to the normal state.

  In the transition between the power saving state and the normal state of the SSD 10 described above, when the first embodiment is applied, the following occurs. For example, when the user is using the notebook personal computer 200 shown in FIG. 13, when the display unit 202 is momentarily closed and then immediately opened, the device sleep described above may be activated for a moment and immediately return to the normal state. .

  FIG. 17 is a time diagram illustrating an example when device sleep is activated in a read.

  As shown in FIG. 17, when data held in the buffer in the nonvolatile semiconductor memory 11 is pulled out by the data control unit of the SSD controller 12 during the period OUT0, device sleep is activated and data is pulled out. Stop temporarily. Thereafter, the device returns to the normal state from the device sleep immediately. By returning to the normal state, the extraction of the buffer data is resumed (rear period OUT0).

  As described above, when the data in the buffer in the nonvolatile semiconductor memory 11 is extracted to the SSD controller 12, the nonvolatile semiconductor is changed to the power saving state, for example, the device sleep and immediately returns to the normal state. If the data extraction from the buffer in the memory 11 is temporarily interrupted and restarted, the time required for reading can be shortened compared with the case where data extraction is performed again from the beginning. Thereby, it is possible to improve the use efficiency of the nonvolatile semiconductor memory.

  FIG. 18 is a conceptual diagram illustrating a usage example of a server equipped with the SSD of the fourth embodiment.

  A server 400 is connected to the Internet 401. The server 400 includes the SSD 10. Further, a terminal such as a computer 402 is connected to the Internet 401. A user accesses the SSD 10 in the server 400 from the computer 402 via the Internet 401. The configuration and operation of the SSD 10 are the same as those in the embodiment described above.

  Although several examples of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10 ... SSD
DESCRIPTION OF SYMBOLS 11 ... Nonvolatile semiconductor memory 12 ... SSD controller 24 ... Semiconductor memory device 25 ... NAND controller 30 ... Semiconductor memory device 34 ... Address acquisition part 39 ... NAND controller 40 ... Timer 100 ... Host 200 ... Personal computer 202 ... Display unit 204 ... Touch Pad 251 ... Command queue unit 253 ... Command issuing unit 254 ... Command monitoring unit 255 ... Command issuing unit 256 ... Decoder 301 ... CPU
353 ... Scheduler 401 ... Non-volatile memory 402 ... Command execution unit 406 ... NAND controller

Claims (10)

Non-volatile memory for storing data;
A measurement unit for obtaining an end time of an operation by a command in the nonvolatile memory and outputting end time information;
An address acquisition unit for acquiring an address;
A first buffer for storing commands;
A command issuing unit that receives an address acquired by the address acquisition unit and issues a command according to the end time information output from the measurement unit;
A command processing unit for storing and processing the command issued from the command issuing unit;
A memory controller that outputs the command processed by the command processing unit to the non-volatile memory and controls the operation of the non-volatile memory;
With
The first command is stored in the first buffer, and the first command stored in the first buffer is output to the nonvolatile memory, and then output from the measurement unit. A semiconductor memory device that stores, in the first buffer, a second command to be executed next to the first command in accordance with the end time information of the command. Non-volatile memory for storing data;
A measurement unit for obtaining an end time of an operation by a command in the nonvolatile memory and outputting end time information;
A first buffer for storing commands;
With
The first command is stored in the first buffer, and the first command stored in the first buffer is output to the nonvolatile memory, and then output from the measurement unit. A semiconductor memory device that stores, in the first buffer, a second command to be executed next to the first command in accordance with the end time information of the command. Non-volatile memory for storing data;
A measurement unit for obtaining an end time of an operation by a command in the nonvolatile memory and outputting end time information;
A command processing unit including a first buffer for storing commands;
A memory controller for controlling the operation of the nonvolatile memory;
The memory controller has a second buffer for storing commands;
With
The first command stored in the first buffer is stored in the second buffer, the first command stored in the second buffer is output to the nonvolatile memory, and then the measurement is performed. A semiconductor memory device that stores a second command to be executed next to the first command in the first buffer in accordance with the end time information of the first command output from the unit.   The command issuing unit includes command correspondence information indicating correspondence with commands to be issued to the plurality of nonvolatile memories, memory information indicating states of the plurality of nonvolatile memories, the command table, and the state table. The semiconductor memory device according to claim 3, further comprising a scheduler that issues a command based on the command.   The semiconductor memory device according to claim 4, wherein the memory controller notifies the measurement unit of any one of temperature and power consumption in the plurality of nonvolatile memories in addition to the memory information and the command. The measuring unit includes the command and processing time information indicating a processing time from when the command is received until the operation according to the command is completed.
Any of the temperature and power consumption information;
Correspondence information indicating the correspondence with the offset of the waiting time when issuing the command,
Preparation time information indicating a preparation time from when the command is issued from the command issuing unit to when the command is output to the nonvolatile memory;
Have
6. The semiconductor memory device according to claim 5, wherein the end information is obtained by adding the processing time and the offset and subtracting the preparation time from the added value. Non-volatile memory in which data is stored;
A command execution unit for accessing the nonvolatile memory and executing a command;
A command output unit that outputs a first command to the command execution unit and outputs a second command based on a time required to execute the first command obtained from command information corresponding to the first command;
A semiconductor memory device. Non-volatile memory for storing data;
A measurement unit for obtaining an end time of the operation by the command output to the nonvolatile memory, and outputting end time information to the command issuing unit;
A command issuing unit for issuing a command based on the end information;
A memory controller for transferring the received command to the nonvolatile memory;
A semiconductor memory device.   The semiconductor memory device according to claim 1, wherein the command includes any one of a read command, a write command, and an erase command.   4. The semiconductor memory device according to claim 1, wherein the first and second commands include any one of a read command, a write command, and an erase command.

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