WO2016092676A1

WO2016092676A1 - Storage device and control method therefor

Info

Publication number: WO2016092676A1
Application number: PCT/JP2014/082883
Authority: WO
Inventors: 洋内垣内; 三浦　誓士
Original assignee: 株式会社日立製作所
Priority date: 2014-12-11
Filing date: 2014-12-11
Publication date: 2016-06-16

Abstract

Provided is a storage device that achieves a reduction in error rate at the time of data write and data erasure in the storage device to thereby enable high-speed data reading and writing. The storage device is provided with a controller and a nonvolatile memory. The nonvolatile memory is structured to generate heat when operated. The controller issues a command ordering a predetermined operation to the nonvolatile memory. The controller is able to refer to an optimum value of a time interval between the operations by the commands. When, after the command was issued to the nonvolatile memory, a physical domain of the nonvolatile memory operated by the command has a predetermined physical placement relationship with another physical domain of the nonvolatile memory to be operated by the next command, the controller controls the operation by the next command to be performed after the elapse of time equal to or greater than the optimum value of the time interval.

Description

Storage device and control method thereof

The present invention relates to high reliability and high speed of a storage device using a nonvolatile memory.

In a storage device equipped with a nonvolatile memory, particularly a phase change memory, current is passed through the phase change memory to generate Joule heat, thereby changing the resistance value of the memory and writing data. Conventionally, when writing to the same memory cell occurs continuously, the circuit that flows current to the phase change memory waits for a certain interval to relax the heat generated by the previous writing, and then the next writing An electric current was passed (see Patent Document 1).

JP 2012-142083

* Joule heat is generated in memory cells when data is written to nonvolatile memory, especially phase change memory. After writing data to the memory, if the next write current is passed without leaving a sufficient time interval, the heat generated during the previous write is not sufficiently relaxed, and the memory becomes hotter than expected. On the other hand, the phase change memory has an optimum temperature for writing data. For this reason, if data is written in a state where the temperature is higher than the optimum temperature, the data cannot be written properly, and an error occurs.

In the prior art, when data is continuously written to the same memory cell, a circuit for supplying a current to the memory cell waits for a certain time interval from the first write and then performs the second write. Current was flowing. As a result, even when data is continuously written to the same memory cell, data can be written at an optimum temperature, and the occurrence of errors is reduced.

However, according to studies by the inventors, heat generated in a certain memory cell propagates to adjacent cells and memory cells that are physically close to each other. For this reason, when data is written to two memory cells that are physically close to each other, the memory cell to which data is next written is more than expected due to the effect of heat generated in the cell to which data is first written. The data becomes too hot to write data properly. In addition, when continuous writing to the same memory cell occurs, the conventional technique has a problem that the time interval must be kept and performance is deteriorated.

An object of the present invention is to solve the above-described problems of the prior art and provide a storage device that operates with high reliability and high speed.

Among the inventions disclosed in the present application, representative ones are as follows.

One aspect of the present invention is a storage device including a controller and a nonvolatile memory. The nonvolatile memory has a structure that generates heat during operation. The controller issues a command for instructing a predetermined operation to the nonvolatile memory. In addition, the controller holds an optimum value of the time interval between operations by commands. As the optimum value of the time interval between operations, the command issue timing interval can be used substantially. In addition, after the controller issues a command to the nonvolatile memory, the physical area of the nonvolatile memory operated by the command has a predetermined physical arrangement relationship with other physical areas of the nonvolatile memory operated by the next command. In this case, the control is performed so that the operation according to the next command is performed after the optimal value of the time interval or a time longer than the optimal value has elapsed.

In a specific preferable aspect of the present invention, the controller holds in advance an optimum value of the time interval between the issuance of a command and the next command as an optimum value of the time interval between operations by the command, and the nonvolatile memory operated by the command If the physical area is adjacent to the physical area of another non-volatile memory that is operated by the next command, the next command is executed until the optimal value of the command issuance time interval or a time longer than the optimal value has elapsed. Wait and issue the next command after waiting. In this way, the optimum value of the command issue time interval is secured.

In another specific preferred aspect of the present invention, the controller holds in advance an optimum value of the time interval between the issuance of a command and the next command as an optimum value of the time interval between the operations by the command, and the non-volatile operated by the command. When the physical area of the non-volatile memory is adjacent to the physical area of another non-volatile memory operated by the next command, the next command is issued after the next command. In this way, the optimum value of the command issue time interval is secured.

In another specific preferred aspect of the present invention, the controller holds in advance an optimum value of the time interval between the issuance of a command and the next command as an optimum value of the time interval between the operations by the command, and the non-volatile operated by the command. If the physical area of the non-volatile memory is adjacent to the physical area of another non-volatile memory that is operated by the following command, an alternative physical area that is not adjacent to the physical area of the non-volatile memory that has been rewritten by the command is selected. The following command is issued to the alternative physical area instead of the physical area of the non-volatile memory. In this way, the optimum value of the command issue time interval is secured.

As a typical example of a specific device configuration, for example, a nonvolatile memory holds data that defines an optimum value of a time interval between commands as an optimum value of a time interval between operations by commands. The controller can read the optimum value of the time interval between commands from the nonvolatile memory as necessary.

* Various commands can be considered. It is desirable to determine the optimum value of the time interval for each command. For example, the optimal value of the time interval between commands is the optimal value of the time interval between the data write command and the data write command, the optimal value of the time interval between the data write command and the data erase command, the data erase command and the data write The optimum value of the time interval between commands and the optimum value of the time interval between data erasure commands can be considered.

As another specific example of the device configuration, the controller manages the execution time of the last executed command for each physical area corresponding to the unit of writing or erasing data in the nonvolatile memory by the command. To do. As a specific example of the physical area, one defined in advance as a page or a block can be considered.

The storage device according to another aspect of the present invention is a storage device including a controller and a nonvolatile memory. The controller can issue a command to a physical area within a predetermined range of the nonvolatile memory, and can refer to the optimum value information of the time interval between commands, and the physical arrangement of the physical area of the nonvolatile memory from which the command is issued Information can be referred to. In addition, after the command is issued to the first physical area of the nonvolatile memory, the second area of the nonvolatile memory to which the next command is to be issued is adjacent to the first area and immediately If the optimal value of the time interval cannot be satisfied when the command is issued, perform one of the following operations. That is, after waiting until the optimal value of the time interval or a time longer than the optimal value elapses, the next command is issued to the second area. Alternatively, the next command is issued to a third area different from the second area before the optimal value of the time interval or a time longer than the optimal value elapses. Alternatively, another command after the next command is preferentially issued before the optimal value of the time interval or a time longer than the optimal value elapses.

As a preferred specific configuration example, the controller can access a management table that manages the physical area in a predetermined range in which commands are issued and the type and time information of the last issued command in the physical area in association with each other. It is a simple configuration. More preferably, the controller refers to the physical arrangement information when storing the physical area in a predetermined range and the type and time information of the last issued command in the physical area. An adjacent physical area adjacent to the physical area in the range is extracted, and the type and time information of the last issued command is stored in the physical area in a predetermined range in association with the adjacent physical area. By referring to such a table, the time interval of commands can be controlled. Although the same applies to the following description, as long as each information is associated, the table may be divided into a plurality of pieces instead of a single table. Further, the physical position of the storage device storing the information is not limited as long as the information can be accessed.

Another aspect of the present invention is a method for controlling a storage device having a memory cell array in which a plurality of memory cells are arranged. In this method, the appropriate time interval between the first command that instructs the memory cell to perform the first operation and the second command that instructs the memory cell to perform the second operation is stored as appropriate time interval information. . Further, a physical arrangement relationship between a range in which the first command is issued simultaneously among the plurality of memory cells and a range in which the second command is issued simultaneously among the plurality of memory cells is stored as physical arrangement relationship information. . After issuing a first command to a memory cell in a first range among a plurality of memory cells, and before issuing a second command to a memory cell in a second range among the plurality of memory cells Based on the physical arrangement relationship information, it is determined whether or not the first range and the second range are different ranges and a predetermined physical arrangement relationship defined in advance. If the predetermined physical arrangement relationship is defined in advance, the second command is not issued for the second range at a time less than the appropriate time interval between the first command and the second command. To control.

Further, in a preferred embodiment, based on the physical arrangement relationship information, even when the first range and the second range are completely or partially overlapping, the first command At a time point less than the appropriate time interval of the second command, control is performed so that the second command is not issued for the second range.

According to the present invention, even when data writing or erasing is continuously performed on another cell that is physically close to the cell, data writing or erasing can be appropriately performed. Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

1 is a configuration diagram showing an example of the overall configuration of a storage system that is an embodiment to which a first example of the present invention is applied. FIG. FIG. 2 is a configuration diagram illustrating an example of a configuration of a storage device in the storage system of FIG. 1. FIG. 3 is a schematic diagram illustrating an example of a configuration of blocks and pages in the chip of the nonvolatile memory in FIG. 2. It is explanatory drawing which shows an example of the temperature change at the time of erase | eliminating the data written in two adjacent blocks in a non-volatile memory continuously. It is explanatory drawing which shows an example of the temperature change at the time of writing data continuously to a non-volatile memory. It is explanatory drawing which shows an example of the temperature change at the time of erasing data continuously after writing data in a non-volatile memory. It is explanatory drawing which shows an example of the temperature change at the time of writing data continuously after erasing the data in a non-volatile memory. It is explanatory drawing which shows an example of the management information showing the physical arrangement of the block in a non-volatile memory, and a page, and the physical arrangement of the block in a non-volatile memory. It is a schematic diagram which shows an example of the method of setting the physical arrangement | positioning of the block in a non-volatile memory, and a page. It is a schematic diagram which shows an example of the method of setting the optimal value of the time interval between commands. It is a schematic diagram which shows the example of the method of changing the optimal value of the time interval between commands. It is a schematic diagram which shows an example of the control which performs the next command after a fixed time interval after command processing. It is a flowchart which shows an example of the control which performs the following command after a fixed time interval after command processing. It is a schematic diagram which shows an example of the time interval management table which manages the time when the last command was performed in each physical block. It is a schematic diagram which shows an example of the time interval management table which manages the time when the last command was performed in each physical page. It is a schematic diagram which shows an example of the control which preferentially executes commands other than the next command after command processing. It is a flowchart which shows an example of the control which preferentially executes commands other than the next command after command processing. It is a schematic diagram which shows an example of the control which performs the next command after changing the physical area which the next command makes object after command processing. It is a flowchart which shows an example of the control which performs the next command after changing the physical area which the next command makes object after command processing. It is a block diagram which shows an example of the whole structure of the server which is embodiment which applied the 2nd Example of this invention. It is a block diagram which shows another example of the whole structure of the server which is embodiment which applied the 2nd Example of this invention.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not construed as being limited to the description of the embodiments below. Those skilled in the art will readily understand that the specific configuration can be changed without departing from the spirit or the spirit of the present invention.

In the structure of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and redundant description may be omitted.

In this specification and the like, notations such as “first”, “second”, and “third” are attached to identify the constituent elements, and do not necessarily limit the number or order. In addition, a number for identifying a component is used for each context, and a number used in one context does not necessarily indicate the same configuration in another context. Further, it does not preclude that a component identified by a certain number also functions as a component identified by another number.

The position, size, shape, range, etc. of each component shown in the drawings and the like may not represent the actual position, size, shape, range, etc. in order to facilitate understanding of the invention. For this reason, the present invention is not necessarily limited to the position, size, shape, range, and the like disclosed in the drawings and the like.

In this specification, a component expressed in the singular shall include the plural unless specifically indicated otherwise.

According to a typical embodiment of the present invention, a storage device disclosed in the present application includes a controller and a nonvolatile memory, and the controller issues a data write command to the nonvolatile memory, The controller holds the optimum value of the time interval between commands, and after the controller issues the command to the nonvolatile memory, the nonvolatile memory in which the physical area of the nonvolatile memory rewritten by the command is rewritten by the next command In the case where it is adjacent to the physical area, the next command is issued after the optimal value of the time interval or a time longer than the optimal value has elapsed.
<A. Storage system configuration>
First, the configuration of the storage system (SS) according to the first embodiment to which the storage device of the present invention is applied will be described with reference to FIGS.

FIG. 1 shows a configuration example of a storage system (SS) which is a first embodiment to which the present invention is applied. The storage system (SS) includes an SSD controller (SSD controller) and a plurality of storage devices (SSD (1) to SSD (N)) connected to the SSD controller. The SSD controller and the storage devices SSD (1) to SSD (N) communicate data and commands, and the SSD controller is connected to a host device (Host) that executes information processing and communicates data and commands with each other. .

The SSD controller is composed of an information processing circuit (CPU) and one or more DRAM chips (DRAM) connected to the information processing circuit (CPU). An information processing circuit (CPU) performs data communication with each other between connected DRAM chips (DRAM). The SSD controller (SSD controller) processes commands sent from the host device (Host) and issues commands to the storage devices (SSD (1) to SSD (N)). Further, the status of each storage device is managed, and the status is notified to the host device (Host) as necessary.

Each storage device (SSD (1) to SSD (N)) is composed of one control circuit (Controller), one or more nonvolatile memory chips (NVM) and one or more DRAM chips (DRAM). The One control circuit (Controller) performs data communication with the nonvolatile memory chip (NVM) and the DRAM chip (DRAM) and controls them.

FIG. 2 shows details of each storage device (SSD) constituting the storage system (SS) shown in FIG.

The storage device (SSD) consists of one control circuit (Controller), a non-volatile memory chip (NVM (1,1) to NVM (i, j)), and a DRAM chip (DRAM (1) to DRAM (p)) It consists of. i, j, and p are natural numbers.

One controller (Controller) consists of an interface, data register (RG), time interval control block (TIME_MNG), nonvolatile memory control circuit (NVMC (1) to NVMC (i)), and DRAM It is composed of control circuits (DRAMC (1) to DRAMC (p)). Each will be described below.

The interface is connected to the SSD controller in FIG. Further, it is connected to the data register (RG) and the time interval control block (TIME_MNG), and performs data communication with each other.

The data register (RG) is connected to the interface and the time interval control block (TIME_MNG), and performs data communication with each other. Further, the data register (RG) stores a time interval value between commands necessary for control by the time interval control block (TIME_MNG).

The time interval control block (TIME_MNG) is a time interval setting block (INT_CNFG), a time interval update block (INT_UPDT), a time wait block (T_WAIT), a subsequent command issue block (NN_CMD), and another physical area command issue It is composed of blocks (OTR_CMD). The time interval control block (TIME_MNG) includes a data register (RG), nonvolatile memory control circuits (NVMC (1) to NVMC (i)), and DRAM control circuits (DRAMC (1) to DRAMC (p)). They are connected and perform data communication with each other.

The non-volatile memory control circuit (NVMC (i_ch)) is connected to the non-volatile memory (NVM (i_ch, 1) to NVM (i_ch, j)), and reads data from the non-volatile memory (NVM) The data is written into the nonvolatile memory (NVM) and the data in the nonvolatile memory (NVM) is erased. However, i_ch is a natural number from 1 to i. In addition, j nonvolatile memory chips (NVM (i_ch, 1), NVM (i_ch, 2), ..., NVM (i_ch, j)) belonging to the channel i_ch (Ch i_ch) are connected to the data transfer bus (I / O ). Also, j nonvolatile memory chips belonging to each channel can independently process instructions from the nonvolatile memory control circuit (NVMC). The j non-volatile memory chips belong to the way 1, way 2, way..., way j in order of physical proximity from the non-volatile memory control circuit (NVMC). The non-volatile memory control circuit (NVMC) determines whether each non-volatile memory chip is processing data by reading the signal of the ready busy line (RY / BY) connected to each non-volatile memory chip. Can do. The nonvolatile memory control circuits (NVMC (1) to NVMC (i)) are connected to the time interval control block (TIME_MNG) and perform data communication with each other.

The DRAM control circuits (DRAMC (1) to DRAMC (p)) are connected to the DRAM chips (DRAM (1) to DRAM (p)), respectively, and read data from the DRAM chips and write data to the DRAM chips. . The DRAM control circuits (DRAMC (1) to DRAMC (p)) are connected to the time interval control block (TIME_MNG) and perform data communication with each other.
<B. Configuration in Nonvolatile Memory NVM Chip>
The configuration in the nonvolatile memory chip will be described with reference to FIG.

Each non-volatile memory NVM chip (NVM chip) is composed of N_b blocks, and each block is composed of N_p pages. However, N_b and N_p are natural numbers. For example, when the data size of one block in a non-volatile memory with a capacity of 8 GB / chip is 1 MB and the data size of one page is 8 kB, N_b = 8k = (8 GB / 1 MB) and N_p = 128 = (1 MB / 8 kB ). Data stored in the non-volatile memory chip (NVM chip) is read in units of pages, and when data is written in the non-volatile memory chips, data is written in units of pages. The data stored in the nonvolatile memory NVM chip is erased in units of blocks.

In FIG. 3, for simplicity, N_b blocks in the nonvolatile memory chip are arranged in two vertical and horizontal directions, and N_p pages in the block are similarly arranged in two vertical and horizontal directions. However, they may be arranged in three directions of length, width and depth, respectively. When a phase change memory is used as a non-volatile memory, Joule heat is generated when data is written or erased, and the heat is also propagated to physically adjacent blocks or pages. For example, when data is written to one of pages (page (L)) and (page (2L)) adjacent in the vertical direction in the same block, heat is transmitted to the other (P1). The same applies to pages (page (1)) and (page (2)) (P2) adjacent in the vertical direction, and pages (page (N_p)) and (page (L)) (P3) belonging to different blocks. Regarding the blocks (block (1)) and (block (M + 1)) adjacent to each other in the vertical direction, when one of the data is erased, heat propagates to the other (B1). The same applies to the blocks (block (M + 1)) and (block (M + 2)) adjacent in the horizontal direction.

In this way, when data writing or erasing is continuously performed on physically adjacent blocks or pages, it is necessary to control in consideration of the influence of heat propagation.
<C. Specific example of control with time interval between commands>
A specific example of control with a time interval between commands performed by the control circuit (Controller) shown in FIG. 2 will be described with reference to FIGS.

FIG. 4 shows a case where the control circuit (Controller) continuously erases the non-volatile memory (NVM) in two adjacent blocks. A, B, and C represent the order of time passage. First, in A, one block (block (1)) is erased (Erase). At this time, the temperature of the cells in (block (1)) has risen to the optimum temperature for data erasure (High 消去 T). At this time, heat propagates to a part of the adjacent block (block (2)). After a certain period of time (B), the cells in (block (1)) and the part of (block (2)) adjacent to (block (1)) are at room temperature (Low T) and the optimal temperature for data erasure It becomes the intermediate temperature (Mid T) of (High T). Therefore, if (block (2)) is erased immediately at the stage B, the shaded area X rises to a temperature higher than the optimum temperature for data erasure, and the data in that area cannot be erased properly. Further, when the time elapses and the stage C is reached, the temperature of the memory cells in (block (1)) and (block (2)) decreases to room temperature. If (block (2)) is erased at this stage, the memory cell in (block (2)) has the optimum temperature for data erasure, so that data can be erased appropriately (R to erase).

FIG. 5 shows a case where the control circuit (Controller) continuously performs a write operation to the nonvolatile memory (NVM).

Fig. 5 (a) shows a case where the control circuit (Controller) writes data continuously on two adjacent pages of the non-volatile memory (NVM). A, B, and C represent the order of time passage.

First, in A, data is written to one page (page (1)) (Write). The cell in (page (1)) rises in temperature to the optimum temperature (High T) for data writing. In addition, heat propagates to a part of the adjacent page (page (2)). After a certain period of time (B), the cells in (page (1)) and the part of (page (2)) adjacent to (page (1)) are the room temperature (Low T) and the optimal temperature for data writing It becomes the intermediate temperature (Mid T) of (High T). Therefore, if data is written immediately (page (2)) at stage B, the shaded area X becomes higher than the optimum temperature for data writing, and data cannot be written appropriately to the cells in that area. . If more time elapses and the stage C is reached, the temperature of the memory cells in (page (1)) and (page (2)) is lowered to room temperature. If data is written in (page (2)) at this stage, the memory cell in (page (2)) has an optimum temperature for data writing, and data can be written appropriately (R to write).

FIG. 5B shows a case where the control circuit (Controller) continuously writes to adjacent cells existing in a page of the nonvolatile memory (NVM). A, B, and C represent the order of time passage. In the figure, the memory cell (Cell) is indicated by a circle. First, in A, data is written to the upper left memory cell (Cell) in the page (Write). At this time, the temperature of the upper left memory cell rises to the optimum temperature (High T) for data writing. Also, heat propagates to adjacent memory cells. After a lapse of a certain time (B), the memory cell into which data is written and the adjacent memory cell have a temperature (Mid T) between room temperature (Low T) and the optimum temperature for data writing (High T). Therefore, if data is immediately written to the adjacent memory cell (hatched X) in stage B, the two memory cells indicated by (X) will be hotter than the optimum temperature for data writing, and the data will be appropriately transferred. Cannot write. If more time elapses and the stage C is reached, the temperatures of the two memory cells are lowered to room temperature. If data is written to two memory cells at this stage, the temperature of the two memory cells becomes the optimum temperature for data writing, and data can be written appropriately (R to write).

FIG. 6 shows a case where the control circuit (Controller) erases data after a data write operation to the nonvolatile memory (NVM).

FIG. 6A shows a case where the control circuit (Controller) erases data after performing a data write operation in the same block (block) of the nonvolatile memory (NVM). In this example, one block is divided by at least one page. A, B, and C represent the order of time passage. First, in A, data is written to one page (page) in the block (Write). The cell in the page rises to the optimum temperature (High な T) for data writing. At this time, heat is transmitted to a region in a block adjacent to the page. After a certain period of time (B), the cells in the page and the area adjacent to the page are between the room temperature (Low T) and the optimum temperature for data writing (High T) (Mid T) It becomes. If the block is erased immediately at this stage, the shaded area (X) becomes higher than the optimum temperature for erasing data, and the data in that area cannot be erased properly. If time passes and it becomes the C stage, the temperature of the memory cell in a block will fall to room temperature. If data in the block is erased at this stage, the memory cells in the block reach the optimum temperature for data erase, and data can be erased appropriately (R to erase).

FIG. 6B shows a case where the control circuit (Controller) erases data after performing a data write operation in two adjacent blocks of the nonvolatile memory (NVM). In this example, one block is divided by at least one page. A, B, and C represent the order of time passage. First, in A, data is written to one page (page) in one block (block (1)) (Write). The cell in the page rises to the optimum temperature (High な T) for data writing. At this time, heat is transmitted to a block (block (1)) including the page (page) and a partial area in the block (block (2)) adjacent to the page (page). After a certain period of time (B), the cells in the page and the area adjacent to the page are between the room temperature (Low T) and the optimum temperature for data writing (High T) (Mid T) It becomes. If the immediately adjacent block (block (2)) is erased at this stage, the shaded area (X) becomes higher than the optimum temperature for data erasure, and data in that area cannot be erased appropriately. If time passes and it becomes the C stage, the temperature of the memory cell in an adjacent block (block (2)) will fall to room temperature. If the data in the adjacent block (block (2)) is erased at this stage, the memory cells in the adjacent block (block (2)) will be at the optimum temperature for erasing data, and data can be erased appropriately. Yes (R to erase).

FIG. 7 shows a case where data is written after the control circuit (Controller) performs a data erasing operation on the nonvolatile memory (NVM).

FIG. 7A shows a case where the control circuit (Controller) performs data writing after performing the data erasing operation in the same block of the nonvolatile memory (NVM). A, B, and C represent the order of time passage. First, at A, the data in the block is erased (Erase). At this time, the temperature of the cells in the block has risen to the optimum temperature (High T) for data erasure. After a certain period of time (B), the cells in the block are lowered to a temperature (MidMT) between room temperature (Low T) and a temperature optimum for data erasure (High T). If data is written to the page immediately at this stage, the shaded area (X) rises to a temperature higher than the optimum temperature for data writing, and data can be written appropriately to the cells in that area. Absent. If time passes and it becomes the C stage, the memory cell in a block will fall to room temperature. If data is written to the page at this stage, the memory cells in the page have the optimum temperature for data writing, and data can be written appropriately (R to write).

FIG. 7B shows a case in which the control circuit (Controller) performs data writing after performing a data erasing operation in two adjacent blocks of the nonvolatile memory (NVM). A, B, and C represent the order of time passage. First, in A, data in one block (block (1)) is erased (Erase). At this time, the temperature of the cells in the block (block (1)) has increased to the optimum temperature (High T) for data erasure. At this time, heat propagates to a part of the adjacent block (block (2)). After a certain period of time (B), cells in the block (block (1)) and a part of the block (block (2)) adjacent to the block (block (1)) can be erased at room temperature (Low T) and data The temperature drops to an intermediate temperature (Mid T) between the optimum temperature (High T). If data is written to the page immediately at this stage, the shaded area (X) rises to a temperature higher than the optimum temperature for data writing, and data can be written appropriately to the cells in that area. Absent. If time passes and it becomes the C stage, the temperature of a memory cell will fall to room temperature. If data is written to the page at this stage, the memory cells in the page have the optimum temperature for data writing, and data can be written appropriately (R to write).

In the example described above with reference to FIGS. 4 to 7, the influence of heat at the time of writing and erasing the phase change memory is mainly discussed. However, the above-mentioned time is also applied to ReRAM which is a nonvolatile memory other than the phase change memory. Control with spacing is effective. ReRAM creates or extinguishes current paths (such as oxygen vacancy paths) in materials by applying voltage. As a result, the electric resistance of the memory element is changed and “0” or “1” is written. At the time of writing, current also flows through the memory element, so Joule heat is also generated.

For example, as shown in FIG. 5B, when data is first written to the upper left memory cell, the influence of heat or an electric field propagates to the physically adjacent memory cell. If data is written to adjacent memory cells without sufficient time interval, the optimum voltage value for writing changes due to the influence of heat and electric field. Therefore, the resistance value of the memory cell after rewriting has a desired value. It will deviate from the value. This causes a read error when the data written in the adjacent memory cell is read next time. In addition, since data is written at a voltage different from the desired voltage, the data retention period is also shorter than when data is written at the desired voltage. Therefore, even in ReRAM, a highly reliable server, storage system, and storage device (SSD) can be provided by executing the following command after an appropriate time interval. As described above, the present invention can be applied to a memory that generates heat during operation and has a characteristic that the heat generation affects the operation.
<D. Setting of physical arrangement of block and page in nonvolatile memory>
Hereinafter, an example of a method for setting the physical arrangement of blocks and pages in the nonvolatile memory will be described with reference to FIGS.

FIG. 8 (a) shows an example of management information (List) representing the physical arrangement of blocks and pages in the non-volatile memory (NVM). In a nonvolatile memory chip (NVM chip) having a three-dimensional structure, a block and a page (page (not shown in FIG. 8)) are arranged in a three-dimensional direction. In such a case, information on how many pages are arranged in the x, y, and z directions in one block (block) is recorded in the management information (# of pages (x), (y), (z)). Similarly, information on how many blocks are arranged in the x, y, and z directions in one nonvolatile memory chip is recorded in the management information.

As shown in FIG. 8B, when 32 blocks are arranged in the x direction, 32 blocks in the y direction, and 16 blocks in the z direction of the nonvolatile memory (NVM chip), “# of blocks (x ), (y), (z) "are recorded as 32, 32, and 16, respectively.

FIG. 9 shows an example in which the physical arrangement of blocks and pages in the nonvolatile memory is set in the control circuit (Controller). Immediately after power is supplied to the control circuit (Controller), the time interval setting block (INT_CNFG) inside the control circuit (Controller) represents the physical arrangement of blocks and pages recorded in the non-volatile memory (NVM) chip. Management information is read from the chip (Read List) and recorded in the data register (RG) in the control circuit (Controller).

As described above, by recording the physical arrangement information of blocks and pages in the nonvolatile memory in the nonvolatile memory, even if the type and generation of the nonvolatile memory changes and the physical arrangement is changed, the control circuit (Controller) Without changing the logic of F. described later. G. H. Can be controlled. Thereby, a low-cost and highly reliable server, storage system, and storage device (SSD) can be provided.
<E. Setting and changing the optimal time interval between commands>
Hereinafter, an example of a method for setting and changing the optimum value of the time interval between commands will be described with reference to FIGS.

FIG. 10 shows an example of a method for initially setting the optimum value of the time interval between commands. Immediately after power is supplied to the control circuit (Controller), the time interval setting block (INT_CNFG) inside the control circuit (Controller) is the optimum value of the time interval between commands recorded in the non-volatile memory (NVM) chip. Is read (Read Int.) And the value is recorded in the data register (RG) in the control circuit (Controller). The control circuit (Controller) uses this optimum value recorded in the data register (RG) to perform F.R. G. H. The control described in is executed. This optimum value includes the time interval between the erase command and the erase command, the time interval between the erase command and the write command, the time interval between the write command and the erase command, the time interval between the write command and the write command, and the like.

By recording the optimal value of the time interval between commands in the non-volatile memory (NVM) chip, the optimal value of the time interval between commands does not disappear even if an unexpected power shutdown occurs. Since the optimum value of the time interval between commands can be read from the nonvolatile memory (NVM) chip and recorded in the data register (RG), a highly reliable server, storage system and storage device (SSD) can be realized.

FIG. 11 shows an example of a method for changing the optimum value of the time interval between commands. The optimum value of the time interval between commands also changes depending on the usage status and state of the nonvolatile memory. Therefore, after the initial setting described with reference to FIG. 10, it is necessary to change the optimum value of the time interval according to the situation and state. When reading data from the nonvolatile memory (NVM), the time interval update block (INT_UPDT) inside the controller (Controller) receives the read bit error rate before error correction together with the data (A-a.aRead ERR). Based on the result, the optimum value of the time interval between commands is updated (B. update). For example, when the error rate is high, there is a possibility that the corresponding page and block are being deteriorated. Therefore, the optimum value of the time interval between commands is lengthened. Further, the time interval update block (INT_UPDT) reads management information such as the number of erases and the number of reads recorded in the memory (DRAM) (A-b. Read Table). Based on the result, the optimum value of the time interval between commands is updated (B. update). For example, when the number of times of erasing and reading of the corresponding block is large, there is a possibility that the corresponding block has been deteriorated. Therefore, the optimum value of the time interval between commands is lengthened.

In this way, the control circuit (Controller) constantly updates the optimal value of the time interval between commands according to the usage status such as the read bit error rate of the nonvolatile memory (NVM), the number of erases and the number of reads. Highly reliable server, storage system and storage device (SSD) can be provided.

Further, the control circuit (Controller) stores the updated optimal value of the time interval between commands in the nonvolatile memory (NVM) chip (C. UPDT Int). As a result, the optimum value of the time interval between the latest commands can be maintained, so even if an unexpected power interruption occurs, the optimum value of the time interval between the latest commands will not be lost. Since the optimum value of the time interval between the commands can be read from the nonvolatile memory (NVM) chip and recorded in the data register (RG), a highly reliable server, storage system and storage device (SSD) can always be realized. The above is an example of the initial setting method and the changing method of the optimal value of the time interval between commands.For example, the initial value of the optimal value is not read from the chip and is stored in the controller from the beginning, or the optimal value is set. Other implementation methods are conceivable, such as holding in a memory (DRAM) instead of a data register (RG) in the controller.
<F. Control to make time interval between commands>
In the following, an example of control for providing a time interval between commands will be described with reference to FIGS.

FIG. 12 shows a conceptual diagram of this operation.

FIG. 13 shows this operation flow.

First, the control circuit (Controller) issues a command (CMD 0) to the non-volatile memory (NVM) (Fig. 12 A.CMD 0 and Fig.13 Step 1). Next, the control circuit (Controller) refers to management information representing the physical arrangement of blocks and pages in the non-volatile memory (NVM), and blocks or pages affected by the heat generated by the execution of the command (CMD 0). (Read (List of Step 2 in FIG. 13). Based on the result, the control circuit (Controller) updates the table for managing the time interval (FIG. 12 B. Update Table and FIG. 13 Step 2 Update TBL).

14 and 15 show an example of a time interval management table.

FIG. 14 is a table in which the physical block address (Physical Block Address) is an entry, and the next command (CMD 1) is erased in the time interval between the first command (CMD 0) and the next command (CMD 1). Used for commands.

FIG. 14 (a) is an example of a table (BLK TBL1) that manages only time intervals.

FIG. 14 (b) is an example of a table (BLKBLTBL2) for managing time intervals together with other block management information (erase count (P / E cycle) and read count (Read cycle)).

For example, assume that the data in the block corresponding to the physical block address 18057 is erased with CMD 0. At this time, the control circuit (Controller) has a row corresponding to the physical block address 18057 in the time interval management table (BLK TBL1) (BLK TBL2) shown in FIG. 14 and two physically adjacent blocks (physical block address 18056). And "Erase" indicating that the command issued by CMD 0 is erased is written in the CMD column of the row corresponding to 158), and the time when the CMD 時間 0 erase command is executed in the Time column of the same row (3.14. 22.33.52.358.782). Blocks that are physically adjacent to each other are determined based on management information representing a physical arrangement in the nonvolatile memory. Although not shown, this management information can be configured as a table in which the physical block addresses 18057 are associated with the physical block addresses 18056 and 18058, for example. Alternatively, the data may be in other formats instead of the table configuration data.

As another example, assume that data is written to a page in a block corresponding to the physical block address 24332 with CMD 0. At this time, the control circuit (Controller) sets a block (physical block address 24333) physically adjacent to the row corresponding to the physical block address 24332 of the time interval management table (BLK TBL1) (BLK TBL2) shown in FIG. “Write” is written in the CMD column of the corresponding row to indicate that the command issued by CMD 0 is a write, and the time when the write command of CMD 0 is executed in the Time column of the same row (3.14.22.33.52.147. 095) is written.

FIG. 15 is a table in which the physical page address (Physical Page Address) is an entry, and the next command (CMD 1) is written in the time interval between the first command (CMD 0) and the next command (CMD 1). Used for commands.

FIG. 15 (a) is an example of a table (PG TBL1) that manages only time intervals.

Fig. 15 (b) is an example of a table (PG TBL2) for managing time intervals together with physical address-logical address conversion.

Suppose, for example, that data is written to the page corresponding to the physical page address 432577 with CMD 0. At this time, the control circuit (Controller), the row corresponding to the physical page address 4332577 in the time interval management table (PG TBL1) (PG TBL2) shown in FIG. 15 and two physically adjacent pages (physical page address 432576). And 432578) are written in the CMD column of the row corresponding to CMD 0, and “Write” indicating that the command issued by CMD 0 is write is written, and the time when the write command of CMD 0 is executed in the Time column of the same row (6.8. 08.50.32.334.905). The physically adjacent pages are determined based on management information representing the physical arrangement in the nonvolatile memory. As another example, assume that a block including a page corresponding to the physical page address 689300 is erased with CMD 0. At this time, the control circuit (Controller) has a row corresponding to the physical page address 689300 in the time interval management table (PG TBL1) (PG TBL2) shown in FIG. 15 and another page ( “Erase” is written in the CMD column of the row corresponding to the physical page address 689301) to indicate that the command issued by CMD 0 is erase, and the time when the CMD 0 erase command was executed in the Time column of the same row ( 6.8.08.50.13.028.347) is written.

Referring back to FIG. After updating the time interval management table shown in FIG. 14 or FIG. 15, the control circuit (Controller) confirms whether there is a next command following CMD 0 (FIG. 13 Step 3). If there is no next command, the process returns to this confirmation routine (N in Step 13 in FIG. 13).

When the next command exists (FIG. 13 Step Ｙ 3 Y), the control circuit (Controller) erases (or writes) the physical block (or data) with the next command (CMD 1) in the time interval management table (or A line corresponding to (physical page) is referenced (FIG. 13 Step 4).

The control circuit (Controller) compares the current time with the time when the previous command (CMD 0) described in the table was executed, and the time interval between them is the time between commands recorded in the data register (RG). It is determined whether or not the interval is longer than the optimum value (FIG. 13, Step 5).

As a result, if the time interval is longer than the optimum value (Y in Step 5 in FIG. 13), the next command (CMD 1) is executed as it is (Step 7 in FIG. 13). If the time interval is shorter than the optimum value (N in Step 5 in FIG. 13), the time waiting block (T_WAIT) in the control circuit (Controller) waits until the time interval becomes longer than the optimum value (Step 6 in FIG. 13). . After waiting, the time waiting block (T_WAIT) executes the next command (CMD 1) (FIG. 12 C. CMD 1 and FIG. 13 Step 7).
<G. Control to execute the following command first>
Hereinafter, an example of control for executing the next and subsequent commands first will be described with reference to FIGS. 16 and 17.

FIG. 16 shows a conceptual diagram of this operation.

FIG. 17 shows this operation flow.

First, the control circuit (Controller) issues a command (CMD 0) to the non-volatile memory (NVM) (Fig. 16 A.CMD 0 and Fig.17 Step 1). Next, the control circuit (Controller) refers to management information representing the physical arrangement of blocks and pages in the non-volatile memory (NVM), and blocks and pages affected by the heat generated by the execution of the command (CMD (0). (Read (List of Step 2 in FIG. 17).

Based on this result, the control circuit (Controller) updates the table for managing the time interval (Fig. 16B. Update Table and Fig.17 Step 2 Update TBL). The method for updating the time interval management table is the same as the method described in F. After updating the time interval management table, the control circuit (Controller) checks whether there is a next command following CMD 0 (FIG. 17 Step 3).

If there is no next command, return to this confirmation routine (N in Step 3 in Fig. 17). When the next command exists (FIG. 17 Step 3 Y), the control circuit (Controller) erases (or writes) the physical block (or physical) with the next command (CMD 1) in the time interval management table. Refer to the line corresponding to (Page) (Fig. 17 Step 4).

The control circuit (Controller) compares the current time with the time when the previous command (CMD 0) described in the table was executed, and the time interval between them is the time interval between the commands recorded in the data register RG. It is determined whether or not it is longer than the optimum value (FIG. 17 Step 5).

As a result, if the time interval is longer than the optimum value (FIG. 17: Step 5 Y), the next command (CMD-1) is executed as it is (Step 17: CMD 1 1). If the time interval is shorter than the optimum value (N in FIG. 17 図 Step 5), the next and subsequent command issue block (NN_CMD) in the Controller has a command after CMD 1 (CMD 以降 2 and later) (Figure 17 Step 6 ) In the time interval management table, the row corresponding to the physical block (or physical page) from which data is erased (or written) by CMD 2 is referred (Step 4 in FIG. 17).

Next, the next and subsequent command issue block (NN_CMD) compares the current time with the time when the previous command (CMD 0) described in the table was executed, and those time intervals were recorded in the data register RG. It is determined whether or not the time interval between commands is longer than the optimum value (FIG. 17 Step 5). Thereafter, when the time interval is longer than the optimum value, the next command is executed (FIG. 16 図 C. CMD 2 and FIG. 17 図 Step 7 CMD 2), and when the time interval is shorter than the optimum value (FIG. 17 Step 5 N) executes Step 6.

In this way, the control circuit (Controller) manages the time interval, so that F.I. As described above, it is possible to process other commands preferentially without leaving a time interval and to read / write data to / from the storage device at high speed. Further, unlike the following example H, there is no need to change the command issue destination address.
<H. Control to issue command to another physical page>
Hereinafter, an example of control for issuing a command to another physical page will be described with reference to FIGS.

FIG. 18 shows a conceptual diagram of this operation.

FIG. 19 shows this operation flow.

First, the control circuit (Controller) issues a command (CMD 0) to the non-volatile memory (NVM) (Fig. 18 A.CMD 0 and Fig.19 Step 1).

Next, the control circuit (Controller) refers to management information representing the physical arrangement of blocks and pages in the non-volatile memory (NVM), and blocks and pages affected by the heat generated by the execution of the command (CMD (0). (Read List of Step 2 in FIG. 19).

Based on this result, the control circuit (Controller) updates the table for managing the time interval (Fig. 18B. Update Table and Fig. 19 Step 2 Update TBL). The method for updating the time interval management table is the same as the method described in F.

After the time interval management table is updated, the control circuit (Controller) checks whether there is a next command following CMD0 (FIG. 19 Step 3). If there is no next command, the process returns to this confirmation routine (N in Step 19 in FIG. 19). When the next command exists (FIG. 19 Step 3 Y), the control circuit (Controller) deletes (or writes) the physical block (or data) with the next command (CMD 1) in the time interval management table (or A row corresponding to (physical page) is referenced (FIG. 19, Step 4).

The control circuit (Controller) compares the current time with the time when the previous command (CMD 0) described in the table was executed, and the time interval between them is the time interval between the commands recorded in the data register RG. It is determined whether or not it is longer than the optimum value (FIG. 19, Step 5).

As a result, if the time interval is longer than the optimal value (Y in Step 19 in FIG. 19), the next command (CMD-1) is executed as it is (CMD-1 in Step 19 in FIG. 19).

When the time interval is shorter than the optimal value (N in Step 19 Step 5), the separate physical area command issue block (OTR_CMD) in the control circuit (Controller) erases data with the next command (CMD 1) (or The physical block (or physical page) to be written is changed to another physical block (or physical page) if possible (FIG. 19, Step 6).

の After the change, issue the following command (CMD 図 1 in Step 7 in Fig. 19). For example, if the previous command (CMD 0) and the next command (CMD 1) are both written, as shown in FIG. 18, in the nonvolatile memory chip (NVM (1,1)), the first command The data of the next command (CMD 1) may be written to another physical page (Pm) that is not physically adjacent to the physical page (P0) written by the write command (CMD 0) (no influence of heat) However, the data of the next command (CMD 1) may be written to the physical page (Pq) in another nonvolatile memory chip (NVM (i, 1)) (FIG. 18 C-1. CMD 1). -2. CMD 1).

In this way, the controller manages the time interval so that F.I. As described above, by changing the physical area of the nonvolatile memory corresponding to the command without leaving a time interval, it is possible to read / write data from / to the storage device at high speed. In addition, the order of command issuance is not changed as in the previous G example.
<I. Application example to server>
Next, a server (SVR) according to a second embodiment of the present invention will be described with reference to FIGS.

FIG. 20 shows an example of a server (SVR) in which a memory module (MM) is connected to each host device (Host). A host device (Host) composed of an information processing circuit (CPU) and a memory (DRAM) performs information processing. The storage device (memory module (MM)) of the present application is connected to the host device (Host) for main memory expansion or cache use. The memory module (MM) includes a non-volatile memory (NVM), a flash memory (DRAM), and a control circuit (Controller) that controls them. Examples of the interface between the host device (Host) and the memory module (MM) include PCIe. A plurality of host devices (Hosts) are connected to each other via an interconnect network (Interconnect) or the like, and can communicate information.

Like the storage device (SSD) described in the first embodiment, the control circuit (Controller) in the memory module (MM) causes F. G. H. The control is executed.

FIG. 21A shows an example in which a non-volatile memory DIMM (Dual Inline Memory Module) (NVM-DIMM) is directly connected to an information processing circuit (CPU) in each host device (Host). In the information processing circuit (CPU), a non-volatile memory DIMM control circuit (DIMMCPUCTL) is mounted, and the E.I.C. for the non-volatile memory DIMM (NVM-DIMM) connected to the information processing circuit (CPU). F. G. Control. In addition, a memory (DRAM) is connected in the information processing circuit (CPU). In addition, the host device (Host) composed of an information processing circuit (CPU), memory (DRAM), and nonvolatile memory DIMM (NVM-DIMM) is connected to each other via an interconnect network (Interconnect) and the like to communicate information. Can do.

FIG. 21B shows a first embodiment of a non-volatile memory DIMM (NVM-DIMM). The non-volatile memory DIMM (NVM-DIMM) is composed of a plurality of non-volatile memory (NVM) chips (NVM chip), and an information processing circuit (DIMM CTL) is processed according to an instruction from the non-volatile memory DIMM control circuit (DIMM CTL). CPU) to communicate data.

FIG. 21C shows a second embodiment of the nonvolatile memory DIMM (NVM-DIMM). The nonvolatile memory DIMM (NVM-DIMM) includes a plurality of nonvolatile memory (NVM) chips (NVM chips) and a nonvolatile memory control circuit (Controller). The nonvolatile memory control circuit (Controller) G. H. Executes part or all of the above control, and reads, writes, and erases data with respect to the nonvolatile memory (NVM). The nonvolatile memory control circuit (Controller) communicates data with the information processing circuit (CPU).
<J. Summary of Effects of Examples>
The main effects obtained by the embodiment of the present invention described above are as follows.

∙ Even when data is written continuously to other cells that are physically close to each other, a sufficient time interval is provided to reduce errors during data writing. In addition, data can be written at high speed when the controller of the storage device preferentially processes the next command, or when the controller of the storage device changes the write destination cell.

In other words, in a non-volatile memory that generates heat when data is written or erased, even if data is continuously written to or erased from another cell, page, or block of the non-volatile memory, By managing the time of the last executed command, the time interval between commands is identified, and the time interval between the commands is compared with the optimum value, thereby waiting for the command or executing another command with priority. Or, the physical area to which data is written (erased) can be changed by a command, thereby reducing the error rate at the time of data writing or data erasing and reading / writing data to / from the storage device at high speed. It becomes possible.

In the first and second embodiments of the present invention described above, DRAM and nonvolatile memory are used in the storage device (SSD) or memory module (MM), and a phase change memory is used as the nonvolatile memory. As described above, instead of DRAM, random access memory such as MRAM, phase change memory, SRAM, NOR flash memory, or ReRAM, which is a resistance change type memory, may be used as the memory. A NAND flash memory or ReRAM may be used instead of the phase change memory, and can be applied to either case.

In the first and second embodiments of the present invention described above, the case where a plurality of storage devices (SSD) and memory modules (MM) are connected has been described. However, the storage device (SSD) is constituted by one storage device (SSD). It may be a system, and the server may be composed of a single computing node.

In the embodiment of the present invention described above, the embodiment of the present application is configured by a control circuit (Controller), a memory (DRAM), a register, and a nonvolatile memory, but manages an area for executing control, an optimum value, and a time interval. The area to be performed is not limited to the above example. For example, a part of the control may be executed in the chip or in the host, or a part of the time interval may be managed in the controller or the chip.

As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace the configurations of other embodiments with respect to a part of the configurations of the embodiments.

It can be used in the semiconductor memory field and the like, and a storage device that operates at high speed and with high reliability can be provided.

CPU ... Information processing circuit
Controller ... Control circuit
NVM… Non-volatile memory
SS ... Storage system
SSD controller ... Storage system control circuit
SSD (1) -SSD (N) ... Storage device
Interface… Interface
RG: Data register
TIME_MNG ... Time interval control block
INT_CNFG: Time interval setting block
INT_UPDT ... Time interval update block
T_WAIT ... Time wait block
NN_CMD ... Next command issuing block
OTR_CMD ... Block for issuing another physical area command
NVMC (1)-NVMC (i) ... Non-volatile memory control circuit
DRAMC (1) to DRAMC (p) ... DRAM control circuit
I / O: Data transfer bus
RY / DY ... Lady Busy Line
Ch. 1 to i ... Channel
Way 1 ~ j ... Way
block ... Data erase block
N_b ... Number of blocks per chip
page ... page
N_p ... Number of pages per block
High T: Optimum temperature for data writing or erasing
Mid. T… The intermediate temperature between room temperature and High T
Low T ... room temperature
Cell ... Memory cell
List: Management information indicating the physical arrangement of blocks and pages in non-volatile memory
Int: Optimum time interval between commands
TIME_INT: Optimum time interval between commands
P / E Table: Block erase count management table
Time Table… Time interval management table
BLK_TBL1 ... Time interval management table for blocks
BLK_TBL2: Time interval and erase / read count management table for blocks
PG_TBL1 ... Time interval management table for pages
PG_TBL2: Time interval for page and physical logical address conversion management table
P0, Pm, Pq… physical page
SVR ... Server
Host (1)-Host (N) ... Host
Interconnect ... Interconnect
MM (1) to MM (N)… Memory module
NVM-DIMM: Non-volatile memory DIMM
DIMM CTL ... Non-volatile memory DIMM control circuit

Claims

A storage device comprising a controller and a non-volatile memory,
The non-volatile memory has a structure that generates heat during operation,
The controller issues a command for instructing a predetermined operation to the nonvolatile memory;
The controller can refer to the optimum value of the time interval between operations by the command,
After the controller issues the command to the nonvolatile memory, the physical area of the nonvolatile memory operated by the command is different from the other physical area of the nonvolatile memory operated by the next command. If there is a placement relationship,
The storage device is controlled to perform an operation according to the next command after an optimal value of the time interval or a time longer than the optimal value has elapsed.
In claim 1,
The controller is
As the optimum value of the time interval between operations by the command, the optimum value of the time interval between the issue of the command and the next command is held in advance,
When the physical area of the nonvolatile memory operated by the command is adjacent to the physical area of the other nonvolatile memory operated by the next command,
By waiting for the next command until the optimal value of the time interval for issuing the command or a time longer than the optimal value elapses, and after waiting, issuing the next command,
A storage device that secures an optimum value of a time interval for issuing the command.
In claim 1,
The controller is
As the optimum value of the time interval between operations by the command, the optimum value of the time interval between the issue of the command and the next command is held in advance,
When the physical area of the nonvolatile memory operated by the command is adjacent to the physical area of the other nonvolatile memory operated by the next command,
By skipping the next command and issuing a command after the next command,
A storage device that secures an optimum value of a time interval for issuing the command.
In claim 1,
The controller is
As the optimum value of the time interval between operations by the command, the optimum value of the time interval between the issue of the command and the next command is held in advance,
When the physical area of the nonvolatile memory operated by the command is adjacent to the physical area of the other nonvolatile memory operated by the next command,
An alternative physical area that is not adjacent to the physical area of the nonvolatile memory rewritten by the command is selected, and the next command is issued to the alternative physical area instead of the physical area of the other nonvolatile memory. By
A storage device that secures an optimum value of a time interval for issuing the command.
In claim 1,
The nonvolatile memory is
As the optimum value of the time interval between operations by the command, data that defines the optimum value of the time interval between the commands is retained,
The controller is
A storage device, wherein an optimum value of a time interval between the commands is read from the nonvolatile memory.
In claim 5,
The optimal value of the time interval between the commands is
The optimum value of the time interval between the data write command and the data write command for the nonvolatile memory, the optimum value of the time interval between the data write command and the data erase command, and the time interval between the data erase command and the data write command. A storage device comprising at least one of an optimum value and an optimum value of a time interval between a data erase command and a data erase command.
In claim 5,
The controller is
A storage device, wherein an optimum value of a time interval between the commands is changed based on management information of the nonvolatile memory.
In claim 7,
The management information of the nonvolatile memory is
A storage device comprising at least one of an erase count for a data erase unit of the nonvolatile memory, a read count for a data read unit, and a read error rate for the data read unit.
In claim 1,
The controller is
A storage device that manages the execution time of the last executed command for each physical area corresponding to a unit of writing or erasing the data in the nonvolatile memory according to the command.
A storage device comprising a controller and a non-volatile memory,
The controller is
Issue a command to a predetermined range of physical area of the non-volatile memory,
It is possible to refer to the optimum value information of the time interval between the commands,
It is possible to refer to physical arrangement information of a physical area of the nonvolatile memory to which the command is issued,
After issuing the command to the first physical area of the non-volatile memory, a second area of the non-volatile memory to which a next command is to be issued is adjacent to the first area; and If the next command is issued immediately and the optimal value of the time interval cannot be satisfied,
After waiting until the optimal value of the time interval or a time longer than the optimal value elapses, the next command is issued to the second area, or
Issuing the next command to a third area different from the second area before the optimal value of the time interval or a time longer than the optimal value elapses, or
Prior to issuing the next command after the next command prior to the optimal value of the time interval or a time longer than the optimal value elapses;
A storage device.
In claim 10,
The controller is
It is possible to access a management table that manages the physical area in a predetermined range where the command is issued and the type and time information of the last issued command in the physical area in association with each other.
A storage device.
In claim 11,
The controller is
In the management table, when storing the physical area in the predetermined range and the type and time information of the last issued command in the physical area,
By referring to the physical arrangement information, an adjacent physical area adjacent to the physical area of the predetermined range is extracted,
In association with the adjacent physical area, information on the type and time of the last issued command is stored in the physical area in the predetermined range.
A storage device.
In claim 11,
The controller is
By referring to the management table and referring to the optimum value information of the time interval between the commands, it is determined whether or not the optimum value of the time interval cannot be satisfied if the next command is issued immediately.
A storage device.
A method of controlling a storage device having a memory cell array in which a plurality of memory cells are arranged,
Storing an appropriate time interval between a first command for instructing a first operation for the memory cell and a second command for instructing a second operation for the memory cell as appropriate time interval information;
The physical arrangement relationship between the range in which the first command is issued simultaneously among the plurality of memory cells and the range in which the second command is issued simultaneously among the plurality of memory cells is used as physical arrangement relationship information. Remember,
After issuing a first command to a first range of memory cells of the plurality of memory cells,
Before issuing a second command to a second range of memory cells of the plurality of memory cells,
Based on the physical arrangement relationship information, it is determined whether the first range and the second range are different ranges, and a predetermined physical arrangement relationship defined in advance,
In the case of a predetermined physical arrangement relationship defined in advance, at a time less than an appropriate time interval between the first command and the second command, the second command is applied to the second range. A method of controlling a storage device that controls not to issue.
Based on the physical arrangement relationship information, even when the first range and the second range are the same range, at a time point less than the appropriate time interval between the first command and the second command, A storage device control method for controlling not to issue a second command to the second range.